Direct current conversion circuit for enhancing transient response, switching power supply and electronic equipment

Abstract

The invention belongs to the field of circuits, and provides a direct current conversion circuit for enhancing transient response, a switching power supply and electronic equipment. The circuit comprises a conversion module, a comparison module, a ripple injection module, a time delay module, a driving module, a reset module and a switch module, the comparison module is connected with the conversion module, the time delay module, the ripple injection module, the switch module and a load, and the driving module is connected with the conversion module, the time delay module and the reset module. The time delay module is connected with the switch module and the reset module. When the feedback voltage is smaller than the reference voltage, namely before the upper tube is switched on each time, the switch module is controlled to be switched on, so that the first ripple signal and the second ripple signal are connected, the two ripple signals input to the comparison module do not have too large influence on loop control, and therefore in the process that the load jumps from light load to heavy load, the loop control is not influenced. Therefore, the suppression effect of injection ripples on the conduction of the upper tube can be weakened, the drop of the output voltage can be reduced, and the transient response of the circuit can be enhanced.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a direct current conversion circuit, a switching power supply and an electronic device for enhancing transient response. Background Art

[0002] At present, the BUCK converter using COT (Constant-on-time) control mode uses ceramic capacitors with small ESR (equivalent series resistance) as output capacitors, which is prone to instability while obtaining a small output voltage and high efficiency. In order to avoid this situation, researchers have proposed a variety of solutions for loop compensation, including adding feedforward capacitors, sampling inductor current ripple injection, simulated inductor current ripple injection, sampling capacitor current ripple injection, slope compensation, etc. Considering factors such as circuit structure, cost and implementation complexity, simulated inductor current ripple injection is generally regarded as a practical and effective solution.

[0003] However, this ripple injection compensation method will inject a large positive ripple signal into the loop during the light load to heavy load transition process. This ripple signal will inhibit the conduction of the upper tube in the BUCK converter, causing a larger output voltage drop and worsening the transient response of the BUCK converter. Summary of the invention

[0004] The embodiments of the present application provide a DC conversion circuit, a switching power supply and an electronic device for enhancing transient response, which can solve the problem of a larger output voltage drop caused by a BUCK converter using simulated inductor current ripple injection compensation method when the BUCK converter jumps from light load to heavy load.

[0005] In a first aspect, an embodiment of the present application provides a DC conversion circuit for enhancing transient response, comprising a conversion module, a comparison module, a ripple injection module, a delay module, a drive module, a reset module and a switch module, wherein the comparison module is respectively connected to the conversion module, the delay module, the ripple injection module, the switch module and the load, the drive module is respectively connected to the conversion module, the delay module and the reset module, and the delay module is respectively connected to the switch module and the reset module; The driving module is used to output a first logic signal, a first driving signal and a second driving signal according to a first control signal; the conversion module is used to convert the input voltage according to the first driving signal and the second driving signal to obtain an output voltage; the ripple injection module is used to output a first ripple signal and a second ripple signal according to the voltage at the switch node in the conversion module; the reset module is used to output a reset signal according to the first logic signal; the comparison module is used to generate a feedback voltage according to the output voltage, and output a comparison signal according to the feedback voltage, a reference voltage, the first ripple signal and the second ripple signal; the delay module is used to delay the comparison signal according to the reset signal when the feedback voltage is less than the reference voltage, and output a first control signal and a second control signal; the switch module is used to be turned on according to the second control signal to connect the first ripple signal with the second ripple signal.

[0006] In a possible implementation of the first aspect, the delay module includes a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, a sixth field effect tube, a seventh field effect tube, a first inverter, a first NAND gate, and a second inverter. The source of the first field effect tube, the source of the second field effect tube, and the source of the fifth field effect tube all receive a power supply voltage. The gate of the first field effect tube is connected to the reset module, the drain of the first field effect tube is respectively connected to the gate of the second field effect tube, the gate of the third field effect tube, and the comparison module, and the drain of the second field effect tube is respectively connected to the drain of the third field effect tube, the gate of the fifth field effect tube, and the drain of the sixth field effect tube. The gate of the first inverter is connected, the source of the third field effect transistor is respectively connected to the gate of the fourth field effect transistor, the drain of the fourth field effect transistor and the drain of the seventh field effect transistor, the drain of the fifth field effect transistor is respectively connected to the drain of the sixth field effect transistor, the gate of the seventh field effect transistor, the input end of the first inverter and the driving module, the source of the fourth field effect transistor, the source of the seventh field effect transistor and the source of the sixth field effect transistor are all grounded, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate receives an enable signal, the output end of the first NAND gate is connected to the input end of the second inverter, and the output end of the second inverter is connected to the switch module.

[0007] In a possible implementation of the first aspect, the reset module includes a second NAND gate and a third inverter, the first input end of the second NAND gate is connected to the driving module, the second input end of the second NAND gate receives an enable signal, the output end of the second NAND gate is connected to the input end of the third inverter, and the output end of the third inverter is connected to the delay module.

[0008] In a possible implementation of the first aspect, the switch module includes an eighth field effect transistor, the gate of the eighth field effect transistor is connected to the delay module, the source of the eighth field effect transistor is respectively connected to the ripple injection module and the comparison module, and the drain of the eighth field effect transistor is respectively connected to the ripple injection module and the comparison module.

[0009] In a possible implementation manner of the first aspect, the comparison module includes a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a twenty-first field effect transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor; a source of the tenth field effect transistor, a source of the twelfth field effect transistor, a source of the fifteenth field effect transistor, and a source of the twenty-first field effect transistor all receive a power supply voltage; and the tenth field effect transistor The gate of the twelfth field effect tube, the gate of the fifteenth field effect tube and the gate of the twenty-first field effect tube all receive a bias voltage, the drain of the tenth field effect tube is respectively connected to the source of the ninth field effect tube and the source of the eleventh field effect tube, the gate of the ninth field effect tube is respectively connected to the ripple injection module and the switch module, the gate of the eleventh field effect tube is respectively connected to the ripple injection module and the switch module, the drain of the ninth field effect tube is respectively connected to the drain of the thirteenth field effect tube, the first end of the first resistor and the gate of the sixteenth field effect tube, the eleventh field effect tube is respectively connected to the drain of the thirteenth field effect tube, the first end of the first resistor and the gate of the sixteenth field effect tube, The drain of the field effect tube is respectively connected to the drain of the fourteenth field effect tube, the first end of the second resistor and the gate of the eighteenth field effect tube, the drain of the twelfth field effect tube is respectively connected to the source of the thirteenth field effect tube and the source of the fourteenth field effect tube, the gate of the fourteenth field effect tube receives the reference voltage, the gate of the thirteenth field effect tube is respectively connected to the first end of the third resistor and the first end of the fourth resistor, the second end of the third resistor is respectively connected to the conversion module and the load, the drain of the fifteenth field effect tube is respectively connected to the source of the sixteenth field effect tube and the source of the eighteenth field effect tube The drain of the sixteenth field effect transistor is respectively connected to the drain of the seventeenth field effect transistor, the gate of the seventeenth field effect transistor and the gate of the nineteenth field effect transistor, the drain of the eighteenth field effect transistor is respectively connected to the drain of the nineteenth field effect transistor and the gate of the twentieth field effect transistor, the drain of the twenty-first field effect transistor is respectively connected to the drain of the twentieth field effect transistor and the delay module, and the second end of the first resistor, the second end of the second resistor, the second end of the fourth resistor, the source of the seventeenth field effect transistor, the source of the nineteenth field effect transistor and the source of the twentieth field effect transistor are all grounded.

[0010] In a possible implementation manner of the first aspect, the ripple injection module includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth inverter, a twenty-second field effect transistor, a twenty-third field effect transistor, and a twenty-fourth field effect transistor. The first end of the fifth resistor is connected to the conversion module, the second end of the fifth resistor is respectively connected to the first end of the sixth resistor, the first end of the seventh resistor, and the first end of the ninth resistor, the second end of the seventh resistor is respectively connected to the first end of the first capacitor and the first end of the eighth resistor, and the second end of the eighth resistor is respectively connected to the first end of the second capacitor, the source of the twenty-fourth field effect transistor, the drain of the twenty-fourth field effect transistor, the switch The module is connected to the comparison module, the second end of the ninth resistor is respectively connected to the first end of the tenth resistor and the drain of the twenty-second field effect transistor, the second end of the tenth resistor is respectively connected to the source of the twenty-second field effect transistor, the second end of the third capacitor, the source of the twenty-third field effect transistor, the drain of the twenty-third field effect transistor, the switch module and the comparison module, the gate of the twenty-third field effect transistor and the gate of the twenty-fourth field effect transistor both receive the third control signal, the gate of the twenty-second field effect transistor is connected to the output end of the fourth inverter, the input end of the fourth inverter is connected to the conversion module, and the second end of the sixth resistor, the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are all grounded.

[0011] In a possible implementation manner of the first aspect, the conversion module includes an upper tube, a lower tube, an inductor and an output capacitor, the first conduction end of the upper tube is used to receive an input voltage, the second conduction end of the upper tube is respectively connected to the first conduction end of the lower tube, the first end of the inductor and the ripple injection module, the second end of the inductor is respectively connected to the first end of the output capacitor, the load and the comparison module, the control end of the upper tube and the control end of the lower tube are respectively connected to the driving module, the control end of the lower tube is also connected to the ripple injection module, and the second conduction end of the lower tube and the second end of the output capacitor are both grounded; wherein the common end of the second conduction end of the upper tube, the first conduction end of the lower tube and the first end of the inductor is a switch node.

[0012] In a possible implementation of the first aspect, the driving module includes a conduction time generator and a driving unit, the conduction time generator is connected to the driving unit and the delay module respectively, and the driving unit is connected to the conversion module and the reset module respectively; The on-time generator is used to output a fourth control signal to the driving unit according to the first control signal; the driving unit is used to output the first driving signal and the second driving signal to the conversion module according to the fourth control signal, and output a first logic signal to the reset module.

[0013] In a second aspect, an embodiment of the present application provides a switching power supply, comprising a DC conversion circuit for enhancing transient response as described in any one of the first aspects.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising a DC conversion circuit for enhancing transient response as described in any one of the first aspects.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: An embodiment of the present application provides a DC conversion circuit for enhancing transient response, including a conversion module, a comparison module, a ripple injection module, a delay module, a drive module, a reset module and a switch module, wherein the comparison module is respectively connected to the conversion module, the delay module, the ripple injection module, the switch module and the load, the drive module is respectively connected to the conversion module, the delay module and the reset module, and the delay module is respectively connected to the switch module and the reset module.

[0016] The driving module is used to output a first logic signal, a first driving signal and a second driving signal according to a first control signal. The conversion module is used to convert the input voltage according to the first driving signal and the second driving signal to obtain an output voltage. The ripple injection module is used to output a first ripple signal and a second ripple signal according to the voltage at the switch node in the conversion module. The reset module is used to output a reset signal according to the first logic signal. The comparison module is used to generate a feedback voltage according to the output voltage, and output a comparison signal according to the feedback voltage, the reference voltage, the first ripple signal and the second ripple signal. The delay module is used to delay the comparison signal according to the reset signal when the feedback voltage is less than the reference voltage (before the upper tube in the conversion module is turned on), and output the first control signal and the second control signal. The switch module is used to turn on according to the second control signal to connect the first ripple signal with the second ripple signal.

[0017] When the load changes from light load to heavy load, the feedback voltage is bound to be smaller than the reference voltage, and is much smaller than the reference voltage. The reason is that the change of the current on the inductor in the conversion module cannot keep up with the rapid change of the load, causing the output voltage to drop downward. Therefore, in the process of the load changing from light load to heavy load, the upper tube in the conversion module will be turned on with its maximum capacity to make the current on the inductor change rapidly and prevent the output voltage from falling. However, in the process of the load changing from light load to heavy load, the first ripple signal and the second ripple signal output by the ripple injection module will inject a large positive ripple signal into the loop, which will inhibit the conduction of the upper tube and cause a larger output voltage drop. Therefore, when the feedback voltage is less than the reference voltage, that is, before the upper tube is turned on each time, the present application controls the switch module to be turned on through the cooperation between the various modules, so that the first ripple signal and the second ripple signal are connected. After the first ripple signal and the second ripple signal are connected, it is equivalent to inputting two equal ripple signals to the comparison module. At this time, it can be considered that the two ripple signals input to the comparison module will not have much impact on the loop control, so the inhibitory effect of the injected ripple on the conduction of the upper tube will be weakened, then the switching frequency of the circuit will increase, the current on the inductor will change rapidly, and the drop of the output voltage will become smaller, thereby achieving the purpose of enhancing the transient response of the circuit.

[0018] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 This is the principle block diagram of the BUCK converter using the COT control mode; Figure 2 This is the schematic diagram for simulating the inductor current ripple injection; Figure 3 It is a schematic diagram of the simulated inductor current ripple injection waveform; Figure 4 This is a waveform diagram of a BUCK converter using the COT control mode when the load changes from light load to heavy load; Figure 5 It is a principle block diagram of a DC conversion circuit for enhancing transient response provided by an embodiment of the present application; Figure 6is a timing diagram of a DC conversion circuit for enhancing transient response provided by an embodiment of the present application; Figure 7 It is a waveform diagram of a DC conversion circuit for enhancing transient response provided by an embodiment of the present application when the load changes from a light load to a heavy load; Figure 8 This is a circuit connection diagram of a DC conversion circuit for enhancing transient response provided by an embodiment of the present application; Fig. 9 This is a circuit connection diagram of a comparison module in a DC conversion circuit for enhancing transient response provided by an embodiment of the present application; Fig.10 It is a circuit connection diagram of a delay module in a DC conversion circuit for enhancing transient response provided in one embodiment of the present application.

[0021] In the figure: 10, conversion module; 20, comparison module; 30, ripple injection module; 40, delay module; 50, drive module; 51, drive unit; 52, on-time generator; 60, reset module; 70, switch module; 80, load. DETAILED DESCRIPTION

[0022] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0023] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0024] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0025] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0026] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0027] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0028] The principle block diagram of the BUCK converter using the COT control mode is as follows: Figure 1 As shown in the figure, due to the use of ceramic capacitors with smaller ESR as output capacitors, while obtaining a small output voltage and higher efficiency, instability problems are prone to occur. In order to avoid this situation, researchers have proposed a variety of solutions for loop compensation, including adding feedforward capacitors, sampling inductor current ripple injection, simulated inductor current ripple injection, sampling capacitor current ripple injection, slope compensation, etc. Considering factors such as circuit structure, cost, and implementation complexity, simulated inductor current ripple injection is generally regarded as a practical and effective solution. Its implementation principle is as follows: Figure 2 As shown, the voltage at the switch node SW is filtered to convert the square wave signal into a signal SW_RC1 in phase with the inductor current. The sufficiently large time constant of the second-order filter makes the signal SW_RC2 approximately equal to the DC component of the output voltage. Since the signal SW_RC1 also includes the signal SW_RC2, the DC amount needs to be removed to obtain a suitable ripple signal for the compensation loop.

[0029] The simulated inductor current ripple injection waveform is as follows Figure 3 As shown, Figure 3The figure includes the inductor current ripple injection waveform in DCM (DiscontinuousConduction Mode) mode and the inductor current ripple injection waveform in CCM (ContinuousConduction Mode). Among them, the solid line represents the signal SW_RC1, and the dotted line represents the signal SW_RC2. In each switching cycle, when the lower tube S2 is turned on, if the signal SW_RC1 is greater than the signal SW_RC2, a positive ripple signal is injected into the loop. The positive ripple signal has the effect of suppressing the conduction of the upper tube S1 and enhancing the stability of the loop. If the signal SW_RC1 is less than the signal SW_RC2, a negative ripple signal is injected into the loop, and the negative ripple signal will promote the conduction of the upper tube S1.

[0030] However, this ripple injection compensation method that simulates the inductor current will cause a larger output voltage drop when the load changes from light load to heavy load, which will deteriorate the transient response of the buck converter. The waveform of the buck converter using the COT control mode when the load changes from light load to heavy load is as follows: Figure 4 As shown, Figure 4 The undershot in the equation means undershoot, i.e. voltage drop. Figure 4 The inductor current iL (shown as the dotted line in Figure 4 The change of (as shown by the solid line in the figure) lags behind the change of the load current iload. During the time period from t2 to t3, the switching frequency increases. Since the signal SW_RC1 is in phase with the inductor current iL, the signal SW_RC1 will also rise rapidly. The time constants of the filter networks are different, and the filtering speeds are also different, making the change of the signal SW_RC2 slower than that of SW_RC1. Therefore, during the time period from t2 to t3, a large positive ripple signal will be injected to inhibit the conduction of the upper tube S1, resulting in a larger output voltage drop, which is undesirable but is also a problem that this compensation method inevitably brings.

[0031] In view of the above problems, the present application provides a DC conversion circuit for enhancing transient response, such as Figure 5 As shown, the DC conversion circuit for enhancing transient response includes a conversion module 10, a comparison module 20, a ripple injection module 30, a delay module 40, a drive module 50, a reset module 60 and a switch module 70. The comparison module 20 is respectively connected to the conversion module 10, the delay module 40, the ripple injection module 30, the switch module 70 and the load 80, the drive module 50 is respectively connected to the conversion module 10, the delay module 40 and the reset module 60, and the delay module 40 is respectively connected to the switch module 70 and the reset module 60.

[0032] Specifically, the driving module 50 is used to output a first logic signal HS_ONB, a first drive signal HS_driver and a second drive signal LS_driver according to a first control signal PWM, wherein the first logic signal HS_ONB is a logic signal for generating the first drive signal HS_driver. The conversion module 10 is used to convert the input voltage Vin according to the first drive signal HS_driver and the second drive signal LS_driver to obtain an output voltage Vout. The ripple injection module 30 is used to output a first ripple signal SW_RC1 and a second ripple signal SW_RC2 according to the voltage at the switch node SW in the conversion module 10. The reset module 60 is used to output a reset signal RST according to the first logic signal HS_ONB. The comparison module 20 is used to generate a feedback voltage VFB according to the output voltage Vout, and output a comparison signal PWM_INT according to the feedback voltage VFB, the reference voltage VREF, the first ripple signal SW_RC1 and the second ripple signal SW_RC2. The delay module 40 is used to delay the comparison signal PWM_INT according to the reset signal RST when the feedback voltage VFB is less than the reference voltage VREF (before the upper tube in the characterization conversion module 10 is turned on), and output the first control signal PWM and the second control signal SET. The switch module 70 is used to be turned on according to the second control signal SET, so that the first ripple signal SW_RC1 is connected to the second ripple signal SW_RC2. It should be noted that when the feedback voltage VFB is less than the reference voltage VREF, the comparison signal PWM_INT flips to a low level, that is, the first control signal PWM flips to a low level; when the first control signal PWM flips to a low level, the second control signal SET flips to a high level. In the embodiment of the present application, the first control signal PWM and the second control signal SET are logically opposite.

[0033] When the load 80 changes from a light load to a heavy load, the feedback voltage VFB is necessarily smaller than the reference voltage VREF, and is much smaller than the reference voltage VREF. The reason is that the change of the current on the inductor L in the conversion module 10 cannot keep up with the rapid change of the load 80, causing the output voltage Vout to drop downward. Therefore, in the process of the load 80 changing from a light load to a heavy load, the upper tube S1 in the conversion module 10 will be turned on with its maximum capacity to make the current on the inductor L change rapidly, preventing the output voltage Vout from falling downward. However, in the process of the load 80 changing from a light load to a heavy load, the first ripple signal SW_RC1 and the second ripple signal SW_RC2 output by the ripple injection module 30 will inject a larger positive ripple signal into the loop, and the ripple signal will inhibit the conduction of the upper tube S1, causing a larger drop in the output voltage Vout. Therefore, when the feedback voltage VFB is less than the reference voltage VREF, that is, before each turn-on of the upper tube S1, the present application controls the switch module 70 to be turned on through the cooperation between the various modules, so that the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected. After the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected, it is equivalent to inputting two equal ripple signals to the comparison module 20. At this time, it can be considered that the two ripple signals input to the comparison module 20 will not have much impact on the loop control, so the inhibitory effect of the injected ripple on the conduction of the upper tube S1 will be weakened, then the switching frequency of the circuit will increase, the current on the inductor L will change rapidly, and the drop of the output voltage Vout will become smaller, thereby achieving the purpose of enhancing the transient response of the circuit.

[0034] It should be noted that the present application does not limit the type of DC conversion circuit. The DC conversion circuit can be a BUCK circuit, a BOOST circuit or a BUCK-BOOST circuit, as long as these circuits use simulated inductor current ripple injection to perform loop compensation.

[0035] The timing sequence of the DC conversion circuit for enhancing transient response provided by the embodiment of the present application is as follows: Figure 6 As shown, at time t0, the feedback voltage VFB is less than the reference voltage VREF, the first control signal PWM flips to a low level, the second control signal SET flips to a high level, the switch module 70 is turned on, so that the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected, at time t1, the reset signal RST output by the reset module 60 becomes a low level, when the reset signal RST becomes a low level, the delay module 40 delays the comparison signal PWM_INT, after a delay period, the comparison signal PWM_INT flips to a high level at time t2, that is, the first control signal PWM flips to a high level, the second control signal SET flips to a low level, the switch module 70 is turned off, so that the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are disconnected.

[0036] The waveform of the load 80 of the DC conversion circuit for enhancing transient response provided in the embodiment of the present application when it changes from light load to heavy load is as follows: Figure 7 As shown, Figure 7 The less undershot in indicates a smaller undershoot, i.e., a smaller drop voltage. Figure 7 The inductor current iL (shown as the dotted line in Figure 7 The change of the load current iload (shown by the solid line in FIG) lags behind the change of the load current iload. Before turning on the upper tube S1 each time, the present application controls the switch module 70 to turn on through the second control signal SET, so that the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected, so that the second ripple signal SW_RC2 follows the change speed of the first ripple signal SW_RC1 in the time period from t2 to t3, weakening the inhibitory effect of the injected ripple on the conduction of the upper tube S1 in this time period, thereby reducing the drop of the output voltage Vout and enhancing the transient response.

[0037] In some embodiments, Figure 8 As shown, the conversion module 10 includes an upper tube S1, a lower tube S2, an inductor L and an output capacitor Cout, the first conduction end of the upper tube S1 is used to receive the input voltage Vin, the second conduction end of the upper tube S1 is respectively connected to the first conduction end of the lower tube S2, the first end of the inductor L and the ripple injection module 30, the second end of the inductor L is respectively connected to the first end of the output capacitor Cout, the load 80 and the comparison module 20, the control end of the upper tube S1 and the control end of the lower tube S2 are respectively connected to the driving module 50, the control end of the lower tube S2 is also connected to the ripple injection module 30, and the second conduction end of the lower tube S2 and the second end of the output capacitor Cout are both grounded. Among them, the common end of the second conduction end of the upper tube S1, the first conduction end of the lower tube S2 and the first end of the inductor L is the switch node SW.

[0038] Specifically, the driving signal of the upper tube S1 is the first driving signal HS_driver, and the driving signal of the lower tube S2 is the second driving signal LS_driver. When the upper tube S1 is turned on and the lower tube S2 is turned off, the inductor current iL starts to rise, and the inductor L stores energy. When the lower tube S2 is turned on and the upper tube S1 is turned off, the inductor current iL starts to decrease, and the inductor L releases energy. By reasonably setting the duty ratio of the first driving signal HS_driver and the second driving signal LS_driver, the storage and release of energy in the inductor L can be controlled, thereby realizing the transformation of the input voltage Vin to obtain the desired output voltage Vout.

[0039] In the embodiment of the present application, the upper tube S1 and the lower tube S2 are both NMOS (N-Metal-Oxide-Semiconductor) tubes.

[0040] In some embodiments, Figure 8 As shown, the driving module 50 includes a conduction time generator 52 and a driving unit 51. The conduction time generator 52 is connected to the driving unit 51 and the delay module 40 respectively, and the driving unit 51 is connected to the conversion module 10 and the reset module 60 respectively. Figure 8 It can be seen that the driving unit 51 is connected to the control end of the upper tube S1 and the control end of the lower tube S2 in the conversion module 10 respectively.

[0041] Specifically, the on-time generator 52 is used to output the fourth control signal to the driving unit 51 according to the first control signal PWM. The driving unit 51 is used to output the first driving signal HS_driver and the second driving signal LS_driver to the conversion module 10 according to the fourth control signal, and output the first logic signal HS_ONB to the reset module 60.

[0042] It should be noted that the specific structures of the on-time generator 52 and the driving unit 51 can be found in the relevant prior art, and the present application does not limit their specific structures.

[0043] In some embodiments, Figure 8As shown, the ripple injection module 30 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth inverter INV4, a twenty-second field effect transistor M22, a twenty-third field effect transistor M23 and a twenty-fourth field effect transistor M24, a first end of the fifth resistor R5 is connected to the conversion module 10, a first end of the fifth resistor R5 is specifically connected to the switch node SW in the conversion module 10, a second end of the fifth resistor R5 is respectively connected to the first end of the sixth resistor R6, a first end of the seventh resistor R7 and a first end of the ninth resistor R9, a second end of the seventh resistor R7 is respectively connected to the first end of the first capacitor C1 and the first end of the eighth resistor R8, a second end of the eighth resistor R8 is respectively connected to the first end of the second capacitor C2, the source of the twenty-fourth field effect transistor M24, the drain of the twenty-fourth field effect transistor M24, the switch module 7 0 and the comparison module 20, the second end of the ninth resistor R9 is respectively connected to the first end of the tenth resistor R10 and the drain of the twenty-second field effect tube M22, the second end of the tenth resistor R10 is respectively connected to the source of the twenty-second field effect tube M22, the second end of the third capacitor C3, the source of the twenty-third field effect tube M23, the drain of the twenty-third field effect tube M23, the switch module 70 and the comparison module 20, the gate of the twenty-third field effect tube M23 and the gate of the twenty-fourth field effect tube M24 both receive the third control signal SETB, the gate of the twenty-second field effect tube M22 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the conversion module 10, and the input end of the fourth inverter INV4 is specifically connected to the control end of the lower tube S2 in the conversion module 10, and the second end of the sixth resistor R6, the second end of the first capacitor C1, the second end of the second capacitor C2 and the second end of the third capacitor C3 are all grounded. In the embodiment of the present application, the ratio of the fifth resistor R5 to the sixth resistor R6 is 3:1.

[0044] Specifically, the voltage at the switch node SW is divided by the fifth resistor R5 and the sixth resistor R6 and then filtered to obtain the first ripple signal SW_RC1 and the second ripple signal SW_RC2. When the feedback voltage VFB is less than the reference voltage VREF, that is, before each turn-on of the upper tube S1, the second control signal SET output by the delay module 40 becomes a high level, and the switch module 70 is controlled to be turned on, so that the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected. After the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected, it is equivalent to inputting two equal ripple signals to the comparison module 20. At this time, it can be considered that the two ripple signals input to the comparison module 20 will not have much impact on the loop control, so the inhibitory effect of the injected ripple on the conduction of the upper tube S1 will be weakened, then the switching frequency of the circuit will increase, the current on the inductor L will change rapidly, and the drop of the output voltage Vout will become smaller, so as to achieve the purpose of enhancing the transient response of the circuit.

[0045] The twenty-second field effect transistor M22 is used to control whether the tenth resistor R10 is connected to the branch where it is located, and by controlling the size of the resistance of the branch, the discharge current is reduced, and the DC error introduced by the ripple injected by the DC conversion circuit in the CCM mode is eliminated. Specifically, since the lower tube S2 is an NMOS tube, when the lower tube S2 is turned on, the second drive signal LS_driver is at a high level, and the second drive signal LS_driver becomes a low level after passing through the fourth inverter INV4, then the twenty-second field effect transistor M22 is disconnected, and the tenth resistor R10 is connected to the branch where it is located. At this time, the third capacitor C3 discharges the switch node SW. Since the resistance of its discharge branch increases, the discharge current can be reduced. The above-mentioned method of eliminating the DC error introduced by the ripple injected by the DC conversion circuit in the CCM mode is not unique, and the same function can also be achieved through circuits such as S / H (sample / hold).

[0046] The twenty-third field effect transistor M23 and the twenty-fourth field effect transistor M24 in the circuit are controlled by the third control signal SETB, and their function is to offset the influence of clock feedthrough and charge injection effects.

[0047] It should be noted that the third control signal SETB is logically opposite to the second control signal SET. In the embodiment of the present application, the third control signal SETB is provided by the delay module 40 .

[0048] In some embodiments, Figure 8As shown, the reset module 60 includes a second NAND gate NAND2 and a third inverter INV3, the first input end of the second NAND gate NAND2 is connected to the driving module 50, the first input end of the second NAND gate NAND2 is specifically connected to the driving unit 51 in the driving module 50, the second input end of the second NAND gate NAND2 receives the enable signal EN, the output end of the second NAND gate NAND2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is connected to the delay module 40. It should be noted that when the DC conversion circuit works normally, the enable signal EN is at a high level.

[0049] Specifically, according to the specific structure of the reset module 60, the reset signal RST output by the reset module 60 has the same logic as the first logic signal HS_ONB. The reset signal RST is used to reset the first logic signal HS_ONB at a specific time (i.e., when the first logic signal HS_ONB is flipped to a low level, it should be noted that when the first logic signal HS_ONB is flipped to a low level, the comparison signal PWM_INT has already been flipped to a low level. Figure 6 The delay module 40 controls the comparison signal PWM_INT output by the comparison module 20 to delay, and obtains the first control signal PWM after the delay, that is, prolongs the time when the first control signal PWM is at a low level. Since the first control signal PWM is logically opposite to the second control signal SET, the time when the second control signal SET is at a high level will also be prolonged, ensuring that the conduction time of the switch module 70 is long enough, and further ensuring that the time when the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected is long enough, so that the effect of reducing the inhibitory effect on the conduction of the upper tube will be better.

[0050] In some embodiments, Figure 8 As shown, the switch module 70 includes an eighth field effect transistor M8, the gate of the eighth field effect transistor M8 is connected to the delay module 40, the source of the eighth field effect transistor M8 is connected to the ripple injection module 30 and the comparison module 20 respectively, and the drain of the eighth field effect transistor M8 is connected to the ripple injection module 30 and the comparison module 20 respectively. Figure 8 It can be known that the source of the eighth field effect transistor M8 is specifically connected to the second end of the tenth resistor R10 in the ripple injection module 30 , and the drain of the eighth field effect transistor M8 is specifically connected to the second end of the eighth resistor R8 in the ripple injection module 30 .

[0051] Specifically, when the feedback voltage VFB is less than the reference voltage VREF, that is, before each turn-on of the upper tube S1, the second control signal SET output by the delay module 40 becomes a high level, and controls the eighth field effect tube M8 to be turned on, so that the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected. After the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected, it is equivalent to inputting two equal ripple signals to the comparison module 20. At this time, it can be considered that the two ripple signals input to the comparison module 20 will not have much impact on the loop control, so the inhibitory effect of the injected ripple on the turn-on of the upper tube S1 will be weakened, then the switching frequency of the circuit will increase, the current on the inductor L will change rapidly, and the drop of the output voltage Vout will become smaller, thereby achieving the purpose of enhancing the transient response of the circuit.

[0052] In some embodiments, Fig. 9 As shown, the comparison module 20 includes a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a sixteenth field effect transistor M16, a seventeenth field effect transistor M17, an eighteenth field effect transistor M18, a nineteenth field effect transistor M19, a twentieth field effect transistor M20, a twenty-first field effect transistor M21, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, a source of the tenth field effect transistor M10, The source of the twelfth field effect transistor M12, the source of the fifteenth field effect transistor M15 and the source of the twenty-first field effect transistor M21 all receive the power supply voltage VDD, the gate of the tenth field effect transistor M10, the gate of the twelfth field effect transistor M12, the gate of the fifteenth field effect transistor M15 and the gate of the twenty-first field effect transistor M21 all receive the bias voltage Vb, the drain of the tenth field effect transistor M10 is respectively connected to the source of the ninth field effect transistor M9 and the source of the eleventh field effect transistor M11, and the gate of the ninth field effect transistor M9 is respectively connected to the ripple injection module 30 and the switch module 70, as shown in FIG. Figure 8 As shown, the gate of the ninth field effect transistor M9 is specifically connected to the second end of the tenth resistor R10 in the ripple injection module 30 and the source of the eighth field effect transistor M8 in the switch module 70, and the gate of the eleventh field effect transistor M11 is connected to the ripple injection module 30 and the switch module 70, respectively. Figure 8As shown, the gate of the eleventh field effect transistor M11 is specifically connected to the second end of the eighth resistor R8 in the ripple injection module 30 and the drain of the eighth field effect transistor M8 in the switch module 70, the drain of the ninth field effect transistor M9 is respectively connected to the drain of the thirteenth field effect transistor M13, the first end of the first resistor R1 and the gate of the sixteenth field effect transistor M16, the drain of the eleventh field effect transistor M11 is respectively connected to the drain of the fourteenth field effect transistor M14, the first end of the second resistor R2 and the gate of the eighteenth field effect transistor M18, the drain of the twelfth field effect transistor M12 is respectively connected to the source of the thirteenth field effect transistor M13 and the source of the fourteenth field effect transistor M14, the gate of the fourteenth field effect transistor M14 receives the reference voltage VREF, the gate of the thirteenth field effect transistor M13 is respectively connected to the first end of the third resistor R3 and the first end of the fourth resistor R4, and the second end of the third resistor R3 is respectively connected to the conversion module 10 and the load 80, as shown in FIG. Figure 8 As shown, the second end of the third resistor R3 is specifically connected to the second end of the inductor L in the conversion module 10, the drain of the fifteenth field effect transistor M15 is respectively connected to the source of the sixteenth field effect transistor M16 and the source of the eighteenth field effect transistor M18, the drain of the sixteenth field effect transistor M16 is respectively connected to the drain of the seventeenth field effect transistor M17, the gate of the seventeenth field effect transistor M17 and the gate of the nineteenth field effect transistor M19, the drain of the eighteenth field effect transistor M18 is respectively connected to the drain of the nineteenth field effect transistor M19 and the gate of the twentieth field effect transistor M20, the drain of the twenty-first field effect transistor M21 is respectively connected to the drain of the twentieth field effect transistor M20 and the delay module 40, and the second end of the first resistor R1, the second end of the second resistor R2, the second end of the fourth resistor R4, the source of the seventeenth field effect transistor M17, the source of the nineteenth field effect transistor M19 and the source of the twentieth field effect transistor M20 are all grounded.

[0053] Specifically, the third resistor R3 and the fourth resistor R4 divide the output voltage Vout to obtain the feedback voltage VFB, and the differential input pair (the ninth field effect transistor M9 and the eleventh field effect transistor M11) performs a differential operation on the first ripple signal SW_RC1 and the second ripple signal SW_RC2. The result of the differential operation is then superimposed on the result of the differential operation of the feedback voltage VFB and the reference voltage VREF, and then compared, and finally the comparison signal PWM_INT is output.

[0054] When the feedback voltage VFB is less than the reference voltage VREF (when the load 80 changes from a light load to a heavy load, the feedback voltage VFB will always be less than the reference voltage VREF), that is, before each turn-on of the upper tube S1, the first ripple signal SW_RC1 is connected to the second ripple signal SW_RC2 through the interaction between the modules. After the first ripple signal SW_RC1 and the second ripple signal SW_RC2 are connected, it is equivalent to inputting two equal ripple signals to the comparison module 20. At this time, it can be considered that the two ripple signals input to the comparison module 20 will not have much impact on the loop control, so the inhibitory effect on the conduction of the upper tube will be weakened, then the current on the inductor will change rapidly, and the drop of the output voltage Vout will become smaller, thereby solving the problem of a larger output voltage drop caused by the process of the load 80 changing from a light load to a heavy load.

[0055] In some embodiments, Fig. 9 As shown, the delay module 40 includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, a first inverter INV1, a first NAND gate NAND1 and a second inverter INV2. The source of the first field effect transistor M1, the source of the second field effect transistor M2 and the source of the fifth field effect transistor M5 all receive the power supply voltage VDD. The gate of the first field effect transistor M1 is connected to the reset module 60, and the drain of the first field effect transistor M1 is respectively connected to the gate of the second field effect transistor M2, the gate of the third field effect transistor M3 and the comparison module 20, as shown in FIG. Figure 8 As shown, the drain of the first field effect transistor M1 is specifically connected to the drain of the twenty-first field effect transistor M21 in the comparison module 20, the drain of the second field effect transistor M2 is respectively connected to the drain of the third field effect transistor M3, the gate of the fifth field effect transistor M5 and the gate of the sixth field effect transistor M6, the source of the third field effect transistor M3 is respectively connected to the gate of the fourth field effect transistor M4, the drain of the fourth field effect transistor M4 and the drain of the seventh field effect transistor M7, the drain of the fifth field effect transistor M5 is respectively connected to the drain of the sixth field effect transistor M6, the gate of the seventh field effect transistor M7, the input end of the first inverter INV1 and the driving module 50, as shown in FIG. Figure 8 As shown, the drain of the fifth field effect transistor M5 is specifically connected to the conduction time generator 52 in the driving module 50, the source of the fourth field effect transistor M4, the source of the seventh field effect transistor M7 and the source of the sixth field effect transistor M6 are all grounded, the output end of the first inverter INV1 is connected to the first input end of the first NAND gate NAND1, the second input end of the first NAND gate NAND1 receives the enable signal EN, the output end of the first NAND gate NAND1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the switch module 70. Figure 8As shown, the output end of the first NAND gate NAND1 is also connected to the gate of the twenty-third field effect transistor M23 and the gate of the twenty-fourth field effect transistor M24 in the ripple injection module 30. The output end of the second inverter INV2 is specifically connected to the gate of the eighth field effect transistor M8 in the switch module 70.

[0056] Specifically, the first field effect tube M1 is used to control when the delay module 40 delays the comparison signal PWM_INT. The second field effect tube M2 to the seventh field effect tube M7 constitute the delay part. Among them, the connection of the fourth field effect tube M4 is equivalent to a diode, which increases the conduction threshold of the third field effect tube M3, thereby realizing the delay effect. When the first control signal PWM is flipped to a high level, the seventh field effect tube M7 short-circuits the fourth field effect tube M4 to form positive feedback, ensuring that the comparison signal PWM-INT will not always be at an intermediate level between VDD and ground, avoiding the problem of high power consumption. In an embodiment of the present application, the delay time is 5ns.

[0057] It should be noted that the implementation structure of the delay module 40 is not unique, and this application only provides an example. It is worth noting that if other structures are used to implement the delay function, it should be considered whether to add a shaping circuit at the next level of the delay module 40 according to actual conditions.

[0058] In summary, the DC conversion circuit for enhancing transient response provided by the embodiment of the present application connects the first ripple signal with the second ripple signal SW_RC2 before turning on the upper tube S1 each time, weakening the influence of the injected ripple on the establishment of the output voltage Vout when the load 80 jumps from a light load to a heavy load, thereby reducing the drop of the output voltage Vout and enhancing the transient response of the circuit. It should be noted that the method of the present application for solving the problem of a larger output voltage drop caused in the process of the load 80 jumping from a light load to a heavy load is not limited to connecting the first ripple signal with the second ripple signal SW_RC2, and can also be implemented by timely cutting off the ripple injection or reducing the influence of the injected ripple on the loop.

[0059] The embodiment of the present application also provides a switching power supply, including the DC conversion circuit for enhancing transient response as described above. Since the switching power supply provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0060] The embodiment of the present application also provides an electronic device, including the DC conversion circuit for enhancing transient response as described above. Since the electronic device provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0061] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0062] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A DC conversion circuit for enhancing transient response, characterized in that: It includes a conversion module, a comparison module, a ripple injection module, a delay module, a drive module, a reset module and a switch module, wherein the comparison module is respectively connected to the conversion module, the delay module, the ripple injection module, the switch module and the load, the drive module is respectively connected to the conversion module, the delay module and the reset module, and the delay module is respectively connected to the switch module and the reset module; The driving module is used to output a first logic signal, a first driving signal and a second driving signal according to a first control signal; the conversion module is used to convert an input voltage according to the first driving signal and the second driving signal to obtain an output voltage; the ripple injection module is used to output a first ripple signal and a second ripple signal according to a voltage at a switch node in the conversion module; the reset module is used to output a reset signal according to the first logic signal; the comparison module is used to generate a feedback voltage according to the output voltage, and output a comparison signal according to the feedback voltage, a reference voltage, the first ripple signal and the second ripple signal; The delay module is used to delay the comparison signal according to the reset signal and output a first control signal and a second control signal when the feedback voltage is less than the reference voltage; the switch module is used to be turned on according to the second control signal to connect the first ripple signal with the second ripple signal.

2. The DC conversion circuit for enhancing transient response according to claim 1, characterized in that: The delay module includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, a first inverter, a first NAND gate and a second inverter. The source of the first field effect transistor, the source of the second field effect transistor and the source of the fifth field effect transistor all receive a power supply voltage. The gate of the first field effect transistor is connected to the reset module. The drain of the first field effect transistor is respectively connected to the gate of the second field effect transistor, the gate of the third field effect transistor and the comparison module. The drain of the second field effect transistor is respectively connected to the drain of the third field effect transistor, the gate of the fifth field effect transistor and the gate of the sixth field effect transistor. The sources of the three field effect transistors are respectively connected to the gate of the fourth field effect transistor, the drain of the fourth field effect transistor and the drain of the seventh field effect transistor, the drain of the fifth field effect transistor is respectively connected to the drain of the sixth field effect transistor, the gate of the seventh field effect transistor, the input end of the first inverter and the driving module, the source of the fourth field effect transistor, the source of the seventh field effect transistor and the source of the sixth field effect transistor are all grounded, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate receives an enable signal, the output end of the first NAND gate is connected to the input end of the second inverter, and the output end of the second inverter is connected to the switch module.

3. The DC conversion circuit for enhancing transient response according to claim 1, characterized in that: The reset module includes a second NAND gate and a third inverter, the first input end of the second NAND gate is connected to the driving module, the second input end of the second NAND gate receives an enable signal, the output end of the second NAND gate is connected to the input end of the third inverter, and the output end of the third inverter is connected to the delay module.

4. The DC conversion circuit for enhancing transient response according to claim 1, characterized in that: The switch module includes an eighth field effect transistor, the gate of the eighth field effect transistor is connected to the delay module, the source of the eighth field effect transistor is respectively connected to the ripple injection module and the comparison module, and the drain of the eighth field effect transistor is respectively connected to the ripple injection module and the comparison module.

5. The DC conversion circuit for enhancing transient response according to claim 1, characterized in that: The comparison module includes a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a twenty-first field effect transistor, a first resistor, a second resistor, a third resistor and a fourth resistor, the source of the tenth field effect transistor, the source of the twelfth field effect transistor, the source of the fifteenth field effect transistor and the source of the twenty-first field effect transistor all receive a power supply voltage, the gate of the tenth field effect transistor, the gate of the twelfth field effect transistor The gate of the fifteenth field effect tube, the gate of the twenty-first field effect tube all receive a bias voltage, the drain of the tenth field effect tube is respectively connected to the source of the ninth field effect tube and the source of the eleventh field effect tube, the gate of the ninth field effect tube is respectively connected to the ripple injection module and the switch module, the gate of the eleventh field effect tube is respectively connected to the ripple injection module and the switch module, the drain of the ninth field effect tube is respectively connected to the drain of the thirteenth field effect tube, the first end of the first resistor and the gate of the sixteenth field effect tube, the drain of the eleventh field effect tube is respectively connected to the drain of the thirteenth field effect tube, the first end of the first resistor and the gate of the sixteenth field effect tube, The first terminal of the second resistor is connected to the drain of the fourteenth field effect transistor, the first terminal of the second resistor and the gate of the eighteenth field effect transistor, the drain of the twelfth field effect transistor is respectively connected to the source of the thirteenth field effect transistor and the source of the fourteenth field effect transistor, the gate of the fourteenth field effect transistor receives a reference voltage, the gate of the thirteenth field effect transistor is respectively connected to the first terminal of the third resistor and the first terminal of the fourth resistor, the second terminal of the third resistor is respectively connected to the conversion module and the load, the drain of the fifteenth field effect transistor is respectively connected to the source of the sixteenth field effect transistor and the source of the eighteenth field effect transistor, The drain of the sixteenth field effect transistor is respectively connected to the drain of the seventeenth field effect transistor, the gate of the seventeenth field effect transistor and the gate of the nineteenth field effect transistor, the drain of the eighteenth field effect transistor is respectively connected to the drain of the nineteenth field effect transistor and the gate of the twentieth field effect transistor, the drain of the twenty-first field effect transistor is respectively connected to the drain of the twentieth field effect transistor and the delay module, and the second end of the first resistor, the second end of the second resistor, the second end of the fourth resistor, the source of the seventeenth field effect transistor, the source of the nineteenth field effect transistor and the source of the twentieth field effect transistor are all grounded.

6. The DC conversion circuit for enhancing transient response according to claim 1, characterized in that: The ripple injection module includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth inverter, a twenty-second field effect transistor, a twenty-third field effect transistor and a twenty-fourth field effect transistor. The first end of the fifth resistor is connected to the conversion module, the second end of the fifth resistor is respectively connected to the first end of the sixth resistor, the first end of the seventh resistor and the first end of the ninth resistor, the second end of the seventh resistor is respectively connected to the first end of the first capacitor and the first end of the eighth resistor, the second end of the eighth resistor is respectively connected to the first end of the second capacitor, the source of the twenty-fourth field effect transistor, the drain of the twenty-fourth field effect transistor, the switch module and the comparison module. The second end of the ninth resistor is respectively connected to the first end of the tenth resistor and the drain of the twenty-second field effect transistor, the second end of the tenth resistor is respectively connected to the source of the twenty-second field effect transistor, the second end of the third capacitor, the source of the twenty-third field effect transistor, the drain of the twenty-third field effect transistor, the switch module and the comparison module, the gate of the twenty-third field effect transistor and the gate of the twenty-fourth field effect transistor both receive the third control signal, the gate of the twenty-second field effect transistor is connected to the output end of the fourth inverter, the input end of the fourth inverter is connected to the conversion module, and the second end of the sixth resistor, the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are all grounded.

7. The DC conversion circuit for enhancing transient response according to claim 1, characterized in that: The conversion module includes an upper tube, a lower tube, an inductor and an output capacitor, the first conduction end of the upper tube is used to receive an input voltage, the second conduction end of the upper tube is respectively connected to the first conduction end of the lower tube, the first end of the inductor and the ripple injection module, the second end of the inductor is respectively connected to the first end of the output capacitor, the load and the comparison module, the control end of the upper tube and the control end of the lower tube are respectively connected to the driving module, the control end of the lower tube is also connected to the ripple injection module, the second conduction end of the lower tube and the second end of the output capacitor are both grounded; wherein the common end of the second conduction end of the upper tube, the first conduction end of the lower tube and the first end of the inductor is a switch node.

8. The DC conversion circuit for enhancing transient response according to claim 1, characterized in that: The driving module comprises a conduction time generator and a driving unit, the conduction time generator is connected to the driving unit and the delay module respectively, and the driving unit is connected to the conversion module and the reset module respectively; The on-time generator is used to output a fourth control signal to the driving unit according to the first control signal; the driving unit is used to output the first driving signal and the second driving signal to the conversion module according to the fourth control signal, and output a first logic signal to the reset module.

9. A switching power supply, characterized in that: A DC conversion circuit for enhancing transient response comprising any one of claims 1 to 8.

10. An electronic device, characterized in that: A DC conversion circuit for enhancing transient response comprising any one of claims 1 to 8.

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