Power-on reset circuit with temperature compensation

Abstract

The present invention discloses a power-on reset circuit with temperature compensation, which converts a power supply voltage into a reset signal and comprises first to third resistors, first to third field effect transistors, and first and second reverse amplifiers. The present invention divides the power supply voltage by the first and second resistors, and performs temperature compensation by the first field effect transistor and the second field effect transistor, so as to ensure that the output starting point voltage remains stable and does not drift with the change of temperature.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuits, and in particular to a power-on reset circuit with temperature compensation. Background Art

[0002] The power-on reset circuit (POR: Power ON Reset) is a necessary functional module in the chip. Due to the presence of some components such as capacitors and inductors at the power supply end, the power-on process of the chip is actually a slow ramp-up process. After the power is turned on, the voltage of the circuit gradually increases. During the power-on process of the chip, when the power supply voltage is not high enough for the circuit to work normally, an accurate reset signal is provided to put the chip in an initialization state. When the power supply is higher than the set threshold and the chip can work normally, the reset signal of the power-on reset circuit is released to allow the chip to leave the initialization state and start working. That is, the power-on reset circuit is used to monitor the power supply voltage, and the output changes from 0 to 1 when the power supply voltage rises to a certain value.

[0003] Therefore, the core requirements for the power-on reset circuit include high reliability, low power consumption and accuracy of the reset voltage.

[0004] Common POR circuits monitor the power supply voltage by inputting the power supply voltage division signal into the amplifier. Its indicator is the trigger point voltage, which is generally a voltage range lower than the normal working voltage. The temperature characteristics of the voltage division signal greatly affect the temperature characteristics of the trigger point voltage.

[0005] Conventional power-on reset circuits do not have a temperature compensation function. The potential of its output node decreases linearly with the increase of the operating temperature of the MOS tube. Therefore, the trigger potential of its output also decreases linearly with the increase of temperature, resulting in an unstable power-on reset working state. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a power-on reset circuit with temperature compensation, whose output voltage has a temperature compensation function to achieve stable voltage output.

[0007] To solve the above problems, the present invention provides a power-on reset circuit with temperature compensation, the power-on reset circuit with temperature compensation, the power-on reset circuit converts the power supply voltage into a reset signal, the circuit includes first to third resistors, first to third field effect transistors, and first and second reverse amplifiers.

[0008] The power-on reset circuit includes a first resistor R1 and a second resistor R2, wherein the first end of the first resistor R1 is connected to a first field effect transistor P, and the power supply voltage is obtained by connecting the first field effect transistor P to a power supply, the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the node where the first resistor R1 and the second resistor R2 are connected is defined as a first node, and its potential is VK; the second end of the second resistor R2 is connected to a second field effect transistor N1, and is grounded through the second field effect transistor N1.

[0009] A third resistor R3, wherein a first end of the third resistor R3 is connected to a power supply, and a second end of the third resistor R3 is connected to ground via a third field effect transistor N2; a connection node between the third resistor R3 and the third field effect transistor N2 is defined as a second node, and a potential thereof is VO; and the third resistor R3 is a load resistor of the reverse amplifier.

[0010] The gate of the third field effect transistor N2 is connected to the first node.

[0011] The output end of the first inverting amplifier INV1 is connected to the input end of the second inverting amplifier INV2 . The input end of the first inverting amplifier INV1 is connected to the second node voltage V0 . The output end of the second inverting amplifier INV2 outputs a reset voltage VOUT.

[0012] Furthermore, the first field effect transistor is a PMOS tube, whose source terminal is short-circuited and connected to the power supply voltage, and whose gate and drain are short-circuited and connected to the first end of the first resistor.

[0013] Furthermore, the first resistor and the second resistor divide the power supply voltage to form a first node potential V0.

[0014] Furthermore, the second field effect transistor is an NMOS transistor, whose gate and drain are short-circuited and connected to the second end of the second resistor, and whose source is grounded.

[0015] Furthermore, the third field effect transistor is an NMOS transistor.

[0016] Furthermore, when the second field effect transistor is in operation, its gate-source voltage gradually decreases with the increase of temperature, causing the potential VK of the first node to gradually decrease, so that the reset voltage finally outputted drifts with the temperature.

[0017] Furthermore, the first node potential VK is:

[0018] VK=VgsN1+(VPWR-VgsN1-|VgsP|)*R2 / (R1+R2)

[0019] =(VPWR+K*VgsN1-|VgsP|) / (1+K);

[0020] Wherein, VgsN1 is the gate-source voltage of the second field effect transistor, VgsP is the gate-source voltage of the first field effect transistor, VPWR is the power supply voltage, and K=R1 / R2.

[0021] The power-on reset circuit of the present invention uses a PMOS tube and an N1 tube, and selects appropriate values ​​of R1 and R2. When the power-on reset circuit is in operation, since both VgsN1 and |VgsP| decrease linearly with increasing temperature, the node potential VK decreases due to the decrease of VgsN1, and the synchronous decrease of |VgsP| causes the power supply voltage to be compensated to the first node, so that the node potential VK is compensated with the change of temperature, and a stable output of the node potential VK is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The present invention provides a schematic diagram of the structure of the power-on reset circuit.

[0023] Figure 2 It is a curve comparison of the trigger point potential changing with temperature. DETAILED DESCRIPTION

[0024] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] It should be understood that the present invention can be implemented in different forms, and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layer and the zone may be exaggerated, and the same reference numerals represent the same elements from beginning to end. It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to " or "coupled to " other elements or layers, it can be directly on other elements or layers, adjacent to it, connected or coupled to other elements or layers, or there can be an intervening element or layer. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to " other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, zones, layers and / or parts, these elements, components, zones, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0026] The power-on reset circuit of the present invention is as follows: Figure 1 As shown, the power-on reset circuit comprises a resistor R1 and a resistor R2, wherein the first end of the first resistor R1 is connected to a PMOS tube (P), and the power supply voltage VPWR is obtained by connecting the PMOS tube to the power supply, and the first end of the resistor R2 is connected to the second end of the resistor R1, and the node where the resistor R1 and the resistor R2 are connected is defined as a first node, and its potential is VK; the second end of the resistor R2 is connected to an NMOS tube N1, and is grounded through N1. The gate and drain of the PMOS tube are short-circuited, and the substrate electrode is short-circuited with the source. The gate and drain of N1 are short-circuited, and the substrate electrode is grounded.

[0027] A third resistor R3, a first end of the third resistor R3 is connected to the power supply, and a second end of the third resistor R3 is connected to the ground through an NMOS tube N2; a connection node between the third resistor R3 and N2 is defined as a second node, and its potential is VO; the third resistor R3 is a load resistor of the reverse amplifier.

[0028] The gate of the NMOS transistor N2 is connected to the first node, and the substrate electrode is grounded.

[0029] The output end of the first inverting amplifier INV1 is connected to the input end of the second inverting amplifier INV2 . The input end of the first inverting amplifier INV1 is connected to the second node voltage V0 . The output end of the second inverting amplifier INV2 outputs a reset voltage VOUT.

[0030] The resistors R1 and R2 form a voltage divider to divide the power supply voltage VPWR, and combine with the PMOS tube and the N1 tube to form a first node potential VK.

[0031] The calculation of the first node potential VK is as follows:

[0032] VK=VgsN1+(VPWR-VgsN1-|VgsP|)*R2 / (R1+R2)

[0033] =(VPWR+K*VgsN1-|VgsP|) / (1+K);

[0034] Wherein, VgsN1 is the gate-source voltage of the second field effect transistor, VgsP is the gate-source voltage of the first field effect transistor, VPWR is the power supply voltage, and K=R1 / R2.

[0035] The potential VK of the first node will be affected by the N1 tube. As the operating temperature of the N1 tube increases, its gate-source voltage VgsN1 will decrease linearly, causing the potential of VK to decrease, thereby reducing the output voltage V0 of the N2 tube, causing the final power-on reset signal voltage to drift.

[0036] Through the PMOS tube at the upper end of R1, when the temperature of the N1 tube rises, the temperature of the PMOS tube will also rise accordingly, and the first node potential VK can be calculated through the above formula, and the gate-source voltage |VgsP| of the PMOS tube will decrease accordingly, so that the potential VK transmitted to the first node by the power supply VPWR through R1 increases, thereby realizing temperature compensation of the node potential VK and stabilizing its output voltage.

[0037] Figure 2 It is a test curve diagram of the trigger point potential of the present invention and the traditional power-on reset circuit. In the absence of temperature compensation function, as shown in the figure, the trigger point potential gradually and linearly increases from about 730mV to nearly 820mV. After temperature compensation, within the same temperature change range, the trigger point voltage of the structure of the present invention does not fluctuate greatly, and is basically stable at about 760mV. The slope of the curve is significantly reduced, almost in an ideal horizontal state, and the effect of temperature compensation is obvious.

[0038] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power-on reset circuit with temperature compensation, wherein the power-on reset circuit converts a power supply voltage into a reset signal, characterized in that: It includes first to third resistors, first to third field effect transistors, and first and second reverse amplifiers; The power-on reset circuit comprises a first resistor and a second resistor, wherein the first end of the first resistor is connected to a first field effect transistor, and the power supply voltage is obtained by connecting the first field effect transistor to a power supply, the first end of the second resistor is connected to the second end of the first resistor, and the node where the first resistor and the second resistor are connected is defined as a first node, and its potential is VK; the second end of the second resistor is connected to a second field effect transistor, and is grounded through the second field effect transistor; a third resistor, wherein a first end of the third resistor is connected to a power supply, and a second end of the third resistor is connected to ground via a third field effect transistor; a connection node between the third resistor and the third field effect transistor is defined as a second node, and a potential thereof is VO; the third resistor is a load resistor of the first reverse amplifier; The gate of the third field effect transistor is connected to the first node; The output end of the first reverse amplifier is connected to the input end of the second reverse amplifier, the input end of the first reverse amplifier is connected to the second node voltage VO, and the output end of the second reverse amplifier outputs a reset voltage VOUT; the first node potential VK is: VK=VgsN1+(VPWR-VgsN1-|VgsP|)*R2 / (R1+R2) =(VPWR+K*VgsN1-|VgsP|) / (1+K); Where VgsN1 is the gate-source voltage of the second field effect transistor, VgsP is the gate-source voltage of the first field effect transistor, VPWR is the power supply voltage, and K=R1 / R2; When the power-on reset circuit is in operation, since both VgsN1 and |VgsP| decrease linearly with increasing temperature, the decrease in VgsN1 causes the node potential VK to decrease, and the synchronous decrease in |VgsP| causes the power supply voltage to be compensated to the first node, so that the node potential VK is compensated with the change in temperature, forming a stable output of the node potential VK.

2. The power-on reset circuit with temperature compensation as claimed in claim 1, characterized in that: The first field effect transistor is a PMOS transistor, a source end of which is short-circuited and connected to a power supply voltage, and a gate and a drain of which are short-circuited and connected to a first end of a first resistor.

3. The power-on reset circuit with temperature compensation as claimed in claim 1, characterized in that: The first resistor and the second resistor divide the power supply voltage to form a first node potential VK.

4. The power-on reset circuit with temperature compensation as claimed in claim 1, characterized in that: The second field effect transistor is an NMOS transistor, whose gate and drain are short-circuited and connected to the second end of the second resistor, and whose source is grounded.

5. The power-on reset circuit with temperature compensation as claimed in claim 1, characterized in that: The third field effect transistor is an NMOS transistor.

6. The power-on reset circuit with temperature compensation as claimed in claim 1, characterized in that: When the second field effect transistor is working, its gate-source voltage gradually decreases with the increase of temperature, causing the potential VK of the first node to gradually decrease, so that the reset voltage finally outputted drifts with the temperature.

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