A multi-cycle full-data A / D conversion sampling method

Abstract

The present invention provides a multi-cycle full-data A / D conversion sampling method, which includes the following steps: S1, the processor is started; S2: after assigning the i-th analog input signal to 0, the i-th analog input signal is selected and gated, and wait for the analog signal to be fully established; S3: start the conversion; S4: start the tasks of the current cycle; S5: determine whether i is less than N-1. If it is less, go to step S6. If i is equal to N-1, assign 0 to i and then go to step 7; S6: increment i by 1; S7: perform parallel processing on the address gating of the (i + 1)-th analog input signal and the conversion judgment of the i-th analog input signal; S8: start the conversion of the data of i + 1 and then perform other tasks of the current cycle; S9: after the tasks of the current cycle are completed, return to step S4 to perform the next cycle. This method fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time during the A / D conversion sampling process.

Description

Technical Field

[0001] The present invention belongs to the field of airborne computers, and particularly relates to an A / D conversion sampling method with multi-cycle full data. Background Art

[0002] The basic circuit model for an airborne embedded computer to perform analog-to-digital conversion on external multi-channel analog input signals is as Figure 3 shown. Among them, a multiplexer is used to select and connect a certain channel of analog signal to the subsequent A / D conversion circuit. Inside the A / D conversion circuit, after sampling and holding the signal, the analog-to-digital conversion is performed. The processor can obtain digital quantity information through the bus interface circuit of the A / D conversion circuit. Based on this hardware structure, the classical A / D conversion sampling method is as Figure 4 shown in the flow. The characteristic of this flow is that when performing the A / D conversion sampling task in this cycle, the digital quantity information of all complete analog signals is obtained within this cycle. The biggest drawback of this method is that it requires a large amount of waiting time. The multiplexer needs time to select data, the establishment after signal selection requires waiting time, sampling and holding requires waiting time, and A / D conversion requires waiting time. The multiple concentrated accumulations of these times will seriously restrict the performance of the real-time characteristics of the embedded computer and affect the timely execution of other tasks in the current cycle. Summary of the Invention

[0003] To solve the above problems, the present invention provides an A / D conversion sampling method with multi-cycle full data, which fully improves the operation efficiency of the processor and effectively reduces the ineffective waiting time-consuming during the A / D conversion sampling process.

[0004] The object of the present invention is to provide an A / D conversion sampling method with multi-cycle full data, and the method includes the following steps:

[0005] S1. The processor starts;

[0006] S2: After assigning the i-th channel of analog input signal to 0, select the i-th channel of analog input signal and wait for the analog signal to be fully established;

[0007] S3: Start the conversion;

[0008] S4: Start the tasks of this cycle;

[0009] S5: Determine whether i is less than N - 1. If it is less, perform step S6. If i is equal to N - 1, assign i to 0 and then perform step 7;

[0010] S6: i is incremented by 1;

[0011] S7: Parallel process the address selection of the (i + 1)-th channel of analog input signal and the conversion judgment of the i-th channel;

[0012] S8: After starting to convert the data of i+1, perform other tasks in this cycle;

[0013] S9: After the tasks in this cycle are completed, return to step S4 for the next cycle.

[0014] The A / D conversion sampling method with multi-cycle full data provided by the present invention also has the following feature: the gating of the i-th analog input signal in S2 is performed by a multiplexer.

[0015] The A / D conversion sampling method with multi-cycle full data provided by the present invention also has the following feature: the steps of S7 are as follows:

[0016] S7.1 Perform address gating for the (i+1)-th analog input signal;

[0017] S7.2: Wait for hold;

[0018] S7.3: Perform conversion judgment for the i-th path. If the conversion is completed, perform S7.4; if the conversion is not complete, repeat S7.3;

[0019] S7.4: Read the conversion result.

[0020] The A / D conversion sampling method with multi-cycle full data provided by the present invention also has the following feature: the steps of the conversion judgment in S7.3 are as follows:

[0021] S7.3.1: Start and enter the "conversion completed" discrimination process;

[0022] S7.3.2: Assign 0 to c, and c is used for loop counting;

[0023] S7.3.3: Judge whether the value of c is less than M. If it is less than M, perform S7.3.5 next; otherwise, perform S7.3.4 next, where M is the counting threshold;

[0024] S7.3.4: Fault handling, and perform S7.3.7 next;

[0025] S7.3.5: Whether the "A / D conversion completed signal indication" is in the completed state. If it is completed, perform S7.3.7 next; otherwise, perform S7.3.6 next:

[0026] S7.3.6: Increment i by 1, that is, increase the value of i by 1, and perform S7.3.3 next;

[0027] S7.3.7: Assign 0 to c;

[0028] S7.3.8: Exit, and the "conversion completed" discrimination process is completed.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] The present invention provides a multi-cycle full-data A / D conversion sampling method, which fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time during the A / D conversion sampling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 Flowchart of the multi-cycle full-data A / D conversion sampling method provided by the embodiments of the present invention;

[0033] Figure 2 Flowchart of the conversion completion step in the method provided by the embodiments of the present invention;

[0034] Figure 3 Basic model of the A / D conversion sampling circuit;

[0035] Figure 4 Single-cycle full-data A / D conversion sampling method in the prior art. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] In order to make the technical means, creative features, achieved purposes and functions of the present invention easy to understand, the following embodiments will specifically describe the multi-cycle full-data A / D conversion sampling method provided by the present invention in conjunction with the drawings.

[0037] In the description of the embodiments of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0038] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0039] The terms "mounted", "connected", and "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] As Figure 1 shown, the present invention provides a multi-cycle full-data A / D conversion sampling method, and the method includes the following steps:

[0041] S1. The processor is started;

[0042] S2: After assigning the i-th analog input signal to 0, the i-th analog input signal is selected and waited for the analog signal to be fully established;

[0043] S3. The conversion is started;

[0044] S4. The tasks of the current cycle are started;

[0045] S5. Determine whether i is less than N - 1. If it is less, go to step S6. If i is equal to N - 1, assign 0 to i and then go to step 7;

[0046] S6. i is incremented by 1;

[0047] S7. The address selection of the (i + 1)-th analog input signal and the conversion judgment of the i-th are processed in parallel;

[0048] S8. After starting the conversion of the data of i + 1, other tasks of the current cycle are performed;

[0049] S9. After the tasks of the current cycle are completed, return to step S4 for the next cycle.

[0050] In some embodiments, the selection of the i-th analog input signal in S2 is performed through a multiplexer.

[0051] In some embodiments, step S7 is as follows:

[0052] S7.1. The address selection of the (i + 1)-th analog input signal is performed;

[0053] S7.2: Wait and hold;

[0054] S7.3: Perform the conversion judgment for the i-th path. If the conversion is completed, go to S7.4; if the conversion is not complete, repeat S7.3;

[0055] S7.4: Read the conversion result.

[0056] In some embodiments, as Figure 2 shown, the steps of the conversion judgment in S7.3 are as follows:

[0057] S7.3.1: Start and enter the "conversion completed" discrimination process;

[0058] S7.3.2: Assign 0 to c, where c is used for loop counting;

[0059] S7.3.3: Determine whether the value of c is less than M. If it is less than M, the next step is to execute S7.3.5; otherwise, the next step is to execute S7.3.4, where M is the counting threshold;

[0060] S7.3.4: Fault handling, and the next step is to execute S7.3.7;

[0061] S7.3.5: Determine whether the "A / D conversion completed signal indication" is in the completed state. If it is completed, the next step is to execute S7.3.7; otherwise, the next step is to execute S7.3.6:

[0062] S7.3.6: Increment i by 1, that is, increase the value of i by 1, and the next step is to execute S7.3.3;

[0063] S7.3.7: Assign 0 to c;

[0064] S7.3.8: Exit, and the "conversion completed" discrimination process is completed.

[0065] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention. The above is only the preferred implementation manner of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and variations can still be made, and these improvements and variations should also be regarded as the protection scope of the present invention.

Claims

1. A multi-cycle full-data A / D conversion sampling method, characterized in that The method includes the following steps: S1. The processor is started; S2: After assigning the i-th analog input signal to 0, the i-th analog input signal is selected and waited for the analog signal to be fully established; S3. Conversion is started; S4. The tasks of this cycle are started; S5. Determine whether i is less than N - 1. If it is less, go to step S6. If i is equal to N - 1, then assign 0 to i and then go to step 7; S6. i is incremented by 1; S7. The address selection of the (i + 1)-th analog input signal and the conversion judgment of the i-th are processed in parallel; S8. After starting the conversion of i + 1, other tasks of this cycle are performed; S9. After the tasks of this cycle are completed, return to step S4 for the next cycle. The steps of S7 are as follows: S7.1 The address of the (i + 1)-th analog input signal is selected; S7.2 Wait for holding; S7.3 The conversion judgment of the i-th is performed. If the conversion is completed, go to S7.

4. If the conversion is not complete, repeat S7.3; S7.4 The conversion result is read. The steps of the conversion judgment of S7.3 are as follows: S7.3.1 Start and enter the "conversion completed" discrimination process; S7.3.2 Assign 0 to c, and c is used for loop counting; S7.3.3 Judge whether the value of c is less than M. If it is less than M, the next step is to execute S7.3.

5. Otherwise, the next step is to execute S7.3.4, where M is the counting threshold value; S7.3.4 Fault handling, and the next step is to execute S7.3.7; S7.3.5 Whether the "A / D conversion completed signal indication" is in the completed state. If it is completed, the next step is to execute S7.3.

7. Otherwise, the next step is to execute S7.3.6: S7.3.6 i is incremented by 1, that is, the value of i is increased by 1, and the next step is to execute S7.3.3; S7.3.7 Assign 0 to c; S7.3.8 Exit, and the "conversion completed" discrimination process is completed.

2. The A / D conversion sampling method for multi-cycle full data according to claim 1, characterized in that The selection of the i-th analog input signal in S2 is performed through a multiplexer.

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