Printed circuit board compensation structure for high bandwidth and high die count memory stacking

Abstract

A circuit interconnect for a high bandwidth and high die count memory stack is disclosed. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multi-layer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multi-layer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.

Description

[0001] Cross-references to related applications and patents

[0002] This application is related to U.S. Patent 10,468,073 filed on December 29, 2017, U.S. Patent 10,637,533 filed on September 28, 2018, US Publication Application No. 20200098728A1 filed on September 26, 2018, U.S. Patent 10,643,676, and U.S. Patent 10,283,200 filed on March 8, 2017. Background Art

[0003] High-speed communication buses induce transmission line effects such as reflections. Multiple senders and receivers along the transmission path increase the locations where signals are reflected. Termination circuits such as on-die termination circuits (resistive / active) reduce the reflections encountered by high-speed signals along the transmission path.

[0004] High frequencies and high bandwidths are difficult to achieve on multi-point buses due to impedance mismatches and reflections, which degrade signal integrity. The impedances of the source / transmitter / driver, transmission line, and receiver may be mismatched. At each point of impedance mismatch, reflection effects may occur, causing signal energy to be dissipated as the signal becomes noisy. This degradation in signal quality may limit the achievable signal speed and bandwidth.

[0005] As memory die counts and memory interface speeds increase, the need to improve signal performance may also increase despite the addition of more potential reflective nodes along the transmission path. Therefore, there is a need to reduce impedance along the transmission path in a manner that simultaneously reduces reflections at the signaling nodes. In this way, signal speed and quality can be improved along high-speed communication buses used in memory devices and other electronic devices. Summary of the invention

[0006] The present disclosure relates to a circuit interconnect for implementing a printed circuit board signal compensation structure for high bandwidth and die count memory stacking. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.

[0007] The present disclosure further relates to a system implementing a printed circuit board signal compensation structure for high bandwidth and die count memory stacking. The system may include a multi-layer printed circuit board, a signal compensation structure, a memory controller, a die stack, and a communication bus. The signal compensation structure may be integrated with the multi-layer printed circuit board. The signal compensation structure may include a first signal trace coupled to a first signal source and two ground traces coupled to a ground source. The memory controller may be coupled to the multi-layer printed circuit board and may be configured to read data from a group of memory dies and write data to a group of memory dies. The die stack may be coupled to the multi-layer printed circuit board and may include a group of memory dies connected to each other by wire bonding. The communication bus may connect the group of memory dies to the memory controller by means of the signal compensation structure.

[0008] Finally, the present disclosure relates to a signal compensation structure for high bandwidth and die count memory stacking. The signal compensation structure may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may be coupled to a lower ground plane of a multilayer printed circuit board via a first ground via. The multilayer printed circuit board may include a substrate, a first layer, a second layer positioned above the first layer, a lower ground plane, and an upper ground plane. An insulating layer may separate the lower ground plane from the first layer, the first layer and the second layer, and the second layer and the upper ground plane. The first signal trace may be positioned adjacent to the first ground trace within the first layer and coupled to a signal source. The second ground trace may be coupled to the upper ground plane via a second ground via. The second signal trace may be positioned adjacent to the second ground trace within the second layer and may be coupled to the signal source via a source via connected to the first signal trace. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0010] Figure 1 A storage system 100 is shown according to one embodiment.

[0011] Figure 2 A storage device 200 according to one embodiment is shown.

[0012] Figure 3 A transverse cross-sectional view of a memory device 300 mounted to a multi-layer printed circuit board is shown.

[0013] Figure 4 A portion of a communication bus 306 is shown according to one embodiment.

[0014] Figure 5 A transverse cross-sectional view of a memory device 500 mounted to a multi-layer printed circuit board is shown according to one embodiment.

[0015] Figure 6 A die stack interconnect model 600 is shown according to one embodiment.

[0016] Figure 7 A die stack interconnect model 700 is shown according to one embodiment.

[0017] Figure 8 A die stack interconnect model 800 is shown according to one embodiment.

[0018] Fig. 9 A die stack interconnect model 900 is shown according to one embodiment.

[0019] Fig. 10A A transverse cross-sectional view of a transfer path 1000a is shown according to one embodiment.

[0020] Fig. 10B A transverse cross-sectional view of a transmission path 1000b including a transmission line and a signal compensation structure according to one embodiment is shown.

[0021] Fig.11A A cross-sectional view of a signal compensation structure 1100 a is shown according to one embodiment.

[0022] Fig. 11B A cross-sectional view of a signal compensation structure 1100b is shown according to one embodiment.

[0023] Fig. 11C A cross-sectional view of a signal compensation structure 1100c is shown according to one embodiment.

[0024] Fig.11D A cross-sectional view of a signal compensation structure 1100d is shown according to one embodiment.

[0025] Fig.11E A cross-sectional view of a signal compensation structure 1100 e is shown according to one embodiment.

[0026] Fig.11F A cross-sectional view of a signal compensation structure 1100f is shown according to one embodiment.

[0027] Fig.11G A cross-sectional view of a signal compensation structure 1100g is shown according to one embodiment.

[0028] Fig. 12A A top view of a signal trace 1200a is shown according to one embodiment.

[0029] Fig. 12B A top view of a ground trace 1200b is shown according to one embodiment.

[0030] Fig.13A graph illustrating the impedance of a signal compensation structure 1300 according to one embodiment.

[0031] Fig.14 is an example block diagram of a computing device 1400 that may incorporate certain embodiments. DETAILED DESCRIPTION

[0032] In order to improve signal speed and quality, several signal and ground trace configurations including signal compensation structures are disclosed herein. "Signal compensation structure" refers to a structure that is configured, designed, arranged, engineered, or programmed to compensate for impedance mismatch, reflection, characteristic impedance, parasitic capacitance, etc. in a transmission line or transmission path. "Trace" refers to a conductive structure configured to carry electrical signals between a transmitting component and a receiving component. The trace can be made of a variety of conductive materials. A common material for traces is copper. Traces may also be interchangeably referred to herein as stripline or microstrip.

[0033] "Signal trace" refers to a structure configured to conduct electronic signals between a sender / transmitter and a receiver. In one embodiment, the signal trace is bidirectional and is configured to conduct electronic signals between a sender / transmitter and a receiver when operating in one mode, and conduct electronic signals in the opposite direction from the receiver to the sender when operating in another mode. When the electronic signal is conducted in the opposite direction, the sender can become the receiver, and the receiver can become the sender. When the wavelength of the electronic signal frequency is within 10 times or less of the physical length of the transmission path, the electrical signal path can be regarded as a transmission line, where the wavelength of the signal is related to the speed of light (v) divided by the signal frequency (f). The transmission line system is managed with signal terminals and may have dependencies (e.g., signal reflections, characteristic impedance, inductance, timing delays, overshoot / undershoot, crosstalk interference, EMI radiation, etc.) relative to the transmission line itself or the transmission path containing the transmission line.

[0034] The signal trace may include one or more structures or active or passive electrical components along the length of the signal trace. In some embodiments, such structures or active or passive electrical components may be part of the signal trace. In some embodiments, the signal trace may include an implementation of a control line. The trace may act as a signal trace carrying a signal, or as a ground trace acting as a ground path structure.

[0035] A "ground trace" refers to a structure configured to conduct an electronic signal to a ground source (also referred to simply as a "ground"). A ground trace may include one or more structures or electrical components along the length of the ground trace. In certain embodiments, such structures or electrical components may be part of a ground trace.

[0036] Signal and ground traces may be configured within a multi-layer printed circuit board so that they physically run parallel to each other as they traverse the board. A single signal may be split across multiple traces in some embodiments to achieve a desired impedance, and desired transmission line behavior when operating in conjunction with adjacent ground traces and a ground plane. "Impedance" refers to a measure of the opposition a circuit presents to current flow when a voltage is applied.

[0037] Quantitatively, the impedance of a two-terminal circuit element is the ratio of the complex representation of the sinusoidal voltage between its terminals to the complex representation of the current flowing through the circuit. In general, the impedance depends on the frequency of the sinusoid. (Search Wikipedia.com for "impedance" on May 31, 2020. Modified. Accessed on June 2, 2020.)

[0038] The characteristic impedance (Zo) of a transmission line is the square root of the ratio of distributed inductance (henry / unit length) to distributed capacitance (farad / unit length), and the impedance of a transmission line is the real impedance in SI units of ohms. These configurations of layers and traces can form the signal compensation structures disclosed herein, and can achieve lower impedance transmission lines (e.g., less than 40 ohms) compared to conventional printed circuit board trace configurations that typically induce an impedance of about 50 ohms.

[0039] Figure 1 1 is a schematic block diagram illustrating one embodiment of a storage system 100 including a storage device according to the disclosed solution. The storage system 100 includes a storage device 200, a storage controller 104, a memory die 112, at least one host 102, a user application 106, a storage client 108, a data bus 116, a bus 114, and a network 110. The storage system 100 includes at least one storage device 200, which includes a storage controller 104 and one or more memory dies 112 connected via a bus 114.

[0040] A "storage controller" refers to any hardware, device, component, element, or circuit configured to manage data operations on a memory medium (non-volatile and / or volatile), and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, a memory controller is configured to store data on and / or read data from a memory medium (non-volatile and / or volatile), transfer data to / from a non-volatile memory device, and the like.

[0041] A "memory die" refers to a small piece of semiconductive material on which a given functional circuit is fabricated. Integrated circuits are typically produced in bulk on a single wafer of electronic grade silicon (EGS) or other semiconductors (e.g., GaAs) by processes such as photolithography. The wafer is cut (divided) into many pieces, each containing a copy of the circuit. Each of these pieces is called a die. (Search Wikipedia.com for "die (integrated circuit)" on October 9, 2019. Accessed on November 18, 2019.) In one embodiment, a memory die is a die containing functional circuits for operating as a memory medium and / or a memory array. The memory medium and / or the memory array may include one or more of a non-volatile memory medium and a volatile memory medium.

[0042] A "memory array" refers to a group of memory cells (also referred to as memory cells, volatile memory cells, or nonvolatile memory cells) organized into an array structure having rows and columns. A memory array is addressable using row and column identifiers.

[0043] In some embodiments, each memory device 200 may include two or more memory dies 112, such as flash memory, nano random access memory ("nano RAM or NRAM"), magnetoresistive RAM ("MRAM"), dynamic RAM ("DRAM"), phase change RAM ("PRAM"), etc. In other embodiments, the data storage device 200 may include other types of non-volatile and / or volatile data storage devices, such as dynamic RAM ("DRAM"), static RAM ("SRAM"), magnetic data storage devices, optical data storage devices, and / or other data storage technologies.

[0044] The storage device 200 may be a component within the host 102 as depicted herein, and may be connected using a data bus 116 such as a Peripheral Component Interconnect Express ("PCI-e") bus, a Serial Advanced Technology Attachment ("serial ATA") bus, etc. In another embodiment, the storage device 200 is external to the host 102 and connected to a Universal Serial Bus ("USB") connection, an Institute of Electrical and Electronics Engineers ("IEEE") 1394 bus ("FireWire"), etc. In other embodiments, the storage device 200 is connected to the host 102 using a Peripheral Component Interconnect ("PCI") Express bus using an external electrical or optical bus extension or bus networking solution such as InfiniBand or PCI Express Advanced Switching ("PCIe-AS").

[0045] In various embodiments, storage device 200 may be in the form of a dual in-line memory module ("DIMM"), a daughter card, or a micromodule. In another embodiment, storage device 200 is a component within a rack-mounted blade. In another embodiment, storage device 200 is contained within a package that is directly integrated onto a higher-level assembly (e.g., a motherboard, a laptop computer, a graphics processor). In another embodiment, individual components including storage device 200 are directly integrated onto a higher-level assembly without the need for an intermediate package. Figure 2 The storage device 200 is described in more detail.

[0046] In another embodiment, the data storage device 200 may be connected to the host 102 via a data network, rather than being directly connected to the host 102 as a DAS. For example, the data storage device 200 may include a storage area network ("SAN") storage device, a network attached storage ("NAS") device, a network share, etc. In one embodiment, the storage system 100 may include a data network, such as the Internet, a wide area network ("WAN"), a metropolitan area network ("MAN"), a local area network ("LAN"), a token ring, a wireless network, a fiber channel network, a SAN, a NAS, an ESCON, etc., or any combination of networks. The data network may also include a network from the IEEE802 family of network technologies, such as Ethernet, a token ring, Wi-Fi, Wi-Max, etc. The data network may include servers, switches, routers, cables, radio equipment, and other equipment for facilitating networking between the host 102 and the data storage device 200.

[0047] The storage system 100 includes at least one host 102 connected to a storage device 200. Multiple hosts 102 may be used and the host 102 may include: a server, a storage controller of a storage area network ("SAN"), a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, a router or a home appliance, a database or storage device, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, etc. In another embodiment, the host 102 may be a client and the storage device 200 may operate autonomously to service data requests sent from the host 102. In this embodiment, the host 102 and the storage device 200 may be connected using a computer network, a system bus, a direct attached storage (DAS), or other communication means suitable for connection between a computer and an autonomous storage device 200.

[0048] The depicted embodiment shows the user application 106 communicating with the storage client 108 (as part of the host 102). In one embodiment, the user application 106 is a software application that operates on or in conjunction with the storage client 108.

[0049] The storage clients 108 manage files and data and utilize the functions and features of the storage controller 104 and the associated memory die 112. Representative examples of storage clients include, but are not limited to, servers, file systems, operating systems, database management systems ("DBMS"), volume managers, and the like. The storage clients 108 communicate with the storage controller 104 within the storage device 200. In some embodiments, the storage clients 108 may include remote storage clients operating on the host 102 or otherwise accessible via the network 110. The storage clients may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0050] In one embodiment, the storage system 100 includes one or more clients connected to one or more hosts 102 via one or more computer networks 110. The host 102 may be a server, a storage controller of a SAN, a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, a router or a home appliance, a database or storage device, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, etc. The network 110 may include the Internet, a wide area network ("WAN"), a metropolitan area network ("MAN"), a local area network ("LAN"), a token ring, a wireless network, a fiber channel network, a SAN, a network attached storage ("NAS"), ESCON, etc., or any combination of networks. The network 110 may also include a network from the IEEE 802 family of network technologies, such as Ethernet, token ring, WiFi, WiMax, etc.

[0051] The network 110 may include servers, switches, routers, cables, radios, and other devices for facilitating networking of hosts 102 or hosts 102 and clients. In one embodiment, the storage system 100 includes multiple hosts 102 communicating as peers via the network 110. In another embodiment, the storage system 100 includes multiple storage devices 200 communicating as peers via the network 110. Those skilled in the art will recognize other computer networks including one or more computer networks and associated devices with single or redundant connections between one or more clients, or other computers with one or more storage devices 200 connected to one or more hosts. In one embodiment, the storage system 100 includes two or more storage devices 200 connected to a remote host 102 via the network 110 rather than directly connected to or integrated within a local host 102.

[0052] In one embodiment, storage client 108 communicates with storage controller 104 via a host interface including an input / output (I / O) interface. For example, storage device 200 may support the ATA interface standard maintained by the International Committee for Information Technology Standards ("INCITS"), the ATA Packet Interface ("ATAPI") standard, the Small Computer System Interface ("SCSI") standard, and / or the Fibre Channel standard.

[0053] In some embodiments, the storage medium of the memory device is divided into volumes or partitions. Each volume or partition may contain multiple sectors. Traditionally, a sector is 512 bytes of data. One or more sectors are organized into blocks (interchangeably referred to as blocks and data blocks in this article).

[0054] In one example embodiment, a data block contains eight sectors and the data block is 4KB. In some storage systems that interface with operating systems, data blocks are referred to as clusters. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, data blocks are simply referred to as blocks. A block or data block or cluster represents the smallest physical amount of storage space on a storage medium that is managed by a storage manager, such as a storage controller, storage system, storage unit, storage device, etc.

[0055] In some embodiments, the storage controller 104 may be configured to store data on one or more asymmetric write-once storage media, such as solid-state storage memory cells within the memory die 112. The memory die 112 may be partitioned into memory partitions (e.g., erase blocks) that may be erased as a group, in order to (among other things) take into account the asymmetric nature of the memory die 112. Thus, modifying a single data segment in-place may involve erasing the entire erase block including the data, and rewriting the modified data to the erase block along with the original unchanged data. This may result in inefficient write amplification, which may excessively wear out the memory die 112.

[0056] Therefore, in some embodiments, the storage controller 104 may be configured to write data offsite. As used herein, writing data "offsite" refers to writing data to a different media storage location, rather than overwriting the data "in place" (e.g., overwriting the original physical location of the data). Modifying data offsite can avoid write amplification because existing valid data on the erase block with the data to be modified does not have to be erased and re-copied. In addition, writing data offsite can remove erase from the latency path of many operations, including storage operations (e.g., erase latency is no longer part of the main path of write operations). Managing data blocks by the storage manager specifically includes addressing specific data blocks for read operations, write operations, or maintenance operations.

[0057] The block storage device may associate n blocks available for user data storage across the storage medium with logical addresses numbered from 0 to n. In some block storage devices, the logical addresses may range from 0 to n per volume or partition. In conventional block storage devices, the logical addresses are directly mapped to specific data blocks on the physical storage medium. In conventional block storage devices, each data block is mapped to a specific set of physical sectors on the physical storage medium. However, some storage devices do not directly or necessarily associate logical addresses with specific physical data blocks. These storage devices may emulate conventional block storage interfaces to maintain compatibility with block storage clients 108.

[0058] In one embodiment, the storage controller 104 provides a block I / O emulation layer that acts as a block device interface or API. In this embodiment, the storage client 108 communicates with the storage device via this block device interface. In one embodiment, the block I / O emulation layer receives commands and logical addresses from the storage client 108 according to this block device interface. Therefore, the block I / O emulation layer provides compatibility between the storage device and the block storage client 108.

[0059] In one embodiment, storage clients 108 communicate with storage controller 104 via a host interface including a direct interface. In this embodiment, storage devices directly exchange information specific to non-volatile storage devices. Storage devices using a direct interface can store data in memory die 112 using a variety of organizational structures including, but not limited to, blocks, sectors, pages, logical blocks, logical pages, erase blocks, logical erase blocks, ECC codewords, logical ECC codewords, or in any other format or structure that is conducive to the technical characteristics of the memory die 112.

[0060] The storage controller 104 receives logical addresses and commands from the storage clients 108 and performs corresponding operations relative to the memory die 112. The storage controller 104 may support block I / O emulation, direct interface, or both.

[0061] Figure 2 is a block diagram of an exemplary memory device 200. The memory device 200 may include a memory controller 104 and a memory array 218. Each memory die 112 in the memory array 218 may include a die controller 202, at least one non-volatile memory array 210 in the form of a three-dimensional array, and a read / write circuit 214.

[0062] "Die controller" refers to a set of circuits, circuitry, logic, or components configured to manage the operation of a die. In one embodiment, the die controller is an integrated circuit. In another embodiment, the die controller is a combination of discrete components. In another embodiment, the die controller is a combination of one or more integrated circuits and one or more discrete components.

[0063] The non-volatile memory array 210 can be addressed by word lines via row decoders 212 and by bit lines via column decoders 216. The read / write circuit 214 includes a plurality of sense blocks SB1, SB2, ..., SBp (sense circuitry) and allows memory cell pages to be read or programmed in parallel. In some embodiments, each memory cell across a row of a memory array together forms a physical page. A physical page may include memory cells for a single plane or for a single memory die along a row of a memory array. In one embodiment, a memory die includes a memory array consisting of two planes of equal size. In one embodiment, a physical page of one plane of a memory die includes four data blocks (e.g., 16KB). In one embodiment, a physical page of a memory die (also referred to as a "die page") includes two planes each having four data blocks (e.g., 32KB).

[0064] Commands and data are communicated between the host 102 and the memory controller 104 via the data bus 116 and between the memory controller 104 and the one or more memory dies 112 via the bus 114. The memory controller 104 may include a memory controller 104 that is configured to communicate with the host 102 and the memory controller 104. Figure 1 Describe the logic modules in more detail.

[0065] The non-volatile memory array 210 may be two-dimensional (2D—arranged in a single manufacturing plane) or three-dimensional (3D—arranged in multiple manufacturing planes). The non-volatile memory array 210 may include one or more memory cell arrays including a 3D array. In one embodiment, the non-volatile memory array 210 may include an integral three-dimensional memory structure (3D array) in which multiple memory levels are formed above (rather than in) a single substrate such as a wafer without an intermediate substrate. The non-volatile memory array 210 may include any type of non-volatile memory integrally formed in one or more physical levels of an array of memory cells having active regions disposed above a silicon substrate. The non-volatile memory array 210 may be in a non-volatile solid-state drive having circuitry associated with the operation of the memory cells (whether the associated circuitry is above or within the substrate).

[0066] A word line may include a segment of a layer containing memory cells disposed in a layer above a substrate.Multiple word lines may be formed on a single layer with the aid of trenches or other non-conductive isolation features.

[0067] The die controller 202 cooperates with the read / write circuits 214 to perform memory operations on the memory cells of the non-volatile memory array 210, and includes a state machine 204, an address decoder 206, and a power control 208. The state machine 204 provides chip-level control of memory operations.

[0068] Address decoder 206 provides an address interface between the address interface used by the host or memory controller 104 and the hardware addresses used by row decoder 212 and column decoder 216. Power control 208 controls the power and voltage supplied to various control lines during memory operations.

[0069] The power control 208 and / or the read / write circuit 214 may include drivers for word lines, source gate select (SGS) transistors, drain gate select (DGS) transistors, bit lines, substrate (in a 2D memory structure), charge pumps, and source lines. In some embodiments, the power control 208 may detect a sudden power failure and take preventive action. The power control 208 may include various first voltage generators (e.g., drivers) to generate the voltages described herein. In one approach, the sense block may include a bit line driver and a sense amplifier.

[0070] In some embodiments, some of the components may be combined. In various designs, in addition to the non-volatile memory array 210, one or more of the components (alone or in combination) may be considered to be at least one control circuit or storage controller configured to perform the techniques described herein. For example, the control circuit may include any one or combination of the following: die controller 202, state machine 204, address decoder 206, column decoder 216, power control 208, sense blocks SB1, SB2, ..., SBp, read / write circuit 214, storage controller 104, etc.

[0071] In one embodiment, host 102 is a computing device (e.g., laptop, desktop, smart phone, tablet, digital camera) including one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory) that stores processor-readable code (e.g., software) for programming storage controller 104 to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces and / or one or more input / output devices that communicate with the one or more processors, and other components well known in the art.

[0072] The associated circuitry is typically involved in the operation of the memory cell and used to communicate with the memory cell. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory cell to implement functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory cell and / or on a separate substrate. For example, a memory controller for memory read and write operations may be located on a separate memory controller chip and / or on the same substrate as the memory cell.

[0073] Those skilled in the art will recognize that the disclosed techniques and devices are not limited to the two- and three-dimensional exemplary structures described, but encompass all related memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0074] Figure 3 300 is shown at a high level. The storage controller 104 can be attached or coupled to a printed circuit board substrate 302. This can be achieved using pins 304 that protrude through the printed circuit board substrate 302. The pins 304 can be connected to signal traces that form a communication bus 306. "Pins" refer to conductive structures used to connect electrical components of semiconductor components and / or chips to bonding pads. Pins can include thin cylindrical structures that are often made of metal. In other embodiments, the pins can be implemented as spherical or hemispherical structures, also referred to as spheres.

[0075] The communication bus 306 may be an 8-bit bus as indicated and may extend through the printed circuit board substrate 302 by means of transmission lines, such as Figure 4 The signals of the communication bus 306 may be connected to the bonding pads 308 on the surface of the printed circuit board substrate 302. "Bond pads" refer to conductive structures used to connect traces and wire bonds or pins to achieve electrical connections.

[0076] Wire bonds 310 pass signals from printed circuit board substrate 302 to memory die 112, as shown. "Wire bonds" refer to electrical wires used for interconnection of integrated circuits, communication buses, and / or communication channels, often made of aluminum, alloyed aluminum, copper, silver, gold, or doped gold.

[0077] Once the control line 312 signal from the communication bus 306 is connected to the memory die 112, the control line 312 signal may be connected to an electrostatic discharge (ESD) protection circuit. The ESD protection circuit 314 may protect the circuitry within the memory die 112 from harmful electrostatic discharge. The ESD circuit may add a significant amount of parasitic capacitance that must be compensated by termination and / or printed circuit board (PCB) compensation structures.

[0078] In addition to the ESD protection circuit 314, the control line may also be connected to an electrical termination circuit 316 circuit. "Electrical termination" refers to the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This is to prevent the signal from reflecting at the end of the transmission line. Reflections at the end of an unterminated transmission line cause distortion, which can produce ambiguous digital signal levels and erroneous operation of digital systems. (Search Wikipedia.com for "electrical termination" on July 23, 2018. Modified. Accessed on June 5, 2020.)

[0079] There are two types of electrical terminations: passive or resistive terminations, and active terminations. A passive electrical termination is a circuit containing passive electrical components such as a resistor or a group of resistors connected in parallel. An active electrical termination is a circuit containing active electrical components such as a transistor or a group of transistors configured to perform electrical termination for an input signal.

[0080] The electrical termination circuit 316 may provide impedance matching to reduce signal reflections due to the signal traversing the pins 304, the printed circuit board substrate 302, the communication bus 306, the bonding pads 308, the wire bonds 310, and the ESD protection circuit 314. The electrical termination circuit 316 may improve the signal quality on the control line 312 by routing high frequency interference, signals that would otherwise be reflected, and reflected signal components to travel to ground.

[0081] The control line 312 signal may then be connected to a communication module 318, which may buffer, manipulate, or otherwise process the signal for use by the die controller 202, such as with respect to Figure 2 The die controller 202 may use control line 312 signals to send commands, data, and / or instructions to direct operations to the nonvolatile memory array 210 including storage operations such as writes and reads.

[0082] Figure 4 Show Figure 3 1. The communication bus 306 introduced in . The communication bus 306 can provide signaling between the storage controller 104 and the memory die 112 using eight parallel signal control lines 402 as shown in one embodiment. A "communication bus" refers to hardware, software, firmware, logic, control lines, and one or more associated communication protocols configured to enable a sender to send data to a receiver. A communication bus can include a data bus and / or a control bus. A communication bus can be implemented as a parallel communication bus or a serial communication bus. A communication bus can be implemented using a set of control lines (e.g., in a parallel communication bus).

[0083] The eight control lines 402 may carry signals from the memory controller 104 to the memory die 112 and may be referred to as transmission lines 404 etched or otherwise formed within the printed circuit board substrate 302. The control lines 402 may be referred to as transmission lines when the wavelength of the frequency of the electronic signal is within ten times or less of the physical length of the transmission path, where the wavelength of the signal is related to the speed of light (v) divided by the frequency of the signal (f). Each transmission line 404 may have a characteristic impedance that may vary based on the geometry of the traces used to form the transmission lines 404 and the materials used when constructing the traces, transmission lines, and / or printed circuit board substrate 302.

[0084] "Control line" refers to a structure, circuit, circuitry, and / or associated logic configured to carry current and / or voltage from a source to a destination. In some embodiments, analog voltages, currents, bias voltages, and / or digital signals supplied or drained via control lines are used to control switches, select gates, and / or other electrical components.

[0085] Certain control lines may have specific names based on which parts of the circuit they control or where they are coupled or connected to other circuits. Examples of named control lines include word lines, bit lines, source control lines, drain control lines, etc.

[0086] "Transmission line" or "electrical transmission line" refers to a specialized cable or other structure designed to conduct alternating current or oscillating signals or voltages at radio frequencies (about 20kHz-300GHz) or higher. The frequency of the signal is high enough that the wave nature of the signal must be considered. The purpose of transmission lines is, for example, to connect radio transmitters and receivers through their antennas (they are therefore called feeder lines or feeders), to distribute cable television signals, trunk lines that route calls between telephone switching centers, computer network connections, and high-speed computer data buses. (Search Wikipedia.com for "transmission line" and "radio frequency" on May 28, 2020. Modified. Accessed on June 4, 2020.)

[0087] The printed circuit board substrate 302 may be formed of alternating laminated layers of insulating dielectric substrates, metals, and insulating bonding materials. The insulating dielectric materials and their thickness contribute to parasitic capacitance and inductance effects between each signal trace and nearby traces and ground or power planes. These parasitic effects may also vary based on the frequency components of the signal.

[0088] "Printed circuit board" or "PCB" refers to a structure that mechanically supports and electrically connects electrical or electronic components using conductive tracks, traces, pads, and other features etched from one or more copper sheet layers laminated onto and / or between sheet layers of a non-conductive substrate. Components can be soldered to the PCB to connect them electrically and mechanically secure them to the PCB.

[0089] PCBs can be single-sided (one copper layer), double-sided (two copper layers on either side of a substrate layer), or multi-layer (outer and inner copper layers alternating with the layers of the substrate). Multi-layer PCBs allow for higher component density because circuit traces on the inner layers free up surface space between components. Multi-layer PCBs may contain two, three, four, or more copper planes (layers for traces). (Search Wikipedia.com for “printed circuit board” May 22, 2020. Modified. Accessed June 4, 2020.)

[0090] "Layer" refers to a group of planar materials in a multilayer structure such as a multilayer printed circuit board.

[0091] "Multilayer printed circuit board" refers to a printed circuit board or "PCB" that includes multiple layers of conductive and non-conductive materials. The layers of the multilayer printed circuit board can be configured to provide one or more of mechanical structural support and / or conductive structures (e.g., signal traces). The non-conductive layers of the multilayer printed circuit board may include insulating layers. The conductive layers of the multilayer printed circuit board may include patterned metals such as copper, aluminum, etc. The patterned structure of the conductive layer may be coated and / or clad with a non-conductive layer formed on top of the conductive layer.

[0092] In some embodiments, the lowermost layer of the multilayer printed circuit board may include a substrate. The number and type of layers of the multilayer printed circuit board may vary depending on the use case. In some embodiments, the multilayer printed circuit board includes 4, 6, 8, 10, 12, or 18 layers. In one embodiment, the multilayer printed circuit board includes a lower ground plane layer positioned adjacent to the substrate and an upper ground plane layer positioned above one or more intermediate layers adjacent to the lower ground plane layer.

[0093] The resistance, capacitance, and inductance effects experienced on the transmission line 404 can therefore be designed to achieve Figure 3 Reducing and matching the impedance of the transmission line 404 may improve signal quality by reducing reflections along the transmission line 404. This may allow for greater signal bandwidth and speed between the memory controller 104 and the memory die 112.

[0094] Various structures with different configurations of transmission lines 404 within the printed circuit board substrate 302 for achieving a desired impedance are referred to herein as signal compensation structures. In one embodiment, the communication bus includes a parallel bus with a set of transmission lines 404, each transmission line 404 including a signal compensation structure.

[0095] Figure 5 A memory device 500 is shown according to one embodiment. A memory controller 502 communicates with a memory die stack 506 via a communication bus 306. A "die stack" refers to a group of memory dies arranged such that each member of the group is positioned directly above or below another memory die or substrate.

[0096] The horizontal cross-section diagram shows a portion of a single transmission line 504 of the communication bus 306. The transmission line 504 travels from the memory controller 502 through the multi-layer printed circuit board 508 to a T-branch 510. A "T-branch" refers to a structure within a multi-layer printed circuit board that is connected to one or more signal traces to form a T-shaped structure and is configured to route signals upward to a die stack mounted on the top of the multi-layer printed circuit board and downward to a die stack mounted on the bottom of the multi-layer printed circuit board.

[0097] At T-branch 510, transmission line 504 splits to connect with upper bonding pad 512 and lower bonding pad 514. Memory controller 502 coupled to multilayer printed circuit board 508 in this manner can be configured to read from and write to one or more memory dies of die stack 506.

[0098] From the upper bonding pad 512, a wire bond 516 can carry the signal on the transmission line 504 from one memory die 520 in the upper die stack 522 to another memory die 520, as shown. From the lower bonding pad 514, a wire bond 518 can connect the transmission line 504 signal from one memory die 520 in the lower die stack 524 to another memory die 520. The path that the transmission line 504 signal traverses from the memory controller 502 to the last memory die 520 in the upper die stack 522 and the lower die stack 524 is referred to herein as a transmission path 526, where Figure 5 Indicated by dotted lines.

[0099] A "transmission path" refers to an electrical signal that travels through a circuit or a portion of a circuit. A transmission path may include a variety of electrical components and may include one or more connections to a ground source, a signal source, and / or a power source. In some embodiments, a transmission path may include a transmitter, a receiver, and one or more transmission lines. A transmission path may also be referred to as a 'main line'.

[0100] In the illustrated embodiment, transmission line 504 includes one or more signal compensation structures, such as signal compensation structure 528. In one embodiment, signal compensation structure 528 is integrated with multilayer printed circuit board 508. Signal compensation structure 528 may include a first signal trace connected to a first signal source and two ground traces connected to ground sources.

[0101] In another embodiment, the signal compensation structure 528 may include a first signal trace and a second signal trace, which may each be connected to a T-branch 510 connected to an upper bonding pad 512 and a lower bonding pad 514. The upper die stack 522 and the lower die stack 524 may each include more than four memory dies 520 in one embodiment. The first signal trace and the second signal trace may be coupled to a first signal source provided by the memory controller 502.

[0102] “Signal source” refers to a circuit, sub-circuit, electronic component, hardware, software, firmware, module, logic, device or equipment that is configured, programmed, designed, arranged or engineered to supply a time-varying voltage, current or electromagnetic wave in an analog or digital waveform to another structure, circuit, sub-circuit, electronic component, logic, device or equipment.

[0103] A "ground plane" refers to a conductive surface or plane that is typically connected to electrical ground. In a printed circuit board, the ground plane is a large area of ​​copper foil of the printed circuit board that is connected to the power supply ground terminal and serves as a return path for current from different components on the printed circuit board.

[0104] In a multilayer PCB, the ground plane can be a separate layer that covers the entire board. This serves to make circuit layout simpler, allowing the designer to ground any component without having to run additional traces; component leads that need to be grounded are routed directly through holes in the printed circuit board to a ground plane on another layer. Large areas of copper also conduct large return currents from many components without significant voltage drops, ensuring that the ground connections of all components are at the same reference potential. (Search Wikipedia.com for “ground plane” on March 31, 2020. Modified. Accessed on June 4, 2020.)

[0105] Figure 6 A die stack interconnect model 600 is shown. The memory controller introduced in the previous figures can be modeled as a variable voltage source 602, an impedance 604, and a parasitic capacitance 606. Figure 3 The transmission path 608 introduced in can be modeled as a transmission line 610 with a characteristic impedance 612 and a series of parasitic capacitances and inductances induced by the die stack interconnect.

[0106] Parasitic capacitance and inductance refer to the unavoidable and often undesirable capacitance and / or inductance present in transmission line components (e.g., vias and connectors) and / or with termination circuits (ESD and transceiver circuits). These unavoidable parasitic effects need to be accounted for by termination and / or PCB compensation components / circuits.

[0107] In the illustrated die stack interconnect model 600, parasitic capacitance 614 and inductance 616 represent the interconnect to the first memory die in the die stack. Parasitic capacitance 618 and inductance 620 represent the connection to the next memory die in the stack, etc. Inductance 622 and parasitic capacitance 624 represent the connection to the end memory die (i.e., the last memory die connected on the transmission path).

[0108] To more closely match the impedance of the transmission path 608 and reduce signal reflections along the path, an end die electrical terminal 626 may be provided on the memory die of the die stack that is farthest from the memory controller. The transmission path 608 impedance may be viewed as an aggregation of the elements along the transmission path 608, including the transmission line 610 characteristic impedance 612, parasitic capacitance, and inductance shown. The end die electrical terminal 626 may thus be configured to terminate the transmission line effects due to each of these components. The end die electrical terminal 626 may be implemented using a passive resistance circuit and / or an active resistance circuit.

[0109] Figure 7 A die stack interconnect model 700 is shown with active die electrical terminations 702. Figure 6In addition to the end die electrical terminal 626 introduced to offset transmission line effects along the entire transmission path 608, an active die electrical terminal 702 can also be provided to offset additional effects induced at a particular memory die when the memory die is in use (e.g., being read from, transmitting signals on a transmission line to a memory controller).

[0110] The active die electrical terminal 702 is often configurable so that it can be switched on or off. Thus, the active die electrical terminal 702 circuitry can be switched on to absorb reflections and other interference at the active memory die when the memory die is in use, but can be switched off when the memory die is not in use to save power and thus not induce additional reflections along the transmission path 608. The active die electrical terminal 702 shown is associated with a node representing the first memory die in the die stack (also characterized by parasitic capacitance 614 and inductance 616) to model the active die electrical terminal 702 when the first memory die is active. A similar structure with a similar relationship with parasitic capacitance 618 and inductance 620 can be modeled to model the active die electrical terminal 702 when the second memory die is active, and so on.

[0111] Figure 8 A die stack interconnect model 800 according to one embodiment is shown. A switch connection between a power supply Vccq and ground can be used to model a signal source provided to the die stack interconnect model 800. A source resistance Rs can be used to model the resistance encountered at the signal source. Rt can be used to model a terminal resistance implemented to reduce reflections along a transmission path.

[0112] In addition, a printed circuit board transmission line 802 having a characteristic impedance Zpcb (which may be implemented at least in part using a signal compensation structure) and a wire bond 804 having a characteristic impedance Zwb are shown. Typically, Zpcb is greater than Zwb. The impedance differences between the source (Rs), the printed circuit board transmission line 802 (Zpcb), the wire bond 804 (Zwb), and the terminal impedance (Rt) may each cause a reflected signal that may cause a weakening of a given signal, which may be expressed as an increased delay in the time it takes for a signal to travel from one end of the transmission path and return. Reducing these reflections by matching the impedances has the same effect as bringing the transmitter (e.g., a controller) closer to the receiver (e.g., a die stack), thereby reducing delays and improving signal speed and bandwidth.

[0113] The reflection coefficient γ can be used to express the extent to which a signal may be affected by reflection at an impedance mismatch point. The reflection coefficient is the ratio of the voltage or current of the reflected wave to the voltage or current of the incident wave or waves that pass the reflection point and continue along the transmission line. γ can also be expressed as a function of the characteristic impedance, as shown in the following equation.

[0114] For example, for the case where Zpcb is configured to match Rs, V1 will be equal to V2, and there will be no reflection, and no reduction in signal strength. In the case where Rt is configured to match Zwb, again, no reflection will occur. However, the mismatch between Zpcb and Zwb may result in reflections, which can be expressed as indicated in Equation 1.

[0115]

[0116] Implementing a signal compensation structure within the printed circuit board transmission line 802 can reduce Zpcb to match Zwb, or substantially match Zwb. In this case, the reflection coefficient Gamma wb The Zpcb signal compensation structure implemented on a multilayer printed circuit board characterized as a printed circuit board transmission line 802 may include a first signal trace coupled to a first signal source and two ground traces coupled to a ground source. A "ground source" refers to a structure or connection or component that acts as a ground or is used to ground an electrical signal.

[0117] A memory controller, represented here by a switching signal between power and ground, may be coupled to a multi-layer printed circuit board and configured to read data from and write data to a group of memory dies. These memory dies may include terminal characteristics modeled here as Rt. A die stack may be coupled to a multi-layer printed circuit board, including a group of memory dies connected to each other by one or more wire bonds 804 (represented here as having impedance Zwb). Signals configured to connect the memory dies to a communication bus of the memory controller via a signal compensation structure may induce minimal or no reflections, as described with respect to this figure.

[0118] Fig. 9 A die stack interconnect model 900 is shown according to one embodiment. A switching signal varying between Vccq and ground, a source resistance Rs, a wire bond 804 having a characteristic impedance Zwb, and a terminal resistor Rt may be similar to Figure 8 Those components introduced in .

[0119] Figure 8 A model of a transmission line comprising two sections is shown. The first section between the memory controller and the signal compensation structure may include a signal trace 902 and a ground trace. The signal trace 902 and the ground trace may include a conventional or ordinary signal trace and a ground trace. The signal trace 902 may be connected to a bonding pad for a pin of the memory controller. The signal trace 902 may also be connected from the memory controller to a source via (which is connected to a signal driver), a signal source. The ground trace corresponding to the signal trace 902 may be connected to a ground source or a ground via.

[0120] A "via" refers to a conductive structure configured to electrically connect a conductor on one level of a multi-layer metal stack to another conductor on another level of the multi-layer metal stack. Vias can be made of a variety of conductive materials. Often vias are made of tungsten and may be referred to as 'plugs' or 'contact plugs'.

[0121] A "source via" refers to a via configured to electrically connect a signal source or a structure that conducts a signal source to a signal trace. A "ground via" refers to a via configured to electrically connect a ground source (also referred to simply as a 'ground') or a structure that conducts an electrical signal to a ground source.

[0122] Signal trace 902 (and its corresponding ground trace) may be represented by signal trace 902 having a characteristic impedance Z reg (comparable to a conventional PCB signal trace).

[0123] The second section of the transmission line may include a signal compensation structure that connects the signal trace 902 to a bonding pad, a T-branch, a memory die pin, etc. The signal compensation structure may be a portion of the transmission path having a low characteristic impedance Z low represented by the signal compensation structure 904. The characteristic impedance Z low may be lower than the characteristic impedance Z reg of a conventional PCB signal trace (e.g., the signal trace 902).

[0124] The signal compensation structure 904 can be connected to the signal trace 902 and its corresponding ground trace using a variety of structures and / or configurations. How the signal compensation structure 904 is connected to the signal trace 902 and its corresponding ground trace depends in part on the configuration of the signal compensation structure 904. For example, the corresponding ground trace can be connected to one of an upper ground plane, a lower ground plane, and one of a plurality of ground vias. The signal trace 902 can be positioned within a first layer of a multilayer printed circuit board. The signal trace 902 can have a characteristic impedance of about 50 ohms in response to a signal source oscillating at a wavelength at a frequency within about ten times the physical length of the transmission path. For example, in one embodiment, the transmission path can be 90 millimeters or about 90 millimeters, and the frequency of the signal on the transmission path can be at or greater than 333 MHz.

[0125] The reflection coefficient (γ) at the impedance mismatch point is shown when Rs is configured to substantially match Z reg. The impedance match between the characteristic impedances shown can make the reflection coefficient at the junction zero, as described by the following equation.

[0126] Equation 2 shows the reflection coefficient (Gamma) at the transition region to the signal compensation structure 904. low ).

[0127]

[0128] Equation 3 shows the reflection coefficient (Gamma wb ).

[0129]

[0130] Equation 4 shows the reflection coefficient (Gamma t ).

[0131]

[0132] Because it may not be possible to match impedance across the entire transmission path, adjustments to the configuration that contributes to these reflection coefficients can allow the freedom needed to reduce reflections and effectively bring the memory controller electrically closer to the memory die.

[0133] Fig. 10A Transmission paths 1000a are shown to an upper die stack (only a single upper memory die is shown for simplicity) and a lower die stack (only a single lower memory die is shown for simplicity). The memory controller 502 may be coupled to a multilayer printed circuit board 508. The multilayer printed circuit board 508 may incorporate a transmission line 1002 configured to be approximately 3.5 inches long and having a characteristic impedance of 20 ohms. The transmission line 1002 is one of many transmission lines that form a communication bus. The transmission line 1002 may be primarily formed by a signal compensation structure 1004 that may traverse the multilayer printed circuit board 508 to a T-branch 510, wherein the signal compensation structure 1004 is split to travel a distance of approximately 1 mm to an upper bonding pad 512 and a distance of approximately 4 mm to a lower bonding pad 514. The bonding pads may be connected via a plurality of channels such as a PCB. Figure 3 The wire bonds introduced in are attached to the memory die 520. In the embodiment shown, the signal compensation structure 1004 can span all or most of the distance between the memory controller and the die stack.

[0134] Fig. 10B Transmission path 1000b is shown according to one embodiment, which includes a conventional signal trace configuration for a portion of transmission path 1000b and a signal compensation structure 1008 for the remainder of transmission path 1000b. Conventional signal traces may include signal traces 1006 connected between bond pads for pins of memory controller 502 and signal compensation structure 1008.

[0135] Transmission path 1000b may include a transition region 1010 or coupling that connects signal trace 1006 and signal compensation structure 1008. In one embodiment, transition region 1010 includes one or more vias that connect one or more traces and associated one or more ground traces of signal trace 1006 with appropriate traces or structures of signal compensation structure 1008. The vias connect traces or ground traces between different layers of multi-layer printed circuit board 508.

[0136] For example, in one embodiment, a signal trace in the signal traces 1006 may be connected to a signal trace of the signal compensation structure 1008 via a source via at the transition region 1010. A ground trace of the signal compensation structure 1008 may be connected to a ground plane directly or with the aid of a ground via. The signal trace 1006 may be positioned within a first layer of the multilayer printed circuit board 508. In response to a signal component consisting of a wavelength of a signal frequency within about ten times the physical length of the transmission path, the signal trace 1006 may include a characteristic impedance of about 50 ohms.

[0137] The signal trace 1006 may traverse the multi-layer printed circuit board 508 a distance of about 1.8 inches and have a typical characteristic impedance of 50 ohms. The signal compensation structure 1008 may traverse the multi-layer printed circuit board 508 a distance of about 1.7 inches, so that the signal trace 1006 and the signal compensation structure 1008 together traverse about 3.5 inches. The signal compensation structure 1008 may have a characteristic impedance as low as 20 ohms.

[0138] Fig. 10B For an example, see Fig. 9 , the characteristic impedance can be stepped down to alleviate signal reflection.

[0139] Fig.11A FIG. 1 is a cross-sectional view of a signal compensation structure 1100a according to one embodiment. The signal compensation structure 1100a is formed within a layer of a multilayer printed circuit board 508 ( Fig. 11B 100a). The signal compensation structure 1100a may include a lower ground plane 1102, an upper ground plane 1104, a pair of signal traces, and a pair of ground traces. An "upper ground plane" refers to a ground plane that is positioned above another ground plane in a multilayer printed circuit board. In some embodiments, the upper ground plane may be the topmost ground plane. A "lower ground plane" refers to a ground plane that is positioned below another ground plane in a multilayer printed circuit board. In some embodiments, the lower ground plane may be the bottommost ground plane and / or the final layer of the substrate adjacent to the lower ground plane. The ground plane provides a ground source and electromagnetic shielding to the signal traces.

[0140] The pair of signal traces (a first signal trace 1106 and a second signal trace 1108 each carrying the same signal SIG A) are positioned between the lower ground plane 1102 and the upper ground plane 1104 and are diagonally positioned relative to each other. The pair of ground traces (a first ground trace 1110 and a second ground trace 1112) are positioned between the lower ground plane 1102 and the upper ground plane 1104 and are diagonally positioned relative to each other, and are each adjacent to one of the first signal trace 1106 and the second signal trace 1108. In this configuration, the first signal trace 1106, the second signal trace 1108, the first ground trace 1110, and the second ground trace 1112 electromagnetically interact with each other and with the lower ground plane 1102 and the upper ground plane 1104 to reduce impedance along the signal compensation structure.

[0141] Fig. 11B A cross-sectional view of a signal compensation structure 1100b is shown that includes details of layers of a multi-layer printed circuit board 508 in one embodiment. The signal compensation structure 1100b is Fig.11A The physical features described with respect to this embodiment are not intended to limit the construction of similar configurations using different materials or arrangements of layers within a multi-layer printed circuit board.

[0142] Fig.11A The lower ground plane 1102, the first ground trace 1110, the first signal trace 1106, the second signal trace 1108, the second ground trace 1112, and the upper ground plane 1104 introduced in the embodiment of the present invention can be implemented in the layers of the multilayer printed circuit board as shown. The multilayer printed circuit board can include a substrate including a substrate layer 0 1114 and a plurality of alternating insulating layers and metal layers.

[0143] "Substrate" refers to a material that provides a surface on which something is deposited or etched (e.g., a silicon wafer used to make integrated circuits and or semiconductors). (Search lexico.com 2020Lexico.com, "Substrate". Edited. Accessed April 3, 2020. ) A substrate can be a rigid or flexible structure and can be planar in shape. Substrates can also be used in printed circuit boards (PCBs). Typically, substrates are non-conductive or semi-conductive and can be formed from a variety of materials including silicon, plastics, resins, fiberglass, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide (GaAs), alloys of silicon and germanium, indium phosphide (InP), and the like.

[0144] In certain embodiments, the substrate may comprise a silicon wafer, and in other embodiments, the substrate may comprise another layer of an integrated semiconductor, including but not limited to, a top surface of a unit film stack, or the like.

[0145] "Insulating layer" refers to a planar layer of material configured to provide electrical insulation between electrical components on either side of the insulating layer. In one embodiment, the insulating layer is made of a dielectric material such as plastic, epoxy, silicon, fiberglass, etc. In some embodiments, a substrate layer is used to provide electrical insulation. Therefore, insulating layer may be used interchangeably with substrate or substrate layer herein.

[0146] In the illustrated embodiment, the multilayer printed circuit board includes a metal layer 0 1116 including a lower ground plane 1102, an insulating layer 0 1118 to prevent metal-to-metal contact with a metal layer 1 1120. A substrate layer 1 1122 is located above the metal layer 1 1120. A metal layer 2 1124 is located above the substrate layer 1 1122. An insulating layer 1 1126 is located above the metal layer 2 1124. A substrate layer 2 1128 is located above the insulating layer 1 1126, and a metal layer 3 1130 is located above the substrate layer 2 1128. The metal layer 3 1130 may include an upper ground plane 1104. In some embodiments, the lower ground plane 1102 and / or the upper ground plane 1104 may be referred to as a ground plane layer. The metal layer 1 1120 may be referred to as a first layer, and the metal layer 2 1124 may be referred to as a second layer.

[0147] In other configurations, the substrate layer and the insulating layer may be incorporated in a different order, depending on the type of printed circuit boards that are laminated together to form the multilayer printed circuit board. In one embodiment, the layer separating metal layer 1 1120 and metal layer 2 1124 may be an insulating layer instead of substrate layer 1 1122 .

[0148] In one embodiment, a first signal trace 1106 carrying SIG A is formed in metal layer 1 1120 adjacent to a first ground trace 1110 also formed in metal layer 1 1120. In one embodiment, the first signal trace 1106 and the first ground trace 1110 are in the same layer of the multi-layer printed circuit board. A second signal trace 1108 also carrying SIG A is formed in metal layer 2 1124 adjacent to a second ground trace 1112 also formed in metal layer 2 1124. In one embodiment, the second signal trace 1108 and the second ground trace 1112 are in the same layer of the multi-layer printed circuit board. The first signal trace 1106, the second signal trace 1108, the first ground trace 1110, and / or the second ground trace 1112 may be formed by conventional manufacturing techniques including metal deposition, metal etching, etc.

[0149] In some embodiments, the first signal trace 1106 of the metal layer 1 1120 is positioned directly below the second ground trace 1112 of the metal layer 2 1124. In addition, the second signal trace 1108 is positioned directly above the first ground trace 1110. Advantageously, this configuration saves space and can enhance electromagnetic coupling between the first signal trace 1106, the second ground trace 1112, the first ground trace 1110, and / or the second signal trace 1108.

[0150] In one embodiment, the signal compensation structure 1100b includes one or more vias connecting traces such as signal traces and / or ground traces. Fig. 11B , the signal compensation structure 1100b may include at least one source via 1132 and / or at least one ground via (e.g., first ground via 1134, second ground via 1136). In the illustrated embodiment, the source via 1132 may provide electrical connection between the first signal trace 1106 and the second signal trace 1108 and a source signal provided by the memory controller. In one embodiment, the via may be wider, as shown, to accept a through-hole pin from the memory controller, such as Figure 3 The source via 1132 can be connected to the first signal trace 1106 and / or the second signal trace 1108 by means of a connector 1138, such as an angled connector (described more below).

[0151] First ground vias 1134 and second ground vias 1136 may be used to connect first ground traces 1110 and second ground traces 1112 to lower ground plane 1102 and / or upper ground plane 1104, and to connect lower ground plane 1102 and upper ground plane 1104 to each other, as shown. Lower ground plane 1102 and / or upper ground plane 1104 may be connected to a ground source. In one embodiment, first ground vias 1134 may connect first ground trace 1110 to lower ground plane 1102, and second ground vias 1136 may connect second ground trace 1112 to upper ground plane 1104. The ground vias may be connected to the ground traces using one or more connectors 1138.

[0152] Fig. 11C A signal compensation structure 1100c according to an embodiment is shown. A first ground trace 1110, a first signal trace 1106, a second signal trace 1108, and a second ground trace 1112 are arranged as shown in FIG. Fig.11A , Fig. 11B and Fig. 11C1140 and the second layer 1142 shown in FIG. The first ground trace 1110 is connected to the first ground via 1134, the first signal trace 1106 and the second signal trace 1108 are connected to the source via 1132, and the second ground trace 1112 can be connected to the second ground via 1136. The first signal trace 1106 and the second signal trace 1108 can both carry the same signal SIG A.

[0153] Embodiments of the signal compensation structure 1100c may further include two traces (third signal trace 1144 and fourth signal trace 1146) carrying SIG B, and a pair of ground traces (third ground trace 1148 and fourth ground trace 1152) each configured and positioned as shown. In certain embodiments, the first signal trace 1106 and the second signal trace 1108 carry SIG A for a first transmission line of the communication bus 306, and the third signal trace 1144 and the fourth signal trace 1146 carry SIG B for a second transmission line of the communication bus 306. In certain embodiments, the layout, pattern, and configuration of the signal compensation structure 1100c may be repeated for each transmission line of the communication bus 306.

[0154] Fig.11D A signal compensation structure 1100d according to another embodiment is shown. A first ground trace 1110 of the two ground traces is positioned within a first layer 1140 of a multilayer printed circuit board, and a first signal trace 1106 is positioned directly above the first ground trace 1110 in a second layer 1142. The second layer 1142 is adjacent to the first layer 1140. A second ground trace 1112 of the two ground traces is positioned directly above the first signal trace 1106 within a third layer 1156 of the multilayer printed circuit board. The third layer 1156 is adjacent to the second layer 1142. In this configuration, the first signal trace 1106 has the first ground trace 1110 below and the second ground trace 1112 above. The cross-sectional view of the embodiment of the signal compensation structure shown herein shows how the signal compensation structure can be configured with respect to the length of the signal compensation structure.

[0155] Fig.11E A signal compensation structure 1100e according to another embodiment is shown. A first signal trace 1106 of the signal compensation structure 1100e is positioned between two ground traces (ground trace 1160 and ground trace 1162) within a first layer 1140 of a multi-layer printed circuit board. In addition, a first ground trace 1110 is positioned directly above the first signal trace 1106 and within a second layer 1142. The second layer 1142 may be above and adjacent to the first layer 1140. The second ground trace 1112 may be positioned directly below the first signal trace 1106 and within another layer 1158, which is adjacent to and below the first layer 1140.

[0156] Fig.11F 1 shows a signal compensation structure 1100f according to one embodiment. The first ground trace 1110, the first signal trace 1106, the second signal trace 1108, and the second ground trace 1112 may be arranged above each other in four layers (e.g., the first layer 1140, the second layer 1142, the third layer 1156, and the fourth layer 1164). Fig.11G As shown in .

[0157] Fig.11G FIG. 1 shows a signal compensation structure 1100g according to one embodiment. Specifically, Fig.11G An embodiment of a signal compensation structure 1100f is shown in more detail. Fig.11F The traces indicated in may be arranged within a physical multi-layer printed circuit board as shown.

[0158] It should be noted that this configuration of printed circuit board material is not intended to limit the arrangement of metal layers and different types of insulating layers, provided that each metal layer is properly insulated and the physical dimensions produce the desired transmission line characteristics.

[0159] A first ground trace 1110 of the two ground traces is positioned within a first layer 1140 of the multi-layer printed circuit board. A first signal trace 1106 is positioned directly above the first ground trace 1110 in a second layer 1142 of the multi-layer printed circuit board. The second layer 1142 is adjacent to the first layer 1140.

[0160] The second signal trace 1108 is positioned directly above the first signal trace 1106 and within the third layer 1156, which is above and adjacent to the second layer 1142. The second of the two ground traces, the ground trace 1112, is positioned directly above the second signal trace 1108 within the fourth layer 1164 of the multi-layer printed circuit board. The fourth layer 1164 is adjacent to the third layer 1156.

[0161] The first signal trace 1106 and the second signal trace 1108 are connected to a source via 1132, which is connected to a common signal source such as a memory controller. Two ground traces can be connected to a first ground via 1134 connected to a lower ground plane, as shown. The ground vias can also be connected to an upper ground plane in some configurations, or separate vias can be used to connect one trace to the lower ground plane and one trace to the upper ground plane. This embodiment is not intended to limit the disclosure in terms of ground via placement.

[0162] Fig. 12AA top view of two signal traces 1200a is shown according to one embodiment. A first signal trace on a first layer 1206 of a printed circuit board 1210 can be routed to a source via to a signal source 1204 using an angled connector 1202. A second signal trace on a second layer 1208 (shown cross-hatched because the second layer can be below the first layer) can also be routed to a source via to a signal source 1204 (a common signal source) using an angled connector 1202.

[0163] An "angled connector" refers to a conductive structure that is configured to connect horizontally to a signal trace within a layer of a printed circuit board in order to connect the signal trace to a via or other structure.

[0164] Each angled connector 1202 can be configured to horizontally route traces within a layer of a multilayer printed circuit board to connect the traces to a via. This can allow a first signal trace on a first layer 1206 and a second signal trace on a second layer 1208 to be configured into a signal compensation structure without interrupting the straight routing of the traces.

[0165] Fig. 12B A top view of two ground traces 1200b is shown according to one embodiment. A first ground via to a ground plane 1212 can be connected to a first ground trace on a first layer 1216 of a printed circuit board 1210 via an angled connector 1202 as shown. A second ground trace on a second layer 1218 (shown cross-hatched because the second layer can be below the first layer) can also be connected to a second ground via to a ground plane 1214 via an angled connector 1202. When combined Fig. 12A When the signal trace 1200a introduced in is used, the signal and ground traces arranged in this manner can form a circuit having, for example, Fig.11A A cross-sectional signal compensation structure introduced in the signal compensation structure 1100a.

[0166] Fig.13 A graph showing the impedance of a signal compensation structure 1300 according to one embodiment. For example, a characteristic impedance of 50 ohms, which may be characteristic of a conventional printed circuit board trace, may produce a signal round trip time of 2.5 nanoseconds or more from a memory controller to a memory die and back. Reducing the impedance of the transmission line through the use of a signal compensation structure so as to better match the impedance along the entire transmission path may shorten the round trip time as shown. For example, when the impedance is reduced to about 20 ohms, the round trip time may drop to 1.5 nanoseconds, representing a significant improvement. In this way, the improved impedance matching may be viewed as effectively reducing the distance that the signal travels.

[0167] In one embodiment, the first signal source may oscillate at a frequency having a wavelength within about ten times the physical length of the transmission path, and the circuit interconnect (which may include or contain an embodiment of the signal compensation structure described herein) may have a characteristic impedance of about 20 ohms. In one embodiment of the claimed solution, in response to the signal source oscillating at a frequency having a wavelength within about ten times the physical length of the transmission path, the signal compensation structure may include a characteristic impedance of less than 40 ohms. In another embodiment, a signal compensation structure used in a transmission path may include a characteristic impedance of 20 ohms.

[0168] Fig.14 is an example block diagram of a computing device 1400 that may incorporate an embodiment of the solution. Fig.14 Only machine systems that implement aspects of the technical processes described herein are shown and do not limit the scope of the claims. A person of ordinary skill in the art will recognize other variations, modifications, and alternatives. In some embodiments, computing device 1400 includes data processing system 1402, communication network 1418, communication network interface 1414, input device 1410, output device 1408, etc.

[0169] like Fig.14 , data processing system 1402 may include one or more processors 1406 and a storage subsystem 1404. Examples of processors may include, but are not limited to, a central processing unit, a general purpose processor, a special purpose processor, a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SoC), a virtual processor, a processor core, etc.

[0170] Processor 1406 communicates with a number of peripheral devices via bus subsystem 1422. These peripheral devices may include input devices 1410, output devices 1408, communication network interface 1414, and storage subsystem 1404. In one embodiment, storage subsystem 1404 includes one or more storage devices and / or one or more memory devices.

[0171] In one embodiment, storage subsystem 1404 includes volatile memory 1412 and non-volatile memory 1416. Volatile memory 1412 and / or non-volatile memory 1416 may store computer executable instructions that, alone or together, form logic 1420 that, when applied to and executed by processor 1406, implement embodiments of the processes disclosed herein.

[0172] Input devices 1410 include devices and mechanisms for inputting information into data processing system 1402. These may include keyboards, keypads, touch screens incorporated into a graphical user interface, audio input devices such as voice recognition systems, microphones, and other types of input devices. In various embodiments, input device 1410 may be embodied as a computer mouse, trackball, trackpad, joystick, wireless remote control, drawing tablet, voice command system, eye tracking system, etc. Input device 1410 typically allows a user to select objects, icons, control areas, text, and the like that appear on a graphical user interface via commands such as clicking buttons or the like.

[0173] Output devices 1408 include devices and mechanisms for outputting information from data processing system 1402. These may include graphical user interfaces, speakers, printers, infrared LEDs, etc., also as understood in the art. In some embodiments, the graphical user interface is coupled directly to bus subsystem 1422 by means of a wired connection. In other embodiments, the graphical user interface is coupled to data processing system 1402 by means of communication network interface 1414. For example, the graphical user interface may include a command line interface on a separate computing device 1400, such as a desktop computer, server, or mobile device.

[0174] The communication network interface 1414 provides an interface to a communication network (e.g., communication network 1418) and devices external to the data processing system 1402. The communication network interface 1414 can serve as an interface for receiving data from other systems and transmitting data to other systems. Embodiments of the communication network interface 1414 can include an Ethernet interface, a modem (telephone, satellite, cable, ISDN), a (asynchronous) digital subscriber line (DSL), FireWire, USB, a wireless communication interface such as Bluetooth or WiFi, a near field communication wireless interface, a cellular interface, etc.

[0175] The communication network interface 1414 may be coupled to the communication network 1418 via an antenna, cable, etc. In some embodiments, the communication network interface 1414 may be physically integrated on a circuit board of the data processing system 1402, or in some cases may be implemented in software or firmware (e.g., a "soft modem" or the like).

[0176] Computing device 1400 may include logic that allows communication over a network using protocols such as HTTP, TCP / IP, RTP / RTSP, IPX, UDP, etc.

[0177] The volatile memory 1412 and the non-volatile memory 1416 are examples of tangible media configured to store computer-readable data and instructions to implement various embodiments of the processes described herein. Other types of tangible media include removable memory (e.g., pluggable USB memory devices, mobile device SIM cards), optical storage media, semiconductor memory such as flash memory, non-transitory read-only memory (ROM), battery-backed volatile memory, networked storage devices, etc. The volatile memory 1412 and the non-volatile memory 1416 can be configured to store basic programming and data structures that provide the functionality of the disclosed processes and other embodiments thereof that fall within the scope of the present disclosure.

[0178] Logic 1420 implementing one or more portions of an embodiment of the solution may be stored in volatile memory 1412 and / or non-volatile memory 1416. Logic 1420 may be read from volatile memory 1412 and / or non-volatile memory 1416 and executed by processor 1406. Volatile memory 1412 and non-volatile memory 1416 may also provide repositories for storing data used by logic 1420.

[0179] The volatile memory 1412 and non-volatile memory 1416 may include several memories, including a main random access memory (RAM) for storing instructions and data during program execution and a read-only memory (ROM) in which read-only non-transitory instructions are stored. The volatile memory 1412 and non-volatile memory 1416 may include a file storage subsystem that provides permanent (non-volatile) storage for program and data files. The volatile memory 1412 and non-volatile memory 1416 may include a removable storage system, such as a removable flash memory.

[0180] Bus subsystem 1422 provides a mechanism for enabling the various components and subsystems of data processing system 1402 to communicate with each other as needed. Although communication network interface 1414 is schematically depicted as a single bus, some embodiments of bus subsystem 1422 may utilize multiple distinct busses.

[0181] Those of ordinary skill in the art will readily appreciate that computing device 1400 may be a device such as a smart phone, a desktop computer, a laptop computer, a rack-mounted computer system, a computer server, or a tablet computer device. As is generally known in the art, computing device 1400 may be implemented as a series of multiple networked computing devices. In addition, computing device 1400 will typically include operating system logic (not shown), the type and nature of which are well known in the art.

[0182] Terms used herein should have the ordinary meaning in the relevant art or be consistent with the meaning indicated by their usage in context, but if an explicit definition is provided, that meaning shall prevail.

[0183] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. The expression "entity" configured to "perform one or more tasks" is used herein to refer to a structure (i.e., a physical object such as an electronic circuit). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be referred to as "configured to" perform a task even if the structure is not currently being operated. "Credit allocation circuitry configured to allocate credits to multiple processor cores" is intended to cover, for example, an integrated circuit having a circuit system that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., not connected to a power source). Therefore, an entity described or recited as "configured to" perform a task refers to a physical object, such as a device, a circuit, a memory storing program instructions that can be executed to implement a task, etc. This phrase is not used herein to refer to an intangible object.

[0184] The term “configured to” does not mean “configurable to.” For example, although an unprogrammed FPGA “can be configured to” perform a particular function after being programmed, the unprogrammed FPGA would not be considered to be “configured to” perform that function.

[0185] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on specified factors or based on specified factors and other unspecified factors. Consider the phrase "determining A based on B." This phrase specifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover embodiments in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0186] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect may be responsive to only those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." This phrase specifies B as the factor that triggers the performance of A. This phrase does not exclude that A may also be performed in response to some other factor, such as C. This phrase is also intended to cover embodiments in which A is performed only in response to B.

[0187] As used herein, unless otherwise stated, the terms "first," "second," and the like are used as labels for the nouns that follow them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, in a register file having eight registers, the terms "first register" and "second register" may be used to refer to any two of the eight registers, rather than, for example, referring only to logical registers 0 and 1.

[0188] When used in the claims, the term "or" is used as an inclusive or rather than an exclusive or. For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, and any combination thereof.

Claims

1. A circuit interconnect, comprising: a first ground trace within a first layer of the multi-layer printed circuit board; a first signal trace positioned within the first layer adjacent to the first ground trace; a second ground trace within a second layer of the multi-layer printed circuit board, wherein the second ground trace is vertically aligned with the first signal trace; a second signal trace adjacent to the second ground trace within the second layer, wherein the second signal trace is vertically aligned with the first ground trace; a first source via connecting the first signal trace and the second signal trace to a first signal source; and a first ground via connecting the first ground trace to a ground source; and A second ground via connects the second ground trace to the ground source, wherein the first source via is located between the first ground via and the second ground via.

2. The circuit interconnect of claim 1 , further comprising: a third ground trace connected to the second ground via and positioned within the second layer and adjacent to the second signal trace; a third signal trace connected to the second source via and positioned within the first layer and adjacent to the first ground trace; a fourth ground trace connected to the third ground via and positioned within the first layer and adjacent to the third signal trace; as well as A fourth signal trace connected to the second source via and positioned within the second layer and adjacent to the third ground trace, the second source via being connected to a second signal source.

3. The circuit interconnect of claim 1 further comprising a third signal trace connected to the first source via and a bond pad for a pin of a memory controller, and a third ground trace connected to the ground source and one of the first ground vias.

4. A circuit interconnect according to claim 1, wherein the first signal trace, the second signal trace, the first ground trace and the second ground trace each include an angled connector; and wherein each angled connector is configured to route the trace horizontally within a layer of the multilayer printed circuit board so as to connect the trace to a through hole.

5. The circuit interconnect of claim 1 , wherein the first signal trace and the second signal trace are connected to a T-branch connected to an upper bonding pad and a lower bonding pad, the upper bonding pad being configured to connect to an upper die stack by means of a first wire bond, and the lower bonding pad being configured to connect to a lower die stack by means of a second wire bond.

6. The circuit interconnect of claim 1, wherein a component of the first signal trace has a wavelength within approximately ten times a physical length of a transmission path including the circuit interconnect, and the circuit interconnect has a characteristic impedance of 20 ohms.

7. The circuit interconnect of claim 1, wherein the multilayer printed circuit board includes a ground plane layer connected to the first ground via and an insulating layer separating the first layer from the second layer.

8. A system comprising: Multilayer printed circuit boards; A signal compensation structure integrated with the multi-layer printed circuit board, the signal compensation structure comprising a first signal trace coupled to a first signal source, a second signal trace and two ground traces coupled to a ground source, wherein: A first of the two ground traces is positioned within a first layer of the multilayer printed circuit board; the first signal trace being positioned within the first layer adjacent to the first ground trace; A second of the two ground traces is positioned within the second layer and directly above the first signal trace; and the second signal trace being positioned within the second layer and being positioned directly above the first ground trace; a memory controller coupled to the multi-layer printed circuit board and configured to read data from and write data to a group of memory dies; a die stack coupled to the multi-layer printed circuit board, the die stack comprising the set of memory dies connected to each other by bond wires; and A communication bus is configured to connect the set of memory dies to the memory controller via the signal compensation structure.

9. The system of claim 8, wherein the communication bus comprises a parallel bus including a set of transmission lines, each transmission line including a signal compensation structure.

10. The system of claim 8, wherein the signal compensation structure comprises: a third signal trace positioned within the first layer and adjacent to the first ground trace; a third ground trace positioned within the second layer and adjacent to the second signal trace, the third ground trace positioned directly above the third signal trace; a fourth ground trace positioned within the first layer and adjacent to the third signal trace; a fourth signal trace positioned within the second layer and adjacent to the third ground trace, the fourth signal trace positioned directly above the fourth ground trace; and The first signal trace and the second signal trace are connected to the first signal source, and the third signal trace and the fourth signal trace are connected to a second signal source that is separate and different from the first signal source.

11. A system comprising Multilayer printed circuit boards; A signal compensation structure integrated with the multi-layer printed circuit board, the signal compensation structure comprising a first signal trace coupled to a first signal source and two ground traces coupled to ground sources, wherein: A first ground trace of the two ground traces is positioned in a first layer of the multi-layer printed circuit board, and the first signal trace is positioned directly above the first ground trace in a second layer of the multi-layer printed circuit board, the second layer being adjacent to the first layer; and a second ground trace of the two ground traces is positioned directly above the first signal trace in a third layer of the multi-layer printed circuit board, the third layer being adjacent to the second layer; a memory controller coupled to the multi-layer printed circuit board and configured to read data from and write data to a group of memory dies; a die stack coupled to the multi-layer printed circuit board, the die stack comprising the set of memory dies connected to each other by bond wires; and A communication bus is configured to connect the set of memory dies to the memory controller via the signal compensation structure.

12. A system comprising: Multilayer printed circuit boards; A signal compensation structure integrated with the multi-layer printed circuit board, the signal compensation structure comprising a first signal trace coupled to a first signal source and two ground traces coupled to ground sources, wherein: The first signal trace is positioned between the two ground traces within a first layer of the multi-layer printed circuit board; A first ground trace of the two ground traces is positioned directly above the first signal trace and within a second layer, the second layer being above and adjacent to the first layer; a second of the two ground traces being positioned directly below the first signal trace and within a third layer, the third layer being below and adjacent to the first layer; a memory controller coupled to the multi-layer printed circuit board and configured to read data from and write data to a group of memory dies; a die stack coupled to the multi-layer printed circuit board, the die stack comprising the set of memory dies connected to each other by bond wires; and A communication bus is configured to connect the set of memory dies to the memory controller via the signal compensation structure.

13. A system comprising: Multilayer printed circuit boards; a signal compensation structure integrated with the multi-layer printed circuit board, the signal compensation structure comprising a first signal trace coupled to a first signal source, a second signal trace and two ground traces coupled to a ground source, wherein: a first ground trace of the two ground traces is positioned within a first layer of the multi-layer printed circuit board; the first signal trace being positioned directly above the first ground trace in a second layer of the multi-layer printed circuit board, the second layer being adjacent to the first layer; the second signal trace being positioned directly above the first signal trace and within a third layer, the third layer being above and adjacent to the second layer; A second ground trace of the two ground traces is positioned directly above the second signal trace in a fourth layer of the multi-layer printed circuit board, the fourth layer being adjacent to the third layer; and The first signal trace and the second signal trace are connected to a source via connected to a common signal source; a memory controller coupled to the multi-layer printed circuit board and configured to read data from and write data to a group of memory dies; a die stack coupled to the multi-layer printed circuit board, the die stack comprising the set of memory dies connected to each other by bond wires; and A communication bus is configured to connect the set of memory dies to the memory controller via the signal compensation structure.

14. A signal compensation structure, comprising: a first ground trace coupled to a lower ground plane of a multi-layer printed circuit board through a first ground via, the multi-layer printed circuit board comprising a substrate, a first layer, a second layer, the lower ground plane, and an upper ground plane, the multi-layer printed circuit board further comprising an insulating layer between each of: the lower ground plane and the first layer, the first layer and the second layer, and the second layer and the upper ground plane; a first signal trace adjacent to the first ground trace within the first layer and coupled to a signal source; a second ground trace coupled to the upper ground plane through a second ground via; a second signal trace adjacent to the second ground trace within the second layer and coupled to the signal source through a source via connected to the first signal trace, wherein: the source via being positioned between the first ground via and the second ground via; The second layer is positioned above the first layer; The first signal trace and the second signal trace are connected to a T-branch connected to an upper bonding pad and a lower bonding pad, the upper bonding pad being configured to connect to an upper die stack by means of a first wire bond and the lower bonding pad being configured to connect to a lower die stack by means of a second wire bond; and The upper die stack includes more than four memory dies and the lower die stack includes more than four memory dies.

15. A signal compensation structure, comprising: a first ground trace coupled to a lower ground plane of a multi-layer printed circuit board through a first ground via, the multi-layer printed circuit board comprising a substrate, a first layer, a second layer, the lower ground plane, and an upper ground plane, the multi-layer printed circuit board further comprising an insulating layer between each of: the lower ground plane and the first layer, the first layer and the second layer, and the second layer and the upper ground plane; a first signal trace adjacent to the first ground trace within the first layer and coupled to a signal source; a second ground trace coupled to the upper ground plane through a second ground via; a second signal trace adjacent to the second ground trace within the second layer and coupled to the signal source through a source via connected to the first signal trace, wherein: the source via being positioned between the first ground via and the second ground via; The second layer is positioned above the first layer; The signal compensation structure is part of a transmission path, and the signal compensation structure is configured to connect to a third signal trace and a third ground trace, the third signal trace connected to the source via and a bonding pad for a pin of a memory controller, the third ground trace connected to one of the upper ground plane, the lower ground plane, and one of the first ground via and the second ground via; and The third ground trace is positioned within the first layer of the multilayer printed circuit board and, in response to a component of the signal source having a signal frequency wavelength within approximately ten times the physical length of the transmission path, the third signal trace comprises a characteristic impedance of approximately 50 ohms.

16. A signal compensation structure, comprising: a first ground trace coupled to a lower ground plane of a multi-layer printed circuit board through a first ground via, the multi-layer printed circuit board comprising a substrate, a first layer, a second layer, the lower ground plane, and an upper ground plane, the multi-layer printed circuit board further comprising an insulating layer between each of: the lower ground plane and the first layer, the first layer and the second layer, and the second layer and the upper ground plane; a first signal trace adjacent to the first ground trace within the first layer and coupled to a signal source; a second ground trace coupled to the upper ground plane through a second ground via; a second signal trace adjacent to the second ground trace within the second layer and coupled to the signal source through a source via connected to the first signal trace, wherein: the source via being positioned between the first ground via and the second ground via; The second layer is positioned above the first layer; In response to a component of the signal source having a signal frequency wavelength within approximately ten times a physical length of a transmission path, the signal compensation structure includes a characteristic impedance of less than 40 ohms.

17. The signal compensation structure of claim 16, wherein the signal compensation structure comprises a characteristic impedance of 20 ohms.

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