Amplification device

Abstract

The amplification device includes a semiconductor chip, a package, a first feedback circuit, and a second feedback circuit. The package has a metal base, insulating sidewalls, input leads, and output leads. The input leads are connected to the gate pads of the semiconductor chip. The output leads are connected to the drain pads of the semiconductor chip. Each feedback circuit has a dielectric substrate mounted on the metal base, a feedback resistor mounted on the dielectric substrate, and a capacitor connected in series with the feedback resistor. Each feedback circuit is connected between the gate pads and the drain pads. The feedback circuits are respectively disposed on the bases of one side and the other side of the semiconductor chip in the extension direction of the first and second terminals.

Description

Technical Field

[0001] This disclosure relates to amplification devices.

[0002] This application claims priority based on Japanese Application No. 2019-098593, filed on May 27, 2019, and incorporates all the contents described in the aforementioned Japanese application. Background Technology

[0003] Patent Document 1 describes a technology related to a broadband amplifier. This broadband amplifier includes a signal amplification transistor. A matching circuit composed of an inductor and a matching circuit composed of a capacitor are connected to the input and output sides of the signal amplification transistor, respectively. Furthermore, a parallel feedback circuit including a resistor and a capacitor is connected between the dividing point of the divided input matching circuit and the dividing point of the divided output matching circuit. By having such a structure, the broadband amplifier described in Patent Document 1 aims to reduce the gain reduction in the high-frequency region and expand the bandwidth of the amplifier.

[0004] Patent Document 2 describes technology related to a microwave amplifier. This microwave amplifier has an amplifying element and a feedback circuit. The amplifying element has an input terminal and an output terminal, and the feedback circuit feeds back a portion of the output to the output terminal side of the amplifying element to the input terminal side. The feedback circuit is formed above or below the surface where the amplifying element is located. Alternatively, the feedback circuit is formed through an inner region sandwiched between two grounded locations grounded by the ground terminal of the amplifying element. The microwave amplifier described in Patent Document 2 attempts to shorten the length of the feedback circuit and improve its characteristics.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 5-315865

[0008] Patent Document 2: Japanese Patent Application Publication No. 6-037559 Summary of the Invention

[0009] The amplification device disclosed herein includes a semiconductor chip, a package, a first feedback circuit, and a second feedback circuit. The semiconductor chip includes a semiconductor substrate, multiple transistors, a gate pad group, a drain pad group, and a source pad group. The semiconductor substrate has a first end edge and a second end edge opposite to each other. Each transistor has a source electrode, a gate electrode, and a drain electrode on the semiconductor substrate. The gate pad group includes multiple gate pads disposed along the first end edge on the semiconductor substrate and connected to the respective gate electrodes of the multiple transistors. The drain pad group includes multiple drain pads disposed along the second end edge on the semiconductor substrate and connected to the respective drain electrodes of the multiple transistors. The source pad group includes multiple source pads connected to the respective source electrodes of the multiple transistors. The package includes a metal base that bonds to the bottom surface of the semiconductor chip, insulating sidewalls surrounding the semiconductor chip, input leads connected to the gate pad group and extending from the inside to the outside of the sidewalls, and output leads connected to the drain pad group and extending from the inside to the outside of the sidewalls. The first feedback circuit and the second feedback circuit each have a dielectric substrate disposed on a metal base, a feedback resistor disposed on the dielectric substrate, and a capacitor connected in series with the feedback resistor. The first feedback circuit and the second feedback circuit are electrically connected between a gate pad group and a drain pad group. The first feedback circuit is disposed on a base on one side of the semiconductor chip in the extension direction of the first and second ends. The second feedback circuit is disposed on a base on the other side of the semiconductor chip in the extension direction. Attached Figure Description

[0010] Figure 1 This is a top view showing the structure of an enlarged device according to one embodiment of the present disclosure.

[0011] Figure 2 It is a top view that is magnified and represents a semiconductor chip.

[0012] Figure 3 This is a diagram showing the semiconductor chip and feedback circuit as viewed from the front wall.

[0013] Figure 4 This is the circuit diagram of the amplification device.

[0014] Figure 5 This is a top view of the enlarged device in the first modified example.

[0015] Figure 6 This is a top view of the enlarged device in the second variation. Detailed Implementation

[0016] [The problem this disclosure aims to solve]

[0017] In recent years, there has been a demand for semiconductor amplification devices capable of handling high frequencies and wide bandwidths. Wide bandwidth here refers to a frequency band, for example, covering the LF (Low Frequency) band from tens to hundreds of kHz to the RF (Radio Frequency) band from several GHz. For such wide bandwidths, one method to improve the amplification characteristics of transistors is to implement feedback from the drain to the gate (see, for example, Patent Documents 1 and 2). Since the signals at the gate and drain of the transistor are 180° out of phase, the circuit implementing feedback from the drain to the gate is called a negative feedback circuit. Furthermore, according to the rule that the gain-bandwidth product (GB product) is constant, the bandwidth increase corresponds to the gain decrease. The feedback circuit is, for example, constructed from a series circuit of a resistor and a capacitor.

[0018] On the other hand, recent years have seen a demand for high-frequency transistors capable of handling larger currents. Consequently, transistor sizes have gradually increased, with structures featuring dozens of gate fingers becoming increasingly practical. In such large transistors, the wiring paths of the feedback circuit connecting the gate and drain become longer, and the inductance of these wirings induces disturbances in the transistor's frequency characteristics.

[0019] Therefore, the purpose of this disclosure is to provide an amplification device that can shorten the wiring path of the feedback circuit and suppress the disturbance of the frequency characteristics of the transistor.

[0020] [The Effects of This Disclosure]

[0021] According to this disclosure, an amplification device is provided that can shorten the wiring path of the feedback circuit and suppress disturbances in the frequency characteristics of the transistor.

[0022] [Description of embodiments of this disclosure]

[0023] First, embodiments of the present disclosure will be described. One embodiment of the amplification device includes a semiconductor chip, a package, a first feedback circuit, and a second feedback circuit. The semiconductor chip includes a semiconductor substrate, a plurality of transistors, a group of gate pads, a group of drain pads, and a group of source pads. The semiconductor substrate has a first end edge and a second end edge opposite to each other. Each transistor has a source electrode, a gate electrode, and a drain electrode on the semiconductor substrate. The group of gate pads includes a plurality of gate pads disposed along the first end edge on the semiconductor substrate and connected to the respective gate electrodes of the plurality of transistors. The group of drain pads includes a plurality of drain pads disposed along the second end edge on the semiconductor substrate and connected to the respective drain electrodes of the plurality of transistors. The group of source pads includes a plurality of source pads connected to the respective source electrodes of the plurality of transistors. The package includes a metal base for bonding the bottom surface of a semiconductor chip, insulating sidewalls surrounding the semiconductor chip, an input lead connected to a gate pad assembly and extending from the inside to the outside of the sidewalls, and an output lead connected to a drain pad assembly and extending from the inside to the outside of the sidewalls. A first feedback circuit and a second feedback circuit include a dielectric substrate disposed on the metal base, a feedback resistor disposed on the dielectric substrate, and a capacitor connected in series with the feedback resistor. The first feedback circuit and the second feedback circuit are electrically connected between the gate pad assembly and the drain pad assembly. The first feedback circuit is disposed on the base on one side of the semiconductor chip in the extension direction of the first and second ends. The second feedback circuit is disposed on the base on the other side of the semiconductor chip in the extension direction.

[0024] In this amplification device, a first feedback circuit and a second feedback circuit are arranged side-by-side with the semiconductor chip on a substrate mounted within the package. Therefore, compared to, for example, arranging the feedback circuit outside the package, the wiring path of the feedback circuit can be shortened. Thus, according to this amplification device, frequency characteristic disturbances of the transistors in the semiconductor chip can be effectively suppressed. Furthermore, in this amplification device, at least two feedback circuits are provided: the first feedback circuit is located on one side of the semiconductor chip in the extension direction of the first and second edges of the semiconductor substrate, and the second feedback circuit is located on the other side of the semiconductor chip in the same extension direction. In this case, compared to arranging the feedback circuit only on one side of the semiconductor chip, characteristic deviations caused by variations in the distances between the gate and drain pads and the feedback circuit can be reduced.

[0025] In the aforementioned amplification device, the resistance values ​​of the feedback resistor in the first feedback circuit and the feedback resistor in the second feedback circuit can also be equal. In this case, giving the first and second feedback circuits equal characteristics can more effectively suppress the frequency characteristic disturbances of the individual transistors in the semiconductor chip.

[0026] In the aforementioned amplification device, the capacitors in the first and second feedback circuits can also be die capacitors located on the output leads. In this case, the capacitors can be easily configured within a narrow package.

[0027] In the aforementioned amplification device, the dielectric substrate may be fixed to a base via a metal-containing adhesive, and the first and second feedback circuits may have an input-side capacitor that serves as an input capacitor electrically connected between the gate pad group and the feedback resistor, and an output-side capacitor that serves as an output capacitor electrically connected between the drain pad group and the feedback resistor. In most cases, the gate bias is negative. If the metal-containing adhesive, such as silver paste, used to fix the dielectric substrate and the base is ionized due to moisture, these metal ions will climb up the negative potential wiring on the dielectric substrate. This is called ion migration. As described above, if input-side and output-side capacitors are provided, the bias voltage is cut off between these capacitors, resulting in an unstable potential. Therefore, ion migration can be suppressed.

[0028] In the aforementioned amplification device, it is also possible to use a sintered metal paste containing a metal binder.

[0029] In the aforementioned amplification device, the semiconductor chip may further include: a first auxiliary pad disposed on one side of the gate pad group in the extending direction of the first and second ends of the semiconductor substrate; and a second auxiliary pad disposed on the other side of the gate pad group in the extending direction. Furthermore, the first feedback circuit may be electrically connected to the gate pad group via the first auxiliary pad, and the second feedback circuit may be electrically connected to the gate pad group via the second auxiliary pad. In this case, the first and second feedback circuits can be easily connected to the gate pad group.

[0030] In the aforementioned amplification device, the feedback resistors of the first and second feedback circuits can also be thin-film resistors formed on the main surface of the dielectric substrate. In this case, the feedback resistors can be easily implemented.

[0031] In the aforementioned amplification device, the dielectric substrate may be thicker than the semiconductor substrate. In this case, the parasitic capacitance generated between the wiring of the feedback circuit on the dielectric substrate and the base can be suppressed to a smaller extent.

[0032] In the aforementioned amplification device, the feedback resistors of the first and second feedback circuits may have multiple bonding pads arranged in the extending direction of the feedback resistors. In this case, by using bonding wires to short-circuit any of the bonding pads, the resistance value of the feedback resistor can be easily adjusted to any value.

[0033] In the aforementioned amplification device, the sidewalls of the package may include a front wall portion and a rear wall portion that are opposite to each other in a direction that intersects the extending directions of the first and second end edges of the semiconductor substrate, with the input lead extending from the inside to the outside of the front wall portion and the output lead extending from the inside to the outside of the rear wall portion.

[0034] In the aforementioned amplification device, the dielectric substrates of the first and second feedback circuits may also have a rectangular planar shape with the extension directions of the first and second ends of the semiconductor substrate as the short side directions. In this case, by bringing one end of the dielectric substrate close to the input lead and the other end of the dielectric substrate close to the output lead to shorten the bonding line, the inductance of the bonding line can be reduced.

[0035] In the aforementioned amplification device, the feedback resistors of the first and second feedback circuits can also be bent and extended multiple times from one end to the other along the length of the dielectric substrate. In this case, the feedback resistors can be lengthened to become even higher resistances.

[0036] In the aforementioned amplification device, the dielectric substrates of the first feedback circuit and the second feedback circuit may also be made of ceramic.

[0037] In the aforementioned amplification device, the capacitance value of the capacitor in the first feedback circuit may also be equal to the capacitance value of the capacitor in the second feedback circuit.

[0038] [Details of the embodiments disclosed herein]

[0039] Specific examples of the amplification device of this disclosure will now be described with reference to the accompanying drawings. Furthermore, the invention is not limited to these examples, but is defined by the claims and is intended to include all modifications within the same meaning and scope as the claims. In the following description, the same reference numerals are used to denote the same elements in the description of the drawings, and repeated descriptions are omitted.

[0040] Figure 1 This is a top view showing the structure of an amplification device according to one embodiment of the present disclosure. The amplification device 1A includes a semiconductor chip 10, a package 20, a first feedback circuit 30A, and a second feedback circuit 40A. The semiconductor chip 10 is formed by incorporating multiple transistors having source electrodes, gate electrodes, and drain electrodes on a semiconductor substrate. The transistors constituting the semiconductor chip 10 are, for example, FETs with a gate width of 6 mm, and in one example, high electron mobility transistors (HEMTs) primarily comprising GaN-based semiconductors. The maximum output of the semiconductor chip 10 is, for example, 30 W.

[0041] Figure 2This is an enlarged top view of the semiconductor chip 10. The semiconductor chip 10 includes a semiconductor substrate 11, a gate pad group 12, a drain pad group 13, a first auxiliary pad 14, a second auxiliary pad 15, and a source pad group 16 disposed on the main surface of the semiconductor substrate 11. The semiconductor substrate 11 has a rectangular planar shape with direction D1 as its length direction. The semiconductor substrate 11 has a pair of end edges 11a and 11b extending along direction D1 and facing each other in a direction intersecting direction D1. End edge 11a is an example of the first end edge in this embodiment. End edge 11b is an example of the second end edge in this embodiment. The semiconductor substrate 11 also has a side edge 11c that connects one end of end edges 11a and 11b to each other and extends in a direction intersecting direction D1, and a side edge 11d that connects the other end of end edges 11a and 11b to each other and extends in a direction intersecting direction D1.

[0042] The gate pad group 12 includes a plurality of gate pads 12a connected to the respective gate electrodes of a plurality of transistors. The plurality of gate pads 12a are metal films, such as Au films, formed on a semiconductor substrate 11. The plurality of gate pads 12a are arranged on the semiconductor substrate 11 along one of a pair of end edges 11a, 11b, for example, end edge 11a. Furthermore, four gate pads 12a are shown as an example in the figure, but the number of gate pads 12a can be any number of two or more. Each gate pad 12a is electrically connected to one or more (e.g., six) gate electrodes, i.e., gate fingers, disposed on an active region of the semiconductor substrate 11. Figure 1 As shown, each gate pad 12a is electrically connected to the input lead 23 of the package 20 (described later) via bonding line 51. Furthermore, the contact width between each gate electrode and the semiconductor, i.e., the unit gate width, is, for example, 200 μm.

[0043] The drain pad group 13 includes multiple drain pads 13a connected to the drain electrodes of the respective transistors. The multiple drain pads 13a are metal films, such as Au films, formed on the semiconductor substrate 11. The multiple drain pads 13a are arranged on the semiconductor substrate 11 along the other of a pair of ends 11a, 11b, for example, end 11b. The number of drain pads 13a is, for example, the same as the number of gate pads 12a. Each drain pad 13a is electrically connected to two or more drain electrodes (not shown) disposed on the active region of the semiconductor substrate 11. Figure 1 As shown, each drain pad 13a is electrically connected to the output lead 24 of the package 20 (described later) via bonding wire 52.

[0044] The auxiliary pad 14 is a metal film, such as an Au film, formed on the semiconductor substrate 11. The auxiliary pad 14 is disposed in a region on the semiconductor substrate 11 on one side of the gate pad group 12 in direction D1, specifically the region between the gate pad group 12 and the side edge 11c. The auxiliary pad 14 is electrically connected to a portion of the gate pads 12a included in the gate pad group 12 via wiring disposed on the semiconductor substrate 11. Figure 1 As shown, the auxiliary pad 14 is electrically connected to the feedback circuit 30A via the bonding line 53.

[0045] The auxiliary pad 15 is a metal film, such as an Au film, formed on the semiconductor substrate 11. The auxiliary pad 15 is disposed in the region on the semiconductor substrate 11 on the other side of the gate pad group 12 in direction D1, i.e., the region between the gate pad group 12 and the side edge 11d. The auxiliary pad 15 is electrically connected to the remaining gate pads 12a included in the gate pad group 12 via wiring disposed on the semiconductor substrate 11. Figure 1 As shown, the auxiliary pad 15 is electrically connected to the feedback circuit 40A via the bonding line 54.

[0046] The source pad group 16 includes multiple source pads 16a connected to the source electrodes of the respective transistors. The multiple source pads 16a are metal films, such as Au films, formed on the semiconductor substrate 11. The multiple source pads 16a are arranged alternately on the semiconductor substrate 11 along one of a pair of end edges 11a, 11b, for example, end edge 11a and gate pad 12a. Each source pad 16a is electrically connected to two or more source electrodes (not shown), i.e., source fingers, disposed on the active region of the semiconductor substrate 11. Each source pad 16a is electrically connected to a back electrode film (not shown) of the semiconductor chip 10 via a through-hole penetrating the semiconductor substrate 11.

[0047] Furthermore, one or more gate fingers connected to a gate pad 12a and source and drain fingers sandwiching these gate fingers constitute a transistor unit. Figure 2 The diagram shows a semiconductor chip 10 containing four transistor units, but the number of transistor units is arbitrary. For example, in the case where the semiconductor chip 10 contains eight transistor units, the entire width of the semiconductor chip 10 in the direction D1, which is the arrangement direction of the transistor units, is also, for example, 6 mm.

[0048] Refer again Figure 1The package 20 has a base 21, sidewalls 22, input leads 23, and output leads 24. The base 21 is a plate-shaped component made of metal. At both ends of the base 21 in direction D1, a pair of semi-circular recesses 21b and 21c are formed for fixing the amplification device 1A by threaded fastening. The base 21 has a flat main surface 21a. At the center of the main surface 21a in direction D1, the bottom surface, i.e., the back electrode film of the semiconductor chip 10, is electrically bonded via a metal-containing adhesive. The metal-containing adhesive is, for example, a sintered metal paste, and in one example, silver paste. The conductive bonding between the semiconductor chip 10 and the base 21 is performed, for example, by applying the metal paste to the main surface 21a of the base 21, placing the semiconductor chip 10 on the metal paste, and then subjecting it to heat treatment to evaporate the resin contained in the metal paste. In most cases, the base 21 is defined as the reference potential, i.e., the GND potential. Therefore, the source electrode of the semiconductor chip 10 is defined as the reference potential through the back electrode film and the via.

[0049] The sidewall 22 is an insulating component surrounding the semiconductor chip 10. The sidewall 22 is erected on the main surface 21a of the base 21. In this embodiment, the sidewall 22 has a generally rectangular frame shape with direction D1 as its length. Specifically, the sidewall 22 includes a front wall portion 22a, a rear wall portion 22b, a sidewall portion 22c, and a sidewall portion 22d. The front wall portion 22a and the rear wall portion 22b extend along direction D1 and are opposite to each other in a direction intersecting direction D1. The sidewall portion 22c connects one end of each of the front wall portion 22a and the rear wall portion 22b. The sidewall portion 22d connects the other end of each of the front wall portion 22a and the rear wall portion 22b. The distance between the semiconductor chip 10 and the front wall portion 22a is smaller than the distance between the semiconductor chip 10 and the rear wall portion 22b. The sidewall 22 is, for example, made of ceramic. A cover (not shown) is joined to the upper surface of the sidewall 22, thereby sealing the inside of the sidewall 22 in an airtight manner.

[0050] The input lead 23 is a plate-shaped component made of metal. The input lead 23 penetrates the front wall portion 22a, extending from the inside to the outside of the front wall portion 22a. The upper surface of the input lead 23 is exposed on both the inside and outside of the front wall portion 22a. The upper surface of the input lead 23 on the inside of the front wall portion 22a is electrically connected to multiple gate pads 12a via multiple bonding wires 51. In one example, one bonding wire 51 is connected to one gate pad 12a. The portion of the input lead 23 located on the outside of the front wall portion 22a is electrically connected to external wiring of the amplifier device 1A.

[0051] Output lead 24 is a plate-shaped component made of the same metal as input lead 23. Output lead 24 penetrates the rear wall portion 22b, extending from the inside to the outside of the rear wall portion 22b. The upper surface of output lead 24 protrudes from the rear wall portion 22b on both the inside and outside sides. The upper surface of output lead 24 on the inside side of the rear wall portion 22b is electrically connected to multiple drain pads 13a via multiple bonding wires 52. In one example, two bonding wires 52 are connected to one drain pad 13a. The portion of output lead 24 located on the outside side of the rear wall portion 22b is electrically connected to external wiring of the amplification device 1A.

[0052] Feedback circuit 30A is disposed on a region of base 21 on one side of semiconductor chip 10 in direction D1. Feedback circuit 30A includes a dielectric substrate 31, a feedback resistor 32, and a capacitor 33. Feedback circuit 40A is disposed on a region of base 21 on the other side of semiconductor chip 10 in direction D1. Feedback circuit 40A includes a dielectric substrate 41, a feedback resistor 42, and a capacitor 43. One end of feedback circuits 30A and 40A is electrically connected to gate pad group 12 via auxiliary pads 14 and 15, respectively. The other end of feedback circuits 30A and 40A is electrically connected to output lead 24.

[0053] The dielectric substrates 31 and 41 have a rectangular planar shape with direction D1 as the short side. The dielectric substrates 31 and 41 are made of ceramic such as Al2O3, for example. Figure 3 This is a diagram showing the semiconductor chip 10 and feedback circuits 30A and 40A as viewed from the front wall portion 22a. (See diagram for reference.) Figure 3 As shown, the dielectric substrates 31 and 41 are thicker than the semiconductor substrate 11. In one example, the thickness of the dielectric substrates 31 and 41 is about 250 μm, and the thickness of the semiconductor substrate 11 is about 100 μm.

[0054] The dielectric substrate 31 has a front surface 31a and a back surface 31b facing each other. Similarly, the dielectric substrate 41 has a front surface 41a and a back surface 41b facing each other. The back surfaces 31b and 41b of the dielectric substrates 31 and 41 face the front surface 21a of the substrate 21 and are bonded to the front surface 21a via a metal-containing adhesive. The metal-containing adhesive is, for example, a sintered metal paste, and in one example, a silver paste. The bonding method between the dielectric substrates 31 and 41 and the substrate 21 is the same as the bonding method between the semiconductor chip 10 and the substrate 21. That is, a sintered metal paste is applied to the front surface 21a of the substrate 21, the dielectric substrates 31 and 41 are placed on the metal paste, and the resin contained in the metal paste is evaporated by heat treatment. The bonding between the dielectric substrates 31 and 41 and the substrate 21 can also be performed simultaneously with the bonding between the semiconductor chip 10 and the substrate 21.

[0055] A feedback resistor 32 is disposed on a dielectric substrate 31 and extends along the length of the dielectric substrate 31. The feedback resistor 32 is, for example, a thin-film resistor formed on the main surface 31a of the dielectric substrate 31, and in one example, is made of NiCr. The resistance value of the feedback resistor 32 is, for example, 300Ω. Wire bonding pads 34 and 35 are provided at both ends of the feedback resistor 32 on the main surface 31a. One end of the aforementioned bonding line 53 is connected to one pad 34, and the pad 34 is electrically connected to the auxiliary pad 14 via the bonding line 53. Thus, the DC potential of the feedback resistor 32 is defined as the gate bias voltage. The gate bias voltage is, for example, -2.8V. The other pad 35 is electrically connected to one electrode of the capacitor 33 via the bonding line 55.

[0056] Feedback resistor 42 is disposed on dielectric substrate 41 and extends along the length of dielectric substrate 41. Like feedback resistor 32, feedback resistor 42 is, for example, a thin-film resistor formed on the main surface 41a of dielectric substrate 41, and in one example, is made of NiCr. The resistance value of feedback resistor 42 is, for example, equal to the resistance value of feedback resistor 32. Wire bonding pads 44 and 45 are provided at both ends of feedback resistor 42 on the main surface 41a. One end of the aforementioned bonding line 54 is connected to one pad 44, and pad 44 is electrically connected to auxiliary pad 15 via bonding line 54. Thus, the DC potential of feedback resistor 42 is defined as the gate bias voltage. The other pad 45 is electrically connected to one electrode of capacitor 43 via bonding line 56.

[0057] Capacitor 33 is connected in series with feedback resistor 32 between output lead 24 and auxiliary pad 14 on the inner side of sidewall 22. In this embodiment, capacitor 33 is a die capacitor disposed on output lead 24 on the inner side of sidewall 22. The electrode of capacitor 33 opposite to the electrode connected to bonding line 55 is electrically bonded to output lead 24. Similarly, capacitor 43 is connected in series with feedback resistor 42 between output lead 24 and auxiliary pad 15 on the inner side of sidewall 22. In this embodiment, capacitor 43 is a die capacitor disposed on output lead 24 on the inner side of sidewall 22. The electrode of capacitor 43 opposite to the electrode connected to bonding line 56 is electrically bonded to output lead 24. The capacitance of capacitor 43 is equal to the capacitance of capacitor 33. The capacitance values ​​of capacitors 33 and 43 are substantially short-circuited in the GHz band to LF band, for example, 20pF.

[0058] In the above example, one end of each of the feedback circuits 30A and 40A is connected to the gate pad group 12 via auxiliary pads 14 and 15, respectively. However, this is not a limitation; one end of each of the feedback circuits 30A and 40A may also be directly connected to the gate pad group 12 via bonding wires or the like, without using auxiliary pads 14 and 15. Furthermore, in the above example, the other end of each of the feedback circuits 30A and 40A is connected to the drain pad group 13 via output lead 24. However, this is not a limitation; the other end of each of the feedback circuits 30A and 40A may also be directly connected to the drain pad group 13 via bonding wires or the like, without using output lead 24.

[0059] The effects obtained by the amplification device 1A of this embodiment as described above will be explained. Figure 4 This is a circuit diagram of the amplification device 1A according to this embodiment. In this embodiment, in order to improve the amplification characteristics of the semiconductor chip 10 over a wide bandwidth, feedback is applied from the drain to the gate of the semiconductor chip 10 through feedback circuits 30A and 40A. Since the signals at the gate and drain of the semiconductor chip 10 are 180° out of phase, the circuit that applies feedback from the drain to the gate is a negative feedback circuit. Moreover, according to the rule that the gain-bandwidth product (GB product) is constant, the bandwidth expansion corresponds to the gain reduction. Furthermore, the feedback mainly depends on the feedback resistors 32 and 42, and the capacitors 33 and 43 are provided to cut off the DC component. The capacitance values ​​of the capacitors 33 and 43 are set to values ​​that can be considered as short-circuited in the frequency band where the feedback is applied.

[0060] On the other hand, high-frequency transistors in recent years have been required to handle larger currents. Therefore, semiconductor chips are becoming increasingly larger, and structures with dozens of gate fingers, as in this embodiment, are becoming practical. In amplifiers with such large semiconductor chips, as in the past, when a feedback circuit is connected outside the package 20 between the input lead 23 and the output lead 24, the wiring path of the feedback circuit becomes longer, and the inductance of the wiring induces disturbances in the frequency characteristics of the transistor.

[0061] In the amplification device 1A of this embodiment, feedback circuits 30A and 40A are arranged side-by-side with the semiconductor chip 10 on the base 21 on which the semiconductor chip 10 is mounted within the package 20. Therefore, compared to the case where the feedback circuit is arranged outside the package 20, the wiring path of the feedback circuit can be shortened. Therefore, according to this amplification device 1A, the frequency characteristics of each transistor in the semiconductor chip 10 can be effectively suppressed.

[0062] Furthermore, when the feedback circuit is only located on one side of the semiconductor chip 10, the more gate pads 12a arranged in direction D1, the more deviations occur in the distance between each gate pad 12a and the feedback circuit, depending on the position of each gate pad 12a. Similarly, the more drain pads 13a arranged in direction D1, the more deviations occur in the distance between each drain pad 13a and the feedback circuit, depending on the position of each drain pad 13a. The wiring connecting each gate pad 12a and the feedback circuit, and the wiring connecting each drain pad 13a and the feedback circuit, have inductance corresponding to their length. Therefore, these distance deviations become deviations in the feedback effect, and thus become the main cause of characteristic deviations of the transistors included in the semiconductor chip 10. Especially in the frequency region exceeding several GHz, the influence of wiring inductance on the feedback effect becomes greater, and significant disturbances in the frequency characteristics of the transistors become apparent.

[0063] In contrast, in this embodiment, two feedback circuits 30A and 40A are provided. One feedback circuit 30A is provided on one side of the semiconductor chip 10 in direction D1, and the other feedback circuit 40A is provided on the other side of the semiconductor chip 10 in direction D1. In this case, compared with the case where the feedback circuit is only provided on one side of the semiconductor chip 10, the deviation in distance between the feedback circuit and each gate pad 12a and the deviation in distance between the feedback circuit and each drain pad 13a can be reduced, and the characteristic deviation of each transistor caused by these distance deviations can be reduced. In addition, compared with the case where the feedback circuit is only provided on one side of the semiconductor chip 10, the average length of the wiring connecting the feedback circuit and the semiconductor chip 10 can be shortened, thus further reducing the influence of wiring inductance on the feedback effect.

[0064] As described above, the resistance value of the feedback resistor 32 in feedback circuit 30A and the resistance value of the feedback resistor 42 in feedback circuit 40A can also be equal to each other. In this case, by giving feedback circuits 30A and 40A equal characteristics, the frequency characteristics of each transistor in semiconductor chip 10 can be suppressed more effectively.

[0065] As described above, the capacitors 33 and 43 in the feedback circuits 30A and 40A can also be die capacitors disposed on the output lead 24. In this case, the capacitors 33 and 43 can be easily arranged within the narrow package 20. In addition, there is no need for the connection wires connecting the capacitors 33 and 43 to the output lead 24, which can reduce the wiring inductance.

[0066] As described above, the semiconductor chip 10 may also have auxiliary pads 14 on one side of the gate pad group 12 in direction D1 and auxiliary pads 15 on the other side of the gate pad group 12 in direction D1. Furthermore, the feedback circuit 30A may be connected to the gate pad group 12 via the auxiliary pad 14, and the feedback circuit 40A may be connected to the gate pad group 12 via the auxiliary pad 15. In this case, the feedback circuits 30A and 40A can be easily connected to the gate pad group 12.

[0067] As described above, the feedback resistor 32 of the feedback circuit 30A can also be a thin-film resistor formed on the main surface 31a of the dielectric substrate 31. Similarly, the feedback resistor 42 of the feedback circuit 40A can also be a thin-film resistor formed on the main surface 41a of the dielectric substrate 41. In these cases, the feedback resistors 32 and 42 can be easily implemented.

[0068] As described above, the feedback resistor 32 of the feedback circuit 30A can also be provided on the dielectric substrate 31. Similarly, the feedback resistor 42 of the feedback circuit 40A can also be provided on the dielectric substrate 41. In this case, the parasitic capacitance generated between the wiring of the feedback circuit 30A on the dielectric substrate 31 and the base 21, and the parasitic capacitance generated between the wiring of the feedback circuit 40A on the dielectric substrate 41 and the base 21, can be suppressed to a smaller extent. In particular, when the dielectric substrates 31 and 41 are thicker than the semiconductor substrate 11, their parasitic capacitance can be suppressed more effectively.

[0069] (First variation)

[0070] Figure 5 This is a top view of the amplification device 1B of the first modification of the above embodiment. The difference between this modification and the above embodiment lies in the structure and shape of the feedback circuit. Specifically, the amplification device 1B of this modification has feedback circuits 30B and 40B instead of feedback circuits 30A and 40A in the above embodiment. Feedback circuit 30B has a feedback resistor 36 instead of feedback resistor 32 in the above embodiment. Feedback circuit 40B has a feedback resistor 46 instead of feedback resistor 42 in the above embodiment.

[0071] like Figure 5As shown, in this modified example, due to the extended feedback resistors, a higher resistance is further formed. Therefore, the feedback resistors 36 and 46 are bent and extended multiple times from one end to the other along the length direction of the dielectric substrates 31 and 41. Furthermore, multiple bonding pads 37 are arranged side-by-side on the feedback resistor 36 along its extension direction. By short-circuiting any pair of bonding pads 37 through wire bonding, the resistance value of the feedback resistor 36 can be varied in stages. Similarly, multiple bonding pads 47 are arranged side-by-side on the feedback resistor 46 along its extension direction. By short-circuiting any pair of bonding pads 47 through wire bonding, the resistance value of the feedback resistor 46 can be varied in stages. Thus, according to this modified example, the resistance values ​​of the feedback resistors 36 and 46 can be easily adjusted to any value. Since the feedback amount of the feedback circuits 30B and 40B is inversely proportional to the resistance values ​​of the feedback resistors 36 and 46, the feedback amount can be easily adjusted. Furthermore, the resistance values ​​of feedback resistors 36 and 46 can be changed independently of the semiconductor chip 10. Therefore, even if there are deviations in the transistor characteristics of each semiconductor chip 10 in the amplification device, the deviations in transistor characteristics can be reduced by setting the feedback amount according to the characteristics of each transistor.

[0072] (Second variation)

[0073] Figure 6 This is a top view of the amplification device 1C of the second modification of the above-described embodiment. The difference between this modification and the first modification lies in the structure of the feedback circuit. Specifically, the amplification device 1C of this modification has feedback circuits 30C and 40C instead of the feedback circuits 30B and 40B of the first modification.

[0074] The feedback circuit 30C, based on the structure of the feedback circuit 30B in the first modification, further includes a capacitor 38. The capacitor 38 is connected in series with the feedback resistor 36 and the capacitor 33 between the input lead 23 and the output lead 24 on the inner side of the sidewall 22. The capacitor 38 is a die capacitor disposed on the input lead 23 on the inner side of the sidewall 22. One electrode of the capacitor 38 is electrically connected to the pad 34 via a bonding wire 57, and the other electrode is electrically bonded to the input lead 23.

[0075] Similarly, the feedback circuit 40C, based on the structure of the feedback circuit 40B in the first modification, also includes a capacitor 48. The capacitor 48 is connected in series with the feedback resistor 46 and the capacitor 43 between the input lead 23 and the output lead 24 on the inner side of the sidewall 22. The capacitor 48 is a die capacitor disposed on the input lead 23 on the inner side of the sidewall 22. One electrode of the capacitor 48 is electrically connected to the pad 44 via the bonding wire 58, and the other electrode is conductively bonded to the input lead 23. The capacitance value of the capacitor 48 is equal to the capacitance value of the capacitor 38.

[0076] Capacitors 38 and 48 correspond to the input-side capacitors of this variant. Capacitors 33 and 43 correspond to the output-side capacitors of this variant. In this variant, capacitors 38 and 48 are connected to the input lead 23, but capacitors 38 and 48 may also be directly connected to the gate pad assembly 12 via bonding wires or the like, without going through the input lead 23.

[0077] In most cases, the gate bias voltage is negative. Therefore, when the metal containing a metal binder, such as silver paste, that holds the dielectric substrates 31 and 41 and the base 21 is ionized by moisture, these metal ions climb toward the negative potential wiring on the dielectric substrates 31 and 41. Furthermore, the wiring on the dielectric substrates 31 and 41 may short-circuit with the base 21, which serves as a reference potential. This phenomenon is called ion migration. If capacitors 38 and 48 on the input side and capacitors 33 and 43 on the output side are provided as in this modified example, the bias voltage between these capacitors is cut off, resulting in an unstable potential, i.e., a floating state. Therefore, ion migration can be suppressed.

[0078] Furthermore, countermeasures against such ion migration are not limited to ceramic packages; they are also effective in resin-molded packages. In resin-molded packages, moisture intrusion into the package is greater than in ceramic packages, making it more effective to keep the DC potential of the wiring on the dielectric substrates 31 and 41 floating.

[0079] The amplification device disclosed herein is not limited to the embodiments described above and can be modified in various other ways. For example, in the embodiments and modifications described above, capacitors 33 and 43 are mounted on the output lead 24, but capacitors 33 and 43 may also be disposed on dielectric substrates 31 and 41, respectively. In this case, capacitors 33 and 43 are connected to the output lead 24 or the drain pad group 13 via bonding wires.

[0080] Explanation of reference numerals in the attached figures

[0081] 1A, 1B, 1C... Amplification devices

[0082] 10… Semiconductor chips

[0083] 11…Semiconductor substrate

[0084] 11a, 11b... End edges

[0085] 11c, 11d...side

[0086] 12… Gate Pad Group

[0087] 12a… Gate pad

[0088] 13…Drain Pad Group

[0089] 13a…Drain pad

[0090] 14, 15... Auxiliary pads

[0091] 16…Source Pad Group

[0092] 16a…Source Pad

[0093] 20… Package

[0094] 21…base

[0095] 21a…Main face

[0096] 21b, 21c… concave portion

[0097] 22…sidewall

[0098] 22a…Anterior wall portion

[0099] 22b…posterior wall portion

[0100] 22c, 22d… Side wall sections

[0101] 23…Input Leads

[0102] 24… Output leads

[0103] 30A, 30B, 30C… First Feedback Circuit

[0104] 40A, 40B, 40C… Second Feedback Circuit

[0105] 31, 41… Dielectric substrate

[0106] 31a, 41a... Main face

[0107] 31b, 41b... Back

[0108] 32, 42… Feedback resistors

[0109] 33, 43… capacitors

[0110] 34, 35, 44, 45… pads

[0111] 36, 46… Feedback resistors

[0112] 37, 47... joint pads

[0113] 38, 48… capacitors

[0114] 51~58…Joint lines

[0115] D1…direction.

Claims

1. An amplification device, comprising: A semiconductor chip includes: a semiconductor substrate having a first end edge and a second end edge opposite to each other; and a plurality of transistors disposed on the semiconductor substrate, each transistor having a source electrode, a gate electrode and a drain electrode. A gate pad group includes a plurality of gate pads disposed along the first end edge on the semiconductor substrate and connected to the gate electrodes of the plurality of transistors respectively; a drain pad group includes a plurality of drain pads disposed along the second end edge on the semiconductor substrate and connected to the drain electrodes of the plurality of transistors respectively; and a source pad group includes a plurality of source pads connected to the source electrodes of the plurality of transistors respectively. The package includes: a metal base that engages the bottom surface of the semiconductor chip; an insulating sidewall surrounding the semiconductor chip; an input lead that is connected to the gate pad set and extends through the sidewall from the inside to the outside of the sidewall; and an output lead that is connected to the drain pad set and extends through the sidewall from the inside to the outside of the sidewall. and The first feedback circuit and the second feedback circuit each have a dielectric substrate disposed on the metal base, a feedback resistor disposed on the dielectric substrate, and a capacitor connected in series with the feedback resistor, and are electrically connected between the gate pad group and the drain pad group. The first feedback circuit is disposed on the base on one side of the semiconductor chip in the extension direction of the first and second ends. The second feedback circuit is disposed on the base on the other side of the semiconductor chip in the extension direction.

2. The amplification device according to claim 1, wherein, The resistance value of the feedback resistor in the first feedback circuit is equal to the resistance value of the feedback resistor in the second feedback circuit.

3. The amplification device according to claim 1, wherein, The capacitors in the first feedback circuit and the second feedback circuit are core capacitors disposed on the output leads.

4. The amplification device according to claim 1, wherein, The dielectric substrate is fixed to the base via a metal-containing adhesive. The first feedback circuit and the second feedback circuit have: an input-side capacitor that serves as the capacitor electrically connected between the gate pad group and the feedback resistor; and an output-side capacitor that serves as the capacitor electrically connected between the drain pad group and the feedback resistor.

5. The amplification device according to claim 4, wherein, The metal-containing binder is a sintered metal paste.

6. The amplification apparatus according to any one of claims 1 to 5, wherein, The semiconductor chip further comprises: a first auxiliary pad disposed on one side of the gate pad group in the extending direction of the first and second end edges on the semiconductor substrate; and a second auxiliary pad disposed on the other side of the gate pad group in the extending direction on the semiconductor substrate. The first feedback circuit is electrically connected to the gate pad group via the first auxiliary pad, and the second feedback circuit is electrically connected to the gate pad group via the second auxiliary pad.

7. The amplification apparatus according to any one of claims 1 to 5, wherein, The feedback resistors of the first feedback circuit and the second feedback circuit are thin-film resistors formed on the main surface of the dielectric substrate.

8. The amplification apparatus according to any one of claims 1 to 5, wherein, The dielectric substrate is thicker than the semiconductor substrate.

9. The amplification apparatus according to any one of claims 1 to 5, wherein, The feedback resistors of the first and second feedback circuits have a plurality of bonding pads arranged along the extension direction of the feedback resistors.

10. The amplification apparatus according to any one of claims 1 to 5, wherein, The sidewalls of the package include a front wall portion and a rear wall portion that are opposite to each other in a direction intersecting the extending directions of the first end edge and the second end edge. The input lead extends from the inside to the outside of the front wall portion. The output lead extends from the inside to the outside of the rear wall portion.

11. The amplification apparatus according to any one of claims 1 to 5, wherein, The dielectric substrate of the first feedback circuit and the second feedback circuit has a rectangular planar shape with the extension directions of the first end edge and the second end edge as the short side direction.

12. The amplification device according to claim 11, wherein, The feedback resistors of the first and second feedback circuits are bent and extended multiple times from one end to the other along the length of the dielectric substrate.

13. The amplification apparatus according to any one of claims 1 to 5, wherein, The dielectric substrates of the first feedback circuit and the second feedback circuit are made of ceramic.

14. The amplification apparatus according to any one of claims 1 to 5, wherein, The capacitance value of the capacitor in the first feedback circuit is equal to the capacitance value of the capacitor in the second feedback circuit.

Images