Comparator low power response

Abstract

In described examples, an amplifier (100) can be arranged to generate a first stage (110) output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source I1 through a common node (114) to generate the first stage output signal. A replica circuit (120) can be arranged to generate a replica load signal in response to the input signal and in response to a current received from the common node (114). A current switch Q7 can be arranged to selectively couple a second current from a second current source (140) to the common node (114) in response to the replica load signal.

Description

BACKGROUND

[0001] Electronic circuits are designed to include increasingly smaller design features. Smaller design features of electronic circuits can be used to achieve smaller form factors, increased functionality, and reduced power consumption of electronic circuits. Such electronic circuits can include amplifiers (including comparators) used to control various systems. Some comparators are arranged as part of control circuits. The stability and accuracy of such control circuits often depends on the delay of included comparators. However, reducing the power consumption of circuitry including comparators can increase the delay and / or reduce the accuracy of output signals generated by included comparators. SUMMARY

[0002] In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to a current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal. BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 is a schematic diagram of an example comparator for low power response to input signal fluctuations.

[0004] Figure 2 is a waveform plot of an example simulation of a disabled low power response of an example comparator to a large input signal transition.

[0005] Figure 3 is a waveform plot of an example simulation of a low power response of an example comparator to a large input signal transition.

[0006] Figure 4 is a waveform plot of an example simulation of a disabled low power response of an example comparator to a small input signal transition.

[0007] Figure 5 is a waveform plot of an example simulation of a low power response of an example comparator to a small input signal transition.

[0008] Figure 6 is a waveform plot of another example simulation of a disabled low power response of an example comparator to a large input signal transition.

[0009] Figure 7 is a waveform plot of another example simulation of an enabled low power response of an example comparator to a large input signal transition.

[0010] Figure 8is a schematic diagram of another example Aux_bias generator for low power response of an example comparator.

[0011] Figure 9 is a flowchart of an example method for response of an example low power comparator to input signal fluctuations. DETAILED DESCRIPTION

[0012] An electronic circuit can include a control circuit. For example, the control circuit can generate a control signal in response to a feedback signal. The feedback signal can be generated by measuring (e.g., comparing) a signal generated in response to a quantity generated at least partially in response to the control signal.

[0013] In some electronic circuits, the feedback signal can be generated by amplifying a signal generated in response to a quantity generated in response to the control signal (e.g., amplifying a voltage difference between respective conductors of a differential signal). Stability and accuracy of such control circuits can depend on a latency (e.g., delay) of circuitry used to generate the feedback signal. Generally, reducing power consumption of circuitry used to generate the feedback signal can increase delay time and / or reduce accuracy of the feedback signal.

[0014] In contrast, increasing power consumption of circuitry used to generate the feedback signal can reduce delay time and / or increase accuracy of the feedback signal. However, increasing power consumption of circuitry used to generate the feedback signal can result in reduced operating characteristics, such as increased power consumption and increased heat dissipation (e.g., which can require remedial cooling), larger components (e.g., for greater power ratings), reduced battery life (e.g., which can additionally require greater energy storage), and / or increased need for line power for active cooling.

[0015] Some electronic systems can include an amplifier (e.g., which can include at least one transistor) that can be arranged to actively control a source current in response to an input signal voltage. Some examples of the amplifier can be arranged as a comparator. For a given source current (e.g., for powering the comparator), the comparator is generally fast to respond to small voltage changes in first and second input signals. Also, the comparator is generally slower to respond to large voltage changes that can exist in the first and second input signals due to the time during which a common node stabilizes to an appropriate (e.g., ideal) value. Increasing a source current output of a current source used to power the comparator can increase speed and / or accuracy of the comparator. However, increasing the source current of the comparator also increases power consumption of the comparator. Increasing power consumption of the comparator can make the comparator design unsuitable for at least some lower power systems.

[0016] The example comparators described herein can be arranged to compare a first input signal voltage to a second input signal voltage and generate an output signal (e.g., a single-ended or complementary output signal) in response to the comparison. The example comparators can selectively increase power during some input conditions that can otherwise degrade performance (e.g., increase latency and / or reduce output accuracy).

[0017] Figure 1 is a schematic diagram of an example comparator 100 for low-power response to input signal fluctuations. Comparator 100 includes a first stage 110, a replica input transistor pair 120, an Aux_bias generator 130, a current switch 140, a second stage 150, and a third stage 160. In at least one implementation, comparator 100 is arranged to compare a pair of differential input signals and selectively add current to a common node of a differential amplifier when a current starvation condition of the common node is detected.

[0018] First stage 110 is an amplifier having an input transistor pair 112 and a current mirror 115. The input transistor pair can comprise PMOS (P-type metal-oxide-semiconductor) transistors such as transistors Ql and Q2, where transistors Ql and Q2 include a common node (e.g., common source node 114) coupled to at least a first current source II. In other examples, transistors Ql and Q2 are different types of transistors. The current mirror includes NMOS (N-type metal-oxide-semiconductor) transistors Q3 and Q4, and resistors Rl and R2 (e.g., for generating a Replica_load_CG signal used to bias a common gate of Q3 and Q4). The drains of Q3 and Q4 are coupled to the drains of Ql and Q2, respectively. Resistors Rl and R2 (e.g., arranged as a voltage divider) are coupled in series between the respective drains of Q3 and Q4 (e.g., where the drains are coupled as first and second inputs of the current mirror including Q3 and Q4). In other examples, transistors Q3 and Q4 are different types of transistors. A central node 113 (e.g., a divided voltage node) between resistors Rl and R2 is coupled to bias respective control terminals of Q3 and Q4 (e.g., to commonly bias the gates of Q3 and Q4).

[0019] The first stage 110 is a differential amplifier coupled to differentially receive input signals, such as a positive input signal (INP) and a negative input signal (INM). The signal INP and the signal INM control the current flowing through Ql and Q2, respectively. The voltage of the common source node 114 is generated in response to the current supplied by a first current source (e.g., current source II) and in response to the current selectively controlled by transistors Ql and Q2. In some conditions (e.g., caused by a voltage change of the input signal), an undercurrent condition of the common source node 114 can occur, such that a voltage rise of the common node can be delayed and / or cause a false output of the comparator 100.

[0020] The replica input transistor pair 120 is a replica circuit of the input transistor pair 112. For example, the replica input transistor pair 120 includes PMOS transistors Q5 and Q6, which can be of the same size or otherwise scaled to determine (e.g., detect, mimic, emulate, and / or simulate) a performance (e.g., at least one operating characteristic of Ql and / or Q2) of the input transistor pair 112. The source nodes of Q5 and Q6 are coupled to the common source node 114, and the gates of Q4 and Q6 are coupled to the signals INP and INM, respectively. In this arrangement, the replica input transistor pair 120 can respond to the same (or similar) contemporaneous input condition experienced by the input transistor pair 112. For example, the replica input transistor pair can detect a voltage drop of the common node, where the detected voltage drop is generated in response to a rise of the input signal (e.g., signal INP or INM).

[0021] The output of the replica input transistor pair 120 (e.g., the commonly coupled drains of Q5 and Q6) is a replica signal (e.g., Replica load) to indicate (e.g., emulate) a contemporaneous response of the input transistor pair 112. The replica signal can be coupled along a feedback path to generate a feedback signal (e.g., Aux bias) to selectively add a current described herein to the common source node 114 via the current switch 140. For example, during an undercurrent condition, the output current (e.g., tail current) of the replica input transistor pair 120 decreases, which indicates the undercurrent condition. In response to the decrease of the tail current of the replica input transistor pair 120, the Aux bias feedback signal can be asserted such that the current flowing through the drain of Q7 contributes supplemental charge to the common source node 114.

[0022] Aux_bias generator 130 is coupled to receive the output of replica input transistor pair 120. Aux_bias generator 130 includes current source I2, NMOS transistor Q8, and NMOS transistor Q9. Transistor Q8 is biased by a normalized common-gate (ncas) control signal and Q9 is biased by a normalized bias (nbias) control signal. The respective control signal voltages are selected such that Aux_bias generator 130 asserts the Aux_bias signal in response to a decrease in the current of the Replica_load signal (and de-asserts the Aux_bias signal when the Replica_load signal indicates that the current insufficiency condition of common source node 114 has decreased).

[0023] When signal Replica_load indicates a current insufficiency condition of common source node 114, less current is added to the current flowing through the drain of Q9 (where the current otherwise flowing through Q9 is coupled from I2 via Q8). In response to less current being added to the current flowing through Q9, the voltage of the source of Q8 (e.g., node Aux_bias) drops such that PMOS transistor Q7 is turned on.

[0024] Current switch 140 includes Q7 and resistor R3. Resistor R3 is a current source for coupling a limited current to be selectively coupled by Q7 into common source node 114. Node Aux_bias is coupled to the control terminal (e.g., gate) of Q7. Transistor Q7 is arranged to selectively apply current to common source node 114 in response to the Aux_bias voltage. In at least one example, current source II is a first current source, current source R3 (e.g., which is coupled to a VDD power rail) is a second current source, and the first and second current sources are coupled in parallel between the power rail and the common node.

[0025] The second stage 150 is a second stage amplifier including PMOS transistors Q10 and Q11 and NMOS transistors Q12 and Q13. The second stage amplifier is coupled to convert a differential input received from the first stage amplifier to a single-ended output of the second stage amplifier. Transistor Q10 is a main transistor and transistor Q11 is a slave transistor. The main and slave transistors are arranged as a current mirror for generating a second stage output signal in response to a first stage output signal (e.g., a first stage differential output signal). For example, the current mirror (Q10 and Q11) transistors are biased in response to a first stage output minus signal (lst_stage_out_minus signal) and a second stage output signal (2nd_stage_output signal) is generated in response to a lst_stage_out_plus signal and in response to a current supplied by Q11. The second stage 150 can be arranged as a differential input to a single-ended output converter. In another example (not shown), the second stage 150 can be arranged to have a differential output, such that the comparator 100 can be arranged to have a differential output.

[0026] The third stage 160 is an amplifier (e.g., a buffer and / or an output stage) arranged to quantify the second stage output (e.g., an analog signal 2nd_stage_output) and output a signal (e.g., a digital signal) indicative of a comparison result of the differential input signal pair. For example, the third stage can include an odd number of inverters for buffering and inverting the second stage output to generate an output signal as a comparator output (Comp Out).

[0027] In some examples, a low-power response comparator includes an input transistor pair (e.g., input transistor pair 112) arranged to receive first and second input signals (e.g., voltages that can vary over time). The input transistor pair can include a first transistor (e.g., Q1) and a second transistor (e.g., Q2). A first current terminal (e.g., source or drain) of the first transistor is coupled to a first current terminal of the second transistor and a common node (e.g., common source node 114). A control terminal (e.g., gate) of the first transistor is coupled to the first input signal and a control terminal of the second transistor is coupled to the second input signal.

[0028] A first current source (e.g., a constant-on current source II) includes a current output coupled to the common node such that (e.g.) the first current source provides a first current coupled through the common node to respective current terminals of the first and second transistors. The term“source” does not necessarily refer to a source terminal of a PMOS or NMOS transistor and can refer to a positive or negative current source depending on the context.

[0029] The transistors of the input transistor pair can individually control respective currents responsive to input signals coupled to control terminals of the transistors of the input transistor pair. In an example, each transistor of the input transistor pair can be arranged to independently control (e.g., by changing a current carried between source and drain terminals responsive to a control signal) a portion of a source current supplied from a common node of the input transistor pair.

[0030] In an example, respective sources of the input transistor pair are coupled to a common node, and respective drains of the input transistor pair are coupled to respective drain nodes. Thus, voltage variations of respective first and second input voltages can control respective magnitudes of first and second currents, where the first and second currents flow from the sources to the drains (or e.g., from the drains to the sources) of respective transistors of the input transistor pair, respectively.

[0031] Examples low-power response comparators described herein (e.g., comparator 100) can include replica circuitry (e.g., replica input transistor pair 120 circuitry) to indicate (e.g., replicate or emulate) a response of an input transistor pair to variations in first and second input signals. The replica circuitry can include a replica input transistor pair coupled to receive current from a common node to which current is supplied by the input transistor pair. The replica input transistor pair need not be instantiated (e.g., physically manufactured) using the same precise design features of each transistor of the input transistor pair; for example, the transistors of the replica input pair can be scaled such that the replica circuitry can emulate a scaled response of the input transistor pair.

[0032] An example replica input transistor pair can include third and fourth transistors. A first current terminal of the third transistor is coupled to a first current terminal of the fourth transistor and to a common node. A second current terminal of the third transistor is coupled to a second current terminal of the fourth transistor and to a feedback signal node. A control terminal of the third transistor is coupled to a first input signal, and a control terminal of the fourth transistor is coupled to a second input signal.

[0033] As described herein, the replica input transistor pair can emulate the input transistor pair. For example, the replica input transistor pair can generate a replica signal (e.g., at the Replica load node of FIG. 1) to indicate (e.g., emulate) a contemporaneous response of the input transistor pair. The replica signal can be arranged to generate a feedback signal (e.g., the Aux bias signal of FIG. 1) to indicate a current deficiency condition of the common node (e.g., generated at the common source node 114) by the input transistor pair. Figure 1 Figure 1 As described herein, the replica input transistor pair can emulate the input transistor pair. For example, the replica input transistor pair can generate a replica signal (e.g., at the Replica load node of FIG. 1) to indicate (e.g., emulate) a contemporaneous response of the input transistor pair. The replica signal can be arranged to generate a feedback signal (e.g., the Aux bias signal of FIG. 1) to indicate a current deficiency condition of the common node (e.g., generated at the common source node 114) by the input transistor pair.

[0034] ​The replica input transistor pair can detect (e.g., through simulation of the input transistor pair) an insufficient response of the input transistor pair to current, as the replica input transistor pair is coupled to a similar input (or a buffered input derived from a similar input), which is coupled to control the first transistor pair (e.g., the input transistor pair), for example.

[0035] The insufficient response is a response of the input transistor pair (e.g., the input transistor pair 112) to current supplied by the first current source and to the first and second input signals. For example, an insufficient condition can exist (e.g., be caused or created) in a node between two transistors, where a first transistor supplies current to the node, and a capacitance of the node (and current conducted away from the node by a second transistor) prevents a voltage change of the node.

[0036] To determine the insufficient response, the second current terminals of the third and fourth transistors are coupled to a feedback signal node to generate a combined current. The combined current is an indication of the determined performance (e.g., the Replica load signal) and is coupled to the feedback signal node to generate a feedback signal (e.g., the Aux bias signal) for controlling a current switch (e.g., the current switch 140).

[0037] The current switch includes a first current terminal coupled to a power rail, a second current terminal coupled to the common source node, and a control terminal coupled to the feedback signal node. The current switch is arranged to selectively couple current into the common node in response to the indication of the determined performance. A bias generator (e.g., the Aux bias generator 130) can generate a feedback signal (e.g., a bias signal) in response to the indication of the determined performance. The feedback signal controls (e.g., activates and / or adjusts) the current switch (e.g., a boost current source such as the current switch 140). For example, the bias generator is arranged to assert the bias signal to activate the current switch in response to a decrease in the indicated current received from the feedback signal node.

[0038] Thus, there is a feedback loop such that, for example, the current switch adjusts (e.g., selectively provides in response to the feedback signal node) coupling of the second current (e.g., an augmented current) to the common node. The feedback signal can include a signal generated in an associated feedback path, such as a control signal for selectively controlling the current switch.

[0039] Current switches can be coupled to generate (e.g., amplify and / or inject) a controlled boost current to dynamically augment a source current for powering the input transistor pair. The source current for powering the input transistor pair can be selectively applied by controlling the addition of a boost current (e.g., as regulated by the current switches) to a common source node of the input transistor pair. Selectively augmenting the source current for powering the input transistor pair can conserve power that would otherwise be dissipated by providing a fixed magnitude source current (e.g., of the first current source) to avoid an undercurrent response of the common source node of the input transistor pair.

[0040] The augmented source current is coupled to the first and second current terminals of the input transistor pair. In an example configuration, the second current terminal (e.g., drain or source) of the first transistor can be coupled to a first input of a second stage of the comparator and the second current terminal of the second transistor can be coupled to a second input of the second stage of the comparator. In an example configuration, an output signal (e.g., an analog output signal) of the second stage can be quantized (e.g., converted to a digital value) and coupled as an output signal of the comparator (e.g., as a digital output). As described herein, the selective augmentation of the common node source current can help reduce latency and output errors while maintaining the low power consumption of the low power response comparator described herein.

[0041] The selective augmentation of the common node source current for powering the input transistor pair can reduce static current otherwise consumed by the input transistor pair and reduce latency (e.g., as described herein with respect to Figure 1 、 Figure 3 、 Figure 5 and Figure 7 . Further, the selective augmentation of the source current can increase amplifier accuracy and eliminate some kinds of parasitic comparator errors (e.g., as described herein with respect to Figure 6 .

[0042] An undercurrent response of the common source node of the comparator 100 can be demonstrated by disabling the turn-on of the current switch 140 in simulation. For example, when the current switch 140 is disabled in simulation, latency caused by the undercurrent common source node is demonstrated (e.g., as described herein with respect to Figure 2 、 Figure 4 and Figure 6 , and output errors caused by the undercurrent common source node are demonstrated (e.g., as described herein with respect to Figure 6 . The simulation is performed using a simulation program, such as SPICE (Simulation Program with Integrated Circuit Emphasis), to mathematically generate a response of the modeled circuit to input signal fluctuations.

[0043] Figure 2is a waveform plot of an example simulation of the disabled low-power response of an example comparator to a large input signal transition. The example simulation 200 includes waveforms INM 210 (e.g., the "input negative" signal coupled to the gate of Q2), INP 220 (e.g., the "input positive" signal of Ql), Comp Out 230 (e.g., the "comparator output" signal of the third stage 160), Source 240 (e.g., the node Common_Source_Node coupled to the respective sources of transistors Ql, Q2, Q5, and Q6 and to the drain of Q7), and Aux_bias 250 (e.g., coupled to the gate of Q7). The low-power enhanced response of the example comparator to a large input signal transition can be disabled in response to a simulation parameter (e.g., the feedback signal for generating the low-power response can be disabled in simulation 200 by coupling the Aux_bias node to 3.9 volts via an ideal switch). Figure 1 is a waveform plot of an example simulation of the disabled low-power response of an example comparator to a large input signal transition. The example simulation 200 includes waveforms INM 210 (e.g., the "input negative" signal coupled to the gate of Q2), INP 220 (e.g., the "input positive" signal of Ql), Comp Out 230 (e.g., the "comparator output" signal of the third stage 160), Source 240 (e.g., the node Common_Source_Node coupled to the respective sources of transistors Ql, Q2, Q5, and Q6 and to the drain of Q7), and Aux_bias 250 (e.g., coupled to the gate of Q7). The low-power enhanced response of the example comparator to a large input signal transition can be disabled in response to a simulation parameter (e.g., the feedback signal for generating the low-power response can be disabled in simulation 200 by coupling the Aux_bias node to 3.9 volts via an ideal switch). Figure 1

[0044] In simulation 200 for illustrating the current-starved response of comparator 100 to a large input signal transition, waveform INM 210 is initially asserted at ground potential (e.g., 0 volts) and waveform INP 220 is initially asserted at approximately 2.90 volts. Because the magnitude of waveform INP 220 is greater than the magnitude of waveform INM 210 (e.g., in steady state conditions), waveform Comp Out 230 is initially logic one (e.g., a logic high level, which is represented herein as a voltage greater than 1.42 volts, for example).

[0045] Waveform Source 240 indicates that the voltage of common source node 114 is initially driven to approximately 1.2 volts in response to the current supplied by the first current source (e.g., current source II) and in response to the current selectively controlled by transistors Ql and Q2. For example, waveform Source 240 is driven to approximately 1.2 volts in response to waveform INM 210 being at ground potential (e.g., which strongly biases Q2 to be conductive), in response to waveform INP 220 being at approximately 2.90 volts (e.g., which moderately biases Ql to be conductive), and in response to the common controlled current mirror of Q3 and Q4 (e.g., which is commonly biased via the resistor network of Rl and R2).

[0046] ​In response to current source I2, waveform Aux_bias 250 is initially driven to a value of approximately 3.90 volts. The low-power enhanced response of the example comparator to large input signal transitions can be disabled in response to an analog parameter (e.g., the feedback signal used to generate the low-power response can be disabled in simulation 200 by coupling the Aux_bias node to 3.9 volts via an ideal switch).

[0047] During operation of comparator 100, the feedback signal of replica input transistor pair 120 circuit can be a voltage generated in response to the "tail" current of replica input transistor pair 120 circuit. In simulation 200, the feedback signal is decoupled from waveform Aux_bias 250 (e.g., as a function of simulation 200 input parameters) (when transistor Q8 is in an off state). The feedback signal is disabled (e.g., by turning off Q8 in response to simulation 200 input parameters) so that, for example, the response of comparator 100 with the disabled low-power enhancement can be seen. In the case where the described low-power selected current enhancement is not enabled in the example, simulation 200 of comparator 100 shows a long delay (e.g., approximately 230 nanoseconds) for the voltage on common source node 114 (e.g., waveform Source 240) to rise to a steady state level.

[0048] Waveform Aux_bias 250 is coupled to the control terminal (e.g., gate) of transistor Q7. Transistor Q7 is arranged as a programmable (e.g., programmable in response to gate voltage) current source for selectively applying current to common source node 114. In simulation 200, transistor Q7 is biased (in response to simulation 200 input) to refrain from selectively applying current to common source node 114 (e.g., applying current in response to the feedback signal generated by replica input transistor pair 120 circuit). Because waveform Aux_bias 250 is approximately 3.90 volts, PMOS transistor Q7 is in an off state so that no boost current is injected into common source node 114 (e.g., of Ql and Q2) by current source Q7.

[0049] At 10 microseconds into simulation 200, waveform INM 210 is driven (e.g., as an input parameter of simulation 200) to undergo a large voltage transition 212 from ground potential to approximately 2.92 volts (e.g., which is close to - but greater than - the contemporaneous voltage of waveform INP 220). The transition 212 of waveform INM 210 causes transients 222 and 252 (e.g., via parasitic coupling and / or "ground bounce").

[0050] In response to transition 212, the gate voltage of transistor Ql is raised to approximately 2.92 volts. Thus, the gate voltage of Ql (after transition 212) is higher than the contemporaneous gate voltage of Q2. Current source II is designed to supply current at a low maximum (e.g., by design to conserve power). The low level of maximum current can result in an undercurrent response that contributes to a delay (e.g., a retardation) in the voltage rise (during transition 242) of common source node 114. Waveform Source 240 during transition 242 is rising (e.g., slowly) in response to the limited current supplied by current source II, the capacitance of common source node 114, and the current drawn by the current mirror comprising transistors Q3 and Q4.

[0051] The parasitic conditions of the structure forming common source node 114 (e.g., of Ql and Q2) prevent the voltage of common source node 114 from rising (e.g., instantaneously). Thus, the slew rate of transition 242 is limited, and the rise of waveform Source 240 to approximately 3.6 volts is achieved with a delay of approximately 200 nanoseconds. (In the following description of the simulation, the delay of the voltage rise of common source node 114 is referred to as a retardation.) Figure 3 In the simulation described, the low power enhancement response can reduce the delay of the voltage rise of common source node 114 by 140 nanoseconds for similar characteristics of waveforms INM 210 and INP 220.

[0052] In simulation 200, waveform Comp Out 230 switches (e.g., switches low) in response to transition 212 of waveform INM 210 to a voltage greater than the contemporaneous voltage of waveform INP 220. In response to transition 212, waveform Comp Out 230 switches from a logic one to a logic zero (where a logic zero is represented as a ground voltage and a logic one is represented as a level of approximately 1.42 volts). Waveform Comp Out 230 switches to a logic zero during transition 232, which reaches the logic zero level at time 202 (e.g., approximately 10.33 microseconds).

[0053] At time 202, simulation 200 is approaching a steady state response. Waveform INM 210 is approximately 2.92 volts and waveform INP 220 is approximately 2.90 volts. After transition 242, waveform Source 240 is maintained at a voltage of approximately 3.6 volts. Because the feedback control of replica input transistor pair 120 circuit is disabled, waveform Aux bias 250 is maintained at a voltage of approximately 3.90 volts.

[0054] The delay of comparator 100 shown in simulation 200 can be measured from the beginning of transition 212 of waveform INM 210 to the end of transition 232 of waveform Comp Out 230. When so measured, the delay of comparator 100 in simulation 200 is approximately 330 nanoseconds, where simulation 200 includes feedback control of the replica input transistor pair 120 circuit being disabled. In the following with respect to Figure 3 The delay of comparator 100 in simulation 200 described, where feedback control of the replica input transistor pair 120 circuit is not disabled as a simulation parameter, is reduced to approximately 124 nanoseconds.

[0055] Figure 3 is a waveform plot of an example simulation of an example comparator pair enhanced response to a large input signal transition at low power. Example simulation 300 includes waveforms INM 310, INP 320, Comp Out 330, Source 340, and Aux bias 350 to illustrate the example operation of the portions of comparator 100 described above with respect to Figure 1

[0056] In simulation 300 for illustrating the current boost response of comparator 100 to a large input signal transition, waveform INM 310 is initially asserted at ground potential (e.g., 0 volts) and waveform INP 320 is initially asserted at approximately 2.90 volts. Because the magnitude of waveform INP 320 is greater than the magnitude of waveform INM 310 (e.g., in steady state conditions), waveform Comp Out 330 is initially logic one (e.g., 1.42 volts).

[0057] Waveform Source 340 (Common_Source_Node) indicates that the voltage of common source node 114 is initially driven to approximately 1.2 volts in response to current supplied by a first current source (e.g., current source II) and in response to current selectively controlled by transistors Ql and Q2. For example, in response to waveform INM 310 being at ground potential (e.g., which strongly biases Q2 to be conductive), in response to waveform INP 320 being at approximately 2.90 volts (e.g., which moderately biases Ql to be conductive), and in response to the common controlled current mirror of Q3 and Q4, waveform Source 340 is driven to approximately 1.2 volts.

[0058] At 10 microseconds into simulation 300, waveform INM 310 is driven to undergo a large voltage transition 312 from ground potential to approximately 2.92 volts. Transition 312 of waveform INM 310 causes a transient 322. ​

[0059] In response to transition 312, the gate voltage of transistor Ql is raised to approximately 2.92 volts. Thus, the gate voltage of Ql (after transition 312) is higher than the contemporaneous gate voltage of Q2. The low level of the current maximum of current source II can result in an undercurrent response that contributes to a delay in the voltage rise (during transition 342) of common source node 114. Waveform Source 340 during transition 342 rises (e.g., slowly) in response to the limited current supplied by current source II, the capacitance of common source node 114, and the current drawn by the current mirror including transistors Q3 and Q4.

[0060] The replica input transistor pair 120 (e.g., coupled to the input of input transistor pair 112) detects the undercurrent condition of common source node 114. In response to the undercurrent condition, the tail current of replica input transistor pair 120 is reduced. In response to the reduction of the tail current of replica input transistor pair 120, less current is added to the current flowing through the drain of Q9. In response to less current being added to the current flowing through Q9, the voltage of the source of Q8 (waveform Aux_bias 350) drops (e.g., as transition 352). For example, transition 352 begins at approximately 40 nanoseconds after the undercurrent condition begins.

[0061] As waveform Aux_bias 350 drops, PMOS transistor (e.g., switch) Q7 increases conduction and adds current (via current switch 140) to common source node 114. The addition of current to common source node 114 by Q7 via current switch 140 reduces the undercurrent condition at common source node 114 and speeds up the rise of waveform Source 340 during transition 342.

[0062] As waveform Source 340 rises to a steady state level (e.g., 3.6 volts) at approximately the end of transition 342, the undercurrent condition of common source node 114 is alleviated. Replica input transistor pair 120 detects the reduction of the undercurrent condition of common source node 114 and increases the tail current of replica input transistor pair 120. In response to the increase of the tail current of replica input transistor pair 120, more current is added to the current flowing through the drain of Q9. In response to more current being added to the current flowing through Q9, the voltage of the source of Q8 (e.g., waveform Aux_bias 350) rises (e.g., as transition 354). For example, transition 354 begins in response to waveform Source 340 rising to a steady state level (e.g., which occurs at approximately 98 nanoseconds after the undercurrent condition begins in simulation 300).

[0063] As the waveform Aux_bias 350 rises during transition 354, the PMOS transistor (e.g., switch) Q7 reduces conduction and gradually adds less current (e.g., supplied from current switch 140) to the common source node 114. The waveform Aux_bias 350 rises to a steady state level (e.g., 3.6 volts) after the comparator 100 responds (e.g., correctly responds) to the relative change in the first input signal occurring at 10 microseconds into the simulation 300.

[0064] In the simulation 300, the waveform Comp_Out 330 switches in response to a transition 312 in the waveform INM 310 to a voltage greater than the contemporaneous voltage of the waveform INP 320. In response to the transition 312, the waveform Comp_Out 330 switches from a logical one to a logical zero. The waveform Comp_Out 330 switches to a logical zero during a transition 332, which reaches a logical zero level at time 302 (e.g., approximately 10.124 microseconds).

[0065] After time 302, the simulation 300 approaches a steady state response. The waveform INM 310 is approximately 2.92 volts and the waveform INP 320 is approximately 2.90 volts. The waveform Source 340 reaches and maintains a steady state voltage of approximately 3.60 volts after a transition 342.

[0066] The latency of the comparator 100 shown in the simulation 300 can be measured from the beginning of the transition 312 in the waveform INM 310 to the end of the transition 332 in the waveform Comp_Out 330. When so measured, the latency of the comparator 100 in the simulation 300 is shortened to approximately 124 nanoseconds by the described current boost added by the current switch 140. The latency of the simulation 300 is 176 nanoseconds faster than the 330 nanoseconds latency of the simulation 200, where the feedback control of the replica input transistor pair 120 circuit is disabled (e.g., in response to the simulation 200 parameter input).

[0067] Figure 4 is a waveform plot of an example simulation of a disabled low power enhanced response of an example comparator to a small input signal transition. The example simulation 400 includes waveforms INM 410, INP 420, Comp_Out 430, Source 440, and Aux_bias 450 for showing example operation of portions of the comparator 100 described above in reference to Figure 1 The example waveforms include waveforms INM 410, INP 420, Comp_Out 430, Source 440, and Aux_bias 450. The low power enhanced response of the example comparator to a small input signal transition can be disabled in response to a simulation parameter (e.g., the feedback signal for generating the low power response can be disabled in the simulation 400 by coupling the Aux_bias node to 3.9 volts via an ideal switch).

[0068] In simulation 400 illustrating the insufficient current response of comparator 100 to small input signal transitions, waveform INM 410 is initially asserted (e.g., prior to time 402) at a potential of 2.88 volts and waveform INP 420 is initially asserted at approximately 2.90 volts. Because the magnitude of waveform INP 420 is greater than the contemporaneous magnitude of waveform INM 410 (e.g., in steady state conditions), waveform Comp Out 430 is initially a logic one (e.g., 1.42V).

[0069] Waveform Source(Common_Source_Node) 440 indicates that the voltage of common source node 114 is initially driven to approximately 3.55 volts in response to current supplied by a first current source (e.g., current source II) and in response to current selectively controlled by transistors Ql and Q2. For example, in response to waveform INM 410 being at 2.88 volts, in response to waveform INP 420 being at approximately 2.90 volts, and in response to a common controlled current mirror of Q3 and Q4 (e.g., which is commonly biased via a resistor network of Rl and R2), waveform Source 440 is driven to approximately 3.55 volts.

[0070] Waveform Aux_bias 450 is driven to a value of approximately 3.90 volts in response to current source I2. The low power enhanced response of an example comparator to small input signal transitions can be disabled in response to simulation parameters (e.g., the feedback signal used to generate the low power response can be disabled in simulation 400 by coupling the Aux_bias node to 3.9 volts via an ideal switch).

[0071] During operation of comparator 100, the feedback signal of replica input transistor pair 120 circuit can be a voltage generated in response to the tail current of replica input transistor pair 120 circuit. In simulation 400, the feedback signal is decoupled from modulating waveform Aux_bias 450 (e.g., as a function of simulation 400 input parameters). The feedback signal is disabled (e.g., by turning off Q8 in response to simulation 400 input parameters) so that, for example, the response of comparator 100 with the disabled low power enhancement can be seen. In the case where the described low power selected current boost enhancement is not enabled in the example, simulation 400 of comparator 100 shows a delay (e.g., approximately 40 nanoseconds) in the voltage of common source node 114 (e.g., waveform Source 440) rising to a steady state level.

[0072] Waveform Aux_bias 450 is coupled to the control terminal (e.g., gate) of transistor Q7. Transistor Q7 is arranged as a programmable (e.g., programmable in response to a gate voltage) current source for selectively applying current to common source node 114. In simulation 400, transistor Q7 is disabled (in response to simulation 400 input) from selectively applying current to common source node 114 (e.g., current is applied in response to feedback signal generated by replica input transistor pair 120 circuit). Because waveform Aux_bias 450 is approximately 3.90 volts, PMOS transistor Q7 is in an off state such that no boost current is injected into common source node 114 (e.g., of Ql and Q2) by current source Q7.

[0073] At 10 microseconds into simulation 400, waveform INM 410 is driven (e.g., as an input parameter to simulation 400) to undergo a small voltage transition 412 from a voltage of 2.88 volts to a voltage of approximately 2.92 volts. Transition 412 of waveform INM 410 causes transients 422 and 452.

[0074] In response to transition 412, the gate voltage of transistor Q2 is raised to approximately 2.92 volts. Thus, the gate voltage of Q2 (after transition 412) is higher than the contemporaneous gate voltage of Ql. Current source II is designed to supply current at a low maximum (e.g., to conserve power). The low level of maximum current can result in an insufficient current response, which contributes to a delay in the voltage rise (during transition 442) of common source node 114. Waveform Source 440 during transition 442 rises (e.g., slowly) in response to the limited current supplied by current source II, the common source node 114 capacitance, and the current drawn by current mirror including transistors Q3 and Q4.

[0075] Parasitic conditions of the structure forming common source node 114 (e.g., of Ql and Q2) prevent the voltage of common source node 114 from rising (e.g., instantaneously). Thus, the slew rate of transition 442 is limited, and the rise of waveform Source 440 to approximately 3.6 volts is achieved with a delay of approximately 40 nanoseconds.

[0076] In simulation 400, waveform Comp Out 430 switches in response to transition 412 of waveform INM 410 to a voltage greater than the contemporaneous voltage of waveform INP 420. In response to transition 412, waveform Comp Out 430 switches from a logic one to a logic zero. Waveform Comp Out 430 switches to a logic zero during transition 432, which reaches the logic zero level approximately 1 nanosecond before time 404 (e.g., where time 404 is 10.056 microseconds).

[0077] At time 404, the simulation 400 approaches a steady state response. The waveform INM 410 is approximately 2.92 volts and the waveform INP 420 is approximately 2.90 volts. After the transition 442, the waveform Source 440 is maintained at a voltage of approximately 3.57 volts. Because the feedback control of the replica input transistor pair 120 circuit is disabled, the waveform Aux_bias 450 is maintained at a voltage of approximately 3.90 volts.

[0078] The delay of the comparator 100 shown in the simulation 400 can be measured from the beginning of the transition 412 of the waveform INM 410 to the end of the transition 432 of the waveform Comp Out 430. When so measured, the delay of the comparator 100 in the simulation 400 is approximately 55 nanoseconds, where the simulation 400 includes the feedback control of the replica input transistor pair 120 circuit being disabled. In the following, the delay of the comparator 100 is measured in the same manner. Figure 5 The delay of the comparator 100 in the simulation 500 is similar to the delay of the comparator 100 in the simulation 400, described above, where the feedback control of the replica input transistor pair 120 circuit is not disabled as a simulation parameter.

[0079] Figure 5 is a waveform diagram of an example simulation of an example comparator pair enhanced response to a small input signal transition at low power. The example simulation 500 includes waveforms INM 510, INP 520, Comp Out 530, Source 540, and Aux_bias 550 to show the example operation of the portions of the comparator 100 described above with reference to Figure 1

[0080] In the simulation 500 for illustrating the current boost response of the comparator 100 to a small input signal transition, the waveform INM 510 is initially asserted (e.g., before time 502) at a potential of 2.88 volts and the waveform INP 520 is initially asserted at approximately 2.90 volts. Because the magnitude of the waveform INP 520 is greater than the magnitude of the waveform INM 510 (e.g., in a steady state condition), the waveform Comp Out 530 is initially a logic one (e.g., 1.42 volts).

[0081] ​Waveform Source (Common_Source_Node) 540 indicates that the voltage of common source node 114 is initially driven (e.g., before time 502) to approximately 3.55 volts in response to current supplied by first current source (e.g., current source II), and in response to current selectively controlled by transistors Ql and Q2. For example, in response to waveform INM 510 being at 2.88 volts, in response to waveform INP 520 being at approximately 2.90 volts, and in response to a commonly controlled current mirror of Q3 and Q4, waveform Source 540 is driven to approximately 3.55 volts.

[0082] At 10 microseconds into simulation 500 (e.g., at time 502), waveform INM 510 is driven to undergo a small voltage transition 512 from a voltage of 2.88 volts to a voltage of approximately 2.92 volts. Transition 512 of waveform INM 510 causes a transient 522.

[0083] In response to transition 512, the gate voltage of transistor Q2 is raised to approximately 2.92 volts. Thus, the gate voltage of Q2 (after transition 512) is higher than the contemporaneous gate voltage of Ql. The low level of the current maximum of current source II can result in an insufficient current response, which contributes to a delay in the voltage of common source node 114 rising (during transition 542). Waveform Source 540 during transition 542 rises in response to the limited current supplied by current source II, the capacitance of common source node 114, and the current drawn by the current mirror including transistors Q3 and Q4.

[0084] Replica input transistor pair 120 (e.g., coupled to the input of input transistor pair 112) detects an insufficient current condition of common source node 114. In response to the insufficient current condition, the tail current of replica input transistor pair 120 is reduced. In response to the reduction of the tail current of replica input transistor pair 120, less current is added to the current flowing through the drain of Q9. In response to less current being added to the current flowing through Q9, the voltage of the source of Q8 (waveform Aux_bias 550) drops (e.g., as transition 552). For example, transition 552 begins at approximately 10 nanoseconds after the start of the insufficient current condition.

[0085] As waveform Aux_bias 550 drops, PMOS transistor (e.g., switch) Q7 increases conductivity and adds current (from current switch 140) to common source node 114. In simulation 500, the resulting insufficient current condition is light (e.g., due to the small voltage change of waveform INM 510, and the added current from current switch Q7 to common source node 114 is not readily able to significantly speed up (to cause a voltage transition of common source node 114) in response to the small voltage change of waveform INM 510. Figure 5The rising of the waveform Source 540 during the transition 542 is shown in the middle. As described below, the transition 552 does not readily turn on the transistor Q7 to add supplemental current to the common source node 114 significantly.

[0086] In the simulation 500, the waveform Comp Out 530 switches in response to a transition 512 of the waveform INM 510 to a voltage greater than the contemporaneous voltage of the waveform INP 520. In response to the transition 512, the waveform Comp Out 530 switches from a logical one to a logical zero. The waveform Comp Out 530 switches to a logical zero during a transition 532, which reaches the logical zero level at time 504 (e.g., approximately 10.055 microseconds).

[0087] At time 504, the waveform INM 510 of the simulation 500 is approximately 2.92 volts, the waveform INP 520 is approximately 2.90 volts, and the waveform Source 540 reaches and maintains a steady state voltage of approximately 3.6 volts after the transition 542.

[0088] The delay of the comparator 100 shown in the simulation 500 can be measured from the beginning of the transition 512 of the waveform INM 510 to the end of the transition 532 of the waveform Comp Out 530. As Figure 5 The delay of the comparator 100 in the simulation 500 shown can be compared to the delay of the comparator 100 in the simulation 400 (described above) as

[0089] Figure 6 is a waveform diagram of another example simulation of a disabled low power enhancement response of an example comparator to a large input signal transition. The example simulation 600 includes waveforms for showing example operations of portions of the comparator 100 described above with reference to Figure 1 The example waveforms include a waveform INM 610, a waveform INP 620, a waveform Comp Out 630, a waveform Source 640, a waveform Aux_bias 650, a waveform 1st_stage_out_plus 660, a waveform 1st_stage_out_minus 670, and a waveform 2nd_stage_output 680. Transistor Q8 is turned off by the simulation 600 to disable the feedback signal (e.g., via the waveform Aux_bias 650) for controlling the current boost of Q7.

[0090] Analog 600 demonstrates an insufficient current response of common source node 114 of comparator 100 to a first value of a first input signal changing to a second value substantially close to a second input signal. For example, when a difference between the first input signal value and the second input signal value is a value within an input offset of an amplifier receiving the first and second input signals, the first input signal value is substantially close to the second input signal value.

[0091] In analog 600, waveform INM 610 is initially asserted (e.g., prior to the 10 microsecond mark of analog 600) at a ground potential (e.g., 0 volts), while waveform INP 620 is initially asserted at approximately 2.90 volts. Because the initial magnitude of waveform INP 620 is greater than a contemporaneous magnitude of waveform INM 610 (e.g., in an initial steady state condition), waveform Comp Out 630 is initially a logic one (e.g., 1.42V). Waveform Comp Out 630 is generated in response to a difference between waveform 1st stage out minus 670 and waveform 1st stage out plus 660, where the difference is indicated by waveform 2nd stage output 680 described below.

[0092] Waveform Source(Common_Source_Node) 640 indicates that a voltage of common source node 114 is initially driven to a low voltage (e.g., 1.2 volts) in response to a current supplied by a first current source (e.g., current source II) and in response to a current selectively controlled by transistors Ql and Q2. For example, in response to waveform INM 610 being grounded, in response to waveform INP 620 being at approximately 2.90 volts, and in response to a common controlled current mirror of Q3 and Q4 (e.g., which is commonly biased via a resistor network of Rl and R2), waveform Source 640 is driven to a low voltage (e.g., 1.2 volts).

[0093] Waveform Aux_bias 650 is driven to a value of approximately 3.90 volts in response to current source I2. A low power enhanced response of an example comparator to a large input signal transition can be disabled in response to an analog parameter (e.g., a feedback signal for generating a low power response can be disabled in analog 600 by coupling the Aux_bias node to 3.9 volts via an ideal switch).

[0094] During operation of comparator 100, the feedback signal of replica input transistor pair 120 circuitry can be a voltage generated in response to the tail current of replica input transistor pair 120 circuitry. In simulation 600, the feedback signal is decoupled from waveform Aux_bias 650 (e.g., in response to simulation 600 input parameters). The feedback signal is disabled (e.g., in response to simulation 600 input parameters) so that, for example, the response of comparator 100 with disabled low power enhancement can be seen. For example, the deficiencies of "robust" operation (e.g., sensitivity to produce false output) can be demonstrated by instances of spurious output pulses of waveform Comp Out 630 (e.g., where the spurious pulses include transitions 632 and 634).

[0095] Waveform Aux_bias 650 is coupled to the control terminal (e.g., gate) of transistor Q7. Transistor Q7 is arranged as a programmable (e.g., programmable in response to a gate voltage) current source for selectively applying current to common source node 114. In simulation 600, transistor Q7 is disabled (in response to simulation 600 input) from selectively applying current to common source node 114 (e.g., applying current in response to the feedback signal generated by replica input transistor pair 120 circuitry). Because waveform Aux_bias 650 is approximately 3.90 volts throughout simulation 600, PMOS transistor Q7 is in an off state so that no boost current is injected into common source node 114 (e.g., of Ql and Q2) by current source Q7.

[0096] Waveforms 1st_stage_out_plus 660 and 1st_stage_out_minus 670 are generated in response to first and second input signals, respectively. For example, waveform 1st_stage_out_plus 660 is initially approximately 169 millivolts (in response to waveform INM 610), and waveform 1st_stage_out_minus 670 is approximately 550 millivolts (in response to waveform INP 620).

[0097] The second stage 150 generates the waveform 2nd_stage_output 680 in response to a difference between the waveform 1st_stage_out_plus 660 and the waveform 1st_stage_out_minus 670 (where the waveform 1st_stage_out_plus 660 and the waveform 1st_stage_out_minus 670 are the first stage 110 output signals). The difference between the initial voltage values of the waveform 1st_stage_out_plus 660 and the waveform 1st_stage_out_minus 670 is greater than the input offset of the input transistors Q12 and Q13 of the second stage 150 (e.g., which results in a reduced probability of an output error). When the difference between the initial voltage values of the waveform 1st_stage_out_plus 660 and the waveform 1st_stage_out_minus 670 is not greater than the input offset of the second stage 150, the second stage is prone to output an erroneous output (as described below).

[0098] In response to the difference in the input signals, the waveform 2nd_stage_output 680 is initially indicative of the magnitude of the waveform 1st_stage_out_plus 660 being less than the voltage of the waveform 1st_stage_out_minus 670 (e.g., ground or near ground potential). The value of the waveform 2nd_stage_output 680 (e.g., initially at ground potential) is received by the third stage 160 and quantized by the input gate of the third stage 160 (e.g., initially as an input logic zero). The third stage 160 buffers and inverts the input logic zero and outputs the buffered inverted value as the waveform Comp_Out 630 (e.g., which is initially a logic one).

[0099] At 10 microseconds into the simulation 600, the waveform INM 610 is driven (e.g., as a simulation 600 input parameter) to undergo a large voltage transition 612 from a ground potential to a voltage of approximately 2.88 volts. The rising of the waveform INM 610 to a voltage of approximately 2.88 volts is still less than the magnitude of the waveform INP 620 (e.g., 2.90 volts), and thus the waveform Comp_Out 630 is not expected to switch (e.g., change output logic state) under ideal conditions (e.g., without logic errors). The transition 612 of the waveform INM 610 causes transients 622, 652, 662, 672, and 682.

[0100] During transition 612, the gate voltage of transistor Q2 rises to approximately 2.88 volts. After transition 612, the gate voltage of Q2 remains lower than the contemporaneous gate voltage of Ql (e.g., such that waveform Comp Out 630 fails to properly switch). Current source II is designed to supply current to Common Source Node (e.g., waveform Source 640) at a low maximum current (e.g., by design to conserve power). The low level of maximum current results in an undercurrent response (e.g., in response to transition 612), which contributes to the delay in the voltage rise of transition 642.

[0101] The undercurrent-induced delay of common source node 114 of first stage 110 (e.g., which occurs during transition 642) also contributes to the delay in the settling of waveforms 1st_stage_out_plus 660 and 1st_stage_out_minus 670. For example, after transients 662 and 672, the voltages of waveforms 1st_stage_out_plus 660 and 1st_stage_out_minus 670 converge to a difference that is less than the input offset of the amplifier of second stage 150 (which can result in an erroneous output of second stage 150).

[0102] The convergence of waveforms 1st_stage_out_plus 660 and 1st_stage_out_minus 670 to low voltages (e.g., near ground) helps ensure that NMOS transistors Q12 and Q13 are more negatively biased, such that transistors Q12 and Q13 do not conduct strongly. When transistors Q12 and Q13 do not conduct strongly during an undercurrent condition (e.g., during transition 642), waveform 2nd_stage_output 680 rises (e.g., gradually rises in response to the drain current produced by the current mirror formed by transistors Q10 and Ql l).

[0103] As the waveform 2nd_stage_output 680 rises in the simulation 600, the second stage 150 outputs (logically incorrectly) reaches a voltage that can be quantized as a logical one by the third stage 160 (e.g., 900 millivolts). The third stage 160 inverts the received logical one value, which causes the third stage 160 to switch low at transition 632. The transition of the third stage 160 output to switch is incorrect because the input signal with the largest magnitude of the first and second input signals (e.g., the waveform INM 610 and the waveform INP 620) did not change. Such an error can lead to incorrect processing of data, such that the incorrect processing can result in corrupted output data or other processing errors. When comparators are used in feedback loops to control external (e.g., external to the comparator 100) processes, for example, the external processes can disrupt the stability and accuracy of the feedback control signals, including signals within safety-critical systems.

[0104] The waveform Source 640 reaches a steady state value (e.g., near steady state value) at the end of the transition 642. At the end of the transition 642 (e.g., at time 602), the current starvation condition is alleviated, such that the waveform 1st_stage_out_plus 660 and the waveform 1st_stage_out_minus 670 rise. As the waveform 1st_stage_out_plus 660 and the waveform 1st_stage_out_minus 670 rise, at least one of the transistors Q12 and Q13 is more strongly biased (e.g., to increase conductivity). As at least one of the transistors Q12 and Q13 is more strongly biased, the output of the second stage 150 (e.g., the waveform 2nd_stage_output 680) falls to a level that can be quantized as a logical zero by the third stage 160. The third stage 160 inverts the received logical zero value, which causes the third stage 160 to switch high (e.g., back to a logically correct value) at transition 634. The transition 634 of the third stage 160 output restores the correct output value of the comparator 100 (e.g., after the current starvation condition during the transition 642 is alleviated).

[0105] At time 604, the simulation 600 approaches a steady state response. The waveform INM 610 is approximately 2.88 volts and the waveform INP 620 is approximately 2.90 volts. After the transition 642, the waveform Source 640 is maintained at a voltage of approximately 3.44 volts. The waveform Aux_bias 650 is maintained at a voltage of approximately 3.90 volts because the feedback control of the replica input transistor pair 120 circuit is disabled. The waveform 1st_stage_out_plus 660 is approximately 332 millivolts, the waveform 1st_stage_out_minus 670 is approximately 394 millivolts, and the waveform 2nd_stage_output 680 is approximately 217 millivolts.

[0106] The delay in comparator 100 during transition 642 may lead to erroneous performance (e.g., logically incorrect output values) during insufficient current conditions encountered, such as when at least one input signal undergoes a large transition (rather than a transition to a logically valid transition value used to indicate comparator 100). Analog 600 includes disabling the feedback control of the duplicate input transistor on circuit 120, allowing the logically erroneous behavior of the comparator under insufficient current conditions to be demonstrated. In analog 700 (where the feedback control of the duplicate input transistor on circuit 120 is not disabled as an analog parameter), comparator 100 selectively couples current from a current switch (e.g., current switch 140) to a common source node 114 (e.g., to more quickly mitigate insufficient current conditions that might otherwise result in erroneous output signals).

[0107] Figure 7 This is a waveform diagram of another example simulation of the comparator's response to a large input signal transition with low-power enhancement enabled. Example Simulation 700 includes waveforms used to illustrate the reference above. Figure 1 The waveforms represent a portion of the described comparator 100 in instance operation. The instance waveforms include waveforms INM 710, INP 720, Comp_Out 730, Source 740, Aux_bias 750, 1st_stage_out_plus 760, 1st_stage_out_minus 770, and 2nd_stage_output 780. The instance comparator in analog 700 is enabled for low-power boosted response to large input signal transitions.

[0108] Analog 700 demonstrates comparator 100's insufficient current response to the voltage transition of the first input signal to the first input signal value within a difference given by the input offset of the amplifier receiving the first and second input signals.

[0109] In Analog 700, waveform INM 710 is initially asserted (e.g., before the 10-microsecond mark of Analog 700) to ground potential, while waveform INP 720 is initially asserted to be at approximately 2.90 volts. Because the initial magnitude of waveform INP 720 is greater than the concurrent magnitude of waveform INM 710 (e.g., in the initial steady-state condition), waveform Comp_Out 730 is initially logic one (e.g., 1.42V). Waveform Comp_Out 730 is generated in response to the difference between waveform 1st_stage_out_minus 770 and waveform 2nd_stage_output 780, as described below.

[0110] Waveform Source (Common_Source_Node) 740 indicates that, in response to the current supplied by the first current source (e.g., current source I1) and in response to the current selectively controlled by transistors Q1 and Q2, the voltage of the common source node 114 is initially driven to a low voltage (e.g., 1.2 volts). For example, in response to waveform INM 710 being grounded, in response to waveform INP 720 being at approximately 2.90 volts, and in response to the common controlled current mirror of Q3 and Q4, waveform Source 740 is driven to a low voltage (e.g., 1.2 volts).

[0111] In response to current source I2, waveform Aux_bias 750 is driven to a value of approximately 3.90 volts. Waveform Aux_bias is unaffected by the Replica_load feedback signal from the replica input transistor to circuit 120 because the replica input transistor does not detect insufficient current at common source node 114 in circuit 120 (in the initial state). Transistor Q8 responds to the signal NCAS (“normalized cascode”). Figure 1 (as shown in the diagram) is biased to be on. When transistor Q8 is on, the feedback path of the feedback signal of the replica input transistor to the circuit 120 (e.g., including the signal Replica_load, the first and second current terminals of transistor Q8 and the signal Aux_bias) is coupled to a feedback circuit (e.g. for coupling the feedback signal to the common source node 114).

[0112] During the operation of comparator 100, the feedback signal to circuit 120 of the duplicate input transistor can be a voltage generated in response to the tail current of circuit 120 of the duplicate input transistor. In analog 700, the feedback signal is coupled to the gate of transistor Q7 (and via the drain of Q7 to the common source node 114), such that, for example, the response of the duplicate input transistor 120 can be observed. For example, "robust" operation (e.g., insensitivity to erroneous outputs from input signals having a voltage offset less than that of the amplifier) ​​can be demonstrated by the absence of a spurious output pulse in waveform Comp_Out 730 (see Comp_Out 630).

[0113] Waveform Aux_bias 750 is coupled to the control terminal (e.g., gate) of transistor Q7. In analog 700, transistor Q7 is enabled (in response to analog 700 input) to selectively apply current to common source node 114 (e.g., in response to feedback signals generated by replica input transistor pair 120 circuit). Because waveform Aux_bias 750 is initially about 3.90 volts in analog 700, PMOS transistor Q7 is in an off state such that no boost current is injected by current source Q7 into common source node 114 (e.g., of Ql and Q2).

[0114] Waveforms 1st_stage_out_plus 760 and 1st_stage_out_minus 770 are generated in response to first and second input signals, respectively. For example, waveform 1st_stage_out_plus 760 is initially about 169 millivolts (in response to waveform INM 710), and waveform 1st_stage_out_minus 770 is about 550 millivolts (in response to waveform INP 720).

[0115] In response to the difference of the input signals, waveform 2nd_stage_output 780 initially indicates that the magnitude of waveform 1st_stage_out_plus 760 is less than waveform 1st_stage_out_minus 770. The value of waveform 2nd_stage_output 780 (e.g., initially at ground potential) is received by third stage 160 and quantized (e.g., initially as an input logic zero) by the input gate of third stage 160. Third stage 160 buffers and inverts the input logic zero and outputs the buffered inverted value as waveform Comp_Out 730 (e.g., which is initially a logic one).

[0116] At 10 microseconds into analog 700, waveform INM 710 is driven (e.g., as an analog 700 input parameter) to undergo a large voltage transition 712 from ground potential to a voltage of about 2.88 volts. The rise of waveform INM 710 to a voltage of about 2.88 volts is still a level less than the magnitude of waveform INP 720, so waveform Comp_Out 730 does not ideally (e.g., without error) switch. The transition 712 of waveform INM 710 causes transients 722, 762, 772, and 782.

[0117] During transition 712, the gate voltage of transistor Ql rises to approximately 2.88 volts. After transition 712, the gate voltage of Ql remains lower than the contemporaneous gate voltage of Q2 (e.g., such that waveform Comp Out 730 fails to properly switch). Current source II is designed to supply current at a low maximum (e.g., by design to conserve power), such that the current produced by first stage 110 is insufficient to respond.

[0118] The current-starved-induced delay of common source node 114 of first stage 110 (e.g., which occurs during transition 742) also contributes to the stable delay of waveforms 1st_stage_out_plus 760 and 1st_stage_out_minus 770. For example, after transients 762 and 772, the voltages of waveforms 1st_stage_out_plus 760 and 1st_stage_out_minus 770 converge to a difference less than the input offset of the amplifier of second stage 150, which would otherwise cause an erroneous output of second stage 150.

[0119] The convergence of waveforms 1st_stage_out_plus 760 and 1st_stage_out_minus 770 to low voltages (e.g., near ground) helps ensure that NMOS transistors Q12 and Q13 are more negatively biased, such that transistors Q12 and Q13 do not conduct strongly. When transistors Q12 and Q13 do not conduct strongly during a current-starved condition (e.g., during transition 742), waveform 2nd_stage_output 780 rises (e.g., gradually rises in response to the drain current produced by the current mirror formed by transistors Q10 and Ql l).

[0120] As the output of second stage 150 (e.g., waveform 2nd_stage_output 780) rises in simulation 700, the output of second stage 150 is prevented from reaching a voltage that would be quantized as a logical one by third stage 160. As described below, the output of second stage 150 is prevented from reaching a voltage that would otherwise be quantized as a logical one by third stage 160. The rise to the logical one threshold of the output of second stage 150 is prevented by the current injection selectively coupled via current switch 140 (where the current injection mitigates the current-starved condition of common source node 114).

[0121] The replica input transistor pair 120 (e.g., coupled to the input of the input transistor pair 112) detects an undercurrent condition at the common source node 114. In response to the undercurrent condition, the tail current of the replica input transistor pair 120 is reduced. In response to the reduction in the tail current of the replica input transistor pair 120, less current is added to the current flowing through the drain of Q9. In response to less current being added to the current flowing through Q9, the voltage at the source of Q8 (waveform Aux_bias 750) drops (e.g., as a transition 752). For example, the transition 752 begins at about 40 nanoseconds after the undercurrent condition begins.

[0122] As the waveform Aux_bias 750 drops, the PMOS transistor (e.g., switch) Q7 increases conduction and adds current (selectively supplied via the current switch 140) to the common source node 114. Adding current to the common source node 114 via the current switch Q7 reduces the undercurrent condition at the common source node 114 and speeds up the rise of the waveform Source 740 during the transition 742.

[0123] As the waveform Source 740 rises to a steady state level (e.g., 3.6 volts) at about the end of the transition 742, the undercurrent condition of the common source node 114 is reduced. The replica input transistor pair 120 detects the reduction in the undercurrent condition of the common source node 114, and the tail current of the replica input transistor pair 120 increases. In response to the increase in the tail current of the replica input transistor pair 120, more current is added to the current flowing through the drain of Q9. In response to more current being added to the current flowing through Q9, the voltage at the source of Q8 (e.g., waveform Aux_bias 750) rises (e.g., as a transition 754). For example, the transition 754 begins in response to the waveform Source 740 rising to a steady state level (e.g., which occurs at about 98 nanoseconds after the undercurrent condition begins in the simulation 700).

[0124] As the waveform Aux_bias 750 rises during the transition 754, the PMOS transistor (e.g., switch) Q7 decreases conduction and gradually adds less current (from the current switch 140) to the common source node 114. The waveform Aux_bias 750 rises to a steady state level (e.g., 3.6 volts) after the comparator 100 responds (e.g., correctly responds) to the relative change in the first input signal that occurs at 10 microseconds into the simulation 700.

[0125] At time 704, the simulation 700 approaches a steady state response. The waveform INM 710 is approximately 2.88 volts and the waveform INP 720 is approximately 2.90 volts. After transition 742, the waveform Source 740 is maintained at a voltage of approximately 3.44 volts. Because the current switch Q7 is off, the waveform Aux_bias 750 is maintained at a voltage of approximately 3.90 volts. The waveform 1st_stage_out_plus 760 is approximately 331 millivolts, the waveform 1st_stage_out_minus 770 is approximately 392 millivolts, and the waveform 2nd_stage_output 780 is approximately 217 millivolts.

[0126] In the simulation 700 of the comparator 100, the feedback control of the replica input transistor pair 120 circuit detects an insufficient current condition at the common source node 114. In response to an indication of the insufficient current condition generated by the replica input transistor pair 120 circuit, the current switch 140 selectively couples current from the current switch 140 into the common source node 114, which accelerates the reduction of the insufficient current condition at the common source node 114. The acceleration of the reduction of the insufficient current condition at the common source node 114 prevents the waveforms 1st_stage_out_plus 760 and 1st_stage_out_minus 770 from converging to a difference that is less than the input offset of the second stage 150 amplifier. The prevention of the convergence of the waveforms 1st_stage_out_plus 760 and 1st_stage_out_minus 770 to a difference that is less than the input offset of the second stage 150 amplifier increases the robustness of the comparator pair against generating false output signals.

[0127] Figure 8 is a schematic diagram of another example Aux_bias generator for low power enhanced response of an example comparator. The example Aux_bias generator 830 of the circuit 800 includes transistors Q80, Q81, Q82, and Q83, and an inverter 832. The Aux_bias generator 830 is similar to the Aux_bias generator 130 described above, for example.

[0128] In at least one embodiment, PMOS transistors Q80 and Q81 are arranged as a current mirror, with current flowing through Q80 controlling current flowing through Q81. Current flowing through Q80 is controlled by a bias signal nbias, such that NMOS transistor Q81 is biased to conduct (e.g., turn on a channel for carrying) a first current "A" of magnitude "x" (e.g., xA). A replica_load_CG signal (e.g., a gate control signal for Q3 and Q4 generated by the first stage 110) is coupled to bias NMOS transistor Q83 in response to replica input transistor pair 120 circuitry to detect an undercurrent condition.

[0129] When the replica_load_CG signal indicates that there is no undercurrent condition, transistor Q83 is biased to conduct a current that is greater than, for example, the current supplied by transistor Q81 by 50% (1.5 x A). Because the biased current capacity of Q83 is greater than the biased current capacity of Q81, the voltage developed between the respective drains of Q81 and Q83 is quantized by inverter 832 as a logic zero. In response, inverter 832 outputs a logic one, causing PMOS transistor Q7 to be turned off and current switch 140 to not inject additional current into common source node 114.

[0130] When the replica_load_CG signal indicates that there is an undercurrent condition, transistor Q83 is biased to not conduct (and / or to conduct a small amount of current that causes inverter 832 to switch, for example). When transistor Q83 is biased to not conduct, the voltage developed between the respective drains of Q81 and Q83 is quantized by inverter 832 as a logic one. In response, inverter 832 outputs a logic zero, causing PMOS transistor Q7 to be turned off and current switch 140 to be coupled to inject additional current into common source node 114 (e.g., thus the undercurrent condition of common source node 114 is mitigated).

[0131] For example, the replica_loadz_CG signal can indicate that there is an undercurrent condition by reducing the voltage level of the replica_load_CG signal (e.g., such that NMOS transistor Q83 is arranged to conduct less and / or be turned off). When the voltage of the replica load signal is reduced to a voltage level selected to indicate that there is an undercurrent condition, Aux_bias generator 830 is coupled to assert a bias signal to activate current switch 140 (e.g., in response to a decrease in the indicated voltage received from the replica_load_CG signal node). Thus, the current of the replica load signal can be reduced in response to a voltage drop of the common source node.

[0132] Figure 9is an example method of an example low-power comparator's response to fluctuations in an input signal. Process 910 of example method 900 includes generating, by a first stage, a first stage output signal in response to an input signal. The input signal is coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal.

[0133] Process 920 includes generating, by a replica input transistor pair, a replica load signal in response to the input signal and in response to a current received from the common node. In an example, the replica load signal is generated in response to detecting an insufficient response of an input transistor pair arranged to generate the first stage output signal. In another example, the replica load signal is generated in response to an emulation of the input transistor pair.

[0134] Process 930 includes selectively coupling a second current from a second current source to the common node in response to the replica load signal.

[0135] Various examples of comparators with lower power consumption and reduced latency (and example operations thereof) are described herein with respect to the accompanying figures. The value of lower power consumption and reduced latency can be the product of the power consumed and the latency reduced (e.g., power * delay). In various simulations described above, a three-fold improvement in delay of comparators of the same power has been observed. In cases where the input signal is within a narrow margin, the synergy of increased robustness with reduced power and latency (e.g., described above with respect to simulation 700) can extend the value three-fold or more.

[0136] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A circuit comprising: First input terminal; Second input terminal; The input transistor pair includes: The first transistor includes: First current terminal; Second current terminal; and Control terminal, which is coupled to the first input terminal; and The second transistor includes: A first current terminal is coupled to a first current terminal of the first transistor, wherein the first current terminal of the first transistor and the first current terminal of the second transistor are configured to receive current from a first current source, wherein a control terminal of the first transistor is coupled to a first input signal of the input transistor pair; and Second current terminal; and A control terminal, which is coupled to the second input terminal; The replica circuit includes: The third transistor includes: First current terminal; Second current terminal; and Control terminal, which is coupled to the first input terminal; and The fourth transistor includes: A first current terminal is coupled to the first current terminal of the first transistor, the first current terminal of the second transistor, and the first current terminal of the third transistor. A second current terminal, which is coupled to the second current terminal of the third transistor; and Control terminal, which is coupled to the second input terminal; and A current switch, comprising: The first current terminal is coupled to the power supply terminal. A second current terminal is coupled to the first current terminal of the first transistor, the first current terminal of the second transistor, the first current terminal of the third transistor, and the first current terminal of the fourth transistor; and Control terminals.

2. The circuit of claim 1, wherein the replica circuit is configured to determine the performance of the input transistor pair to produce the determined performance.

3. The circuit of claim 2, wherein the indicator of determined performance is coupled to the control terminal of the current switch.

4. The circuit of claim 2, wherein the replica circuit is configured to detect insufficient current at the first current terminal of the first transistor and the first current terminal of the second transistor.

5. The circuit of claim 1, further comprising a bias generator configured to generate a bias signal in response to an indication received from the second current terminal of the third transistor and the second current terminal of the fourth transistor.

6. The circuit of claim 5, wherein the bias signal is asserted to activate the current switch in response to a decrease in the indicated current received from the second current terminal of the third transistor and the second current terminal of the fourth transistor.

7. The circuit of claim 5, wherein the current switch is configured to selectively couple current from a second current source to the first current terminal of the first transistor, the first current terminal of the second transistor, the first current terminal of the third transistor, and the first current terminal of the fourth transistor in response to the bias signal.

8. The circuit of claim 1, further comprising a current mirror, the current mirror comprising: A first input terminal, which is coupled to the second current terminal of the first transistor; and The second input terminal is coupled to the second current terminal of the second transistor.

9. The circuit of claim 8, further comprising: The first resistor includes: A first terminal, which is coupled to the first input terminal of the current mirror; and Second terminal; and The second resistor includes: A first terminal, which is coupled to the second input terminal of the current mirror; and The second terminal is coupled to the second terminal of the first resistor.

10. The circuit of claim 8, further comprising a second stage, wherein the current mirror is a first current mirror, and wherein the second stage includes a second current mirror, the second current mirror comprising: The main transistor is based on a signal at the first input terminal of the first current mirror; and The second-stage output signal is generated in response to a signal at the first input terminal of the first current mirror and in response to the current supplied by the transistor.

11. The circuit of claim 10, wherein the second stage is the differential input of a single-ended output converter.

12. The circuit of claim 10, further comprising a third stage, the third stage being configured to: Quantize the second-stage output signal to convert it into a digital value; and A digital signal is output in response to the digital value.

13. A circuit comprising: A first-stage amplifier coupled to receive an input signal, wherein the first-stage amplifier includes a common node that couples a first current from a first current source to at least one transistor of the first-stage amplifier, wherein the first-stage amplifier is coupled to generate a first-stage output signal in response to the input signal. A replica circuit, coupled to receive current from the common node and arranged to generate a replica load signal in response to the input signal; A bias generator, coupled to generate a bias signal in response to the composite load signal; A current switch is arranged to selectively couple a second current from a second current source to the common node in response to the bias signal; and A second-stage amplifier is coupled to convert the differential input received from the first-stage amplifier into a single-ended output of the second-stage amplifier.

14. The circuit of claim 13, wherein the bias generator is coupled to assert the bias signal in response to a decrease in the voltage of the replica load signal to activate the current switch.

15. The circuit of claim 13, further comprising the first and second current sources, wherein the first and second current sources are coupled in parallel between the power rail and the common node.

16. The circuit of claim 13, further comprising an output stage coupled to generate an output signal in response to the single-ended output of the second stage amplifier.

17. A method comprising: A first-stage amplifier generates a first-stage output signal in response to an input signal, wherein the input signal is coupled to control a first current coupled from a first current source through a common node to generate the first-stage output signal; A duplicate load signal is generated by a duplicate input transistor in response to the input signal and the current received from the common node; In response to the duplicate load signal, a second current from the second current source is selectively coupled to the common node; and The differential input is received from the first stage amplifier by the second stage amplifier, and the differential input is converted into a single-ended output of the second stage amplifier.

18. The method of claim 17, wherein the replica load signal is generated in response to detecting insufficient current in the input transistor pair arranged to generate the first stage output signal.

19. The method of claim 18, wherein the replica load signal is generated in response to the simulation of the input transistor pair.

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