Comparator circuits, semiconductor devices

Abstract

The comparison circuit outputs an output voltage of a first logic level when an input voltage exceeds a first threshold voltage, and outputs an output voltage of a second logic level when the input voltage is lower than a second threshold voltage lower than the first threshold voltage. The comparison circuit includes: a conversion circuit that converts the input voltage into a first voltage and a second voltage lower than the first voltage; and a logic circuit that outputs the output voltage of the first logic level when the first voltage exceeds a third threshold voltage, and outputs the output voltage of the second logic level when the second voltage is lower than a fourth threshold voltage lower than the third threshold voltage.

Description

Technical Field

[0001] The present invention relates to a comparison circuit and a semiconductor device. Background Art

[0002] As a circuit for detecting a logic signal, a comparator circuit is generally used, which uses a Schmitt trigger circuit having a hysteresis characteristic (for example, Patent Document 1).

[0003] There are also hysteresis comparators using differential comparators as shown below, which can adjust hysteresis characteristics (Patent Documents 2 and 3).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 6-53783

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 2002-300011

[0008] Patent Document 3: Japanese Patent Application Laid-Open No. 10-209823 Summary of the Invention

[0009] Technical problem to be solved by the invention

[0010] Furthermore, for example, when a Schmitt trigger circuit as disclosed in Patent Document 1 is used as a comparison circuit, the hysteresis characteristic is determined by the threshold voltage of the MOS transistor of the Schmitt trigger circuit, making it difficult to change the hysteresis characteristic.

[0011] Furthermore, since the hysteresis comparator disclosed in Patent Documents 2 or 3 requires a differential comparator, bias current continues to flow during comparison, resulting in high power consumption. Furthermore, the area of ​​the comparator itself also increases.

[0012] The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a comparison circuit capable of changing hysteresis characteristics.

[0013] Technical means for solving technical problems

[0014] In the comparison circuit method of the present invention for solving the above-mentioned technical problem, the comparison circuit outputs an output voltage of a first logic level when the input voltage exceeds a first threshold voltage, and outputs the output voltage of a second logic level when the input voltage is lower than a second threshold voltage which is lower than the first threshold voltage. The comparison circuit includes: a conversion circuit which converts the input voltage into a first voltage and a second voltage which is lower than the first voltage; and a logic circuit which outputs the output voltage of the first logic level when the first voltage exceeds a third threshold voltage, and outputs the output voltage of the second logic level when the second voltage is lower than a fourth threshold voltage which is lower than the third threshold voltage.

[0015] In an embodiment of a semiconductor device according to the present invention, the semiconductor device includes: a power supply circuit that generates a low power supply voltage lower than the power supply voltage based on a power supply voltage; a detection circuit that operates at the low power supply voltage and detects a control signal for driving a switching element of an upper arm and a switching element of a lower arm; and a drive circuit that drives the switching element of the upper arm and the switching element of the lower arm based on a detection result of the detection circuit. The detection circuit includes a comparison circuit that outputs the detection result of a first logic level when the voltage level of the control signal exceeds a first threshold voltage, and outputs the detection result of a second logic level when the voltage level of the control signal is lower than a second threshold voltage lower than the first threshold voltage. The comparison circuit includes a conversion circuit that converts the voltage level of the control signal into a first voltage and a second voltage lower than the first voltage; and a logic circuit that outputs the detection result of the first logic level when the first voltage exceeds a third threshold voltage, and outputs the detection result of the second logic level when the second voltage is lower than a fourth threshold voltage lower than the third threshold voltage.

[0016] Effects of the Invention

[0017] According to the present invention, it is possible to provide a comparison circuit capable of changing hysteresis characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a diagram showing an example of the structure of the power module 10 .

[0019] Figure 2 1 is a diagram showing an example of the structure of the HVIC 20 .

[0020] Figure 3 1 is a diagram showing a configuration of a comparison circuit 21 a which is one embodiment of the comparison circuit 21 .

[0021] Figure 4 1 is a diagram showing an example of the configuration of the logic circuit 50 .

[0022] Figure 5 1 is a diagram for explaining the operation of the logic circuit 50 .

[0023] Figure 6 2 is a diagram showing changes in the threshold value when the comparison circuit 21 a is used.

[0024] Figure 7 2 is a diagram showing an example of the configuration of the comparison circuit 21 b.

[0025] Figure 8 2 is a diagram showing an example of the configuration of the comparison circuit 21 c. DETAILED DESCRIPTION

[0026] Cross-reference to related applications

[0027] This application claims priority based on Japanese Patent Application No. 2019-218974 filed on December 3, 2019, and cites the contents thereof.

[0028] At least the following matters are clarified from the description of this specification and the drawings.

[0029] ======Present embodiment======

[0030] Power Module 10

[0031] Figure 1 This figure shows an example of the structure of a power module 10, which is one embodiment of the present invention. Power module 10 includes power semiconductors and a drive circuit for power conversion, and is, for example, a semiconductor device that drives a load 11. Power module 10 includes a capacitor 14 for generating a bootstrap voltage Vb, an HVIC 20, a bridge circuit 30, and terminals PWR, D, P, S, N, and COM.

[0032] A power supply voltage VCC is applied to a terminal PWR, and a control signal IN from an MCU (not shown) is input to a terminal D. A load 11 is connected between a terminal S and a terminal N. A power supply voltage Vdc is applied to a terminal P, and a capacitor 12 for stabilizing the power supply voltage Vdc is connected between the terminals P and N.

[0033] The HVIC 20 receives a control signal IN from an MCU (not shown) and outputs drive signals HO and LO to the bridge circuit 30 to drive the bridge circuit 30 .

[0034] The bridge circuit 30 drives the load 11 (eg, an inductor) based on the drive signals HO and LO from the HVIC 20. The bridge circuit 30 includes NMOS transistors 31 and 32. The NMOS transistors 31 and 32 correspond to "switching elements."

[0035] <HVIC20>

[0036] Figure 2 This figure shows an example of the structure of an HVIC 20. The HVIC (High Voltage Integrated Circuit) 20 includes a comparator circuit 21, an inverter 22, a filter circuit 23, a pulse generator circuit 24, a high-side driver circuit 25, a power supply circuit 26, a low-side driver circuit 27, and terminals PVCC, DS, VB, H, VS, L, and G.

[0037] The comparison circuit 21 is an input detection circuit that detects the input control signal IN, inverts the control signal IN, and outputs it. Furthermore, for example, in this embodiment, the control signal IN varies within a range of 0 to 15V. Therefore, the comparison circuit 21 is composed of high-voltage components. Furthermore, the control signal IN is a rectangular wave that varies between 0 and 15V. When the control signal IN is at a high level (hereinafter referred to as an "H" level), the NMOS transistor 31 of the upper arm is turned on, and when the control signal IN is at a low level (hereinafter referred to as an "L" level), the NMOS transistor 32 of the lower arm is turned on.

[0038] The inverter 22 inverts the output of the comparison circuit 21 and outputs the inverted output to the filter circuit 23 .

[0039] The filter circuit 23 includes, for example, a low-pass filter (not shown), and outputs a signal S obtained by removing noise from a signal output from the inverter 22 .

[0040] The pulse generating circuit 24 generates a set signal set at a rising edge of the signal S and generates a reset signal reset at a falling edge.

[0041] The high-side driver circuit 25 outputs a drive signal HO for driving the NMOS transistor 31 of the upper arm through a terminal H based on the set signal set and the reset signal reset from the pulse generation circuit 24 .

[0042] The power supply circuit 26 is, for example, a step-down regulator, which steps down the power supply voltage VCC (e.g., 15V) from the terminal PVCC to generate a low power supply voltage VDD (e.g., 5V), and supplies it to the comparison circuit 21 , the inverter 22 , the filter circuit 23 , and the pulse generation circuit 24 .

[0043] The low-side driver circuit 27 outputs a drive signal LO for driving the NMOS transistor 32 of the lower arm through a terminal L based on the signal S from the filter circuit 23 .

[0044] <Comparison Circuit 21>

[0045] ===Comparison Circuit 21a of This Embodiment==

[0046] Figure 3 1 is a diagram showing a configuration of a comparison circuit 21 a which is one embodiment of the comparison circuit 21 .

[0047] When the voltage level of the control signal IN changes from a low voltage level (e.g., 0V) to a high voltage level (e.g., VDD) and exceeds a high threshold voltage VtH, the comparator circuit 21a changes the logic level of the output voltage Vout from an "H" level to a "L" level. Furthermore, when the voltage level of the control signal IN changes from a high voltage level to a low voltage level and falls below a low threshold voltage VtL, the comparator circuit 21a changes the logic level of the output voltage Vout from an "L" level to a "H" level. The comparator circuit 21a includes a voltage conversion circuit 40a and a logic circuit 50.

[0048] The voltage conversion circuit 40 a converts the voltage generated at the node N1 to which the control signal IN is input into a voltage VNG and a voltage VPG lower than the voltage VNG. Hereinafter, the voltage generated at the node N1 is referred to as an input voltage Vin.

[0049] Voltage conversion circuit 40a includes resistors 41 to 44. Resistors 41 to 44 are connected in series between a node to which low power supply voltage VDD is applied and ground. When input voltage Vin is applied to node N1, voltage conversion circuit 40a generates voltage VNG at the connection point between resistors 41 and 42, and generates voltage VPG at the connection point between resistors 43 and 44.

[0050] Voltage VNG is applied to the gate electrodes of NMOS transistors 51 and 52 , which are inputs of the logic circuit 50 , and voltage VPG is applied to the gate electrodes of PMOS transistors 54 and 55 , which are inputs of the logic circuit 50 .

[0051] Here, assuming that the resistance values ​​of the resistors 41 to 44 are R1 , R2 , R3 , and R4 , the voltage VNG and the voltage VPG are calculated as follows.

[0052] VNG=(R1 / (R1+R2))×Vin+(R2 / (R1+R2))×VDD···(1)

[0053] VPG=(R4 / (R3+R4))×Vin···(2)

[0054] The logic circuit 50 is a Schmitt trigger circuit that changes the logic level of the output voltage Vout with hysteresis characteristics according to changes in the voltage levels of voltages VNG and VPG. The logic circuit 50 includes NMOS transistors 51 to 53 and PMOS transistors 54 to 56.

[0055] NMOS transistors 51 and 52 and PMOS transistors 54 and 55 are connected in series between a power supply node to which low power supply voltage VDD is applied and ground, in the order of PMOS transistors 55 and 54, and NMOS transistors 52 and 51, from the power supply side. Furthermore, voltage VNG is applied to the gate electrodes of NMOS transistors 51 and 52, which serve as inputs to logic circuit 50, and voltage VPG is applied to the gate electrodes of PMOS transistors 54 and 55.

[0056] The output voltage Vout output from the connection point between the NMOS transistor 52 and the PMOS transistor 54 is applied to the gate electrode of the NMOS transistor 53 , the low power supply voltage VDD is applied to the drain terminal of the NMOS transistor 53 , and the source of the NMOS transistor 53 is connected to the connection point between the NMOS transistors 51 and 52 .

[0057] The output voltage Vout is applied to the gate electrode of the PMOS transistor 56 . The drain terminal of the PMOS transistor 56 is grounded, and the source of the PMOS transistor 56 is connected to the connection point between the PMOS transistors 54 and 55 .

[0058] Furthermore, the maximum value of the voltage of the control signal IN is higher than the power supply voltage of the logic circuit 50. Therefore, the NMOS transistors 51 to 53 and the PMOS transistors 54 to 56 are formed of high-voltage MOS transistors.

[0059] In the present embodiment, the resistance values ​​R1 to R4 have resistance values ​​that turn off either the group of PMOS transistors 54 and 55 or the group of NMOS transistors 51 and 52 when the input voltage Vin is not applied to the node N1 .

[0060] Resistors 41 to 44 correspond to the "first resistor," "second resistor," "third resistor," and "fourth resistor," respectively. Voltage VNG corresponds to the "first voltage," and voltage VPG corresponds to the "second voltage." NMOS transistors 51 and 52 correspond to "two NMOS transistors," and PMOS transistors 54 and 55 correspond to "two PMOS transistors." The logic level of output voltage Vout corresponds to the "detection result."

[0061] Furthermore, the logic circuit 50 operates at a low power supply voltage VDD (eg, 5 V) that is lower than the maximum value of the input voltage Vin (eg, 15 V).

[0062] ==Basic Operation of Logic Circuit 50==

[0063] Here, in order to explain the basic operation of the Schmitt trigger circuit, the gates of the two NMOS transistors 51 and 52 and the two PMOS transistors 54 and 55 of the logic circuit 50 are common. Figure 4 Here, the voltage applied to the gates of the two NMOS transistors 51 and 52 and the two PMOS transistors 54 and 55 of the logic circuit 50 is referred to as input voltage Vin_org.

[0064] <<Description of Operation of Logic Circuit 50>>

[0065] Figure 5 1 is a diagram illustrating the operation of the logic circuit 50. Figure 5 , the operations of the NMOS transistors 51 to 53 and the PMOS transistors 54 to 56 of the logic circuit 50 will be described.

[0066] A straight line indicated by a dotted line indicates the relationship between the input voltage Vin_org input to the logic circuit 50 and the applied voltages applied to the gate electrodes of the NMOS transistors 51 and 52 and the PMOS transistors 54 and 55 .

[0067] First, let's describe the case X where the input voltage Vin_org changes from X1 to X3. At X1, the input voltage Vin_org is 0V. At this point, NMOS transistors 51 and 52 are off, and NMOS transistor 53 is on. Meanwhile, PMOS transistors 54 and 55 are on, and PMOS transistor 56 is off. Consequently, the output voltage Vout reaches the power supply voltage VDD.

[0068] At X2, where the input voltage Vin_org is higher than X1, NMOS transistor 51 is turned on, NMOS transistor 52 is turned off, and NMOS transistor 53 is turned on. Meanwhile, PMOS transistors 54 and 55 are turned off, and PMOS transistor 56 is turned off. Because the parasitic capacitors at the nodes to which the output voltage Vout is applied are directly charged, the output voltage Vout remains constant at the power supply voltage VDD.

[0069] When the input voltage Vin_org exceeds the voltage at point X2, NMOS transistors 51 and 52 turn on, while NMOS transistor 53 turns off. Meanwhile, PMOS transistors 54 and 55 turn off, while PMOS transistor 56 turns on. At this point, the output voltage Vout changes from the power supply voltage VDD to 0V. Therefore, the voltage value of the input voltage Vin_org at this time becomes the high threshold voltage VtH_org. Furthermore, when the input voltage Vin_org reaches the high threshold voltage VtH_org of the logic circuit 50, the voltage applied to the gate electrodes of the NMOS transistors 51 and 52 reaches the voltage level indicated by point A1 (i.e., VtH_org). At this point, the output voltage Vout changes from the "H" level to the "L" level via point A1.

[0070] At X3, the input voltage Vin_org reaches a voltage higher than the power supply voltage VDD (e.g., 15V). At this point, NMOS transistors 51 and 52 are turned on, while NMOS transistor 53 is turned off. Meanwhile, PMOS transistors 54 and 55 are turned off, while PMOS transistor 56 is turned on. Therefore, the output voltage Vout remains at 0V.

[0071] Next, we will describe the case Y where the input voltage Vin_org changes from Y1 to Y3. At Y1, the input voltage Vin_org reaches a voltage higher than the power supply voltage VDD (e.g., 15V). At this point, PMOS transistors 54 and 55 are turned off, while PMOS transistor 56 is turned on. Meanwhile, NMOS transistors 51 and 52 are turned on, while NMOS transistor 53 is turned off. Consequently, the output voltage Vout reaches 0V.

[0072] At Y2, where input voltage Vin_org is lower than Y1, PMOS transistor 54 is off, PMOS transistor 55 is on, and PMOS transistor 56 is on. Meanwhile, NMOS transistors 51 and 52 are off, and NMOS transistor 53 is off. Because the parasitic capacitors at the nodes to which output voltage Vout is applied are discharged directly, output voltage Vout remains at 0V.

[0073] When the input voltage Vin_org falls below the voltage at point Y2, PMOS transistors 54 and 55 turn on, and PMOS transistor 56 turns off. Meanwhile, NMOS transistors 51 and 52 turn off, and NMOS transistor 53 turns on. Consequently, the output voltage Vout changes from 0V to the power supply voltage VDD. Therefore, the voltage value of the input voltage Vin_org at this point becomes the low threshold voltage VtL_org. Furthermore, when the input voltage Vin_org reaches the low threshold voltage VtL_org of the logic circuit 50, the voltage applied to the gate electrodes of the PMOS transistors 54 and 55 reaches the voltage level shown at point B1 (i.e., VtL_org). At this point, the output voltage Vout changes from the "L" level to the "H" level via point B1.

[0074] At Y3, the input voltage Vin_org is 0 V. At this time, PMOS transistors 54 and 55 are on, and PMOS transistor 56 is off. On the other hand, NMOS transistors 51 and 52 are off, and NMOS transistor 53 is on. Therefore, the output voltage Vout remains constant at the power supply voltage VDD.

[0075] Therefore, when the voltage level of the input voltage Vin_org of the logic circuit 50 changes from a low voltage level (e.g., 0V) to a high voltage level (e.g., VDD) and exceeds the high threshold voltage VtH_org, the logic level of the output voltage Vout changes from an "H" level to an "L" level (case X). Furthermore, when the voltage level of the input voltage Vin_org of the logic circuit 50 changes from a high voltage level to a low voltage level and falls below the low threshold voltage VtL_org, the logic level of the output voltage Vout changes from an "L" level to an "H" level (case Y).

[0076] <<Calculation of Threshold Voltage of Logic Circuit 50>>

[0077] As described above, logic circuit 50 has hysteresis characteristics implemented by a high threshold voltage VtH_org and a low threshold voltage VtL_org. The high threshold voltage VtH_org is determined when NMOS transistors 51 and 52 are simultaneously on. The low threshold voltage VtL_org is determined when PMOS transistors 54 and 55 are simultaneously on.

[0078] That is, the high threshold voltage VtH_org is determined based on the threshold voltage vtn of each of the NMOS transistors 51 and 52 , and the low threshold voltage VtL_org is determined based on the threshold voltage vtp of each of the PMOS transistors 54 and 55 .

[0079] Here, the threshold voltages of the PMOS transistors 54 and 55 are assumed to be the same vtp, but the threshold voltages of the PMOS transistors 54 and 55 may be different. The threshold voltages vtn of the NMOS transistors 51 and 52 are also the same.

[0080] Hereinafter, how the high threshold voltage VtH_org is determined by the threshold voltage vtn will be described. Similarly, how the low threshold voltage VtL_org is determined by the threshold voltage vtp will also be described.

[0081] First, in order to express the high threshold voltage VtH_org using the threshold voltage vtn, a case will be described where the input voltage Vin changes from a low voltage (for example, 0 V) ​​to a high voltage (for example, VDD).

[0082] exist Figure 4 The logic circuit 50 is described using a circuit including NMOS transistors 51 to 53. When the gate-source voltages of NMOS transistors 51, 52, and 53 are represented by VGS51, VGS52, and VGS53, respectively, the circuits are expressed as follows. Here, the voltage at the connection point between NMOS transistors 51 and 52 is represented by voltage Vx.

[0083] VGS51=Vin_org···(3)

[0084] VGS52=Vin_org-Vx···(4)

[0085] VGS53=Vout-Vx···(5)

[0086] exist Figure 5 At X1 of FIG. 1 , when the input voltage Vin_org is 0 V, the NMOS transistors 51 and 52 are turned off, and the NMOS transistor 53 is turned on.

[0087] When the input voltage Vin approaches the threshold voltage vtn of the NMOS transistor 51, the NMOS transistor 51 is turned on, and the drain current flowing into the NMOS transistor 53 and the drain current flowing into the NMOS transistor 51 become equal.

[0088] In this case, the following formula (6) holds true.

[0089] β3×(VDD-Vx-vtn)^2 / 2=β1×(Vin_org-vtn)^2 / 2···(6)

[0090] Here, β1 and β3 are coefficients determined by the physical structures of the NMOS transistors 51 and 53. For example, β = μCoxW / L, where μ is mobility, Cox is the capacitance per unit area of ​​the gate oxide film, W is the gate width, and L is the gate length.

[0091] In order to obtain the voltage Vx, the equation (6) is transformed as follows.

[0092] Vx=VDD+(√(β1 / β3)-1)×vtn-√(β1 / β3)×Vin_org···(7)

[0093] When the input voltage Vin reaches a higher voltage, further reaching the high threshold voltage VtH_org, and VGS52 = Vin_org - Vx = vtn, NMOS transistor 52 turns on. Since NMOS transistors 51 and 52 are turned on, the output voltage Vout becomes 0 V. When the input voltage Vin_org at this time is VtH_org, the following equation (8) holds.

[0094] VtH_org-VDD-(√(β3 / β1)-1)×vtn+√(β3 / β1)×VtH_org=vtn···(8)

[0095] When VtH_org is obtained according to equation (8), the following equation (9) holds.

[0096] VtH_org=(VDD+√(β1 / β3)×vtn) / (1+√(β1 / β3))=(√(β3 / β1)×VDD+vtn) / (1+√(β3 / β1))···(9)

[0097] When the NMOS transistors 51 and 52 are turned on, Vx=Vout=0 and VGS53=0, so the NMOS transistor 53 is turned off.

[0098] Next, in order to express the low threshold voltage VtL_org using the threshold voltage vtp, a case where the input signal Vin_org changes from a high voltage to a low voltage will be described. Here, the threshold voltage vtp is a negative value.

[0099] exist Figure 4 The logic circuit 50 is described using a circuit including PMOS transistors 54 to 56. When the gate-source voltages of PMOS transistors 54, 55, and 56 are represented by VGS54, VGS55, and VGS56, respectively, the following are expressed. Here, the voltage at the connection point between PMOS transistors 54 and 55 is represented by voltage Vy.

[0100] VGS54=Vin_org-Vy···(10)

[0101] VGS55=Vin_org-VDD···(11)

[0102] VGS56=Vout-Vy···(12)

[0103] When the input voltage Vin_org is VDD, the PMOS transistors 54 and 55 are turned off, and the PMOS transistor 56 is turned on. At this time, Vout=0, Vy=vtp.

[0104] When the input voltage Vin_org approaches VDD+vtp, the PMOS transistor 55 is turned on, and the drain current flowing into the PMOS transistor 56 and the drain current flowing into the PMOS transistor 55 become equal.

[0105] In this case, the following formula (13) holds true.

[0106] β5×(Vin_org-VDD-vtp)^2 / 2=β6×(―Vy-vtp)^2 / 2···(13)

[0107] Here, β5 and β6 are coefficients determined by the physical structures of the PMOS transistors 55 and 56. For example, β = μCoxW / L, where μ is mobility, Cox is the capacitance per unit area of ​​the gate oxide film, W is the gate width, and L is the gate length.

[0108] In order to obtain the voltage Vy, the equation (13) is transformed as follows.

[0109] Vy=√(β5 / β6)×VDD+(√(β5 / β6)-1)×vtp-√(β5 / β6)×Vin_org···(14)

[0110] When the input voltage Vin_org becomes lower, VGS54 = Vin_org - Vy = vtp, the PMOS transistor 54 turns on. Since the PMOS transistors 54 and 55 turn on, the output voltage Vout reaches VDD. When the input voltage Vin_org at this time is VtL_org, the following equation (15) holds.

[0111] VtL_org-√(β5 / β6)×VDD-(√(β5 / β6)-1)×vtp+√(β5 / β6)×VtL_org=vtp···(15)

[0112] When VtL_org is obtained according to equation (15), the following equation (16) holds.

[0113] VtL_org=(√(β5 / β6)×VDD+√(β5 / β6)×vtp) / (1+√(β5 / β6))=(VDD+vtp) / (1+√(β6 / β5))···(16)

[0114] In addition, when the PMOS transistors 54 and 55 are turned on, Vy=Vout=VDD, VGS56=0, and therefore the PMOS transistor 56 is turned off.

[0115] As can be seen from the above, the high threshold voltage VtH_org is a voltage corresponding to the threshold voltage vtn of each of the NMOS transistors 51 and 52 , and the low threshold voltage VtL_org is a voltage corresponding to the threshold voltage vtp of each of the PMOS transistors 54 and 55 .

[0116] <<Calculation of Threshold Voltage of Comparison Circuit 21a>>

[0117] In the comparison circuit 21 a , a voltage VNG is applied to the gate electrodes of the NMOS transistors 51 and 52 , and a voltage VPG is applied to the gate electrodes of the PMOS transistors 54 and 55 .

[0118] Therefore, when voltage VNG changes from a low voltage to a high voltage, if it exceeds the high threshold voltage VtH_org, the logic level of output voltage Vout changes from an "H" level to an "L" level. Similarly, when voltage VPG changes from a high voltage to a low voltage, if it falls below the low threshold voltage VtL_org, the logic level of output voltage Vout changes from an "L" level to an "H" level.

[0119] Therefore, when the high threshold voltage VtH_org of the logic circuit 50 is applied to the logic circuit 50, when the voltage level of the control signal IN of the comparison circuit 21a becomes the threshold voltage VtH as the input voltage Vin,

[0120] VtH_org=(R1 / (R1+R2))×VtH+(R2 / (R1+R2))×VDD···(17)

[0121] When the high threshold voltage VtH is calculated according to equation (17), it becomes as follows.

[0122] VtH=((R1+R2) / R1)×VtH_org-(R2 / R1)×VDD···(18)

[0123] Similarly, when the low threshold voltage VtL_org of the logic circuit 50 is applied to the logic circuit 50, when the voltage level of the control signal IN of the comparison circuit 21a becomes the threshold voltage VtL as the input voltage Vin,

[0124] VtL_org=(R4 / (R3+R4))×VtL···(19)

[0125] When the low threshold voltage VtL is calculated according to equation (19), it becomes as follows.

[0126] VtL=((R3+R4) / R4)×VtL_org···(20)

[0127] As described above, the high threshold voltage VtH and low threshold voltage VtL of the comparator circuit 21a can be set to values ​​different from the high threshold voltage VtH_org and low threshold voltage VtL_org of the logic circuit 50. Furthermore, when the comparator circuit 21a is used, the high threshold voltage VtH and low threshold voltage VtL of the comparator circuit 21a can be changed by changing the resistance values ​​R1 to R4 of the resistors 41 to 44. Therefore, the hysteresis characteristics of the logic circuit 50 can be varied.

[0128] Furthermore, when the input voltage Vin increases and reaches the high threshold voltage VtH of the comparison circuit 21a, the resistance values ​​R3 and R4 of resistors 43 and 44 are designed so that the voltage VPG is higher than the low threshold voltage VtL_org. On the other hand, when the input voltage Vin decreases and reaches the low threshold voltage VtL of the comparison circuit 21a, the resistance values ​​R1 to R4 of resistors 41 and 44 are designed so that the voltage VNG is lower than the high threshold voltage VtH_org.

[0129] Therefore, even if the input signal Vin changes, as described in the description of the operation of the logic circuit 50 , the NMOS transistors 51 to 53 and the PMOS transistors 54 to 56 operate.

[0130] In addition, sometimes the "L" level corresponds to the "first logic level" and the "H" level corresponds to the "second logic level", and conversely, sometimes the "H" level corresponds to the "first logic level" and the "L" level corresponds to the "second logic level".

[0131] <<Comparison of Input / Output Characteristics between Comparison Circuit 21a and Logic Circuit 50>>

[0132] Figure 6 2 is a diagram showing changes in the threshold value when the comparison circuit 21 a is used. Figure 6 In FIG. 1 , a straight line indicated by a dotted line represents a relationship between an input voltage Vin_org input to the logic circuit 50 and applied voltages applied to the gate electrodes of the NMOS transistors 51 and 52 and the PMOS transistors 54 and 55 .

[0133] The dashed line represents the change in voltage VNG relative to input voltage Vin to comparator circuit 21a. Specifically, the dashed line represents the change in voltage applied to the gate electrodes of NMOS transistors 51 and 52 relative to input voltage Vin.

[0134] The straight line shown by the two-dot chain line represents the change in voltage VPG relative to input voltage Vin to comparator circuit 21a. Specifically, the straight line shown by the two-dot chain line represents the change in voltage applied to the gate electrodes of PMOS transistors 54 and 55 relative to input voltage Vin. The straight line showing voltages VNG and VPG is an example of a case where the relationship between the resistance values ​​R1 to R4 of resistors 41 to 44 is R2:R1=R3:R4=1:2.

[0135] Hereinafter, the relationship between the input voltage Vin, the high threshold voltage VtH, and the low threshold voltage VtL of the comparison circuit 21 a in the case of the comparison circuit 21 a will be described.

[0136] First, when the input voltage Vin changes from a low voltage (e.g., 0V) to a high voltage (e.g., VDD), and the voltage VNG reaches the same voltage level as the voltage level shown at point A1, namely, the voltage level shown at point A2 (i.e., VtH_org), the logic level of the output voltage Vout changes from an "H" level to an "L" level, as indicated by the solid line passing through point A2. Therefore, when the voltage level of voltage VNG reaches point A2, the input voltage Vin reaches the high threshold voltage VtH of the comparison circuit 21a.

[0137] Next, when the input voltage Vin changes from a high voltage to a low voltage, and the voltage VPG reaches the same voltage level as that shown at point B1, namely, the voltage level shown at point B2 (i.e., VtL_org), the logic level of the output voltage Vout changes from an "L" level to an "H" level, as indicated by the solid line passing through point B2. Therefore, when the voltage level of voltage VPG reaches point B2, the input voltage Vin reaches the lower threshold voltage VtL of the comparison circuit 21a.

[0138] Thus, the comparator circuit 21a applies the voltages VNG and VPG generated by the voltage conversion circuit 40a to the NMOS transistors 51 and 52 and the PMOS transistors 54 and 55. Consequently, the comparator circuit 21a can change the high threshold voltage VtH_org and the low threshold voltage VtL_org, which are determined by the threshold values ​​of the MOS transistors, into the high threshold voltage VtH and the low threshold voltage VtL of the comparator circuit 21a. Consequently, the comparator circuit 21a can change the hysteresis characteristics of the logic circuit 50.

[0139] Furthermore, as shown in the above equation (9) or equation (16), the value of the high threshold voltage VtH_org depends on the voltage corresponding to the threshold voltage vtn of each of the NMOS transistors 51 and 52, and the value of the low threshold voltage VtL_org depends on the voltage corresponding to the threshold voltage vtp of each of the PMOS transistors 54 and 55. A lower threshold voltage can be used, and in this case, the hysteresis characteristics can be changed.

[0140] In addition, in the present invention, as the logic circuit 50, the conventional Figure 4 Circuit in. Components that can change the hysteresis width, the threshold from "H" level to "L" level, and the threshold from "L" level to "H" level by using a hysteresis comparator require the use of multiple differential amplifiers. The differential amplifier has a large area, and it is necessary to allow the bias current to flow continuously when it is operating, which increases power consumption. When the output of the logic circuit 50 is stable at a high level, the NMOS transistors 51 and 52 are turned off, so the through current does not flow into the logic circuit 50. Similarly, when the output of the logic circuit 50 is stable at a low level, the PMOS transistors 54 and 55 are turned off, so the through current does not flow into the logic circuit 50. As a result, the current consumption is small except when switching the output, so the power consumption can be suppressed.

[0141] ===Modifications===

[0142] ==Comparison circuit 21b==

[0143] Figure 7 2 is a diagram showing an example of the configuration of the comparison circuit 21b. The voltage conversion circuit 40b of the comparison circuit 21b is similar to the voltage conversion circuit 40a of the comparison circuit 21a, but a resistor 45 is further added between the node to which the input voltage is applied and the ground.

[0144] ==Comparison circuit 21c==

[0145] Figure 8 This diagram shows an example of the structure of the comparison circuit 21c. The voltage conversion circuit can also be implemented with a structure different from that of the voltage conversion circuits 40a and 40b. As an example, the voltage conversion circuit 40c is composed of a source follower circuit 61a, which has an input voltage Vin applied to its gate electrode and outputs a voltage VNGb from its source electrode, and a source follower circuit 61b, which has an input voltage Vin applied to its gate electrode and outputs a voltage VPGb from its source electrode.

[0146] The source follower circuit 61a includes a constant current source 62a and a PMOS transistor 63a, and the source follower circuit 61b includes a constant current source 62b and an NMOS transistor 63b.

[0147] In addition, the source follower circuit 61a corresponds to a “first source follower circuit”, and the source follower circuit 62b corresponds to a “second source follower circuit”.

[0148] The output voltage VNGb of the source follower circuit 61a is basically a voltage obtained by offsetting the input voltage Vin by the gate-source voltage of the PMOS transistor 63a. Similarly, the output voltage VPGb of the source follower circuit 61b is basically a voltage obtained by offsetting the gate-source voltage of the NMOS transistor 63b.

[0149] However, due to the properties of the source follower circuit, the input voltage Vin that exceeds the output amplitude after subtracting the voltage drop amount used in the constant current source and the transistor is cut off and output, so the amplitude of the voltage VNGb and the voltage VPGb becomes smaller than the potential difference between the low power supply voltage VDD and the ground voltage.

[0150] The voltage conversion circuit 40c receives the input voltage Vin, so it requires high-voltage components. However, since the amplitudes of the voltages VNG and VPG, which receive the outputs of the source follower circuit operating at the low power supply voltage VDD, are below the potential difference between the ground voltage and the low power supply voltage VDD, component damage can be more reliably prevented even if high-voltage components are not used in the comparator circuit 21a. Therefore, in this variation, high-voltage components are used in the voltage conversion circuit 40c, while low-voltage components are used in the logic circuit 50, which operates at the potential difference between the low power supply voltage VDD and the ground voltage.

[0151] ===Summary===

[0152] The power module 10 of this embodiment has been described above. When a Schmitt trigger circuit is used as the comparator circuit 21, the hysteresis characteristics are determined by the threshold voltages of the NMOS transistors 51 and 52 and the PMOS transistors 54 and 55, respectively, making it difficult to change the hysteresis characteristics. However, by converting the input voltage Vin into voltages VNG and VPG and applying these voltages to the gate electrodes of the NMOS transistors 51 and 52 and, in turn, to the gate electrodes of the PMOS transistors 54 and 55, respectively, the hysteresis characteristics observed from the input voltage Vin can be changed.

[0153] Furthermore, since the input voltage Vin is higher than the power supply voltage VDD of the logic circuit 50, high-voltage MOS transistors are used for the NMOS transistors 51 to 53 and the PMOS transistors 54 to 56. In this case, when the logic circuit 50 is used, the hysteresis characteristics determined by the threshold values ​​of the high-voltage MOS transistors can be changed by adjusting the resistance values ​​R1 to R4 of the resistors 41 to 44.

[0154] Furthermore, in this embodiment, when the NMOS transistor 32 is turned on by the low-side driver circuit 27, the voltage Vs at the terminal VS sometimes becomes negative due to the influence of the inductance component of the load 11. Furthermore, current flows from the ground to the voltage line to which the voltage Vs at the terminal VS is applied, and the potential of the terminal G (e.g., the ground) sometimes fluctuates. Consequently, the low power supply voltage VDD sometimes fluctuates. By configuring the logic circuit 50 with two PMOS transistors and two NMOS transistors, when the comparator is used as a Schmitt trigger circuit, it is not affected by fluctuations in the bias current generated when the low power supply voltage VDD fluctuates. Therefore, the logic circuit 50 operates as a high-precision Schmitt trigger circuit.

[0155] Furthermore, by configuring the voltage conversion circuit 40 a using the resistors 41 to 44 , it is possible to generate the voltages VNG and VPG with high precision.

[0156] Furthermore, the resistance values ​​R1 to R4 of resistors 41 to 44 are determined so as to turn off either the pair of two PMOS transistors 54 and 55 or the pair of NMOS transistors 51 and 52 in logic circuit 50. This prevents a through current from flowing into logic circuit 50 even when input voltage Vin is not applied to node N1.

[0157] Furthermore, the voltage conversion circuit 40 b is implemented by two source follower circuits. Therefore, similarly to the logic circuit 50 , the hysteresis characteristic observed from the input voltage Vin can be changed.

[0158] When the resistor 45 is connected between the node N1 and the ground, the node N1 can be pulled down when the input voltage Vin is not applied to the node N1 , and the resistance values ​​R1 to R4 of the resistors 41 to 44 can be freely designed to a certain extent.

[0159] The above embodiments are for the purpose of facilitating understanding of the present invention, and are not intended to limit the present invention. In addition, the present invention may be modified or improved without departing from its gist, and the present invention naturally includes its equivalents.

[0160] Description of labels

[0161] 10 Power Module

[0162] 11 Load

[0163] 12, 14 capacitors

[0164] 13 DC power supply

[0165] 20 HVIC

[0166] 21, 21a, 21b, 21c Comparison circuits

[0167] 22 Inverter

[0168] 23 Filter Circuit

[0169] 24 Pulse generation circuit

[0170] 25 High-side driver circuit

[0171] 26 Power Circuit

[0172] 27 Low-side driver circuit

[0173] 30 Bridge Circuit

[0174] 31, 32, 51 to 53, 63b NMOS transistors

[0175] 40a, 40b, 40c voltage conversion circuit

[0176] 41~45 resistor

[0177] 50 Logic Circuits

[0178] 54~56, 63a PMOS transistors

[0179] 61a, 61b Source follower circuit

[0180] 62a, 62b constant current source.

Claims

1. A comparison circuit, The comparator circuit outputs an output voltage of a first logic level when an input voltage exceeds a first threshold voltage, and outputs the output voltage of a second logic level when the input voltage is lower than a second threshold voltage lower than the first threshold voltage. The comparator circuit is characterized by comprising: a conversion circuit, the conversion circuit converting the input voltage into a first voltage and a second voltage lower than the first voltage; as well as a logic circuit that outputs the output voltage of the first logic level when the first voltage exceeds a third threshold voltage, and outputs the output voltage of the second logic level when the second voltage is lower than a fourth threshold voltage that is lower than the third threshold voltage, The logic circuit is a Schmitt trigger circuit, which includes: The second voltage is applied to each of the two gate electrodes of the two PMOS transistors connected in series on the power supply side; as well as The first voltage is applied to each of the two gate electrodes of the two NMOS transistors connected in series between the two PMOS transistors and the ground, The third threshold voltage is a voltage corresponding to a threshold voltage of each of the two NMOS transistors, and the fourth threshold voltage is a voltage corresponding to a threshold voltage of each of the two PMOS transistors.

2. The comparison circuit according to claim 1, wherein: The logic circuit operates at a power supply voltage lower than the maximum value of the input voltage.

3. The comparison circuit according to claim 1, wherein: The conversion circuit includes: first to fourth resistors connected in series between a node to which a power supply voltage of the logic circuit is applied and a ground, When the input voltage is applied to a connection point between a second resistor and a third resistor, the conversion circuit generates the first voltage at a connection point between the first resistor and the second resistor, and generates the second voltage at a connection point between the third resistor and the fourth resistor.

4. The comparison circuit according to claim 3, wherein: When the input voltage is not applied to the conversion circuit, the first to fourth resistors have resistance values ​​that turn off either the group of two PMOS transistors or the group of two NMOS transistors.

5. The comparison circuit according to any one of claims 1 to 3, wherein: The conversion circuit includes: a first source follower circuit that applies the input voltage to a gate electrode and outputs the first voltage from a source electrode; and A second source follower circuit applies the input voltage to a gate electrode and outputs the second voltage from a source electrode.

6. The comparison circuit according to any one of claims 1 to 3, wherein: The conversion circuit further includes: A resistor is connected between the node to which the input voltage is applied and the ground.

7. A semiconductor device comprising: a power supply circuit that generates a low power supply voltage lower than the power supply voltage based on the power supply voltage; a detection circuit that operates at the low power supply voltage and detects control signals for driving the switching elements of the upper arm and the lower arm; and a driving circuit that drives the switching element of the upper arm and the switching element of the lower arm based on the detection result of the detection circuit, wherein the semiconductor device is characterized in that: The detection circuit comprises: a comparison circuit that outputs the detection result of a first logic level when the voltage level of the control signal exceeds a first threshold voltage, and outputs the detection result of a second logic level when the voltage level of the control signal is lower than a second threshold voltage that is lower than the first threshold voltage; The comparison circuit comprises: a conversion circuit configured to convert a voltage level of the control signal into a first voltage and a second voltage lower than the first voltage; and a logic circuit that outputs the detection result of the first logic level when the first voltage exceeds a third threshold voltage, and outputs the detection result of the second logic level when the second voltage is lower than a fourth threshold voltage that is lower than the third threshold voltage, The logic circuit is a Schmitt trigger circuit, which includes: The second voltage is applied to each of two gate electrodes of two PMOS transistors connected in series on the power supply side; and The first voltage is applied to each of the two gate electrodes of the two NMOS transistors connected in series between the two PMOS transistors and the ground, The third threshold voltage is a voltage corresponding to a threshold voltage of each of the two NMOS transistors, and the fourth threshold voltage is a voltage corresponding to a threshold voltage of each of the two PMOS transistors.

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