One-time etching method for different depth silicon cavities of microsystem module

Abstract

The application provides a one-time etching method for different-depth silicon cavities of a micro-system module, which comprises the following steps: forming a first photoresist layer and a second photoresist layer in a stacked mode on a semiconductor substrate, forming a first etching opening and a second etching opening, forming an initial silicon cavity based on the formed photoresist pattern, removing the remaining first photoresist layer, and etching to form a first-depth silicon cavity and a second-depth silicon cavity. Through the above scheme, the first photoresist layer and the second photoresist layer are formed on the semiconductor substrate, the photoresist patterns of all different-depth cavities are formed before one-time etching, and during the etching process, the cleaning of the photoresist on the front surface of the silicon cavity of the previous depth and the silicon cavity of the next depth is realized by changing the etching atmosphere and etching energy, so that the one-time etching of the different-depth silicon cavities is realized, the problem of poor coverage of the photoresist when the photoresist is coated on the deep silicon cavity is avoided, the work efficiency is improved, and the pollution is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and in particular to a one-time etching method for silicon cavities of different depths in a microsystem module. Background Technology

[0002] With the development of silicon-based microelectromechanical systems (MEMS) and radio frequency through-silicon via (RF TSV) technologies, three-dimensional heterogeneous integrated microsystems technology has become an important direction for the development of next-generation military high-integration electronic systems. Three-dimensional heterogeneous integration is an integration method that embeds chips of different sizes and textures into silicon cavities on a silicon substrate, fans them out using post-wiring technology, and then achieves high-density integration through through-silicon vias.

[0003] However, as the integration density and functionality of silicon interposers increase, embedding only one type of chip (i.e., a chip of one thickness) on a single silicon interposer is no longer sufficient to meet integration requirements. Therefore, it is necessary to fabricate embedded cavities for different chips on the same silicon interposer, i.e., to create silicon cavities of different depths on the same silicon interposer. However, the etching of silicon cavities of different depths often affects the cavity morphology, the process is often complex, and it also leads to problems such as wasted time and reduced efficiency in wafer manufacturing equipment and increased susceptibility to wafer contamination.

[0004] Therefore, it is necessary to provide a one-time etching method for silicon cavities of different depths in microsystem modules to solve the above-mentioned problems in the prior art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a one-time etching method for silicon cavities of different depths in microsystem modules, which solves the problems of the influence on the morphology of the etched cavity and the waste and pollution of the process during the etching of silicon cavities of different depths.

[0006] To achieve the above and other related objectives, the present invention provides a method for one-time etching of silicon cavities of different depths in a microsystem module, comprising the following steps:

[0007] Provide semiconductor substrates;

[0008] A first photoresist layer and a second photoresist layer are sequentially formed on the semiconductor substrate;

[0009] A first etching opening is formed that penetrates both the first and second photoresist layers vertically, and a second etching opening is formed that penetrates both the first and second photoresist layers vertically. The first etching opening corresponds to a first-depth silicon cavity to be formed, and the second etching opening corresponds to a second-depth silicon cavity to be formed. The depth of the first-depth silicon cavity is greater than the depth of the second-depth silicon cavity.

[0010] Based on the first photolithography layer and the second photoresist layer, etching is performed downwards to form an initial silicon cavity of a predetermined depth in the semiconductor substrate at the position corresponding to the first etching opening, and the first photoresist layer of a predetermined thickness is etched away at the position corresponding to the second etching opening.

[0011] Remove the remaining first photoresist layer to expose the semiconductor substrate at the location corresponding to the second etched opening;

[0012] Based on the first photolithography layer and the second photoresist layer, etching continues downward to form the first depth silicon cavity corresponding to the initial silicon cavity, and the second depth silicon cavity is formed corresponding to the second etching opening.

[0013] Optionally, after forming the first photoresist layer, the process further includes a soft baking step on the first photoresist layer at a temperature between 85°C and 135°C for a time between 2 min and 10 min.

[0014] Optionally, after forming the second photoresist layer, the process further includes a soft baking step on the second photoresist layer and the first photoresist layer at a temperature between 85°C and 135°C for a time between 2 min and 10 min.

[0015] Optionally, the thickness of the first photoresist layer is between 1 and 100 μm; the thickness of the second photoresist layer is between 1 and 100 μm.

[0016] Optionally, the step of forming the first etched opening and the second etched opening includes:

[0017] A first opening and a second opening are formed in the second photoresist layer using a first photolithography process, wherein the second opening constitutes the second etching opening;

[0018] A second photolithography process is used to form a third opening in the first photoresist layer below the first opening, corresponding to the first opening. The first opening and the third opening constitute the first etching opening.

[0019] Optionally, the first photolithography process includes a first exposure and a first development process; the second photolithography process includes a second exposure and a second development process, wherein the second exposure includes the step of baking at a temperature between 50°C and 100°C for a time between 1 min and 30 min; the second development includes the step of hard baking at a temperature between 50°C and 150°C for a time between 0.5 h and 1.5 h.

[0020] Optionally, the step of forming the first etched opening and the second etched opening includes:

[0021] A third exposure process is performed on the second photoresist layer to form a first exposure area and a second exposure area in the second photoresist layer, wherein the first exposure area corresponds to the position of the first etching opening and the second exposure area corresponds to the position of the second etching opening;

[0022] A fourth exposure process is performed on the second photoresist layer and the first photoresist layer to form a third exposure area in the first photoresist layer, wherein the third exposure area corresponds vertically to the first exposure area.

[0023] Post-baking is performed at a temperature between 50℃ and 100℃ for a time between 1 minute and 30 minutes;

[0024] A third development process is performed on the first photoresist layer and the second photoresist layer to form the first etching opening corresponding to the first exposure area and the third exposure area, and to form the second etching opening corresponding to the second exposure area.

[0025] Perform hard baking at a temperature between 50℃ and 150℃ for a time between 0.5h and 1.5h.

[0026] Optionally, the step of forming the first etched opening and the second etched opening includes:

[0027] a) A fourth opening is formed in the second photoresist layer using a third photolithography process, the fourth opening constituting the second etching opening;

[0028] b) A fifth opening is formed in the second photoresist layer and the first photoresist layer through the vertical direction by a fourth photolithography process, and the fifth opening constitutes the first etching opening;

[0029] In this case, step a) is performed before step b), or step b) is performed before step a).

[0030] Optionally, the third photolithography process includes a fifth exposure and a fourth development process; the fourth photolithography process includes a sixth exposure and a fifth development process, wherein the sixth exposure is followed by a step of post-baking at a temperature between 50°C and 100°C for a time between 1 min and 30 min; the fifth development is followed by a step of hard baking at a temperature between 50°C and 150°C for a time between 0.5 h and 1.5 h.

[0031] Optionally, the step of forming the first etched opening and the second etched opening includes:

[0032] c) Perform a seventh exposure process on the second photoresist layer to form a fourth exposure area in the second photoresist layer, wherein the fourth exposure area corresponds to the position of the second etching opening;

[0033] d) Perform an eighth exposure process on the second photoresist layer and the first photoresist layer to form a fifth exposure region that runs vertically through the first photoresist layer and the second photoresist layer, wherein the fifth exposure region corresponds to the position of the first etching opening; wherein step c) is performed before step d) or step d) is performed before step c);

[0034] e) Perform post-baking at a temperature between 50℃ and 100℃ for a time between 1 min and 30 min;

[0035] f) Perform a sixth development process on the first photoresist layer and the second photoresist layer to form the second etching opening corresponding to the fourth exposure area and the first etching opening corresponding to the fifth exposure area.

[0036] g) Perform hard baking at a temperature between 50℃ and 150℃ for a time between 0.5h and 1.5h.

[0037] Optionally, the preset depth is between 50-150 μm; the preset thickness is greater than 3 / 5 of the thickness of the first photoresist layer.

[0038] Optionally, the depth of the first deep silicon cavity is between 200μm and 350μm, and the depth of the second deep silicon cavity is between 100μm and 200μm.

[0039] As described above, the single-etching method for silicon cavities of different depths in the microsystem module of the present invention forms two layers of photoresist, namely a first photoresist layer and a second photoresist layer, to form photoresist patterns for all cavities of different depths before the first etching. During the etching process, the etching atmosphere and etching energy are changed to achieve etching of the silicon cavity of the previous depth and cleaning of the photoresist on the surface before etching of the silicon cavity of the next depth. This achieves single-etching of silicon cavities of different depths, avoids the problem of poor photoresist coverage when applying photoresist to deep silicon cavities, and also improves work efficiency and reduces pollution. Attached Figure Description

[0040] Figure 1 The flowchart shown is a process for etching silicon cavities of different depths in a microsystem module according to an embodiment of the present invention.

[0041] Figure 2 The diagram shows a semiconductor substrate provided in a single etching method for silicon cavities of different depths in an embodiment of the present invention.

[0042] Figure 3 The illustration shows the formation of the first photoresist layer in a single etching method for silicon cavities of different depths in an embodiment of the present invention.

[0043] Figure 4 The illustration shows the formation of the second photoresist layer in a single etching method for silicon cavities at different depths in an embodiment of the present invention.

[0044] Figure 5 The diagram shows a schematic representation of the structure forming the first and second etching openings in a single etching method for silicon cavities at different depths in an embodiment of the present invention.

[0045] Figure 6 The diagram shows a schematic representation of the structure forming the first and second etched openings in one etching method for silicon cavities of different depths according to an embodiment of the present invention.

[0046] Figure 7 Displayed as corresponding Figure 6 The example shows a schematic diagram of the structure that forms the third opening.

[0047] Figure 8 This diagram illustrates a fourth opening in another example of a single etching method for silicon cavities at different depths, used in an embodiment of the present invention to form the first and second etched openings.

[0048] Figure 9 Displayed as corresponding Figure 6 The example shows a schematic diagram of the structure that forms the fifth opening.

[0049] Figure 10 This diagram illustrates the formation of an initial silicon cavity in a single etching method for silicon cavities of different depths, as shown in an embodiment of the present invention.

[0050] Figure 11 The diagram shows a structural schematic of removing the remaining first photoresist layer in a single etching method for silicon cavities at different depths in an embodiment of the present invention.

[0051] Figure 12 The diagram shows the structure of forming a first-depth silicon cavity and a second-depth silicon cavity in a single etching method for silicon cavities of different depths in an embodiment of the present invention.

[0052] Figure 13 The diagram shows a schematic of removing the photoresist layer in a single etching method for silicon cavities of different depths in an embodiment of the present invention.

[0053] Figure 14 The diagram shows the structural schematics of each step in the silicon cavity etching process at different depths in the comparative example of this invention.

[0054] Component designation explanation

[0055] 100 Semiconductor substrate

[0056] 101 First photoresist layer

[0057] 102 Second photoresist layer

[0058] 103 First Etching Opening

[0059] 104 Second Etching Opening

[0060] 105 First Opening

[0061] 106 Second opening

[0062] 107 Third Opening

[0063] 108 Fourth Opening

[0064] 109 The Fifth Opening

[0065] 110 Initial silicon cavity

[0066] 111 Remaining first lithography layer

[0067] 112 The sixth opening

[0068] 113 First-depth silicon cavity

[0069] 114 Second-depth silicon cavity

[0070] 200 First Mask Version

[0071] 201 Second Mask Version

[0072] 202 Third Mask Version

[0073] 203 Fourth Mask Version

[0074] 300 silicon substrate

[0075] 301 photoresist

[0076] 302 Second-depth silicon cavity

[0077] 303 The first deep silicon cavity

[0078] 304 bad pixels

[0079] Steps S1 to S6 Detailed Implementation

[0080] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0081] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0082] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0083] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0084] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0085] like Figure 1 As shown, this invention provides a one-step etching method for silicon cavities of different depths in a microsystem module, comprising the following steps:

[0086] S1: Provides a semiconductor substrate;

[0087] S2: A first photoresist layer and a second photoresist layer are sequentially formed on the semiconductor substrate;

[0088] S3: Form a first etching opening that penetrates the first photoresist layer and the second photoresist layer vertically and a second etching opening that penetrates the second photoresist layer vertically, wherein the first etching opening corresponds to a first depth silicon cavity to be formed, the second etching opening corresponds to a second depth silicon cavity to be formed, and the depth of the first depth silicon cavity is greater than the depth of the second depth silicon cavity.

[0089] S4: Based on the first photolithography layer and the second photoresist layer, etching is performed downward to form an initial silicon cavity of a preset depth in the semiconductor substrate at the position corresponding to the first etching opening, and the second photoresist layer of a preset thickness is etched away at the position corresponding to the second etching opening.

[0090] S5: Remove the remaining second photoresist layer to expose the semiconductor substrate at the location corresponding to the second etched opening;

[0091] S6: Based on the first photolithography layer and the second photoresist layer, continue etching downwards to form the first depth silicon cavity corresponding to the initial silicon cavity, and form the second depth silicon cavity corresponding to the second etching opening.

[0092] The following will describe in detail, with reference to the accompanying drawings, the single-stage etching method for silicon cavities of different depths in the microsystem module of the present invention. It should be noted that the above order does not strictly represent the order of steps in the single-stage etching method for silicon cavities of different depths in the microsystem module of the present invention, and those skilled in the art can modify it according to the actual process steps. Figure 1 The steps of a single etching method for silicon cavities at different depths in a microsystem module are shown in only one example.

[0093] like Figure 1 S1 and Figure 2 As shown, step S1 is performed first, providing a semiconductor substrate 100. The semiconductor substrate 100 is a structure that requires the formation of grooves of different depths, and can be a structure that requires the formation of cavities of different depths as referred to in this invention, such as silicon cavities of different depths. The semiconductor substrate 100 can be a single-layer material structure or a stacked structure composed of multiple material layers. In this example, the semiconductor substrate 100 is selected as a silicon substrate. Of course, in other examples, it can also be silicon-on-insulator (SOI), etc., and is not limited thereto.

[0094] like Figure 1 S2 and Figure 3-4As shown, step S2 is then performed, where a first photoresist layer 101 and a second photoresist layer 102 are sequentially formed on the semiconductor substrate 100. The first photoresist layer 101 can be either a positive or negative photoresist, and the second photoresist layer 102 can also be either a positive or negative photoresist. In one example, the materials of the first photoresist layer 101 and the second photoresist layer 102 can be the same type of photoresist or different types. Existing processes can be used to form the first photoresist layer 101 and the second photoresist layer 102. In this example, the first photoresist layer 101 and the second photoresist layer 102 are both of the same type, namely, positive photoresist. It will be understood by those skilled in the art that the difference in the etching selectivity of the two photoresist layers and the thickness of the two photoresist layers can be arbitrarily adjusted to achieve the desired etching effect. For example, the etching characteristics based on the two photoresist layers can be achieved by changing the type, material composition, model, or baking time and temperature of the two photoresist layers.

[0095] As an example, the thickness of the first photoresist layer 101 is between 1 and 100 μm, and can be 2 μm, 20 μm, or 50 μm; the thickness of the second photoresist layer 102 is between 1 and 100 μm, and can be 50 μm, 60 μm, or 80 μm.

[0096] As an example, after forming the first photoresist layer 101, a soft baking step is further included, where the first photoresist layer 101 is subjected to a temperature between 85°C and 135°C and a time between 2 min and 10 min. In one example, the soft baking temperature after forming the first photoresist layer 101 (lower photoresist layer) can be 90°C, 100°C, 105°C, or 110°C, and the soft baking time can be 3 min, 5 min, 6 min, or 8 min.

[0097] As an example, after forming the second photoresist layer 102, a soft baking step is further included on the second photoresist layer 102 and the first photoresist layer 101 at a temperature between 85°C and 135°C for a time between 2 min and 10 min. In one example, the soft baking temperature after forming the second photoresist layer 102 (upper photoresist layer) can be 90°C, 100°C, 105°C, or 110°C, and the soft baking time can be 3 min, 5 min, 6 min, or 8 min.

[0098] like Figure 1 S3 and Figure 5-9As shown, step S3 is then performed to form a first etching opening 103 that penetrates vertically through the first photoresist layer 101 and the second photoresist layer 102, and a second etching opening 104 that penetrates vertically through the second photoresist layer 102. The first etching opening 103 corresponds to the first depth silicon cavity to be formed, and the second etching opening 104 corresponds to the second depth silicon cavity to be formed.

[0099] Through the above process, the present invention forms patterns of cavities of different depths using different photoresist layers (such as the first photoresist layer 101 and the second photoresist layer 102) before a single etching step. This forms the photoresist patterns for subsequent silicon cavities of first depth 113 and second depth 114. Alternatively, etching openings for silicon cavities of other depths can be formed in the first photoresist layer 101 and the second photoresist layer 102. Therefore, based on the above patterns, silicon cavities of different depths can be formed simultaneously in a subsequent etching process.

[0100] like Figure 6-7 As shown, an example of forming the first etched opening 103 and the second etched opening 104 is provided. The specific forming process includes the following steps:

[0101] First, such as Figure 6 As shown, a first opening 105 and a second opening 106 are formed in the second photoresist layer 102 using a first photolithography process. The second opening 106 constitutes the second etching opening 104. The first photolithography process can be obtained based on the first mask 200.

[0102] In an optional example, the first photolithography process includes a first exposure and a first development process. That is, after forming two photoresist layers, a half-exposure (first exposure and first development) process is first used to simultaneously half-exposure the photoresist above two cavities at different depths, forming a first opening 105 and a second opening 106. The first photolithography process can be performed under the first photomask 200.

[0103] Next, as Figure 7 As shown, a second photolithography process is used to form a third opening 107 in the first photoresist layer 101 directly below the first opening 105, corresponding to the first opening 105. The first opening 105 and the third opening 107 constitute the first etching opening 103.

[0104] In one optional example, the second photolithography process includes a second exposure and a second development process. That is, after the first photolithography process, an overexposure (second exposure and second development) process is performed to expose the photoresist (first photoresist layer) above the cavity with a larger initial etching depth, so that it is fully developed to form the structure shown in 5. The second exposure includes a baking step: performing a baking at a temperature between 50℃ and 100℃ for a time between 1 min and 30 min. The baking temperature can be 60℃, 70℃, 80℃, or 9℃, and the baking time can be 10 min, 15 min, 20 min, or 25 min. In another example, the second development includes a hard baking step: performing a hard baking at a temperature between 50℃ and 150℃ for a time between 0.5 h and 1.5 h. The baking temperature can be 90℃, 100℃, 105℃, or 110℃, and the baking time can be 0.8 h, 1 h, 1.2 h, or 1.3 h. The second photolithography process can be performed under the second mask 201.

[0105] refer to Figure 6-7 Another method for forming the first etched opening 103 and the second etched opening 104 is provided, the specific steps of which include:

[0106] First, a third exposure process is performed on the second photoresist layer 102 to form a first exposure area and a second exposure area (not shown in the figure) in the second photoresist layer 102, wherein the first exposure area corresponds to the position of the first etching opening 103 and the second exposure area corresponds to the position of the second etching opening 104.

[0107] Next, a fourth exposure process is performed on the second photoresist layer 102 and the first photoresist layer 101 to form a third exposure area (not shown in the figure) in the first photoresist layer 101. The third exposure area corresponds vertically to the first exposure area; that is, after the first exposure (the third exposure process), no development is performed and a second overexposure (the fourth exposure process) is performed directly.

[0108] Next, after two exposures, a post-baking process is performed at a temperature between 50℃ and 100℃ and for a time between 1 min and 30 min. The baking temperature can be 60℃, 70℃, 80℃, or 9℃, and the baking time can be 10 min, 15 min, 20 min, or 25 min.

[0109] Next, a third development process is performed on the first photoresist layer 101 and the second photoresist layer 102, that is, after two exposures, post-baking is performed, and after post-baking, development is performed (the third development) to form a first etching opening 103 corresponding to the first exposure area and the third exposure area, and a second etching opening 104 corresponding to the second exposure area.

[0110] Finally, after development (the third development), a hard baking is performed at a temperature between 50°C and 150°C for a time between 0.5h and 1.5h; the baking temperature can be 90°C, 100°C, 105°C, or 110°C, and the baking time can be 0.8h, 1h, 1.2h, or 1.3h.

[0111] like Figure 8-9 As shown, the present invention also provides another example of forming the first etched opening 103 and the second etched opening 104, the specific forming steps of which include:

[0112] First, such as Figure 8 As shown, in step a), a third photolithography process is used to form a fourth opening 108 in the second photoresist layer, and the fourth opening 108 constitutes the second etching opening 104.

[0113] As an example, the third photolithography process includes a fifth exposure and a fourth development process, that is, firstly, a photoresist pattern of a cavity (the second depth silicon cavity) with a smaller depth is obtained by exposure through a half-exposure process (the fifth exposure process and the fourth development process). The third photolithography process can be performed under the third mask 202.

[0114] Next, as Figure 9 As shown, in step b), a fifth opening 109 is formed in the second photoresist layer 102 and the first photoresist layer 101 through the vertical direction by a fourth photolithography process. The fifth opening 109 constitutes the first etching opening 103. The fourth photolithography process can be performed under the fourth photomask 203.

[0115] As an example, the fourth photolithography process includes a sixth exposure and a fifth development process, that is, by further exposing and developing the photoresist pattern of the previously etched, deeper cavity (the first depth silicon cavity) through an overexposure process (the sixth exposure process and the fifth development process), the photoresist pattern is fully developed. The sixth exposure includes a step of post-baking at a temperature between 50℃ and 100℃ for a time between 1 min and 30 min, where the baking temperature can be 60℃, 70℃, 80℃, or 9℃, and the baking time can be 10 min, 15 min, 20 min, or 25 min. The fifth development includes a step of hard baking at a temperature between 50℃ and 150℃ for a time between 0.5 h and 1.5 h, where the baking temperature can be 90℃, 100℃, 105℃, or 110℃, and the baking time can be 0.8 h, 1 h, 1.2 h, or 1.3 h.

[0116] In this case, step a) is performed before step b), or step b) is performed before step a). That is, the photoresist pattern of the second depth silicon cavity with a smaller depth can be formed first, or the photoresist pattern of the first depth silicon cavity with a larger depth can be formed first.

[0117] refer to Figure 8-9 The present invention also provides another example of forming the first etched opening 103 and the second etched opening 104, the specific steps of which include:

[0118] First, step c) is performed to perform a seventh exposure process on the second photoresist layer 102 to form a fourth exposure area (not shown in the figure) in the second photoresist layer 102, wherein the fourth exposure area corresponds to the position of the second etching opening 104.

[0119] Next, step d) is performed, in which the second photoresist layer 102 and the first photoresist layer 101 are subjected to an eighth exposure process, forming a fifth exposure area (not shown in the figure) that runs vertically through the first photoresist layer 101 and the second photoresist layer 102. The fifth exposure area corresponds to the position of the first etching opening 103. That is, after the first half-exposure (the seventh exposure process), development is not performed and the second overexposure (the eighth exposure process) is performed directly.

[0120] Wherein, step c) is performed before step d), or step d) is performed before step c); that is, it can be an exposure pattern of the photoresist pattern of the second depth silicon cavity with a smaller depth formed first, or it can be an exposure pattern of the photoresist pattern of the first depth silicon cavity with a larger depth formed first.

[0121] Next, proceed to step e), after the exposure of the two patterns described above, perform a post-baking process at a temperature between 50℃ and 100℃ and for a time between 1 min and 30 min; wherein the baking temperature can be 60℃, 70℃, 80℃, or 9℃, and the baking time can be 10 min, 15 min, 20 min, or 25 min.

[0122] Next, in step f), after baking, a sixth development process is performed on the first photoresist layer 101 and the second photoresist layer 102 to form the second etching opening 104 corresponding to the fourth exposure area and the first etching opening 103 corresponding to the fifth exposure area; at the same time, the patterns corresponding to the two cavities are developed.

[0123] Finally, proceed to step g), which involves hard baking at a temperature between 50℃ and 150℃ for a time between 0.5h and 1.5h. The baking temperature can be 90℃, 100℃, 105℃, or 110℃, and the baking time can be 0.8h, 1h, 1.2h, or 1.3h.

[0124] like Figure 1 S4 and Figure 10 As shown, in step S4, etching is performed downwards based on the first photolithography layer 101 and the second photoresist layer 102 after photolithography, so as to form an initial silicon cavity 110 with a preset depth d1 in the semiconductor substrate 100 at the position corresponding to the first etching opening 103, and the first photoresist layer 101 with a preset thickness h is etched away at the position corresponding to the second etching opening 104.

[0125] In this step, the initial silicon cavity 110 is first formed for the larger first-depth silicon cavity. For example, the preset depth d1 is between 50-150 μm, and can be 80 μm, 100 μm, or 120 μm. During this process, simultaneously, due to the etching effect, almost all of the lower photoresist layer (the first photoresist layer) remaining after half-exposure above the small cavity is also etched away, resulting in the remaining first photoresist layer 111. For example, the preset thickness h is greater than 3 / 5 of the thickness of the first photoresist layer 101, and can be 4 / 5. Of course, the preset thickness can also be selected as other values ​​according to the actual situation to achieve the desired etching effect. The etching method here can be either dry etching or wet etching. In this step, etching is performed based on the etching patterns formed in the first photoresist layer 101 and the second photoresist layer 102 in the previous steps. This process removes most of the first photoresist layer 101 while etching away the semiconductor substrate 100 to a predetermined depth. This process can be achieved through selectivity during etching. For example, given the materials of the semiconductor substrate 100 and the first photoresist layer 101, a suitable etching atmosphere and a correspondingly designed thickness of the first photoresist layer 101 can be selected. Furthermore, the etching characteristics of the material layer can be controlled by adjusting the baking temperature and time during the formation and exposure / development processes of the first photoresist layer 101. Additionally, the type of the second photoresist (e.g., photoresists with different material compositions and types) can be changed to achieve the desired photoresist layer characteristics. Those skilled in the art will understand that the difference in selectivity between the etching atmosphere (or solution) for the two photoresist layers, the thickness of the two photoresist layers, and the etching depth of the large cavity can be arbitrarily adjusted to achieve the desired etching effect.

[0126] like Figure 1 S5 and Figure 11As shown, step S5 is performed to remove the remaining first photoresist layer (i.e., the remaining first photoresist layer 111) to expose the semiconductor substrate 100 at the position corresponding to the second etching opening 104, forming a sixth opening 112, thereby cleaning the surface of the semiconductor substrate 100 at the position of the sixth opening 112. In this step, after etching to form the initial silicon cavity 110 in the previous step, the reaction atmosphere (or etching solution) in the etching cavity is changed, so that the residual photoresist (the remaining first photoresist layer 111) above the post-etched cavity is completely cleaned, exposing the lower silicon substrate (the semiconductor substrate 100). The method for removing the residual photoresist (the remaining first photoresist layer 111) here can be either dry cleaning or wet cleaning. That is, in this step, a suitable etching atmosphere can be selected based on the material characteristics of the remaining first photoresist layer 111 and the semiconductor substrate 100, thereby removing the remaining first photoresist layer 111 without consuming the semiconductor substrate in the initial cavity. The etching atmosphere and etching energy can be changed to achieve the etching of the silicon cavity at the previous depth and the cleaning of the surface photoresist before etching the silicon cavity at the next depth. Furthermore, after this step, the surface of the semiconductor substrate 100 at the location requiring further etching is free of photoresist. Those skilled in the art will understand that the difference in the selectivity of the atmosphere (or solution) for etching the two photoresist layers and the thickness of the two photoresist layers can be arbitrarily adjusted to achieve the desired cleaning and removal effect.

[0127] like Figure 1 S6 and Figure 12-13 As shown, in step S6, etching continues downward based on the first photolithography layer 101 and the second photoresist layer 102 to form the first deep silicon cavity 113 corresponding to the initial silicon cavity 110, and the second deep silicon cavity 114 corresponding to the second etching opening 104.

[0128] In this step, silicon cavities of different depths, namely the first depth silicon cavity 113 and the second depth silicon cavity 114, are ultimately formed in the semiconductor substrate 100. Optionally, the depth d3 of the first depth silicon cavity 113 is between 200μm and 350μm, and can be 250μm, 280μm, or 300μm; the depth d2 of the second depth silicon cavity 114 is between 100μm and 200μm, and can be 50μm, 120μm, or 180μm. In one example, such as... Figure 13 As shown, the process also includes removing the photoresist (the first photoresist layer 101 and the second photoresist layer 102) to form a wafer containing two silicon cavities of different depths. The etching method used here can be either dry etching or wet etching.

[0129] In addition, such as Figure 14As shown, the present invention also provides a comparative example in which the method for fabricating silicon cavities of different depths in a silicon substrate 300 is a two-step etching method. Specifically, after photoresist coating, exposure, and development to form a pattern of one depth of silicon cavity, the photoresist is etched out and removed. Then, another layer of photoresist 301 is coated, and the pattern of another depth of silicon cavity is exposed, developed, and etched out. Due to the poor coverage of the photoresist when coating deep silicon cavities, this existing method cannot completely cover the first depth of silicon cavity 303 etched in the first etching when the photoresist 301 is coated a second time. Figure 14 As shown in (a), this results in the destruction of the previously etched silicon cavity 303 morphology when etching the silicon cavity 302 at the second depth, forming a bad spot 304, as shown in (a). Figure 14 (b) and Figure 14 (c) shows the process. Furthermore, the two-step etching method involves a process of photoresist coating and exposure – etching – re-coating and exposure – re-etching. Since photolithography and etching are performed in different process equipment, this repeated process wastes time and reduces efficiency in wafer manufacturing, and the wafer is also easily contaminated during equipment switching. The present invention addresses this by coating two layers of photoresist with different etching options and thicknesses (a first photoresist layer and a second photoresist layer) and using different exposure processes such as half-exposure or over-exposure to form patterns of cavities at all different depths (a first etching opening and a second etching opening) before a single etching operation. The surface photoresist is cleaned before etching the silicon cavity at the previous depth (such as the first depth silicon cavity) and the next depth silicon cavity (such as the second depth silicon cavity). This allows for the etching of silicon cavities of different depths (the first depth silicon cavity and the second depth silicon cavity) in a single operation, avoiding the problem of poor photoresist coverage when applying photoresist to the deep silicon cavity (the first depth silicon cavity), and also improving work efficiency.

[0130] In summary, this invention forms two photoresist layers, namely a first photoresist layer and a second photoresist layer, to create photoresist patterns for cavities of different depths before a single etching operation. During the etching process, by changing the etching atmosphere and etching energy, the surface photoresist is cleaned before etching the silicon cavities of the previous depth and the silicon cavities of the next depth are etched. This achieves single etching of silicon cavities of different depths, avoiding the problem of poor photoresist coverage when coating deep silicon cavities, while also improving work efficiency and reducing contamination. This invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0131] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for etching different depth silicon cavities in a microsystem module in one etching step, characterized in that, The method comprises the following steps: providing a semiconductor substrate; forming a first photoresist layer and a second photoresist layer on the semiconductor substrate in sequence; forming a first etching opening penetrating the first photoresist layer and the second photoresist layer and a second etching opening penetrating the second photoresist layer, wherein the first etching opening corresponds to a first-depth silicon cavity to be formed, the second etching opening corresponds to a second-depth silicon cavity to be formed, and the first-depth silicon cavity has a greater depth than the second-depth silicon cavity; etching downward based on the first photoresist layer and the second photoresist layer to form an initial silicon cavity with a preset depth in the semiconductor substrate at a position corresponding to the first etching opening and to remove a photoresist layer with a preset thickness at a position corresponding to the second etching opening; wherein the preset depth is between 50 μm and 150 μm, and the preset thickness is greater than 3 / 5 of the thickness of the first photoresist layer; removing the remaining first photoresist layer to expose the semiconductor substrate at a position corresponding to the second etching opening; continuing etching downward based on the first photoresist layer and the second photoresist layer to form the first-depth silicon cavity by continuing etching at the initial silicon cavity and to form the second-depth silicon cavity at the second etching opening; wherein the step of forming the first etching opening and the second etching opening comprises: forming a first opening and a second opening in the second photoresist layer by using a first photoetching process, wherein the second opening forms the second etching opening; forming a third opening in the first photoresist layer below the first opening by using a second photoetching process, wherein the first opening and the third opening form the first etching opening.

2. The method according to claim 1, wherein the different depths of the silicon cavities are etched in one step. After forming the first photoresist layer, the method further comprises the step of soft baking the first photoresist layer at a temperature between 85 ℃ and 135 ℃ for a time between 2 min and 10 min.

3. The method of claim 1, wherein the different depths of the silicon cavities are etched in one step. After forming the second photoresist layer, the method further comprises the step of soft baking the second photoresist layer and the first photoresist layer at a temperature between 85 ℃ and 135 ℃ for a time between 2 min and 10 min.

4. The method of claim 1, wherein the different depths of the silicon cavities are etched in one step. The thickness of the first photoresist layer is between 1 μm and 100 μm, and the thickness of the second photoresist layer is between 1 μm and 100 μm.

5. The method of claim 1, wherein the different depths of the silicon cavities are etched in one step. The first photoetching process comprises a first exposure and a first development, and the second photoetching process comprises a second exposure and a second development, wherein the second exposure is followed by the step of baking at a temperature between 50 ℃ and 100 ℃ for a time between 1 min and 30 min, and the second development is followed by the step of hard baking at a temperature between 50 ℃ and 150 ℃ for a time between 0.5 h and 1.5 h.

6. The method according to any one of claims 1-5, wherein the method is a one-etch method for different depth silicon cavities of a microsystem module, characterized in that, The depth of the first-depth silicon cavity is between 200 μm and 350 μm, and the depth of the second-depth silicon cavity is between 100 μm and 200 μm.

7. A method for etching different depth silicon cavities in a microsystem module in one etching step, characterized in that The method comprises the following steps: providing a semiconductor substrate; forming a first photoresist layer and a second photoresist layer on the semiconductor substrate in sequence; forming a first etching opening penetrating the first photoresist layer and the second photoresist layer and a second etching opening penetrating the second photoresist layer, wherein the first etching opening corresponds to a first depth silicon cavity to be formed, and the second etching opening corresponds to a second depth silicon cavity to be formed, and the first depth silicon cavity has a greater depth than the second depth silicon cavity; etching downwardly based on the first photoresist layer and the second photoresist layer to form an initial silicon cavity with a preset depth in the semiconductor substrate at a position corresponding to the first etching opening, and etching to remove the first photoresist layer with a preset thickness at a position corresponding to the second etching opening; wherein the preset depth is between 50-150 μm, and the preset thickness is greater than 3 / 5 of the thickness of the first photoresist layer; removing the remaining first photoresist layer to expose the semiconductor substrate at a position corresponding to the second etching opening, and continuing etching downwardly based on the first photoresist layer and the second photoresist layer to form the first depth silicon cavity corresponding to the initial silicon cavity, and form the second depth silicon cavity corresponding to the second etching opening; wherein the step of forming the first etching opening and the second etching opening comprises: performing a third exposure process on the second photoresist layer to form a first exposure area and a second exposure area in the second photoresist layer, wherein the first exposure area corresponds to the position of the first etching opening, and the second exposure area corresponds to the position of the second etching opening; performing a fourth exposure process on the second photoresist layer and the first photoresist layer to form a third exposure area in the first photoresist layer, wherein the third exposure area corresponds to the first exposure area; performing a post-baking process with a temperature between 50-100 ℃ and a time between 1-30 min; performing a third development process on the first photoresist layer and the second photoresist layer to form the first etching opening corresponding to the first exposure area and the third exposure area, and form the second etching opening corresponding to the second exposure area; and performing a hard-baking process with a temperature between 50-150 ℃ and a time between 0.5-1.5 h.

8. The method of claim 7, wherein the different depths of the silicon cavities are etched in one step. The step of forming the first photoresist layer further comprises a soft-baking process with a temperature between 85-135 ℃ and a time between 2-10 min.

9. The method of claim 7, wherein the different depths of the silicon cavities are etched in one step. The step of forming the second photoresist layer further comprises a soft-baking process with a temperature between 85-135 ℃ and a time between 2-10 min on the second photoresist layer and the first photoresist layer.

10. The method of claim 7, wherein the different depths of the silicon cavities are etched in one step. The thickness of the first photoresist layer is between 1-100 μm, and the thickness of the second photoresist layer is between 1-100 μm.

11. A method of etching different depth silicon cavities in a microsystem module according to any of claims 7-10, characterized in that, The depth of the first depth silicon cavity is between 200-350 μm, and the depth of the second depth silicon cavity is between 100-200 μm.

12. A method for etching different depth silicon cavities in a microsystem module in one etching step, characterized in that The method comprises the following steps: providing a semiconductor substrate; forming a first photoresist layer and a second photoresist layer on the semiconductor substrate in sequence; forming a first etching opening penetrating through the first photoresist layer and the second photoresist layer and a second etching opening penetrating through the second photoresist layer, wherein the first etching opening corresponds to a first depth silicon cavity to be formed, and the second etching opening corresponds to a second depth silicon cavity to be formed, and the first depth silicon cavity has a greater depth than the second depth silicon cavity; etching downwardly based on the first photoresist layer and the second photoresist layer to form an initial silicon cavity with a preset depth in the semiconductor substrate at a position corresponding to the first etching opening, and etching to remove the first photoresist layer with a preset thickness at a position corresponding to the second etching opening; wherein the preset depth is between 50-150 μm, and the preset thickness is greater than 3 / 5 of the thickness of the first photoresist layer; removing the remaining first photoresist layer to expose the semiconductor substrate at a position corresponding to the second etching opening, and continuing etching downwardly based on the first photoresist layer and the second photoresist layer to form the first depth silicon cavity by continuing etching the initial silicon cavity, and form the second depth silicon cavity corresponding to the second etching opening; wherein the step of forming the first etching opening and the second etching opening comprises: a) forming a fourth opening in the second photoresist layer by a third photoetching process, wherein the fourth opening constitutes the second etching opening; b) forming a fifth opening penetrating through the second photoresist layer and the first photoresist layer by a fourth photoetching process, wherein the fifth opening constitutes the first etching opening; wherein step a) is performed before step b), or step b) is performed before step a).

13. The method of claim 12, wherein the different depths of the silicon cavities are etched in one step. The third photoetching process comprises a fifth exposure and a fourth development process; the fourth photoetching process comprises a sixth exposure and a fifth development process, wherein the sixth exposure is followed by a post-baking step with a temperature between 50-100 ℃ and a time between 1-30 min; and the fifth development is followed by a hard-baking step with a temperature between 50-150 ℃ and a time between 0.5-1.5 h.

14. The method of claim 12, wherein the different depths of the silicon cavities are etched in one step. The step of forming the first photoresist layer further comprises a soft-baking step with a temperature between 85-135 ℃ and a time between 2-10 min.

15. The method of claim 12, wherein the different depths of the silicon cavities are etched in one step. The step of forming the second photoresist layer further comprises a soft-baking step with a temperature between 85-135 ℃ and a time between 2-10 min for the second photoresist layer and the first photoresist layer.

16. The method of claim 12, wherein the different depths of the silicon cavities are etched in one step. The thickness of the first photoresist layer is between 1-100 μm, and the thickness of the second photoresist layer is between 1-100 μm.

17. A method of etching different depth silicon cavities in a microsystem module according to any of claims 12-16, characterized in that The depth of the first depth silicon cavity is between 200-350 μm, and the depth of the second depth silicon cavity is between 100-200 μm.

18. A method for etching different depth silicon cavities in a microsystem module in one etching step, characterized in that The method comprises the following steps: providing a semiconductor substrate; forming a first photoresist layer and a second photoresist layer on the semiconductor substrate in sequence; forming a first etching opening penetrating through the first photoresist layer and the second photoresist layer and a second etching opening penetrating through the second photoresist layer, wherein the first etching opening corresponds to a first depth silicon cavity to be formed, and the second etching opening corresponds to a second depth silicon cavity to be formed, and the first depth silicon cavity has a greater depth than the second depth silicon cavity; etching downwardly based on the first photoresist layer and the second photoresist layer to form an initial silicon cavity with a preset depth in the semiconductor substrate at a position corresponding to the first etching opening, and to remove the first photoresist layer with a preset thickness at a position corresponding to the second etching opening, wherein the preset depth is between 50-150 μm, and the preset thickness is greater than 3 / 5 of the thickness of the first photoresist layer; removing the remaining first photoresist layer to expose the semiconductor substrate at a position corresponding to the second etching opening, and continuing etching downwardly based on the first photoresist layer and the second photoresist layer to form the first depth silicon cavity by continuing etching the initial silicon cavity, and to form the second depth silicon cavity corresponding to the second etching opening; wherein the step of forming the first etching opening and the second etching opening comprises: c) performing a seventh exposure process on the second photoresist layer to form a fourth exposure area in the second photoresist layer, wherein the fourth exposure area corresponds to a position of the second etching opening; d) performing an eighth exposure process on the second photoresist layer and the first photoresist layer to form a fifth exposure area penetrating through the first photoresist layer and the second photoresist layer, wherein the fifth exposure area corresponds to a position of the first etching opening; wherein the step c) is performed before the step d) or the step d) is performed before the step c); e) performing a post-baking with a temperature between 50-100 °C and a time between 1-30 min; f) performing a sixth developing process on the first photoresist layer and the second photoresist layer to form the second etching opening corresponding to the fourth exposure area, and to form the first etching opening corresponding to the fifth exposure area; g) performing a hard-baking with a temperature between 50-150 °C and a time between 0.5-1.5 h.

19. The method of claim 18, wherein the different depths of the silicon cavities are etched in one step. After forming the first photoresist layer, a step of performing a soft-baking on the first photoresist layer with a temperature between 85-135 °C and a time between 2-10 min is further included.

20. The method of claim 18, wherein the different depths of the silicon cavities are etched in one step. After forming the second photoresist layer, a step of performing a soft-baking on the second photoresist layer and the first photoresist layer with a temperature between 85-135 °C and a time between 2-10 min is further included.

21. The method of claim 18, wherein the different depths of the silicon cavities are etched in one step. The thickness of the first photoresist layer is between 1-100 μm, and the thickness of the second photoresist layer is between 1-100 μm.

22. The method for etching silicon cavities of different depths in a microsystem module according to any one of claims 18-21, characterized in that, The depth of the first depth silicon cavity is between 200-350 μm, and the depth of the second depth silicon cavity is between 100-200 μm.

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