Multi-register clock driver loaded memory subsystem

Abstract

The present disclosure relates to a memory subsystem loaded with multiple register clock drivers. A memory subsystem architecture is described herein, which includes two register clock driver RCD devices to increase the number of output drivers used to signal the memory of the memory subsystem. In a dual RCD device implementation, a first RCD device and a second RCD device can provide first subchannel C / A information and second subchannel C / A information to the corresponding first group of memories and second group of memories of the memory subsystem respectively at the same time in response to a common clock signal. Because each of the first RCD device and the second RCD device operates in response to the common clock signal, the operation of the first RCD device and the second RCD device can be synchronized so that all subchannel driver circuits drive the corresponding subchannel C / A information at the same time.

Description

Technical Field

[0001] The present disclosure relates to a multi-register clock driver loaded memory subsystem. Background Art

[0002] High data reliability, high-speed memory access, lower power consumption and reduced chip / package size are the features required for semiconductor memory. In some memory module embodiments, many supported memory dies may be limited by the signaling driver on the module. For example, the sub-channel driver circuit system of the register clock driver may only have the physical capacity of driving the command and address bus information to the fixed number of memory devices of the memory module. In addition, the existing memory module architecture only supports a single register clock driver chip. Therefore, the register clock driver circuit may limit the number of supported memory devices, which may limit the size of the memory module. Summary of the invention

[0003] In one aspect, the present disclosure relates to a device, comprising: a first semiconductor package, the first semiconductor package being configured to receive first sub-channel command and address information corresponding to a channel through a first command and address bus and to receive a clock signal, the first package comprising: a first register clock driver, the first register clock driver being configured to provide the first sub-channel command and address information to a first internal command and address bus in response to the clock signal; and a first memory, the first memory being configured to perform a memory access operation in response to the first sub-channel command and address information received through the first internal command and address bus; and a second semiconductor package, the second semiconductor package being configured to receive second sub-channel command and address information corresponding to the channel through a second command and address bus and to receive the clock signal, the second package comprising: a second register clock driver, the second register clock driver being configured to provide the second sub-channel command and address information to a second internal command and address bus in response to the clock signal; and a second memory, the second memory being configured to perform a memory access operation in response to the second sub-channel command and address information received through the second internal command and address bus.

[0004] On the other hand, the present disclosure relates to a memory subsystem, comprising: a first register clock driver, the first register clock driver being configured to receive first subchannel command and address information corresponding to a channel through a first command and address bus and to receive a clock signal, wherein the first register clock driver is further configured to provide the first subchannel command and address information to a first plurality of internal command and address connections in response to the clock signal; a second register clock driver, the second register clock driver being configured to receive second subchannel command and address information corresponding to the channel through a second command and address bus and to receive the clock signal, wherein the second register clock driver is further configured to provide the second subchannel command and address information to a second plurality of internal command and address connections in response to the clock signal; a first group of memories, the first group of memories being configured to perform a memory access operation in response to the first subchannel command and address information received through one of the first plurality of internal command and address connections; and a second group of memories, the second group of memories being configured to perform a memory access operation in response to the second subchannel command and address information received through one of the second plurality of internal command and address connections.

[0005] On the other hand, the present disclosure relates to a method, comprising: receiving a clock signal at a first register clock driver of a memory subsystem and receiving first subchannel command and address information corresponding to a channel through a first command and address bus; receiving the clock signal at a second register clock driver of the memory subsystem and receiving second subchannel command and address information corresponding to the channel through a second command and address bus; providing the first subchannel command and address information to a first plurality of internal command and address connections of a first group of memories coupled to the memory subsystem in response to the clock signal; and providing the second subchannel command and address information to a second plurality of internal command and address connections of a second group of memories coupled to the memory subsystem in response to the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a memory system including a memory subsystem according to an embodiment of the present disclosure.

[0007] Figure 2 is a block diagram of a memory system including a memory subsystem coupled to a memory controller according to an embodiment of the present disclosure.

[0008] Figure 3A and 3B 2 are block diagrams of a two-stack memory package and a single-stack memory package, respectively, according to embodiments of the present disclosure.

[0009] Figure 4 is a block diagram of a memory system including a memory subsystem coupled to a memory controller according to an embodiment of the present disclosure.

[0010] Figure 5 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 6 is a flow chart of a method for dual register clock driver loading of a memory subsystem according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The present disclosure describes a memory subsystem architecture that includes two register clock driver (RCD) devices to increase the number of output drivers used to signal the memory of the memory subsystem, thereby providing the ability to support a greater number of memories, compared to an implementation using only a single RCD device. In some architectures, for a single channel, a memory controller (e.g., or a host, a central processor unit, one or more other processor units, etc.) can provide corresponding command and address (C / A) information in parallel through two independent sub-channels (e.g., using different corresponding groups of C / A signal lines), and a single clock signal for synchronizing the timing of the two sub-channels, so that the corresponding C / A information of each sub-channel is provided to the corresponding memory (e.g., die, device, etc.) group (e.g., memory library, memory package, or some other grouping) at the same time.

[0013] Therefore, in the embodiment of the dual RCD device, the clock signal can be separated (for example, by a clock tee) so that the clock signal is provided to the two RCD devices at the same time. The clock tee can be arranged to reduce the possibility of asynchronous timing between the two RCD devices. In an example, the first RCD device and the second RCD device can be configured to provide the first subchannel C / A information and the second subchannel C / A information to the corresponding first group of memory and the second group of memory of the memory subsystem respectively. Each RCD device in the first RCD device and the second RCD device can include a dual (for example, A and B) independent subchannel driver circuit, and the dual independent subchannel driver circuit is configured to provide the corresponding subchannel C / A information to the corresponding subset of the corresponding memory group. For example, in response to the clock signal, the first subchannel driver circuit of the first RCD device can provide the first subchannel C / A information to the first subset and the second subset of the first group of memory, and at the same time, the second subchannel driver circuit of the first RCD device provides the first subchannel C / A information to the third subset and the fourth subset of the first group of memory. In response to the clock signal, the first sub-channel driver circuit and the second sub-channel driver circuit of the second RCD device can perform similar operations to simultaneously provide second sub-channel C / A information to the corresponding subset of the second group of memories. Because each of the first RCD device and the second RCD device operates in response to the common clock signal, the operation of the first RCD device and the second RCD device can be synchronized so that all sub-channel driver circuits drive the corresponding sub-channel C / A information simultaneously. As previously mentioned, the ability to support more than one RCD device on a memory subsystem can increase the number of output drivers, which can correspondingly provide support for an increase in the number of memories on the memory subsystem compared to an embodiment of a single RCD device memory subsystem.

[0014] Figure 11 is a block diagram of a memory system 100 including a memory subsystem 104 according to an embodiment of the present disclosure. The memory subsystem 104 may be coupled to a C / AA bus, a C / AB bus, and a clock bus providing a clock signal CLK to receive command and address information from a memory controller (e.g., or a host, a central processing unit, one or more other processor units or controllers, a DRAM controller, etc.) (not shown) of the memory system 100. The memory subsystem 104 may include a memory package 110(1) and a memory package 110(2). The memory subsystem 104 may include a memory module, such as a dual in-line memory module (DIMM) (e.g., a registered DIMM, a load-reduced DIMM (LRDIMM), a micro DIMM, a non-volatile DIMM (NVDIMM)) (e.g., including a non-volatile memory and a controller (not shown)) or any other type of DIMM. In some examples, the memory subsystem 104 may include a soldered memory subsystem in addition to the memory modules and / or DIMMs.

[0015] Memory package 110(1) may include register clock driver circuit 112(1) coupled to memory 114(1), and memory package 110(2) may include register clock driver circuit 112(2) coupled to memory 114(2). Register clock driver circuit 112(1) may be configured to receive first subchannel C / A information from C / AA bus and CLK signal, and register clock driver circuit 112(2) may be configured to receive second subchannel C / A information from C / AB bus and CLK signal. The first subchannel C / A information and the second subchannel C / A information may correspond to C / A information of a single channel. The first subchannel C / A information and the second subchannel C / A information may include memory access commands and addresses corresponding to the first subchannel and the second subchannel, chip select signals, etc., respectively. The first subchannel C / A information and / or the second subchannel C / A information may also include information for configuring components of memory subsystem 104 and / or memory package 110(1) and / or memory package 110(2). Register clock driver circuit 112(1) may provide first subchannel C / A information to each of the C / A A1-A4 buses in parallel in response to the CLK signal, and register clock driver circuit 112(2) may provide second subchannel C / A information to each of the C / A B1-B4 buses in parallel in response to the CLK signal.

[0016] Each memory in memory 114(1) may be coupled to a corresponding one of the C / A A1-A4 buses to receive first subchannel C / A information, and each memory in memory 114(2) may be coupled to a corresponding one of the C / A B1-B4 buses to receive second subchannel C / A information. Each memory in memory 114(1) may also be coupled to a corresponding data bus to receive write data from a memory controller and provide read data to the memory controller in response to the first subchannel C / A information. Additionally, each memory in memory 114(2) may be coupled to a corresponding data bus to receive write data from a memory controller and provide read data to the memory controller in response to the second subchannel C / A information. Memory 114(1) and / or memory 114(2) may each include one or more memory devices, packages, and / or memory dies. In some examples, the one or more memory devices or packages may each include one or more memory die stacks. In some examples, memory 114(1) and / or memory 114(2) may each include dynamic random access memory (DRAM) (eg, double data rate (DDR) 4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.).

[0017] In operation, for a given communication channel, the memory controller of the memory system 100 can simultaneously provide corresponding first subchannel C / A information and second subchannel C / A information through two independent subchannels through the C / AA bus and the C / AB bus, respectively, and a single clock signal for synchronizing the timing of the two subchannels to the memory subsystem 104. In some examples, the memory subsystem 104 and / or one or both of the memory packages 110(1) and 110(2) can further include a control plane hub (e.g., a device or chip) (not shown) to provide control plane communication between components of the memory subsystem 104 and / or one or both of the memory packages 110(1) and 110(2), such as the register clock driver circuit 112(1), the register clock driver circuit 112(2), a thermal sensor (not shown), a power management integrated circuit (not shown), etc. or any combination thereof based on at least one of the first subchannel C / A information from the C / AA bus or the second subchannel C / A information from the C / AB bus. Control plane communications may be used to configure parameters of components of the memory subsystem 104 and / or one or both of the memory packages 110(1) and 110(2), such as voltage levels, clock timing characteristics, operating modes, and the like.

[0018] The memory package 110(1) is configured to receive the first sub-channel C / A information and respond to the first sub-channel C / A information to receive write data through a corresponding data bus and store the write data at the memory 114(1) and provide read data from the memory to the memory controller, while the memory package 110(2) is configured to receive the second sub-channel C / A information and respond to the second sub-channel C / A information to receive write data through a corresponding data bus and store the write data at the memory 114(2) and provide read data from the memory to the memory controller.

[0019] Register clock driver circuit 112(1) and register clock driver circuit 112(2) may each be configured to drive first subchannel C / A information and second subchannel C / A information received from C / AA bus and C / AB bus, respectively, to C / AA1-A4 bus and C / AB1-B4 bus, respectively, in response to CLK signal. CLK signal may be separated (e.g., by clock tees) so that the signals are simultaneously routed to register clock driver circuit 112(1) and register clock driver circuit 112(2) and simultaneously received at these register clock driver circuits. The clock tees may be arranged (e.g., impedance matching, trace length and shape, etc.) to reduce the possibility of timing differences at register clock driver circuit 112(1) and register clock driver circuit 112(2). Each of register clock driver circuit 112(1) and register clock driver circuit 112(2) may include dual (e.g., A and B) independent sub-channel driver circuits that are each configured to drive corresponding sub-channel C / A information to corresponding two of the C / A A1-A4 buses or corresponding two of the C / A B1-B4 buses. For example, in response to the CLK signal, a first sub-channel driver circuit of register clock driver circuit 112(1) may provide first sub-channel C / A information to the C / A A1-A2 bus, while a second sub-channel driver circuit of register clock driver circuit 112(1) may provide first sub-channel C / A information to the C / A A3-A4 bus. The sub-channel driver circuits of register clock driver circuit 112(2) may each similarly provide second sub-channel C / A information to corresponding two of the C / A B1-B4 buses in response to the CLK signal.

[0020] The memory 114(1) may be divided into four subsets, wherein the memories in each subset are coupled to a separate bus of the C / A A1-A4 buses to receive the first subchannel C / A information. Similarly, the memory 114(2) may be divided into four subsets, wherein the memories in each subset are coupled to a separate bus of the C / AB1-B4 buses to receive the second subchannel C / A information. One or more memories in the memory 114(1) may receive write data from the memory controller or provide read data to the memory controller through corresponding data buses and perform other operations in response to the first subchannel C / A information. Similarly, one or more memories in the memory 114(2) may receive write data from the memory controller or provide read data to the memory controller through corresponding data buses and perform other operations in response to the second subchannel C / A information.

[0021] It should be understood that the memory subsystem 104 can be scaled to include more than two memory packages, more than two RCD circuits, and / or more than two memory groups, such as to support additional subchannels (e.g., supported by additional C / A buses and / or CLK signals) without departing from the scope of the present disclosure. It should also be understood that each of the register clock driver circuits 112(1) and the register clock driver circuits 112(2) can be configured with additional driver circuits to support more than four independent C / A buses. The ability to support more than one RCD circuit on the memory subsystem 104 can increase the number of output drivers, which can correspondingly provide support for an increase in the number of memories on the memory subsystem 104 compared to a single RCD device memory subsystem embodiment.

[0022] Figure 22 is a block diagram of a memory system 200 including a memory subsystem 204 coupled to a memory controller 202 according to an embodiment of the present disclosure. The memory subsystem 204 can be coupled to a C / AA bus, a C / AB bus, and a clock signal CLK driven by the memory controller 202. The memory controller 202 can include a host, a central processing unit, one or more other processor units or controllers, a DRAM controller, etc. The memory subsystem 204 can include a printed circuit board 205 having traces to support signal lines for the C / AA bus, the C / AB bus, and the CLK signal, and can include infrastructure for supporting the installation of the memory package 210(1) and the memory package 210(2). In some instances, the printed circuit board 205 can include a memory module printed circuit board, such as a DIMM printed circuit board. In other instances, the printed circuit board 205 includes a motherboard printed circuit board, or any other type of printed circuit board. In some examples, the memory subsystem 204 may include memory modules, such as DIMMs (e.g., including registered DIMMs, LRDIMMs, micro DIMMs, NVDIMMs, or any other type of DIMMs). In some examples, the memory subsystem 204 may include a soldered memory subsystem in addition to the memory modules and / or DIMMs. In some examples, Figure 1 The memory subsystem 104 may implement the memory subsystem 204 .

[0023] The memory package 210(1) may include a register clock driver circuit 212(1) coupled to the memory 214(1), and the memory package 210(2) may include a register clock driver circuit 212(2) coupled to the memory 214(2). The register clock driver circuit 212(1) may be configured to receive first subchannel C / A information from the C / AA bus and receive a CLK signal, while the register clock driver circuit 212(2) may be configured to receive second subchannel C / A information from the C / AB bus and receive a CLK signal. The first subchannel C / A information and the second subchannel C / A information may correspond to C / A information of a single channel. The first subchannel C / A information and the second subchannel C / A information may include memory access commands and addresses corresponding to the first subchannel and the second subchannel, chip select signals, etc., respectively. The first subchannel C / A information and / or the second subchannel C / A information may also include information for configuring components of the memory subsystem 204 and / or the memory package 210(1) and / or the memory package 210(2). Register clock driver circuit 212(1) may provide first sub-channel C / A information to each of the C / A A1-A4 buses in parallel (e.g., simultaneously) in response to the CLK signal, and register clock driver circuit 212(2) may provide second sub-channel C / A information to each of the C / A B1-B4 buses in parallel in response to the CLK signal.

[0024] Register clock driver circuit 212(1) may include first driver circuit 240(1) and second driver circuit 242(1) each configured to receive first subchannel C / A information in parallel (e.g., simultaneously) from C / AA bus via 232(1) and clock driver circuit 244(1) configured to receive CLK signal. In response to CLK signal driven from clock driver circuit 244(1), first driver circuit 240(1) may be configured to drive first subchannel C / A information to C / AA1-A2 bus, while second driver circuit 242(1) may be configured to drive first subchannel C / A information to C / AA A3-A4 bus.

[0025] Similarly, register clock driver circuit 212(2) may include first driver circuit 240(2) and second driver circuit 242(2) each configured to receive second subchannel C / A information in parallel (e.g., simultaneously) from C / AB bus via 232(2) and clock driver circuit 244(2) configured to receive CLK signal. In response to CLK signal driven from clock driver circuit 244(1), first driver circuit 240(1) may be configured to drive second subchannel C / A information to C / A B1-B2 bus, while second driver circuit 242(1) may be configured to drive second subchannel C / A information to C / A B3-B4 bus.

[0026] Each memory in memory 214(1) may be coupled to a corresponding one of the C / A A1-A4 buses to receive first subchannel C / A information, and each memory in memory 214(2) may be coupled to a corresponding one of the C / A B1-B4 buses to receive second subchannel C / A information. Each memory in memory 214(1) may also be coupled to a corresponding data bus to receive write data from a memory controller and provide read data to the memory controller in response to the first subchannel C / A information. Additionally, each memory in memory 214(2) may be coupled to a corresponding data bus to receive write data from a memory controller and provide read data to the memory controller in response to the second subchannel C / A information. Memory 214(1) and / or memory 214(2) may each include one or more memory devices, packages, and / or memory dies. In some examples, the one or more memory devices or packages may each include one or more memory die stacks. In some examples, memory 214(1) and / or memory 214(2) may each include dynamic random access memory (DRAM) (eg, double data rate (DDR) 4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.).

[0027] In operation, for a given communication channel, the C / AA driver and the C / AB driver of the memory controller 202 can simultaneously provide corresponding first sub-channel C / A information and second sub-channel C / A information through two independent sub-channels through the C / AA bus and the C / AB bus, respectively, while the CLK driver provides a single clock signal for synchronizing the timing of the two sub-channels to the memory subsystem 204 through the clock signal line. In some examples, the logic chip on 206 and / or one or both of the memory packages 210(1) and 210(2) may further include a control plane hub (e.g., a device or chip) (not shown) to provide control plane communications between components of the memory subsystem 204 and / or one or both of the memory packages 210(1) and 210(2), such as the register clock driver circuit 212(1), the register clock driver circuit 212(2), a thermal sensor (not shown), a power management integrated circuit (not shown), etc., or any combination thereof, based on at least one of the first subchannel C / A information from the C / AA bus or the second subchannel C / A information from the C / AB bus. The control plane communications may be used to configure parameters of components of the memory subsystem 204 and / or one or both of the memory packages 210(1) and 210(2), such as voltage levels, clock timing characteristics, operating modes, etc.

[0028] The memory package 210(1) is configured to receive the first sub-channel C / A information and respond to the first sub-channel C / A information to receive write data through a corresponding data bus and store the write data at the memory 214(1) and provide read data from the memory to the memory controller, while the memory package 210(2) is configured to receive the second sub-channel C / A information and respond to the second sub-channel C / A information to receive write data through a corresponding data bus and store the write data at the memory 214(2) and provide read data from the memory to the memory controller.

[0029] Register clock driver circuit 212(1) and register clock driver circuit 212(2) can each be configured to drive first subchannel C / A information and second subchannel C / A information received from C / AA bus and C / AB bus, respectively, to C / A A1-A4 bus and C / A B1-B4 bus, respectively, in response to CLK signal. CLK signal can be separated (e.g., by clock tees) so that the signals are simultaneously routed to register clock driver circuit 212(1) and register clock driver circuit 212(2) and simultaneously received at these register clock driver circuits. The clock tees can be arranged (e.g., impedance matching, trace length and shape, etc.) to reduce the possibility of timing differences between register clock driver circuit 212(1) and register clock driver circuit 212(2).

[0030] The first driver circuit 240(1) and the second driver circuit 242(1) of the register clock driver circuit 212(1) can each receive the first subchannel C / A information from the C / AA bus in parallel (e.g., simultaneously), and the clock driver circuit 244(1) can receive the CLK signal. The C / AA bus can be separated by the three-way 230(1) to provide the first subchannel C / A information to each driver circuit in the first driver circuit 240(1) and the second driver circuit 242(1). In response to the CLK signal driven from the clock driver circuit 244(1), the first driver circuit 240(1) can drive the first subchannel C / A information to the C / A A1-A2 bus, and the second driver circuit 242(1) can drive the first subchannel C / A information to the C / A A3-A4 bus.

[0031] The first driver circuit 240(2) and the second driver circuit 242(2) of the register clock driver circuit 212(2) can receive the second subchannel C / A information from the C / AB bus in parallel (e.g., simultaneously), and the clock driver circuit 244(2) can receive the CLK signal. The C / AB bus can be separated by the tee 230(2) to provide the first subchannel C / A information to each of the first driver circuit 240(2) and the second driver circuit 242(2). In response to the CLK signal driven from the clock driver circuit 244(1), the first driver circuit 240(1) can drive the second subchannel C / A information to the C / A B1-B2 bus, and the second driver circuit 242(1) can drive the second subchannel C / A information to the C / A B3-B4 bus. The second driver circuit 242(1), the clock driver circuit 244(1), the second driver circuit 242(2), and the clock driver circuit 244(2) can all operate in a synchronous manner with timing based on the common CLK signal.

[0032] The memory 214(1) can be divided into four subsets, wherein the memories in each subset are coupled to a separate bus of the C / A A1-A4 buses to receive the first subchannel C / A information. Similarly, the memory 214(2) can be divided into four subsets, wherein the memories in each subset are coupled to a separate bus of the C / A B1-B4 buses to receive the second subchannel C / A information. One or more memories in the memory 214(1) can receive write data from the memory controller or provide read data to the memory controller through corresponding data buses and perform other operations in response to the first subchannel C / A information. Similarly, one or more memories in the memory 214(2) can receive write data from the memory controller or provide read data to the memory controller through corresponding data buses and perform other operations in response to the second subchannel C / A information.

[0033] It should be understood that the memory subsystem 204 can be scaled to include more than two memory packages, more than two RCD circuits, and / or more than two memory groups, such as to support additional subchannels (e.g., supported by additional C / A buses and / or CLK signals) without departing from the scope of the present disclosure. It should also be understood that each of the register clock driver circuits 212(1) and the register clock driver circuits 212(2) can be configured with additional driver circuits to support more than four independent C / A buses. The ability to support more than one RCD circuit on the memory subsystem 204 can increase the number of output drivers, which can correspondingly provide support for an increase in the number of memories on the memory subsystem 204 compared to a single RCD device memory subsystem embodiment.

[0034] Figure 3A and 3B 3 and 4 are block diagrams of a dual stack memory package 310 and a single stack memory package 311 according to embodiments of the present disclosure. In some examples, Figure 1 The memory package 110(1) and / or the memory package 110(2) and / or Figure 2 The memory package 210 ( 1 ) and / or the memory package 210 ( 2 ) may implement a dual stack memory package 310 and / or a single stack memory package 311 .

[0035] Figure 3A A side view 301 and a top (eg, plan) view 302 of a dual stack memory package 310 are included. Figure 3A3, side view 301 depicts memory package 310 from the perspective of side 305 of memory package 310 (i.e., to the right of top view 302). Dual stack memory package 310 may include register clock driver circuit 312 and memory 314. Register clock driver circuit 312 may be configured to perform reference Figure 1 The register clock driver circuit 112(1) or the register clock driver circuit 112(2) and / or Figure 2 The dual stack memory package 310 may be coupled to a C / A bus (eg, Figure 1 and / or 2) to receive the corresponding subchannel C / A information, coupled to the clock signal line to receive the clock signal CLK (e.g., Figure 1 and / or CLK signals of 2), and is coupled to a corresponding data bus to receive write data and provide read data.

[0036] Memory 314 may include die stacks 342(1) and die stacks 342(2), each of which includes ten of memory die 360 ​​stacked in a tile or cascade stack arrangement (e.g., each of memory die 360 ​​is horizontally offset from an adjacent memory die 360). In some examples, each of memory die 360 ​​may include a DRAM architecture, such as a DDR4 DRAM, a DDR5 DRAM, a DDR6 DRAM, etc. Each of memory die 360 ​​of die stack 342(1) and die stack 342(2) may be coupled to other circuitry via corresponding wire bonds 350 to perform memory access operations. It should be understood that die stacks 342(1) and die stacks 342(2) may include more or less than ten of memory die 360 ​​without departing from the scope of the present disclosure. It should also be understood that in some examples, die stack 342(1) may include a different number of memory dies 360 than die stack 342(2). It should also be understood that die stack 342(1) and / or die stack 342(2) may be arranged using other stacking and connection implementations (e.g., 3D TSV stacking) without departing from the scope of the present disclosure.

[0037] In some examples, the dual stack memory package 310 may further include a control plane hub (e.g., a device or chip) (not shown) to provide control plane communications between components of the dual stack memory package 310, such as register clock driver circuits 312, thermal sensors (not shown), power management integrated circuits (not shown), etc., or any combination thereof, based on corresponding sub-channel C / A information from corresponding C / A buses. The control plane communications may be used to configure parameters of the components of the dual stack memory package 310, such as voltage levels, clock timing characteristics, operating modes, etc.

[0038] Figure 3B A side view 303 and a top (eg, plan) view 304 of a single stack memory package 311 are included. Figure 3B 3, side view 303 depicts memory package 311 from the perspective of side 306 of memory package 310 (i.e., to the right of top view 304). Single stack memory package 311 may include register clock driver circuit 312 and memory 315. Register clock driver circuit 312 may be configured to perform reference Figure 1 The register clock driver circuit 112(1) or the register clock driver circuit 112(2) and / or Figure 2 The single stack memory package 311 may be coupled to a C / A bus (eg, Figure 1 and / or 2) to receive the corresponding subchannel C / A information, coupled to the clock signal line to receive the clock signal CLK (e.g., Figure 1 and / or CLK signals of 2), and is coupled to a corresponding data bus to receive write data and provide read data.

[0039] The memory 315 may include a die stack 343 including 20 of the memory dies 360 stacked in a tile or cascade stack arrangement (e.g., each of the memory dies 360 is horizontally offset from an adjacent one of the memory dies 360). Each of the memory dies 360 of the die stack 343 may be coupled to other circuitry via corresponding wire bonds 350 to perform memory access operations. It should be understood that the die stack 343 may include more or less than 20 of the memory dies 360 without departing from the scope of the present disclosure. It should also be understood that the die stack 343 may be arranged using other stacking and connection implementations (e.g., 3D through silicon via stacking) without departing from the scope of the present disclosure.

[0040] In some examples, the dual stack memory package 310 may further include a control plane hub (e.g., a device or chip) (not shown) to provide control plane communications between components of the single stack memory package 311, such as register clock driver circuits 312, thermal sensors (not shown), power management integrated circuits (not shown), etc., or any combination thereof, based on corresponding sub-channel C / A information from corresponding C / A buses. The control plane communications may be used to configure parameters of the components of the single stack memory package 311, such as voltage levels, clock timing characteristics, operating modes, etc.

[0041] Figure 4 4 is a block diagram of a memory system 400 including a memory subsystem 404 coupled to a memory controller 402 according to an embodiment of the present disclosure. The memory subsystem 404 may include memory modules such as DIMMs (e.g., registered DIMMs, load-reduced DIMMs (LRDIMMs), micro DIMMs, NVDIMMs, or any other type of DIMMs). In some instances, the memory subsystem 404 may include a soldered memory subsystem in addition to the memory modules and / or DIMMs. In some instances, Figure 1 The memory subsystem 104 and / or Figure 2 The memory subsystem 204 may implement the memory subsystem 404 .

[0042] The memory subsystem 404 may be configured to communicate with the memory controller 402 to perform memory access operations based on the clock signal CLK, the first subchannel C / A information from the C / AA bus, the second subchannel C / A information from the C / AB bus, and / or data transmitted by signals through the corresponding data bus. In some examples, the memory controller 402 may include a C / AA bus driver 462 configured to drive the first subchannel C / A information from the C / AA bus, a C / AB bus driver 464 configured to drive the second subchannel C / A information from the C / AB bus, and a clock driver 466 configured to drive the CLK signal through the clock signal line. The memory controller 402 may further include a driver and a receiver (not shown) coupled to the corresponding data bus to provide write data and receive read data, respectively.

[0043] The memory subsystem 404 may include a memory 414(1)-(8) coupled to a register clock driver circuit 412(1) and a memory 414(9)-(16) coupled to a register clock driver circuit 412(2). The register clock driver circuit 412(1) may be configured to receive first subchannel C / A information from a C / AA bus and a CLK signal, and the register clock driver circuit 412(2) may be configured to receive second subchannel C / A information from a C / AB bus and a CLK signal. The first subchannel C / A information and the second subchannel C / A information may correspond to C / A information of a single channel. The first subchannel C / A information and the second subchannel C / A information may include memory access commands and addresses corresponding to the first subchannel and the second subchannel, chip select signals, etc., respectively. The first subchannel C / A information and / or the second subchannel C / A information may also include information for configuring the memory subsystem 404 and / or components of the memory subsystem 404. Register clock driver circuit 412(1) may provide first subchannel C / A information to each of the A1-A2 buses in parallel in response to the CLK signal, and register clock driver circuit 412(2) may provide second subchannel C / A information to each of the C / A B1-B2 buses in parallel in response to the CLK signal. It should be understood that without departing from the scope of the present disclosure, Figure 4 The memory subsystem 404 may include a dual-sided memory module, wherein an opposite side (not shown) of the memory subsystem 404 includes additional memory arranged similarly to the memory 414(0)-(15), and the register clock driver circuit 412(1) and the register clock driver circuit 412(2) may provide first subchannel C / A information and second subchannel C / A information on additional C / A A3-A4 buses and C / AB3-B4 buses, respectively.

[0044] In some examples, memories 414(1)-(16) may all be the same type of memory. In other examples, memories 414(1)-(16) may be a mix of different types of memory. In some examples, memories 414(1)-(16) may be implemented as follows: Figure 1 Memory 114(1) and / or memory 114(2), Figure 1 Memory 214(1) and / or memory 214(2), Figure 3A memory 314 and / or one or more memory dies in memory die 360, Figure 3B 315 and / or one or more memory dies in memory die 360, or any combination thereof. Although memory module 404 is Figure 416 memories 414(1)-(16) are shown in FIG. 1 , but more or fewer memories may be used in other embodiments. In some instances, the memory subsystem 404 may include additional memory (not shown) for error correction code (ECC) storage. Each of the memories 414(1)-(16) may include one or more memory devices, packages, and / or memory dies. In some instances, the one or more memory devices or packages may each include one or more memory die stacks. The memories 414(1)-(16) may include DRAM architectures, such as DDR4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.

[0045] Each of the memories 414(1)-(4) can be coupled to the C / A A1 bus, and each of the memories 414(5)-(8) can be coupled to the C / A A2 bus to receive first subchannel C / A information. Each of the memories 414(9)-(12) can be coupled to the C / A B1 bus, and each of the memories 414(13)-(16) can be coupled to the C / A B2 bus to receive second subchannel C / A information. Each of the memories 414(1)-(16) can also be coupled to a corresponding data bus to receive write data from the memory controller 202 and provide read data to the memory controller in response to the first subchannel C / A information or the second subchannel C / A information.

[0046] In some embodiments, memories 414(1)-(16) may be organized into different physical banks and / or may be included on one or both sides of memory subsystem 404. In some embodiments, there may be 4, 8, 16, or more memories per physical bank, and one or more physical banks may be present in memory subsystem 404. For example, memory subsystem 404 may include a first physical bank (e.g., 16 memories 414(1)-(16)) located on a first side of memory subsystem 404, and a second physical bank located on the back side of memory subsystem 404 (e.g., 16 or more memories located on the reverse side of memory subsystem 404).

[0047] In operation, for a given communication channel, the C / AA bus driver 462 and the C / AB bus driver 464 of 402 can simultaneously provide corresponding first subchannel C / A information and second subchannel C / A information through two independent subchannels through the C / AA bus and the C / AB bus, respectively, while the clock driver 466 provides a single clock signal for synchronizing the timing of the two subchannels to the memory subsystem 404 through the clock signal line. In some examples, the memory subsystem 404 can further include a control plane hub (e.g., a device or chip) (not shown) to provide control plane communication between components of the memory subsystem 404 based on at least one of the first subchannel C / A information from the C / AA bus or the second subchannel C / A information from the C / AB bus, such as the register clock driver circuit 412 (1), the register clock driver circuit 412 (2), a thermal sensor (not shown), a power management integrated circuit (not shown), etc. or based on any combination thereof. The control plane communication can be used to configure parameters of the components of the memory subsystem 404, such as voltage levels, clock timing characteristics, operation modes, etc.

[0048] Register clock driver circuit 412(1) and register clock driver circuit 412(2) can each be configured to drive first subchannel C / A information and second subchannel C / A information received from C / AA bus and C / AB bus, respectively, to C / A A1-A2 bus and C / A B1-B2 bus, respectively, in response to CLK signal. CLK signal can be separated (e.g., by clock tees) so that the signals are simultaneously routed to register clock driver circuit 412(1) and register clock driver circuit 412(2) and simultaneously received at these register clock driver circuits. The clock tees can be arranged (e.g., impedance matching, trace length and shape, etc.) to reduce the possibility of timing differences between register clock driver circuit 212(1) and register clock driver circuit 212(2).

[0049] Each of the memories 414(1)-(4) may receive the first subchannel C / A information via the C / A A1 bus, and each of the memories 414(5)-(8) may receive the first subchannel C / A information via the C / A A2 bus. One or more of the memories 414(1)-(8) may perform a memory access operation in response to the first subchannel C / A information to receive data from a corresponding data bus in communication with the memory controller 402 and to provide data to the data bus.

[0050] Each of the memories 414(9)-(12) may receive the second subchannel C / A information via the C / A B1 bus, and each of the memories 414(13)-(16) may receive the second subchannel C / A information via the C / A B2 bus. One or more of the memories 414(9)-(16) may perform a memory access operation in response to the second subchannel C / A information to receive data from a corresponding data bus in communication with the memory controller 402 and to provide data to the data bus.

[0051] It should be appreciated that memory subsystem 404 may be scaled to include more than 16 (or 32) memories, more than two register clock driver circuits, and / or more than two memory banks, such as to support additional subchannels (e.g., supported by additional C / A buses and / or CLK signals) without departing from the scope of the present disclosure. It should also be appreciated that each of register clock driver circuits 412(1) and register clock driver circuits 412(2) may be configured with additional driver circuits to support more than four independent C / A buses. The ability to support more than one register clock driver circuit on memory subsystem 404 may increase the number of output drivers, which may in turn provide support for an increase in the number of memories on memory subsystem 404 as compared to an embodiment of a single RCD device memory module.

[0052] Figure 5 is a block diagram of a semiconductor device 500 according to at least one embodiment of the present disclosure. The semiconductor device 500 may be a semiconductor memory device such as a DRAM device (eg, double data rate (DDR) 4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.) integrated on a single semiconductor chip. Figure 5 Example device 500 may include a memory package such as a memory die stack positioned on a substrate 523, which may be used as (and may be referred to as) an interface. Although certain components are shown in the die in the memory die stack and certain components are shown on substrate 523, in other example embodiments, other arrangements of components of device 500 between the stack and substrate 523 are possible. In some embodiments, device 500 may include multiple memory die stacks. In other embodiments, the memory die stack may include a single memory die. In some examples, Figure 1 memory package 110(1) and / or memory package 110(2), Figure 2 The memory package 210(1) and / or the memory package 210(2), Figure 3A dual stack memory package 310 and / or either or both of die stack 342(1) and die stack 342(2), Figure 3B Single stack memory package 311 and / or die stack 343, Figure 4 Any one of the memory register clock driver circuits 412 ( 1 )-( 16 ) or any combination thereof may implement the semiconductor device 500 .

[0053] For simplicity and clarity of illustration, Figure 5 Only the components of one memory die in the memory die stack are shown. Typically, different dies in the memory die stack may each have components similar to each other. In some embodiments, each die in the memory die stack may be physically identical to each other. Substrate 523 may act as an interface, and may send information (e.g., data, commands) to the outside and receive information from the outside, while the memory dies in the memory die stack communicate with the components of substrate 523. As described herein, commands and other signals sent by substrate 523 may be sent to all dies in the memory die stack, or may be individually addressed to individual dies in the memory die stack.

[0054] Semiconductor device 500 includes memory array 518. Memory array 518 may be positioned in a die in a stack of memory dies. Memory array 518 is shown as including a plurality of memory banks. Figure 5 In the embodiment of , the memory array 518 is shown to include N+1 memory groups BANK0-N, where N is any integer value, such as 2, 4, 8, 16, 32, etc. Each of the memory groups BANK0-N may include a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. The selection of the word lines WL is performed by a row decoder 508, and the selection of the bit lines BL and / BL is performed by a column decoder 510. The row decoder 508 and the column decoder 510 may also be positioned in the memory die in the memory die stack. Figure 5 In the embodiment of the present invention, the row decoder 508 includes a corresponding row decoder for each memory group, and the column decoder 510 includes a corresponding column decoder for each memory group. The bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMP). The read data from the bit line BL or / BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 520 through the complementary local data line (LIOT / B), the transmission gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 520 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transmission gate TG and the complementary local data line LIOT / B and written into the memory cell MC coupled to the bit line BL or / BL.

[0055] The semiconductor device 500 may employ a plurality of external terminals including a command and address (C / A) terminal coupled to a command and address bus for receiving commands and addresses and a CS signal, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for receiving and providing data (e.g., via a multi-channel data bus), and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The external terminals may be positioned on the substrate 523.

[0056] The clock terminal is supplied with external clocks CK and / CK provided to the input circuit 514. The external clocks may be complementary. The input circuit 514 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 510 and the internal clock generator 512. The internal clock generator 512 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 522 to time the operation of the circuits included in the input / output circuit 522, for example, to the data receiver to time the reception of the write data.

[0057] The memory address can be supplied to the C / A terminal. The memory address supplied to the C / A terminal is transmitted to the address decoder 504 through the command / address input circuit 502. The address decoder 504 receives the address and supplies the decoded row address XADD to the row decoder 508 and supplies the decoded column address YADD to the column decoder 510. The address decoder 504 can also supply the decoded group address BADD, which can indicate the group containing the decoded row address XADD and column address YADD in the memory array 518. In some embodiments, the address decoder 504 can also indicate a specific memory die in the memory die stack for activation. Commands can be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory (such as read commands for performing read operations and write commands for performing write operations) and other commands and operations. The access command can be associated with one or more row addresses XADD, column addresses YADD and group addresses BADD to indicate one or more memory cells to be accessed.

[0058] The command may be provided as an internal command signal to the command decoder 506 through the command / address input circuit 502. The command decoder 506 includes circuits for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 506 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0059] The semiconductor device 500 may receive an access command as a read command. When the read command is received and the group address, row address, and column address (and optionally the die address) are supplied in time by the read command, read data is read from the memory cell corresponding to the row address and the column address in the memory array 518. The read command is received by the command decoder 506, which provides an internal command so that the read data from the memory array 518 is provided to the read / write amplifier 520. The read data is output to the outside from the data terminal DQ through the input / output circuit 522.

[0060] The semiconductor device 500 can receive an access command as a write command. When the write command is received and the group address, row address and column address (and optional die address) are supplied in time by the write command, the write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and column address in the memory array 518. The write command is received by the command decoder 506, which provides an internal command so that the write data is received by the data receiver in the input / output circuit 522. A write clock can also be provided to the external clock terminal for timing the reception of the write data by the data receiver of the input / output circuit 522. The write data is supplied to the read / write amplifier 520 through the input / output circuit 522, and is supplied to the memory array 518 by the read / write amplifier 520 to be written into the memory cell MC.

[0061] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 524. The internal voltage generator circuit 524 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 508, the internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 518, and the internal potential VPERI is used in many peripheral circuit blocks.

[0062] Power supply potentials VDDQ and VSSQ are also supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 522. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 522 so that the power supply noise generated by the input / output circuit 522 does not propagate to other circuit blocks.

[0063] Figure 6 6 is a flow chart of a method 600 for dual register clock driver loading of a memory subsystem according to an embodiment of the present disclosure. Figure 1 The memory subsystem 104, Figure 2 The memory subsystem 204, Figure 3A Dual stack memory package 310, Figure 3B Single stack memory package 311, Figure 4 The method 600 is performed by the memory subsystem 404 or any combination thereof.

[0064] At 610, method 600 may include receiving, at a first register clock driver of a memory subsystem, first subchannel command and address information corresponding to a channel via a first command and address bus and receiving a clock signal. At 620, method 600 may include receiving, at a second register clock driver of the memory subsystem, second subchannel command and address information corresponding to a channel via a second command and address bus and receiving a clock signal. The first register clock driver and / or the second register clock driver may include Figure 1 register clock driver circuit 112(1) and / or register clock driver circuit 112(2), Figure 2 register clock driver circuit 212(1) and / or register clock driver circuit 212(2), Figure 3A and 3B The register clock driver circuit 312, Figure 4 The register clock driver circuit 412(1) and / or the register clock driver circuit 412(2) or any combination thereof. The first command and address bus and the second command and address bus and the clock signal may include Figure 1 The C / AA bus and / or C / AB bus and CLK signal, Figure 2 The C / AA bus and / or C / AB bus and CLK signal, Figure 3A and 3BC / A bus and CLK signal, Figure 4 The C / AA bus and / or C / AB bus and the CLK signal or any combination thereof.

[0065] At 630, method 600 may include providing first subchannel command and address information to a first plurality of internal command and address connections (e.g., buses, signal lines, etc.) coupled to a first group of memories of the memory subsystem in response to the clock signal. At 640, method 600 may include providing second subchannel command and address information to a second plurality of internal command and address connections coupled to a second group of memories of the memory subsystem in response to the clock signal. The first group of memories and / or the second group of memories may include Figure 1 Memory 114(1) and / or memory 114(2), Figure 2 Memory 214(1) and / or memory 214(2), Figure 3A Memory 314, Figure 3B Memory 315, Figure 4 414(1)-(16) or any combination thereof. In some examples, the first plurality of internal command and address connections and / or the second plurality of internal command and address connections include more than two buses. The first plurality of internal command and address connections may include Figure 1 C / A A1-A4 bus, Figure 2 C / A A1-A4 bus, Figure 3A and 3B C / A bus, Figure 4 C / A A1-A2 (and A3-A4 - not shown) or any combination thereof. The second plurality of internal command and address connections may include Figure 1 C / A B1-B4 bus, Figure 2 C / A B1-B4 bus, Figure 3A and 3B C / A bus, Figure 4 The first and second groups of memory include DRAM (e.g., DDR4, DDR5, DDR6, etc.). In some examples, providing first subchannel command and address information to the first plurality of internal command and address connections occurs simultaneously with providing subchannel command and address information to the second plurality of internal command and address connections.

[0066] In some instances, method 600 may include driving first (or second) sub-channel command and address information to a first subset of the first (or second) plurality of internal command and address connections via a first driver circuit of a first (or second) register clock driver, and driving first (or second) sub-channel command and address information to a second subset of the first (or second) plurality of internal command and address connections via a second driver circuit of the first (or second) register clock driver.

[0067] In some examples, method 600 may further include performing a first memory access operation at one of the first group of memories in response to a first subchannel command and address information, and performing a second memory access operation at one of the second group of memories in response to a second subchannel command and address information. The first memory access operation and the second memory access operation may include any memory operation, including a read or write operation.

[0068] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes or separated and / or performed in separate devices or device portions according to the present systems, devices, and methods.

[0069] The foregoing description of certain embodiments is merely exemplary in nature and is not intended to limit the scope of the present disclosure or its application or use. In the detailed description of the embodiments of the system and method of the present invention, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific embodiments of the described systems and methods are illustrated by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, when the detailed description of certain features is obvious to those skilled in the art, it will not be discussed so as not to obscure the description of the embodiments of the present disclosure. Therefore, the detailed description should not be considered restrictive, and the scope of the present disclosure is limited only by the appended claims.

[0070] Finally, the above discussion is intended to be merely illustrative of the inventive system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the inventive system has been described in particular detail with reference to exemplary embodiments, it should also be understood that a person skilled in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the inventive system as set forth in the following claims. Therefore, the present specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: A first semiconductor package, the first semiconductor package being configured to receive first sub-channel command and address information corresponding to a channel and receive a clock signal through a first command and address bus, the first package comprising: a first register clock driver configured to provide the first subchannel command and address information to a first internal command and address bus in response to the clock signal; and a first memory configured to perform a memory access operation in response to the first subchannel command and address information received via the first internal command and address bus; and A second semiconductor package, the second semiconductor package being configured to receive second sub-channel command and address information corresponding to the channel and the clock signal through a second command and address bus, the second package comprising: a second register clock driver configured to provide the second subchannel command and address information to a second internal command and address bus in response to the clock signal; and A second memory is configured to perform a memory access operation in response to the second sub-channel command and address information received via the second internal command and address bus.

2. The device of claim 1 , wherein the first register clock driver comprises a pair of driver circuits each configured to receive the first sub-channel command and address information, wherein each of the pair of driver circuits is configured to drive the first sub-channel command and address information to a first pair of internal command and address connections and a second pair of internal command and address connections, the first pair of internal command and address connections and the second pair of internal command and address connections each being respectively coupled to a corresponding memory of the first package containing the first memory, wherein the first internal command and address bus is contained in one of the first pair of internal command and address connections or the second pair of internal command and address connections.

3. The device of claim 1 , wherein the second register clock driver comprises a second pair of driver circuits each configured to receive the second sub-channel command and address information, wherein each of the second pair of driver circuits is configured to drive the second sub-channel command and address information to a third pair of internal command and address connections and a fourth pair of internal command and address connections, the third pair of internal command and address connections and the fourth pair of internal command and address connections each being respectively coupled to a corresponding memory of the second package containing the second memory, wherein the second internal command and address bus is contained in one of the third pair of internal command and address connections or the fourth pair of internal command and address connections. 4 . The apparatus of claim 2 , wherein the first semiconductor package is configured to provide a copy of the first command and address information to each driver circuit of the pair of driver circuits in parallel.

5. The apparatus of claim 1 , further comprising a printed circuit board configured to mount the first semiconductor package and the second semiconductor package, wherein the printed circuit board comprises a first set of traces and a second set of traces, the first set of traces being configured to couple the first command and address bus to the first semiconductor package, the second set of traces being configured to couple the second command and address bus to the second semiconductor package. 6 . The apparatus of claim 5 , wherein the printed circuit board further comprises a clock trace configured to couple the clock signal to both the first semiconductor package and the second semiconductor package. 7 . The apparatus of claim 1 , wherein the first register clock driver is a first semiconductor device and the second register clock driver is a second semiconductor device.

8. The apparatus of claim 1, wherein operation of the first register clock driver is synchronized with operation of the second register clock driver.

9. The apparatus of claim 1, wherein the first semiconductor package is associated with a plurality of memory dies, each of the plurality of memory dies being configured to receive the first command and address information from the first register clock driver.

10. A memory subsystem comprising: a first register clock driver configured to receive first sub-channel command and address information corresponding to a channel via a first command and address bus and to receive a clock signal, wherein the first register clock driver is further configured to provide the first sub-channel command and address information to a first plurality of internal command and address connections in response to the clock signal; a second register clock driver configured to receive second subchannel command and address information corresponding to the channel over a second command and address bus and to receive the clock signal, wherein the second register clock driver is further configured to provide the second subchannel command and address information to a second plurality of internal command and address connections in response to the clock signal; a first group of memory configured to perform memory access operations in response to the first subchannel command and address information received via one of the first plurality of internal command and address connections; as well as A second group of memory is configured to perform memory access operations in response to the second subchannel command and address information received via one of the second plurality of internal command and address connections. 11 . The memory subsystem of claim 10 , wherein the first register clock driver is included in a first semiconductor device and the second register clock driver is included in a second semiconductor device.

12. The memory subsystem of claim 10, wherein each of the first group of memory and the second group of memory comprises a respective memory device.

13. The memory subsystem of claim 10, wherein at least two memories of the first group of memories are contained in a first memory die stack and at least two memories of the second group of memories are contained in a second memory die stack.

14. The memory subsystem of claim 10, further comprising a printed circuit board configured to mount the first register clock driver, the first group of memories, the second register clock driver, and the second group of memories.

15. A method comprising: receiving a clock signal at a first register clock driver of the memory subsystem and receiving first sub-channel command and address information corresponding to a channel via a first command and address bus; receiving the clock signal at a second register clock driver of the memory subsystem and receiving second sub-channel command and address information corresponding to the channel via a second command and address bus; providing the first subchannel command and address information to a first plurality of internal command and address connections coupled to a first group of memory of the memory subsystem in response to the clock signal; as well as The second subchannel command and address information is provided to a second plurality of internal command and address connections coupled to a second group of memory of the memory subsystem in response to the clock signal.

16. The method of claim 15, wherein providing the first subchannel command and address information to the first plurality of internal command and address connections occurs simultaneously with providing the second subchannel command and address information to the second plurality of internal command and address connections.

17. The method according to claim 15, further comprising: performing a first memory access operation at one of the first set of memories in response to the first subchannel command and address information; as well as A second memory access operation is performed at one of the second set of memories in response to the second subchannel command and address information.

18. The method of claim 15, further comprising: In response to the clock signal: driving the first subchannel command and address information to a first subset of the first plurality of internal command and address connections via a first driver circuit of the first register clock driver; as well as The first sub-channel command and address information is driven to a second subset of the first plurality of internal command and address connections through a second driver circuit of the first register clock driver.

19. The method of claim 15, wherein the first plurality of internal command and address connections comprises more than two buses.

20. The method of claim 15, wherein the first group of memory and the second group of memory comprise dynamic random access memory.

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