Method of manufacturing a semiconductor-on-insulator structure

Abstract

The application provides a manufacturing method of a semiconductor-on-insulator structure, which comprises the following steps: forming a semiconductor layer with light ion doping on a first wafer with heavy ion doping; forming a first oxide bonding layer on the surface of the semiconductor layer; forming a second oxide bonding layer on the surface of a second wafer; further bonding the first oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer; and removing the first wafer by etching to expose the semiconductor layer, thereby forming the semiconductor-on-insulator structure. The method is simple and easy to perform, and the thickness of the top layer of silicon of the semiconductor-on-insulator structure can be accurately controlled, so that the film thickness of the top layer of silicon of the semiconductor-on-insulator structure is relatively thin, and the manufacturing requirement of high-performance devices is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing, in particular to a manufacturing method of a semiconductor-on-insulator structure. BACKGROUND

[0002] Semiconductor-on-insulator, such as Silicon-On-Insulator (SOI), Germanium-On-Insulator, Silicon-Germanium-On-Insulator, etc., is a semiconductor material with a unique three-layer structure of "bottom semiconductor layer / insulating buried layer / top semiconductor layer", which realizes full dielectric isolation between devices (formed in the top semiconductor layer) and the substrate (i.e. the bottom semiconductor layer) through the insulating buried layer (usually silicon dioxide SiO2), and can completely eliminate the parasitic latch-up effect in CMOS circuits formed by bulk silicon, and the circuit based on the semiconductor-on-insulator substrate also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and is particularly suitable for low-voltage and low-power circuits. Therefore, the semiconductor-on-insulator substrate has been widely used in the field of microelectronics.

[0003] However, the semiconductor-on-insulator substrate manufactured by the traditional technology has problems such as a relatively thick top semiconductor layer and defects on the surface, and cannot meet the demand for further improvement of device performance, so it needs to be improved. SUMMARY

[0004] The purpose of the present application is to provide a manufacturing method of a semiconductor-on-insulator structure, which can make the film thickness of the top silicon in the semiconductor-on-insulator structure thinner to meet the manufacturing demand of high-performance devices.

[0005] To solve the above technical problems, the present application provides a manufacturing method of a semiconductor-on-insulator structure, comprising the following steps:

[0006] providing a first wafer with first ion dense doping;

[0007] forming a second ion light-doped semiconductor layer on the surface of the first wafer;

[0008] forming a first oxide bonding layer on the surface of the semiconductor layer;

[0009] providing a second wafer and forming a second oxide bonding layer on the surface of the second wafer;

[0010] bonding the first oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer;

[0011] removing the first wafer by a wet etching process to expose the semiconductor layer, and the wet etching rate of the wet etching process on the first wafer is greater than the wet etching rate on the semiconductor layer.

[0012] Optionally, in the wet etching process, a wet etching selectivity range of the first wafer to the semiconductor layer is 20-50.

[0013] Optionally, the etchant of the wet etching process comprises at least one of nitric acid, hydrofluoric acid and acetic acid, a molar ratio of nitric acid, hydrofluoric acid and acetic acid in the solution is 1:10:60-1:1:1, a process temperature is 25-45°C, and an etching time is 1-10 minutes.

[0014] Optionally, the first ion dense doping and the second ion light doping are both N-type ion doping or both P-type ion doping, a concentration range of the first ion dense doping is 5E+17 cm -3 -5E+19 cm -3 , and a concentration range of the second ion light doping is 5E+14 cm -3 -5E+16 cm -3 .

[0015] Optionally, a material of the first wafer is monocrystalline silicon, a material of the semiconductor layer is monocrystalline silicon, and a material of the second wafer is monocrystalline silicon.

[0016] Optionally, the first oxide bonding layer and / or the second oxide bonding layer are formed by a vapor deposition process with a process temperature lower than 600°C.

[0017] Optionally, the second wafer comprises a monocrystalline silicon layer and a microcrystalline layer between the monocrystalline silicon layer and the second oxide bonding layer.

[0018] Optionally, the microcrystalline layer comprises at least one of a polysilicon layer, a silicon-germanium alloy layer and a germanium layer.

[0019] Optionally, materials of the first oxide bonding layer and the second oxide bonding layer both comprise silicon dioxide.

[0020] Optionally, after bonding the first oxide bonding layer and the second oxide bonding layer, an entire structure after the bonding is annealed and reinforced, an annealing temperature is 300-1100°C, an annealing time is 30-180 minutes, and an annealing gas comprises at least one of nitrogen, argon and hydrogen.

[0021] Optionally, after bonding the first wafer to the second wafer, and before removing the first wafer by the wet etching process, a surface of the first wafer opposite to the second wafer is polished and thinned.

[0022] Optionally, the manufacturing method further comprises, after removing the first wafer and exposing the semiconductor layer, measuring the thickness of the semiconductor layer, and performing ion reaction treatment on the whole surface or partial surface of the semiconductor layer according to the measurement result of the thickness, so as to further surface finish the semiconductor layer.

[0023] Optionally, the gas used by the ion beam comprises at least one of NF3, CF4, CHF3, oxygen, nitrogen and argon, the energy is 5-500 watts, and the single wafer processing time is 1-30 minutes.

[0024] Optionally, after removing the first wafer and exposing the semiconductor layer, and before further surface finishing the semiconductor layer, the surface of the semiconductor layer is subjected to chemical mechanical polishing.

[0025] Optionally, the manufacturing method further comprises, after removing the first wafer and exposing the semiconductor layer, removing the damage layer on the surface of the semiconductor layer by surface oxidation treatment process and / or anisotropic etching process.

[0026] Optionally, the surface oxidation treatment process comprises: first performing oxidation treatment on the semiconductor layer to form a regrown oxide layer on the semiconductor layer, the process temperature is 700-1100 DEG C, and the thickness of the regrown oxide layer is 100-500 angstroms; and then removing the regrown oxide layer by at least one of wet etching, dry etching or chemical mechanical polishing.

[0027] Optionally, the anisotropic etching process comprises: anisotropic etching the surface of the semiconductor layer by using an alkaline solution to remove the damage layer on the surface of the semiconductor layer.

[0028] Compared with the prior art, the technical scheme of the present application has one of the following beneficial effects:

[0029] Compared with the prior art, the technical scheme of the present application has one of the following beneficial effects:

[0030] 1. The method comprises the following steps: forming a semiconductor layer with light doping of second ions on a first silicon wafer with heavy doping of first ions, forming a first oxide bonding layer on the surface of the semiconductor layer, forming a second oxide bonding layer on the surface of a second wafer, further bonding the first oxide bonding layer and the second oxide bonding layer to bond the first silicon wafer to the second wafer, and then removing the first wafer by a wet etching process to expose the semiconductor layer, thereby forming a semiconductor-on-insulator structure. The process is simple and easy to perform, and the wet etching rate of the first wafer is greater than that of the semiconductor layer in the wet etching process, so that the first silicon wafer is an etching enhancement layer, which can be quickly removed without causing unnecessary damage to the semiconductor layer, so that the top semiconductor layer of the finally formed semiconductor-on-insulator structure is thinner and the film thickness is more uniform.

[0031] 2. The second oxide bonding layer provided on the surface of the second wafer is arranged below a microcrystalline layer, which can form a trap rich layer in the second wafer, hinder the flow of free carriers in the semiconductor-on-insulator structure, reduce parasitic phenomena in the semiconductor-on-insulator structure, and improve the electrical performance of the semiconductor-on-insulator structure.

[0032] 3. After removing the first silicon wafer and exposing the semiconductor layer, the thickness of the semiconductor layer is measured, and according to the measurement result of the thickness, ion beam is used to perform ion bombardment on the whole surface or part of the surface of the semiconductor layer to further perform surface finishing on the semiconductor, so that the thickness of the top semiconductor in the semiconductor-on-insulator structure is further thinned and the film thickness uniformity is further improved.

[0033] 4. After removing the first wafer and exposing the semiconductor layer, surface oxidation treatment or anisotropic etching is performed on the semiconductor layer to remove surface damage of the top semiconductor layer in the semiconductor-on-insulator structure. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a flow chart of the manufacturing method of the semiconductor-on-insulator structure according to an embodiment of the present application.

[0035] Figures 2 to 8 is a schematic diagram of the device cross-sectional structure in the manufacturing method of the semiconductor-on-insulator structure according to an embodiment of the present application.

[0036] The reference signs in the drawings are as follows:

[0037] 10-first wafer; 11-semiconductor layer; 11a-top semiconductor layer; 12-first oxide bonding layer; 13-regenerated oxide layer; 20-second wafer; 200-single crystal silicon layer; 201-microcrystalline layer; 21-second oxide bonding layer. Detailed Implementation

[0038] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. In this document, "and / or" means either one or both.

[0039] Please refer to Figure 1 An embodiment of the present invention provides a method for manufacturing a semiconductor-on-insulator structure, comprising the following steps:

[0040] S1 provides a first wafer heavily doped with the first ion;

[0041] S2, a second ion-lightly doped semiconductor layer is formed on the surface of the first wafer;

[0042] S3, a first oxide bonding layer is formed on the surface of the semiconductor layer;

[0043] S4, a second wafer is provided, and a second oxide bonding layer is formed on the surface of the second wafer;

[0044] S5, bonding the first oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer;

[0045] S6, the first wafer is removed by a wet etching process to expose the semiconductor layer, wherein the wet etching rate of the first wafer is greater than the wet etching rate of the semiconductor layer.

[0046] Please refer to Figure 2 In step S1, a first wafer 10 with concentrated first ion doping is provided. The substrate material of the first wafer 10 can be any substrate material well known in the art, such as silicon, germanium, or germanium-silicon. In this embodiment, the substrate of the first wafer 10 is single-crystal silicon, and it is entirely concentratedly doped with the first ion. The ions in the concentrated first ion doping are N-type or P-type ions, where N-type ions include phosphorus, arsenic, antimony, etc., and P-type ions include boron, indium, gallium, etc. The concentration range of the concentrated first ion doping is 5E+17cm. -3 ~5E+19cm -3 For example, 1E+18cm -3 The surface of the first wafer 10 may be mechanically polished, and its thickness may be, for example, 10 micrometers to 80 micrometers.

[0047] Please continue to refer to this. Figure 2In step S2, an epitaxial growth process such as molecular beam epitaxy (MBE), chemical vapor deposition (CVD), or liquid phase epitaxy (LPE) can be used to form the semiconductor layer 11 on the surface of the first wafer 10. At this time, the thickness of the semiconductor layer 11 can be slightly higher than the thickness of the top semiconductor layer required by the semiconductor-on-insulator structure to be formed, for example, 200 angstroms to 80 microns. Optionally, N-type ions or P-type ions can be doped during the epitaxial growth of the semiconductor layer 11, and further annealing can be performed to form a second ionically lightly doped semiconductor layer 11. Alternatively, N-type ions or P-type ions can be implanted into the semiconductor layer 11 after the epitaxial growth of the semiconductor layer 11 is completed, and further annealing can be performed to form a second ionically lightly doped semiconductor layer 11. The concentration of the second ionically lightly doped semiconductor layer 11 ranges from 5E+14 cm -3 to 5E+16 cm -3 In this step, the epitaxial growth process is used to form the semiconductor layer 11, which can accurately control the thickness of the semiconductor layer 11, and ultimately form a semiconductor-on-insulator structure that meets the requirements. In addition, the main material of the semiconductor layer 11 determines the material of the top semiconductor layer of the semiconductor-on-insulator structure to be formed. For example, when the main material of the semiconductor layer 11 is single crystal silicon, the semiconductor-on-insulator structure produced in this embodiment is a silicon-on-insulator structure. When the main material of the semiconductor layer 11 is germanium, the semiconductor-on-insulator structure produced in this embodiment is a germanium-on-insulator structure. When the main material of the semiconductor layer 11 is silicon germanium, the semiconductor-on-insulator structure produced in this embodiment is a silicon germanium-on-insulator structure.

[0048] Optionally, the second ionically lightly doped semiconductor layer 11 can be further polished to meet the requirements of film thickness uniformity, and the thickness of the polished semiconductor layer 11 is, for example, 200 angstroms to 80 microns. As an example, the thickness of the polished semiconductor layer 11 is 5 microns to 20 microns. A thicker semiconductor layer 11 is beneficial to prevent the semiconductor layer 11 from being completely ground off during mechanical thinning.

[0049] Optionally, the semiconductor layer 11 and the first wafer 10 have the same type of ion doping, i.e., both are N-type ion doping or both are P-type ion doping. In this way, the efficiency of epitaxial growth of the semiconductor layer 11 can be improved, and the diffusion of doping ions in the semiconductor layer 11 and the first wafer 10 can be prevented, which affects the etching selectivity of the two in the subsequent step S6. This is beneficial to make the wet etching process in step S6 stop well at the surface of the semiconductor layer, and ultimately ensure the performance of the top semiconductor layer in the semiconductor-on-insulator structure formed.

[0050] Please refer to Figure 3In step S3, an atomic layer deposition process, a chemical vapor deposition process with a process temperature below 600°C is used to form the first oxide bonding layer 12 on the surface of the semiconductor layer 11. The process temperature for forming the first oxide bonding layer 12 is controlled below 600°C, which can avoid the ion diffusion from the first wafer 10 into the semiconductor layer 11, affect the distribution of the doping ions of the semiconductor layer 11 and the first wafer 10, blur the interface between the semiconductor layer 11 and the first wafer 10, and further reduce the etching selectivity ratio of the semiconductor layer 11 and the first wafer 10 in the subsequent step S6, which causes the wet etching process in step S6 to not stop well at the surface of the semiconductor layer, and further affect the performance of the top semiconductor layer in the semiconductor-on-insulator structure formed in the end. The material of the first oxide bonding layer 12 can include at least one of silicon dioxide and silicon oxynitride. The thickness of the first oxide bonding layer 12 is 2000 angstroms to 5000 angstroms. If the thickness is too thin, it cannot provide a sufficient bonding interface; and if the thickness is too thick, the bonding strength will be reduced to different degrees.

[0051] Please refer to Figure 4 In step S4, first, the second wafer 20 is provided, which can be any suitable substrate material known to those skilled in the art, such as monocrystalline silicon, germanium, silicon germanium, etc. In this embodiment, the second wafer 20 includes a monocrystalline silicon layer 200 at the bottom and a microcrystalline layer 201 on the surface of the monocrystalline silicon layer 200, wherein the microcrystalline layer 201 can include at least one of a polysilicon layer, a silicon germanium alloy layer, a metal silicide, a metal germanide, and a germanium layer. The grain size of the microcrystalline layer 201 is 1 nanometer to 10 micrometers, and the microcrystalline layer 201 can form a trap rich layer in the second wafer 20, thereby being able to hinder the flow of free carriers in the subsequently formed semiconductor-on-insulator structure, reduce parasitic phenomena in the semiconductor-on-insulator structure, and improve the electrical performance of the semiconductor-on-insulator structure. The thickness of the microcrystalline layer 201 is 1 micrometer to 5 micrometers, and the forming process is, for example, a polysilicon process of low pressure chemical vapor deposition or an ion implantation process. The thickness of the microcrystalline layer needs to be controlled to be above 1 micrometer in order to have sufficient trap capacity, and a polysilicon layer with a thickness exceeding 5 micrometers has problems in process stability and yield.

[0052] Please continue to refer to Figure 4 In step S4, a thermal oxidation process or a chemical vapor deposition process is continued to be used to form the second oxide bonding layer 21 on the surface of the microcrystalline layer 201. The material of the second oxide bonding layer 21 can include at least one of silicon dioxide and silicon oxynitride. The thickness of the second oxide bonding layer 21 is 2000 angstroms to 5000 angstroms. If the thickness is too thin, it cannot provide a sufficient bonding interface; and if the thickness is too thick, the bonding strength will be reduced to different degrees.

[0053] It should be noted that step S4 can be performed after step S3, or after step S1 and before step S3, or simultaneously with step S3, or before step S1. Alternatively, after step S2, the first wafer 10 and the second wafer 20 on which the semiconductor layer 11 is formed are put into the same deposition process equipment to form the first oxide bonding layer 12 and the second oxide bonding layer 21 simultaneously by using the same process condition, thereby simplifying the process and improving the efficiency, i.e., step S4 is performed simultaneously with step S3, and the thickness and performance of the first oxide bonding layer 12 and the second oxide bonding layer 21 formed at this time are basically consistent, which is beneficial to improving the bonding performance in step S5.

[0054] Please refer to Figure 5 In step S5, the first oxide bonding layer 12 and the second oxide bonding layer 21 are bonded together by wafer bonding process and annealing is performed to reliably bond the first wafer 10 together with the semiconductor layer 11 to the second wafer 20.

[0055] It should be noted that in this step, too high annealing temperature can cause ion redistribution between the first wafer 10 and the semiconductor layer 11, and too low annealing temperature is not sufficient to reliably bond the first oxide bonding layer 12 and the second oxide bonding layer 21 together. Moreover, too high annealing temperature and too long annealing time can cause longitudinal diffusion of ion doping in the semiconductor layer 11, affecting the control of ion diffusion depth, and in severe cases, can cause the thickness of the top semiconductor layer of the finally formed semiconductor-on-insulator structure to be uncontrollable. On the other hand, the annealing process in this step can further "smooth" the uneven doping in the semiconductor layer 11 to form a uniform ion doping layer, which is beneficial to the removal of the first wafer 10 in the subsequent step S6 and to the control of the thickness of the remaining semiconductor layer 11. Therefore, it is critical to select a suitable annealing temperature and annealing time. Alternatively, the annealing temperature is 300°C-1100°C, and the annealing time is 30 minutes-180 minutes, and the annealing gas includes at least one inert gas among helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), nitrogen (N2), etc. As an example, the annealing temperature can be 300°C-500°C, and the annealing time is 30 minutes-150 minutes.

[0056] In addition, in this step, the first oxide bonding layer 12 and the second oxide bonding layer 21 can be formed by a vapor deposition process, which has lower density than an oxide layer formed by a thermal oxidation process, can perform atomic diffusion at a lower annealing temperature, and thus has higher bonding strength.

[0057] Please refer to Figure 5 and Figure 6In step S6, the first wafer 10 can be first thinned by a fine chemical mechanical polishing (CMP) process until it is thinned to a proper thickness, for example, to 70 microns. The fine chemical mechanical polishing process can improve the removal efficiency of the first wafer 10 as a whole and provide a good process surface for the subsequent selective wet etching process. Then, a selective wet etching process with a high etching selectivity of the first wafer 10 relative to the semiconductor layer 11 is used to etch and remove the first wafer 10 to expose the semiconductor layer 11. In this step, the backside of the first wafer 10 is thinned before the first wafer 10 is wet etched, which can shorten the overall process time for removing the first wafer 10. In the selective wet etching process, the ion doping concentration in the first wafer 10 and the semiconductor layer 11 is different, so the two layers of materials can have a relatively high etching selectivity, for example, in the range of 20-50. The wet etching selectivity of the wet etching process on the first wafer is greater than that on the semiconductor layer, so the first wafer 10 can be easily removed, and the etching can stop on the surface of the semiconductor layer 11 without causing serious damage to the semiconductor layer 11. As an example, the etchant used includes at least one of nitric acid, hydrofluoric acid and acetic acid, for example, a mixed solution of nitric acid, hydrofluoric acid and acetic acid, with a molar ratio of 1:10:60-1:1:1, for example, 15:25:60. The process temperature is 25-45°C, and the etching time is 1-10 minutes. The etching rate of this mixed solution on high-concentration doped P+Si is very fast (more than 10 microns / min), and the etching rate on low-concentration doped P-Si is very low (less than 0.01 microns / min), so that the etching reaction is self-stopped when it reaches the semiconductor layer 11.

[0058] Optionally, after the first wafer 10 is removed, the semiconductor layer 11 can be further polished by a fine chemical mechanical polishing process to remove the residues on the semiconductor layer 11 after the selective wet etching process and further thin the semiconductor layer 11.

[0059] Further, after removing the first wafer 10 and further polishing and thinning the semiconductor layer 11, the thickness of the semiconductor layer 11 is measured, and the semiconductor layer 11 is further trimmed according to the measurement result of the thickness, so that the thickness of the semiconductor layer 11 is continuously thinned and the film thickness uniformity is further improved. The thickness measurement and trimming process can be performed multiple times until the overall thickness and uniformity of the semiconductor layer 11 meet the requirements. Alternatively, according to the measurement result of the thickness, the overall surface or partial surface of the semiconductor layer 11 is subjected to ion reaction treatment by using an "ion beam surface treatment machine", so as to further trim the semiconductor layer 11. The gas used by the ion beam includes at least one of NF3, CF4, CHF3, oxygen (O2), nitrogen (N2), argon (Ar), etc., the energy range is 5-500 watts, the single wafer processing time is 1-30 minutes, and the energy size and processing time are adjusted according to actual requirements. The surface trimming process of the semiconductor layer 11 by using the ion beam has higher precision than the existing fine chemical mechanical polishing, so that the remaining semiconductor layer 11 (i.e. the top layer silicon of the silicon-on-insulator structure) can be controlled to be thinner and the film thickness is more uniform.

[0060] So far, please refer to Figure 6 and Figure 8 , the semiconductor-on-insulator structure and the top layer semiconductor layer 11a thereof are formed, wherein the second wafer 20 is the bottom layer semiconductor layer of the semiconductor-on-insulator structure, the second oxide bonding layer 21 and the first oxide bonding layer 12 are the insulating buried layer of the semiconductor-on-insulator structure, and the trimmed semiconductor layer 11 is the top layer semiconductor layer 11a of the semiconductor-on-insulator structure. The thickness of the top layer semiconductor layer 11a of the semiconductor-on-insulator structure can reach

[0061] Alternatively, please refer to Figure 7 and Figure 8After the surface of the semiconductor layer 11 is modified by the ion beam, the surface damage of the semiconductor layer 11 is further removed and repaired by a surface oxidation treatment process and / or an anisotropic etching process. An example method for removing and repairing the surface damage of the semiconductor layer 11 is to first perform a high-temperature oxidation treatment on the surface of the semiconductor layer 11, with a process temperature of 700-1100°C, to form a regrown oxide layer 13 on the semiconductor layer 11, the thickness of the regrown oxide layer 13 being 50-500 angstroms. In addition to growing the regrown oxide layer, the high-temperature oxidation condition can also be used to simultaneously reinforce the bonding interface, and the oxidation thickness takes into account the depth of the surface damage layer. Then at least one process including wet etching, dry etching or fine chemical mechanical polishing is used to remove the regrown oxide layer 13. Another example method for removing and repairing the surface damage of the semiconductor layer 11 is to use an alkaline solution such as tetramethylammonium hydroxide (TMAH) to perform anisotropic etching on the surface of the semiconductor layer 11, with an etching time of 15 seconds to 2 minutes and an etching temperature of normal temperature, for example 25-45°C, to remove and repair the surface damage of the semiconductor layer 11. The anisotropic etching of silicon by the alkaline solution has the feature of forming regular crystal planes distributed according to the crystal direction on the wafer surface, thereby obtaining a relatively perfect wafer surface after the surface damage layer is removed.

[0062] Optionally, after the first wafer 10 is removed and the semiconductor layer 11 is exposed, a wet cleaning process is further performed on the semiconductor layer 11 using a cleaning liquid such as deionized water, to remove surface contamination.

[0063] In summary, the technical solution of the present application forms a second ion lightly doped semiconductor layer on a first ion heavily doped first wafer, forms a first oxide bonding layer on the surface of the semiconductor layer, forms a second oxide bonding layer on the surface of a second wafer, further bonds the first oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer, then removes the first wafer by an etching process to expose the semiconductor layer, and further forms a semiconductor-on-insulator structure. The process is simple and easy to perform, and the semiconductor layer can be used to accurately define the thickness of the top layer silicon of the semiconductor-on-insulator structure to be formed, so that the film thickness of the top layer semiconductor layer in the semiconductor-on-insulator structure is relatively thin, meeting the manufacturing requirements of high-performance devices, and the high etching selectivity between the first wafer and the semiconductor layer can be used to etch and remove the first wafer, and the process of removing the first wafer does not cause serious damage to the top layer semiconductor layer in the semiconductor-on-insulator structure.

[0064] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the scope of the technical solution of the present application.

Claims

1. A method of manufacturing a semiconductor-on-insulator structure, characterized in that, The method comprises the following steps: providing a first wafer with a first ion concentration doping; forming a second ion light doping semiconductor layer on the surface of the first wafer; forming a first oxide bonding layer on the surface of the semiconductor layer by using a vapor deposition process with a process temperature lower than 600℃; providing a second wafer and forming a second oxide bonding layer on the surface of the second wafer by using a vapor deposition process with a process temperature lower than 600℃; bonding the first oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer, and further annealing the whole structure after bonding to reinforce the structure, with an annealing temperature of 300-500℃ and an annealing time of 30-150 minutes; removing the first wafer by a wet etching process to expose the semiconductor layer, with a wet etching rate of the first wafer being higher than that of the semiconductor layer; after removing the first wafer and exposing the semiconductor layer, the method further comprises: chemically and mechanically polishing the surface of the semiconductor layer by a fine chemical mechanical polishing process; measuring the thickness of the semiconductor layer, and according to the measurement result, performing ion reaction treatment on the whole surface or partial surface of the semiconductor layer by using an ion beam to further surface finish the semiconductor layer; after surface finishing the semiconductor layer by using an ion beam, performing oxidation treatment on the semiconductor layer to form a regrown oxide layer on the semiconductor layer and simultaneously reinforce the bonding interface, with a process temperature of 700-1100℃; then, removing the regrown oxide layer to remove and repair damages on the surface of the semiconductor layer.

2. The production method according to claim 1, wherein In the wet etching process, the wet etching selectivity ratio of the first wafer to the semiconductor layer ranges from 20 to 50.

3. The production method according to claim 2, wherein The etchant of the wet etching process comprises at least one of nitric acid, hydrofluoric acid and acetic acid, with a molar ratio of nitric acid, hydrofluoric acid and acetic acid in the solution being 1:10:60-1:1:1, a process temperature being 25-45℃ and an etching time being 1-10 minutes.

4. The production method according to claim 1, wherein The first ion heavily doped and the second ion lightly doped are both N-type ion doping or both P-type ion doping, the concentration of the first ion heavily doped ranges from 5E+17 cm -3 ~ 5E+19 cm -3 ; the concentration of the second ion lightly doped ranges from 5E+14 cm -3 ~ 5E+16 cm -3 .

5. The production method according to claim 1, wherein The material of the first wafer is single crystal silicon, the semiconductor layer is single crystal silicon, and the material of the second wafer is single crystal silicon.

6. The production method according to claim 1, wherein The second wafer comprises a single crystal silicon layer and a microcrystalline layer between the single crystal silicon layer and the second oxide bonding layer.

7. The production method according to claim 6, wherein The microcrystalline layer comprises at least one of a polysilicon layer, a silicon-germanium alloy layer and a germanium layer.

8. The production method according to claim 1, wherein The materials of the first oxide bonding layer and the second oxide bonding layer both comprise silicon dioxide.

9. The production method according to claim 1, wherein The annealing gas used when annealing and reinforcing the whole structure after bonding comprises at least one of nitrogen, argon and hydrogen.

10. The production method according to claim 1, wherein After bonding the first wafer to the second wafer and before removing the first wafer by the wet etching process, the surface of the first wafer opposite to the second wafer is polished and thinned.

11. The production method according to claim 1, wherein The gas used by the ion beam comprises at least one of NF3, CF4, CHF3, oxygen, nitrogen and argon, with an energy of 5-500 watts and a single wafer processing time of 1-30 minutes.

12. The production method according to any one of claims 1 to 11, wherein After the first wafer is removed and the semiconductor layer is exposed, further comprising: removing damage on the surface of the semiconductor layer by an anisotropic etching process.

13. The production method according to claim 1, wherein The thickness of the regenerated oxide layer is 100-500 angstroms; and at least one process including wet etching, dry etching or chemical mechanical polishing is used to remove the regenerated oxide layer.

14. The production method according to claim 12, wherein The step of the anisotropic etching process includes: anisotropic etching the surface of the semiconductor layer by an alkaline solution to remove the damage layer on the surface of the semiconductor layer.

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