Semiconductor structure and method of forming the same

Abstract

A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multilayer interconnect structure, and a dielectric layer. The semiconductor substrate includes a front side and a back side. The multilayer interconnect structure is located on the front side of the semiconductor substrate. The dielectric layer is located on the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a wire of the multilayer interconnect structure. The isolation layer is located between the conductive via and the first wafer. The spacer structure is located between the conductive via and the isolation layer, wherein the spacer structure is separated from the wire. Since the spacer structure is disposed on the isolation layer, leakage problems can be avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure and a method of forming a semiconductor structure. BACKGROUND

[0002] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advances in materials and design of integrated circuits have produced generations of integrated circuits, with each generation having smaller and more complex circuits than the previous generation.

[0003] As the number of electronic components on a single wafer rapidly increases, three-dimensional (3D) integrated circuit layouts or stacked wafer designs have been used for certain semiconductor components to overcome feature size and density limitations associated with two-dimensional (2D) layouts. Generally, in a three-dimensional integrated circuit design, two or more semiconductor dies are bonded together and electrical connections are formed between each die. One method of facilitating wafer-to-wafer electrical connections is to use through-silicon vias (TSVs). TSVs are vertical electrical connections through a silicon wafer that allow for simplified interconnection of vertically arranged electronic components, thereby significantly reducing the complexity of integrated circuit layouts and the overall size of multi-wafer circuits. Some benefits associated with interconnection techniques supported by three-dimensional integrated circuit designs include accelerated data exchange, reduced power consumption, and higher input / output voltage density. SUMMARY

[0004] One aspect of the present disclosure is a semiconductor structure.

[0005] According to some embodiments of the present disclosure, a semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multilayer interconnect structure, and a dielectric layer. The semiconductor substrate includes a front side and a back side. The multilayer interconnect structure is located on the front side of the semiconductor substrate. The dielectric layer is located on the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a wire of the multilayer interconnect structure. The isolation layer is located between the conductive via and the first wafer. The spacer structure is located between the conductive via and the isolation layer, wherein the spacer structure is separated from the wire.

[0006] In some embodiments, the isolation layer has a straight portion and a tapered portion located on the straight portion, the straight portion is located in the semiconductor substrate, and the tapered portion contacts the dielectric layer.

[0007] In some embodiments, the spacer structure contacts the tapered portion of the isolation layer, and the spacer structure is separated from the straight portion of the isolation layer.

[0008] In some embodiments, the spacer structure is located between the tapered portion of the isolation layer and the conductive via.

[0009] In some implementations, the isolation layer further includes a horizontal portion on the dielectric layer.

[0010] In some implementations, the isolation layer contacts the wire.

[0011] In some implementations, a top surface of the isolation layer is substantially coplanar with a top surface of the spacer structure.

[0012] In some implementations, the isolation layer and the spacer structure are made of the same material.

[0013] In some implementations, the isolation layer contacts a first sidewall of the dielectric layer and a second sidewall of the semiconductor substrate, and the first sidewall of the dielectric layer is more sloped than the second sidewall of the semiconductor substrate.

[0014] In some implementations, the conductive via includes a top portion, a bottom portion, and a neck portion. The neck portion is between the top portion and the bottom portion, wherein the neck portion has a width, and the width of the neck portion is less than a width of the bottom portion.

[0015] In some implementations, the bottom portion of the conductive via is separated from the spacer structure.

[0016] In some implementations, the top portion has a tapered profile.

[0017] In some implementations, the semiconductor structure further includes a second wafer and a bonding layer. The second wafer is on a front side of the semiconductor substrate of the first wafer. The bonding layer is between the first wafer and the second wafer.

[0018] Another technical aspect of the present disclosure is a method of forming a semiconductor structure.

[0019] According to some implementations of the present disclosure, a method of forming a semiconductor structure includes the following steps. Bonding a second wafer to a first wafer, wherein the first wafer includes a semiconductor substrate and a multilayer interconnect structure on a front side of the semiconductor substrate. Forming a dielectric layer on a back side of the semiconductor substrate. Etching the dielectric layer, the semiconductor substrate, and the multilayer interconnect structure to form an opening such that a wire of the multilayer interconnect structure is exposed. Forming an isolation layer on the wire, a sidewall of the semiconductor substrate exposed by the opening, and a sidewall of the dielectric layer exposed by the opening. Forming a spacer structure on the isolation layer. Performing an etching process to remove a portion of the isolation layer on the wire. Filling a conductive material in the opening to form a conductive via.

[0020] In some implementations, the spacer structure is formed such that a tapered portion of the isolation layer contacts the spacer structure, and a straight portion of the isolation layer is separated from the spacer structure.

[0021] In some implementations, the spacer structure is formed such that the spacer structure is on the dielectric layer.

[0022] In some embodiments, performing the etching process further includes removing a portion of the spacer structure on the dielectric layer.

[0023] In some embodiments, the isolation layer and the spacer structure are formed using different deposition processes.

[0024] In some embodiments, the isolation layer and the spacer structure are oxide layers.

[0025] In some embodiments, the opening is formed such that a sidewall of the dielectric layer exposed by the opening is more sloped than a sidewall of the semiconductor substrate exposed by the opening.

[0026] According to the above embodiments of the present disclosure, since the spacer structure is disposed on the isolation layer, the leakage problem can be avoided. In this way, the performance of the semiconductor structure can be improved.

[0027] It should be noted that the foregoing general description and the following detailed description are only examples, and are intended to provide further explanation of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] Aspects of the present disclosure can be understood from the following detailed description in conjunction with the accompanying drawings.

[0029] Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0030] Figure 2 is a partial enlarged view of the dashed area R of Figure 1

[0031] Figures 3 to 7 is a cross-sectional view of a method of forming a semiconductor structure at various stages according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. For the purpose of explanation, numerous specific details will be set forth in the following description in order to provide a thorough understanding of the embodiments. It will be apparent, however, to one skilled in the art that embodiments of the present disclosure can be practiced without specific details. In other instances, well-known structures and devices are not described in exhaustive detail in order to avoid obscuring the present disclosure. Additionally, the size and shape of various elements in the drawings can not be to scale in order to more clearly show the features of the present disclosure.

[0033] Figure 1 is a cross-sectional view of a semiconductor structure 100 according to some embodiments of the present disclosure, and Figure 2 is a partial enlarged view of the dashed area R of Figure 1 Figure 1 and Figure 2 ​​The semiconductor structure 100 includes a first wafer W1, a second wafer W2, a bonding layer 105, an isolation layer 130, a spacer structure 140, and a conductive via 150. The second wafer W2 is bonded to the first wafer W1 by the bonding layer 105.

[0034] In some implementations, the first wafer W1 includes a semiconductor substrate 110, a plurality of elements 118, a multilayer interconnect structure 120, and a dielectric layer 160. The semiconductor substrate 110 has a front side 110f and a back side 110b opposite to the front side 110f. The elements 118 are disposed on the front side 110f of the semiconductor substrate 110. In some implementations, the elements 118 can be active elements (e.g., transistors or diodes), passive elements (e.g., resistors or capacitors), or a combination thereof.

[0035] The multilayer interconnect structure 120 is disposed on the front side 110f of the semiconductor substrate 110 and connected to the elements 118. The multilayer interconnect structure 120 includes a plurality of conductive lines 122 that provide interconnections (wirings) between the elements 118, as well as between the conductive lines 122 themselves. The conductive lines 122 can be insulated from each other by inter-metal dielectric (IMD) layers 124. The multilayer interconnect structure 120 can further include various conductive vias 126 disposed in the inter-metal dielectric layers 124 for connecting the conductive lines 122.

[0036] The dielectric layer 160 is disposed on the back side 110b of the semiconductor substrate 110. In some implementations, at least one opening 170 is through a portion of the dielectric layer 160, the semiconductor substrate 110, and the multilayer interconnect structure 120, such that the opening 170 exposes a sidewall 111 of the semiconductor substrate 110 and a sidewall 161 of the dielectric layer 160. In some implementations, the opening 170 has different profiles in the dielectric layer 160 and the semiconductor substrate 110. For example, the opening 170 has a tapered profile in the dielectric layer 160 and a substantially straight profile in the semiconductor substrate 110.

[0037] The isolation layer 130 is disposed on the sidewall 161 of the dielectric layer 160 and the sidewall 111 of the semiconductor substrate 110. In some embodiments, the isolation layer 130 further extends to the top surface of the dielectric layer 160. The isolation layer 130 is conformal to the sidewall 161 and the sidewall 111. For example, the isolation layer 130 has a straight portion 132 that contacts the semiconductor substrate 110 and the multilayer interconnect structure 120, and a tapered portion 134 that contacts the dielectric layer 160. It is noted that "straight" here means that the straight portion 132 is straighter than the tapered portion 134 in the Z-axis direction. The extension direction of the straight portion 132 does not need to be parallel to the Z-axis direction. In some embodiments, the isolation layer 130 also includes a horizontal portion 136 on the top surface of the dielectric layer 160.

[0038] The spacer structure 140 is disposed on the isolation layer 130. For example, the spacer structure 140 contacts the tapered portion 134 of the isolation layer 130. In some embodiments, the spacer structure 140 is separated from the straight portion 132 of the isolation layer 130. In some other embodiments, the spacer structure 140 contacts the top of the straight portion 132 of the isolation layer 130, and the spacer structure 140 is separated from the bottom of the straight portion 132 of the isolation layer 130. That is, the spacer structure 140 is separated from the wire 122 exposed by the opening 170.

[0039] The conductive via 150 is disposed in the semiconductor substrate 110 and the dielectric layer 160, and on the wire 122 exposed by the opening 170. That is, the conductive via 150 is electrically connected to the wire 122 exposed by the opening 170. The conductive via 150 also contacts the straight portion 132 of the isolation layer 130 and the spacer structure 140, but is separated from the tapered portion 134 and the horizontal portion 136 of the isolation layer 130. As shown in FIG. 1, the conductive via 150 is separated from the wire 122 exposed by the opening 170. Figure 2As shown, the conductive via 150 includes a top portion 152, a bottom portion 156, and a neck portion 154 between the top portion 152 and the bottom portion 156. The top portion 152 and the neck portion 154 are disposed in the dielectric layer 160, and the bottom portion 156 is disposed in the semiconductor substrate 110. In some embodiments, the width w1 of the top portion 152 is tapered. The top portion 152 has a (maximum) width w1. The (minimum) width w2 of the neck portion 154 is less than the width w3 of the bottom portion 156. The width w2 of the neck portion 154 is also less than the width w1 of the top portion 152. In other words, the width w2 of the neck portion 154 is less than the width w1 of the top portion 152 and the width w3 of the bottom portion 156. In some embodiments, the width of the bottom portion 156 varies less than the width of the neck portion 154, and also less than the width of the top portion 152. For example, the width w3 of the bottom portion 156 is substantially constant. In other words, the bottom portion 156 has a strip profile, while the top portion 152 has a tapered profile. In some embodiments, the top portion 152 and the neck portion 154 of the conductive via 150 contact the spacer structure 140, while the bottom portion 156 of the conductive via 150 is separated from the spacer structure 140.

[0040] In some embodiments, the top surface 131 of the isolation layer 130, the top surface 141 of the spacer structure 140, and the top surface 151 of the conductive via 150 are substantially coplanar. In some embodiments, the spacer structure 140 is disposed between the tapered portion 134 of the isolation layer 130 and the conductive via 150. In this embodiment, the conductive via 150 can be considered as a through-substrate via or a through-silicon via (TSV).

[0041] Since the spacer structure 140 is disposed on the isolation layer 130, the isolation layer 130 can remain on the sidewall 111 of the semiconductor substrate 110 during the etching process, which will be described in detail in the following paragraphs. In this way, the leakage problem (e.g., leakage of the conductive via 150 to the semiconductor substrate 110) can be improved or avoided.

[0042] Figures 3 to 7 are cross-sectional views of a method of forming a semiconductor structure 100 according to some embodiments of the present disclosure at various stages.

[0043] Referring to Figure 3In some embodiments, the second wafer W2 is a semiconductor material and can include some structures, such as structures including graded layers or buried oxides. In some embodiments, the second wafer W2 includes bulk silicon, which can be un-doped or doped (e.g., p-type, n-type, or a combination thereof). Other materials suitable for semiconductor devices can be used. Other materials, such as fused silica, germanium, quartz, sapphire, and glass, can alternatively be used for the second wafer W2. In some embodiments, the bonding layer 105 is a dielectric layer, such as an oxide layer or other suitable material.

[0044] In some embodiments, the second wafer W2 is a semiconductor material and can include some structures, such as structures including graded layers or buried oxides. In some embodiments, the second wafer W2 includes bulk silicon, which can be un-doped or doped (e.g., p-type, n-type, or a combination thereof). Other materials suitable for semiconductor devices can be used. Other materials, such as fused silica, germanium, quartz, sapphire, and glass, can alternatively be used for the second wafer W2. In some embodiments, the bonding layer 105 is a dielectric layer, such as an oxide layer or other suitable material.

[0045] The first wafer Wl includes a semiconductor substrate 110, devices 118, and a multilayer interconnect structure 120. The semiconductor substrate 110 includes an elemental semiconductor, a compound semiconductor, an alloy semiconductor, or a combination thereof. The elemental semiconductor can be, for example, germanium or silicon. The compound semiconductor can include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor can include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0046] In some embodiments, the devices 118 are formed on a front side 110f of the semiconductor substrate 110, and the multilayer interconnect structure 120 is formed on the devices 118. The multilayer interconnect structure 120 includes conductive lines 122, intermetal dielectric layers 124, and conductive vias 126. The intermetal dielectric layers 124 can be made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials.

[0047] After the second wafer W2 is bonded to the first wafer Wl, a dielectric layer 160 can be formed on a back side 110b of the semiconductor substrate 110. The dielectric layer 160 can be made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials.

[0048] Referring toFigure 4 After the dielectric layer 160 is formed, the dielectric layer 160, the semiconductor substrate 110, and the multilayer interconnect structure 120 are etched to form an opening 170 such that one of the conductive lines 122 is exposed through the opening 170. In detail, the sidewall 111 of the semiconductor substrate 110 and the sidewall 161 of the dielectric layer 160 are exposed through the opening 170. Since the dielectric layer 160 and the semiconductor substrate 110 comprise different materials, the etch profile of the opening 170 is different in the dielectric layer 160 and the semiconductor substrate 110. For example, the opening 170 has a tapered profile in the dielectric layer 160 and a substantially straight profile in the semiconductor substrate 110. In other words, the sidewall 161 of the dielectric layer 160 is more sloped than the sidewall 111 of the semiconductor substrate 110. In some embodiments, the etching of the dielectric layer 160, the semiconductor substrate 110, and the multilayer interconnect structure 120 can be performed using a dry etching or a wet etching method. When a dry etching is used, the processing gas can comprise CF4, CHF3, NF3, SF6, Br2, HBr, Cl2, or a combination thereof. A dilution gas such as N2, O2, or Ar can be optionally used. When a wet etching is used, the etching solution (etchant) can comprise NH4OH:H2O2:H2O (APM), NH2OH, KOH, HNO3:NH4F:H2O, etc.

[0049] Referring to Figure 5 After the dielectric layer 160, the semiconductor substrate 110, and the multilayer interconnect structure 120 are etched, the isolation layer 130 is conformally formed on the sidewall 111 of the semiconductor substrate 110 and the conductive line 122. In detail, the isolation layer 130 is also formed on the sidewall 161 of the dielectric layer 160 and on the dielectric layer 160. The isolation layer 130 has a bottom portion 138, a straight portion 132 on the bottom portion 138, a tapered portion 134 on the straight portion 132, and a horizontal portion 136 on the tapered portion 134. The bottom portion 138 of the isolation layer 130 contacts the conductive line 122, the straight portion 132 of the isolation layer 130 contacts the sidewall 111 of the semiconductor substrate 110, the tapered portion 134 of the isolation layer 130 contacts the sidewall 161 of the dielectric layer 160, and the horizontal portion 136 of the isolation layer 130 contacts the top surface 163 of the dielectric layer 160. In some embodiments, the isolation layer 130 has a thickness Tl in a range from about 100 nanometers (nm) to about 800 nm. For example, the thickness Tl of the isolation layer 130 is about 400 nm. In some embodiments, the isolation layer 130 is made of an oxide, such as silicon oxide (SiO2), or other suitable materials.

[0050] Referring to Figure 6After the isolation layer 130 is formed, a spacer structure 140 is formed on the isolation layer 130. In detail, the spacer structure 140 is formed on the dielectric layer 160. In some embodiments, the tapered portion 134 of the isolation layer 130 contacts the spacer structure 140, and the straight portion 132 of the isolation layer 130 is separated from the spacer structure 140.

[0051] In some embodiments, the isolation layer 130 and the spacer structure 140 are formed using different deposition processes. For example, the isolation layer 130 can be formed using an atomic layer deposition (ALD) process, or other suitable process. The spacer structure 140 can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, or other suitable process. The atomic layer deposition process can provide better step coverage than the plasma-enhanced chemical vapor deposition. Step coverage, which can also be referred to as shadowing, refers to the level of thickness uniformity of a thin film deposited on a non-planar or three-dimensional surface (e.g., containing steps or other irregularities). For example, the spacer structure 140 is not formed on the straight portion 132 of the isolation layer 130, which indicates relatively poor step coverage (e.g., due to the plasma-enhanced chemical vapor deposition process used to deposit the spacer structure 140). The spacer structure 140 can have a curved surface 143. In contrast, the isolation layer 130 can be considered a thin film, and is formed on the sidewall 111 of the semiconductor substrate 110 and the sidewall 161 of the dielectric layer 160, which indicates better step coverage (e.g., due to the atomic layer deposition process used to deposit the isolation layer 130). In some embodiments, the thickness T2 of the spacer structure 140 is greater than the thickness Tl of the isolation layer 130. In some embodiments, the thickness T2 of the spacer structure 140 is in a range from about 500 nanometers to about 3000 nanometers. For example, the thickness T2 of the spacer structure 140 is about 1500 nanometers.

[0052] In some embodiments, the isolation layer 130 and the spacer structure 140 are made of the same material. For example, the isolation layer 130 and the spacer structure 140 are made of an oxide, such as silicon dioxide (Si02), or other suitable material. In some other embodiments, the isolation layer 130 and the spacer structure 140 are made of different materials.

[0053] Referring to Figure 7 After the spacer structure 140 is formed, an etching process is performed to remove the bottom portion 138 of the isolation layer 130 on the wire 122 (see FIG. 1C). In other words, the bottom portion 138 of the isolation layer 130 is removed (see FIG. 1C). Figure 6 ). In other words, the bottom portion 138 of the isolation layer 130 is removed (see FIG. 1C). Figure 6The etching process also includes removing portions of the spacer structure 140 on the dielectric layer 160. For example, most of the isolation layer 130 and the spacer structure 140 are removed from the exposed horizontal surface, leaving the isolation layer 130 and the spacer structure 140 on a vertical surface, such as the sidewall 111 of the semiconductor substrate 110. Furthermore, a portion of the spacer structure 140 located on the tapered portion 134 of the isolation layer 130 is not removed, and the tapered portion 134 of the isolation layer 130 is protected from etching. In some embodiments, the etching process is a punch etch process using a dry etching process, such as reactive ion etching (RIE), sputtering etching, or other suitable processes. After the etching process, the thickness T2' of the spacer structure 140 is equal to or less than the thickness T2 of the spacer structure 140 (see...). Figure 6 In some embodiments, the thickness T2' of the spacer structure 140 is less than about 500 nanometers. In some other embodiments, the thickness T2' of the spacer structure 140 is less than about 3000 nanometers.

[0054] Because the sidewalls 161 of the dielectric layer 160 are more inclined than the sidewalls 111 of the semiconductor substrate 110, the tapered portion 134 of the isolation layer 130 is easier to etch than the straight portion 132 of the isolation layer 130 without the spacer structure 140. If the tapered portion 134 is etched, the back surface 110b of the semiconductor substrate 110 may be exposed, and the conductive via 150 (see...) Figure 1 Leakage may occur between the semiconductor substrate 110 and the semiconductor substrate 110. However, in Figure 6 Since the spacer structure 140 is formed on the isolation layer 130, especially on the tapered portion 134 of the isolation layer 130, the spacer structure 140 protects the isolation layer 130 so that the tapered portion 134 of the isolation layer 130 is not etched during the etching process. Therefore, the leakage problem between the conductive via 150 and the semiconductor substrate 110 can be improved or avoided.

[0055] Back Figure 1 After the etching process is completed, conductive material is filled into the opening 170, and planarization, such as chemical mechanical polishing (CMP), is performed to remove excess conductive material outside the opening 170, so that conductive vias 150 are formed in the remaining opening 170. Specifically, conductive vias 150 are formed on the wire 122 and in a portion of the multilayer interconnect structure 120, the semiconductor substrate 110, and the dielectric layer 160. In this way, a result can be obtained as... Figure 1 The semiconductor structure 100 shown.

[0056] While this disclosure has been disclosed with reference to the embodiments described above, other embodiments are possible, and therefore the spirit or scope of the disclosure should not be limited to the description of the embodiments. Therefore, the appended claims should not be limited to the description of the embodiments.

[0057] Those skilled in the art will appreciate that various modifications and substitutions can be made to the present disclosure without departing from the spirit and scope thereof, and all such modifications and substitutions are intended to be encompassed within the scope of the appended claims.

[0058]

Symbol Description

[0059] 100: semiconductor structure

[0060] 105: bonding layer

[0061] 110: semiconductor substrate

[0062] 110f: front surface

[0063] 110b: back surface

[0064] 111: sidewall

[0065] 118: element

[0066] 120: multilayer interconnect structure

[0067] 122: wire

[0068] 124: intermetallic dielectric layer

[0069] 126: conductive via

[0070] 130: isolation layer

[0071] 131: top surface

[0072] 132: straight portion

[0073] 134: tapered portion

[0074] 136: horizontal portion

[0075] 138: bottom portion

[0076] 140: spacer structure

[0077] 141: top surface

[0078] 143: curved surface

[0079] 150: conductive via

[0080] 151: top surface

[0081] 152: top portion

[0082] 154: neck portion

[0083] 156: bottom portion

[0084] 160: dielectric layer

[0085] 161: sidewall

[0086] 163: top surface

[0087] 170: opening

[0088] R: region

[0089] T1: thickness

[0090] T2: thickness

[0091] T2’: thickness

[0092] W1: first wafer

[0093] W2: second wafer

[0094] w1: width

[0095] w2: width

[0096] w3: width

[0097] Z: axis

Claims

1. A semiconductor structure, characterized by, Comprising: a first wafer comprising: a semiconductor substrate having a front side and a back side; a multilayer interconnect structure on the front side of the semiconductor substrate; and a dielectric layer on the back side of the semiconductor substrate; a conductive via extending from the dielectric layer to a wire of the multilayer interconnect structure; an isolation layer between the conductive via and the first wafer, wherein the isolation layer has a straight portion extending onto the wire, a tapered portion on the straight portion, and a horizontal portion on the tapered portion; and a spacer structure between the conductive via and the isolation layer, wherein the spacer structure is separate from the wire, and wherein the conductive via contacts the straight portion of the isolation layer and the spacer structure.

2. The semiconductor structure of claim 1, wherein the tapered portion of the isolation layer contacts the dielectric layer.

3. The semiconductor structure of claim 1, wherein the spacer structure contacts the tapered portion of the isolation layer and is separate from the straight portion of the isolation layer.

4. The semiconductor structure of claim 1, wherein the spacer structure is between the tapered portion of the isolation layer and the conductive via.

5. The semiconductor structure of claim 1, wherein the horizontal portion of the isolation layer is on the dielectric layer.

6. The semiconductor structure of claim 1, wherein the isolation layer contacts the wire.

7. The semiconductor structure of claim 1, wherein a top surface of the isolation layer and a top surface of the spacer structure are substantially coplanar.

8. The semiconductor structure of claim 1, wherein the isolation layer and the spacer structure are made of the same material.

9. The semiconductor structure of claim 1, wherein the isolation layer contacts a first sidewall of the dielectric layer and a second sidewall of the semiconductor substrate, and the first sidewall of the dielectric layer is more sloped than the second sidewall of the semiconductor substrate.

10. The semiconductor structure of claim 1, wherein the conductive via comprises: a top portion; a bottom portion; and a neck portion between the top portion and the bottom portion, wherein the neck portion has a width, and the width of the neck portion is less than a width of the bottom portion.

11. The semiconductor structure of claim 10, wherein the bottom portion of the conductive via is separate from the spacer structure.

12. The semiconductor structure of claim 10, wherein the top portion has a tapered profile.

13. The semiconductor structure of claim 1, wherein, Further comprising: a second wafer on the front side of the semiconductor substrate of the first wafer; and a bonding layer between the first wafer and the second wafer.

14. A method of forming a semiconductor structure, comprising: Comprising: bonding a second wafer to a first wafer, wherein the first wafer comprises a semiconductor substrate and a multilayer interconnect structure on a front side of the semiconductor substrate; forming a dielectric layer on a back side of the semiconductor substrate; etching the dielectric layer, the semiconductor substrate, and the multilayer interconnect structure to form an opening such that a wire of the multilayer interconnect structure is exposed; forming an isolation layer on the wire, a sidewall of the semiconductor substrate exposed by the opening, and a sidewall of the dielectric layer exposed by the opening; forming a spacer structure on the isolation layer; performing an etching process to remove a portion of the isolation layer on the wire such that the isolation layer has a straight portion extending onto the wire, a tapered portion on the straight portion, and a horizontal portion on the tapered portion; and filling a conductive material in the opening to form a conductive via, wherein the conductive via contacts the straight portion of the isolation layer and the spacer structure.

15. The method of claim 14, wherein the spacer structure is formed such that the tapered portion of the isolation layer contacts the spacer structure and the straight portion of the isolation layer is separated from the spacer structure.

16. The method of claim 14, wherein the spacer structure is formed such that the spacer structure is on the dielectric layer.

17. The method of claim 16, wherein performing the etching process further comprises removing a portion of the spacer structure on the dielectric layer.

18. The method of claim 14, wherein the isolation layer and the spacer structure are formed using different deposition processes.

19. The method of claim 14, wherein the isolation layer and the spacer structure are oxide layers.

20. The method of claim 14, wherein the opening is formed such that the sidewall of the dielectric layer exposed by the opening is more sloped than the sidewall of the semiconductor substrate exposed by the opening.

Images