Storage devices

Abstract

A memory device includes: a substrate; an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction, and including an open first side, a closed second side, and a channel layer between the first side and the second side; and a word line surrounding the channel layer and laterally oriented in a second direction intersecting the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0080872, filed on Jul. 1, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device with a higher integration density. Background Art

[0004] Because the integration density of two-dimensional (2D) memory devices is primarily determined by the area occupied by each unit cell, it is limited by the technology used to form fine patterns. Forming fine patterns requires extremely expensive equipment, but this still presents limitations in increasing the integration density of 2D memory devices. To address this issue, 3D memory devices with memory cells arranged in a three-dimensional pattern have been proposed. Summary of the Invention

[0005] Embodiments of the present invention are directed to three-dimensional memory devices with higher integration density.

[0006] According to one embodiment of the present invention, a memory device includes: a substrate; an active layer, which is spaced apart from a surface of the substrate and laterally oriented in a first direction, and includes an open first side, a closed second side, and a channel layer between the first side and the second side; and a word line, which surrounds the channel layer and is laterally oriented in a second direction intersecting the first direction.

[0007] According to another embodiment of the present invention, a memory device includes: a plurality of cylindrical active layers spaced apart from each other in a horizontal direction above a substrate, the cylindrical active layers each including a channel layer; a word line surrounding the channel layer of the cylindrical active layer and extending horizontally, wherein the word line includes: an upper portion located at a higher level than the channel layer; a lower portion located at a lower level than the channel layer; and an intermediate connector located between the upper portion and the lower portion and at the same level as the channel layer.

[0008] According to another embodiment of the present invention, a memory device includes: a substrate including a peripheral circuit portion; an active layer including a nanowire channel, which is spaced apart from the substrate and oriented laterally; a word line, which surrounds the nanowire channel and is oriented laterally in a direction crossing the nanowire channel; a bit line, which is coupled to an end portion of one side of the active layer and is oriented vertically starting from the peripheral circuit portion; and a lateral capacitor, which is coupled to the other end of the active layer and spaced apart from the substrate.

[0009] These and other features and advantages of the present invention will be better understood by those skilled in the art from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a perspective view showing the structure of a memory cell according to an embodiment of the present invention.

[0011] Figure 2 It is along Figure 1 A cross-sectional view taken along line A1-A1' is shown.

[0012] Figures 3A to 3C is a perspective view showing the structure of the active layer ACT.

[0013] Figure 4 It is along Figure 1 A cross-sectional view taken along line A2-A2' is shown.

[0014] Figure 5 A modified example of the word line is shown.

[0015] Figure 6A and Figure 6B is a perspective view showing other modified examples of the word line.

[0016] 7A to 7D is a perspective view showing other modified examples of the word line.

[0017] Figures 8A to 8C An active layer according to another embodiment of the present invention is shown.

[0018] Figure 9A is a perspective view showing a memory cell array.

[0019] Figure 9B It is along Figure 9A A cross-sectional view taken along line A21-A21' is shown.

[0020] Figure 10 3D is a perspective view showing a mirror-type memory cell array sharing a plate line.

[0021] Figure 11 It is a perspective view showing a mirror-type memory cell array that shares bit lines.

[0022] Figure 12 and Figure 13 is a layout diagram showing an example of word lines of a memory cell array.

[0023] Figure 14 FIG. 1 is a diagram showing a layout of a memory cell array according to another embodiment of the present invention. DETAILED DESCRIPTION

[0024] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure more thorough and comprehensive and to enable those skilled in the art to fully understand the scope of the invention. Throughout this disclosure, in the various figures and embodiments of the present invention, like reference numerals refer to like parts.

[0025] The drawings are not necessarily drawn to scale, and in some cases, the proportions may have been exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on a substrate," it refers not only to a case where the first layer is directly formed on the second layer or substrate, but also to a case where a third layer exists between the first layer and the second layer or substrate.

[0026] A memory device according to an embodiment of the present invention may include a lateral active layer, a surrounding gate word line, a vertical bit line, and a lateral capacitor.

[0027] According to an embodiment of the present invention, the word line of the transistor can have a gate-all-around (GAA) structure, which is conducive to improving the controllability of the transistor and increasing the cell current. Moreover, the gate-all-around structure can reduce the word line resistance of each memory cell and completely shield adjacent memory cells from interference during operation.

[0028] Figure 1 is a perspective view showing the structure of a memory cell according to an embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view taken along line A1-A1' is shown.

[0029] refer to Figure 1 and Figure 2 The memory device may include a memory cell MC. The memory cell MC may be located on a substrate LS. The memory cell MC may be vertically oriented along a first direction D1 starting from the substrate LS. The memory cell MC may include a dynamic random access memory (DRAM) memory cell. The memory cell MC may have a three-dimensional structure.

[0030] A memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The bit line BL may be vertically oriented along a first direction D1. The transistor TR and the capacitor CAP may be laterally arranged in a second direction D2 away from the bit line BL. The second direction D2 may intersect the first direction D1, and a third direction D3 may intersect the first direction D1 and the second direction D2. The second direction D2 may be perpendicular to the vertically oriented first direction D1, and the third direction D3 may be perpendicular to a plane formed by the first direction D1 and the second direction D2. The memory cell MC may include a memory cell of a three-dimensional (3D) DRAM having a 1T-1C (1 transistor-1 capacitor) structure.

[0031] The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be laterally oriented in a second direction D2 between the bit line BL and the capacitor CAP. The active layer ACT may include a channel layer CH, a first source / drain region SD1, and a second source / drain region SD2. The first source / drain region SD1 of the active layer ACT may be coupled to the bit line BL, and the second source / drain region SD2 of the active layer ACT may be coupled to the capacitor CAP. The transistor TR may include a gate-all-around transistor, for example, a gate-all-around field-effect transistor (GAA FET).

[0032] The word line WL may be elongated along the third direction D3. The plate line PL may extend along the third direction D3 while being vertically oriented in the first direction D1. The plate line PL may be coupled to the capacitor CAP.

[0033] The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN of the capacitor CAP may be coupled to the second source / drain region SD2 of the active layer ACT, and the plate node PN of the capacitor CAP may be coupled to the plate line PL. The plate node PN may be integrated with the plate line PL.

[0034] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include metal-based materials. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide SiO2 may have a dielectric constant of approximately 3.9, and the dielectric layer DE may include a high-k material having a dielectric constant of approximately 4 or greater. The high-k material may have a dielectric constant of approximately 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be a composite layer including two or more layers of the above-mentioned high-k materials.

[0035] The dielectric layer DE may be formed of a zirconium-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) stacked layer or a ZAZ (ZrO2 / Al2O3 / ZrO2) stacked layer. The ZA stacked layer may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stacked layer may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked sequentially. The ZA stacked layer and the ZAZ stacked layer may be referred to as zirconium oxide-based layers (ZrO2-based layers). According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium-based oxide. The dielectric layer DE may have a stacked structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked sequentially. The HA stack and the HAH stack may be referred to as hafnium oxide-based layers (HfO2-based layers). In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, the band gap of aluminum oxide (Al2O3) may be larger than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) may be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material, the high-bandgap material having a bandgap greater than that of the high-k material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may include silicon oxide (SiO2) as a high-bandgap material. The dielectric layer DE may include a high-bandgap material to suppress leakage current. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a laminated structure in which high-k materials and high-bandgap materials are alternately stacked. For example, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the laminated structure as described above, the aluminum oxide (Al2O3) can be very thin.

[0036] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure including zirconium oxide, hafnium oxide, and aluminum oxide, a laminated structure, or a combination thereof.

[0037] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0038] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacking, or tungsten nitride / tungsten (WN / W) stacking. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a stacking of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-fill material filling the cylindrical interior of the storage node SN, and titanium nitride (TiN) may substantially serve as a plate node of the capacitor CAP, while tungsten nitride may be a low-resistance material.

[0039] The storage node SN may have a three-dimensional structure that is a lateral three-dimensional structure parallel to the second direction D2. As an example of the three-dimensional structure, the storage node SN may have a cylindrical shape, a columnar shape, or a pylinder shape in which the cylindrical shape and the columnar shape are combined.

[0040] The substrate LS may be a material suitable for semiconductor processing. The substrate LS may include at least one or more of a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed on the substrate LS. The substrate LS may include a semiconductor substrate. The substrate LS may be formed from a material including silicon. The substrate LS may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate LS may include other semiconductor materials, such as germanium. The substrate LS may include a Group III / V semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). The substrate LS may include a silicon-on-insulator (SOI) substrate.

[0041] According to another embodiment of the present invention, the substrate LS may include a peripheral circuit portion (not shown). The peripheral circuit portion may include multiple control circuits for controlling the memory cells MC. At least one control circuit in the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuit portion PC may include an address decoder circuit, a read circuit, and a write circuit. At least one control circuit in the peripheral circuit cell PC may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin-channel transistor (FinFET), or the like.

[0042] For example, the peripheral circuit portion may include a sense amplifier SA, and the sense amplifier SA may be coupled to the bit line BL of the memory cell MC. The peripheral circuit portion may also include a word line driver, and the word line driver may be coupled to the word line WL of the memory cell MC.

[0043] Although not shown, the plate line PL may be coupled to other peripheral circuit parts or the substrate LS.

[0044] The bottom of the bit line BL can be coupled to the substrate LS. The bit line BL can have a columnar shape. The bit line BL can be referred to as a vertically oriented bit line or a pillar-type bit line. The bit line BL may include a low-resistance conductive material. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include titanium nitride (TiN) or polysilicon doped with N-type impurities. The bit line BL may include a stack of titanium nitride and tungsten (TiN / W). The bit line BL may also include an ohmic contact layer such as a metal silicide. The bit line BL may include pillar-type tungsten and titanium nitride surrounding the outer wall of the pillar-type tungsten.

[0045] The active layer ACT may include a semiconductor material. The active layer ACT may include a silicon layer, for example, doped polysilicon, undoped polysilicon, or amorphous silicon. The active layer ACT may include polysilicon nanowires. According to another embodiment of the present invention, the active layer ACT may include an oxide semiconductor material. The active layer ACT may include a compound of a transition metal and a chalcogen. The active layer ACT may include InGaZnO x (IGZO), InSnZnO x 、ZnSnO x , MoS 2 , WS 2 or MoSe 2 . The first source / drain region SD1 and the second source / drain region SD2 may be located at both ends of the active layer ACT, respectively.

[0046] The word line WL may surround a portion of the active layer ACT. The word line WL may include a gate-all-around (GAA) structure. The portion surrounded by the word line WL may be the channel layer CH of the active layer ACT. The word line WL may include a low-resistance conductive material. The word line WL may include a low-resistance metal material. The word line WL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The word line WL may include a silicon-based material, a metal-based material, or a combination thereof. The word line WL may include tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbonitride (TaCN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), cobalt (Co), or a combination thereof. The word line WL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the word line WL may include a stack of titanium nitride and tungsten (TiN / W).

[0047] The gate dielectric layer GD may be located between the word line WL and the active layer ACT. The gate dielectric layer GD may cover the outer surface of the active layer ACT. The gate dielectric layer GD may surround the active layer ACT. The gate dielectric layer GD may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof.

[0048] Return Reference Figure 2 , the gap-filling material GM may be located in the active layer ACT. The gap-filling material GM may be embedded in the active layer ACT. The gap-filling material GM may include a dielectric material. The gap-filling material GM may include silicon oxide or silicon nitride. One side of the gap-filling material GM may be coupled to the bit line BL. The gap-filling material GM may extend along the second direction D2. The gap-filling material GM may not be coupled to the storage node SN of the capacitor CAP. The gap-filling material GM may pass through the first source / drain region SD1, the channel region and enter the second source / drain region SD2, but may not penetrate the second source / drain region SD2. The first source / drain region SD1 may surround an end portion of one side of the gap-filling material GM. The channel layer CH may surround a middle portion of the gap-filling material GM. The second source / drain region SD2 may surround an end portion of the other side of the gap-filling material GM. The gap-filling material GM may be located centrally inside the first source / drain region SD1 and the channel region CH.

[0049] Figures 3A to 3C is a perspective view showing the structure of the active layer ACT. Figure 3A is a detailed diagram of the active layer ACT, and Figure 3B is a detailed view of the active layer ACT including embedded gap-filling material. Figure 3C It is along Figure 3B A cross-sectional view taken along line A11-A11'.

[0050] refer to Figures 3A to 3CThe active layer ACT may have a three-dimensional cylindrical shape. The active layer ACT may extend along a second direction D2. The active layer ACT may include a first side S1 and a second side S2 opposite to the first side S1. The first side S1 and the second side S2 may face each other in the second direction D2. The active layer ACT may include a channel layer CH between the first side S1 and the second side S2.

[0051] According to an embodiment of the present invention, the channel layer CH may include four outer surfaces S11, S12, S13, and S14. The first outer surface S11 and the second outer surface S12 may face each other in the first direction D1 and may be parallel in the second direction D2. The third outer surface S13 and the fourth outer surface S14 may face each other in the third direction D3 and may be parallel in the second direction D2. The first outer surface S11 to the fourth outer surface S14 may extend in the second direction D2.

[0052] The first side S1 may be an open side, while the second side S2 may be a closed side. The first side S1 may have a rectangular ring-shaped cross section in the first direction D1, and the second side S2 may have a rectangular cross section in the first direction D1. According to another embodiment of the present invention, the first side S1 may have a circular ring-shaped cross section in the first direction D1, an elliptical ring-shaped cross section, or a polygonal ring-shaped cross section in the first direction D1. The second side S2 may have a circular, elliptical, or polygonal cross section in the first direction D1.

[0053] The active layer ACT may further include an internally empty space, i.e., an internal gap IG. The internal gap IG may extend in the second direction D2. The internal gap IG may be defined within the active layer ACT by the first side S1, the second side S2, and the channel layer CH. The internal gap IG may be open by the first side S1 and may be closed by the second side S2. The active layer ACT including the internal gap IG, the first side S1, and the second side S2 may have a cylindrical shape or a macaroni shape. The active layer ACT may have a macaroni-shaped nanowire structure. The active layer ACT may include macaroni-shaped polycrystalline silicon nanowires, oxide semiconductor nanowires, or transition metal and chalcogen compound nanowires. The channel layer CH may include a nanowire channel, and for example, the channel layer CH may include macaroni-shaped polycrystalline silicon nanowires, oxide semiconductor nanowires, or transition metal and chalcogen compound nanowires. According to an embodiment of the present invention, the channel layer CH may include macaroni-shaped polycrystalline silicon nanowires.

[0054] The first source / drain region SD1 and the second source / drain region SD2 may be located on either side of the channel layer CH, respectively. The first source / drain region SD1 and the second source / drain region SD2 may be formed by an impurity doping process. For example, the first source / drain region SD1 may be formed by doping and diffusing impurities on the first side S1 of the active layer ACT. The second source / drain region SD2 may be formed by doping and diffusing impurities on the second side S2 of the active layer ACT. The dimensions ("widths") of the first source / drain region SD1 and the second source / drain region SD2 in the second direction D2 may be smaller than the width of the channel layer CH in the second direction D2. The first source / drain region SD1 may be coupled to the bit line BL, and the second source / drain region SD2 may be coupled to the storage node SN of the capacitor CAP. When the bit line BL includes a tungsten pillar and titanium nitride surrounding the outer wall of the tungsten pillar, the first source / drain region SD1 may directly contact the titanium nitride. A portion of the bit line BL may close the opened first side S1 of the active layer ACT.

[0055] refer to Figure 3B , the internal gap IG can be filled with a gap-filling material GM. The gap-filling material GM can have a transverse columnar shape extending laterally in the second direction D2. The active layer ACT filled with the gap-filling material GM can be referred to as an active layer ACT containing an embedded gap-filling material GM. The gap-filling material GM can directly contact the inner surface of the channel layer CH. The gap-filling material GM can directly contact the inner surface of the first source / drain region SD1. The gap-filling material GM can directly contact the inner surface of the second source / drain region SD2. The first source / drain region SD1 can surround the outer surface of the gap-filling material GM. A portion of the second source / drain region SD2 can surround the outer surface of the gap-filling material GM, and an edge portion of the second source / drain region SD2 can cover an edge portion of the gap-filling material GM.

[0056] The active layer ACT may include a semiconductor material such as polysilicon. The active layer ACT may include doped polysilicon, undoped polysilicon, or amorphous silicon. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type impurities or P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with impurities of the same conductivity type. The first source / drain region SD1 and the second source / drain region SD2 may include at least one of arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The channel layer CH may serve as a channel of the transistor TR. According to another embodiment of the present invention, the active layer ACT may include InGaZnO x 、InSnZnO x 、ZnSnO x , MoS2, WS2 or MoSe2.

[0057] refer to Figure 3B and Figure 3C The first source / drain region SD1 may provide a first side S1 and surround an end S41 on one side of the gap-filling material GM. The second source / drain region SD2 may include a vertical sidewall SD21 providing a second side S2 and a protrusion SD22 extending from the vertical sidewall SD21. The protrusion SD22 may surround an end S42 on the other side of the gap-filling material GM. The channel layer CH may surround the gap-filling material GM. According to some embodiments of the present invention, the gap-filling material GM may include an embedded air gap S43.

[0058] Figure 4 It is along Figure 1 A cross-sectional view taken along line A2-A2' is shown.

[0059] refer to Figure 4 , the word line WL may extend along the third direction D3. The word line WL may include a surrounding portion SWL and an extension portion EWL, and the extension portion EWL extends in the third direction D3 from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL may surround the channel layer CH of the active layer ACT. The gate dielectric layer GD may be located between the surrounding portion SWL of the word line WL and the channel layer CH of the active layer ACT. The gate dielectric layer GD may surround the channel layer CH of the active layer ACT. The gap filling material GM may be embedded inside the active layer ACT. The surrounding portion SWL of the word line WL may surround the channel layer CH of the active layer ACT, while the gate dielectric layer GD is interposed therebetween. The extension portion EWL of the word line WL may not surround the channel layer CH of the active layer ACT.

[0060] The surrounding portion SWL and the extension portion EWL of the word line WL may have the same height ( H1 = H2 ) in the first direction D1 , and may have a height greater than a height H3 of the channel layer CH.

[0061] The surrounding portion SWL and the extension portion EWL of the word line WL may have the same length in the third direction D3 .

[0062] refer to Figure 1 and Figure 4 , the surrounding portion SWL and the extension portion EWL of the word line WL may have the same width in the second direction D2.

[0063] The surrounding portion SWL and the extension portion EWL of the word line WL may be formed of the same material.

[0064] Figure 5 Shown with Figure 4The word line WL is compared with the modified example WL'. Figure 5 Also appears in Figure 4 The same reference numerals in the drawings may represent the same components. Figure 4 in Figure 5 The components are not described in detail.

[0065] refer to Figure 5 The word line WL' may extend along the third direction D3 and may include a surrounding portion SWL and an extension portion EWL', the extension portion EWL' extending in the third direction D3 from both sides of the surrounding portion SWL.

[0066] The surrounding portion SWL of the word line WL' may surround the channel layer CH of the active layer ACT. The gate dielectric layer GD may be located between the surrounding portion SWL of the word line WL' and the channel layer CH of the active layer ACT. The gate dielectric layer GD may surround the channel layer CH of the active layer ACT. A gap fill material GM may be embedded in the active layer ACT. The surrounding portion SWL of the word line WL' may surround the channel layer CH of the active layer ACT, with the gate dielectric layer GD interposed therebetween. The extended portion EWL' of the word line WL' may not surround the channel layer CH of the active layer ACT.

[0067] The surrounding portion SWL and the extended portion EWL' of the word line WL' may have different heights in the first direction D1 (H1>H2). The height H1 of the surrounding portion SWL may be greater than the height H2 of the extended portion EWL'. The height H2 of the extended portion EWL of the word line WL may be the same as the height H3 of the channel layer CH. According to another embodiment of the present invention, the height H2 of the extended portion EWL of the word line WL may be greater than or less than the height H3 of the channel layer CH.

[0068] An upper surface of the surrounding portion SWL may be located at a higher level than an upper surface of the extension portion EWL′. A lower surface of the surrounding portion SWL may be located at a lower level than a lower surface of the extension portion EWL′.

[0069] The surrounding portion SWL of the word line WL may have the same length as each of the extension portions EWL′ of the word line WL in the third direction D3 .

[0070] Figure 6A and Figure 6B is a perspective view showing another modification example of the word line. Hereinafter, the word lines WL11 and WL12 may be similar to Figure 4 and Figure 5 The word lines WL and WL' shown in FIG. Figure 6A and Figure 6B Also appears in Figure 4 and Figure 5 The reference numerals in the same figure may represent the same component. Figure 4 and Figure 5 in Figure 6A and Figure 6B The components are not described in detail.

[0071] refer to Figure 6A The word line WL11 may extend along the third direction D3. The word line WL11 may include a surrounding portion SWL and an extension portion EWL, each extending in the third direction D3 from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL11 may surround the channel layer CH of the active layer ACT. The extension portion EWL of the word line WL11 may not surround the channel layer CH of the active layer ACT.

[0072] The surrounding portion SWL and the extension portion EWL of the word line WL11 may have different widths in the second direction D2 (W1>W2). The width W1 of the surrounding portion SWL may be greater than the width W2 of the extension portion EWL.

[0073] The surrounding portion SWL and the extension portion EWL of the word line WL11 may have the same length in the third direction D3 .

[0074] refer to Figure 6B The word line WL12 may extend along the third direction D3. The word line WL12 may include a surrounding portion SWL and an extension portion EWL, each extending in the third direction from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL12 may surround the channel layer CH of the active layer ACT. The extension portion EWL of the word line WL12 may not surround the channel layer CH of the active layer ACT.

[0075] The surrounding portion SWL and the extended portion EWL of the word line WL12 may have different widths in the second direction D2. The width of the surrounding portion SWL may be greater than the width of the extended portion. In addition, the surrounding portion SWL and the extended portion EWL of the word line WL12 may have different heights in the first direction D1. The height of the surrounding portion SWL may be greater than the height of the extended portion EWL. The extended portion EWL of the word line WL12 may have the same height as the channel layer CH. The upper surface of the surrounding portion SWL may be located at a higher level than the upper surface of the extended portion EWL. The lower surface of the surrounding portion SWL may be located at a lower level than the lower surface of the extended portion EWL.

[0076] The surrounding portion SWL and the extension portion EWL of the word line WL12 may have the same length in the third direction D3 .

[0077] 7A to 7Dis a perspective view showing other modified examples of word lines. Hereinafter, word lines WL21, WL22, WL23 and WL24 may be similar to Figure 4 、 Figure 5 、 Figure 6A and Figure 6B The word lines WL, WL', WL11 and WL12 are shown. 7A to 7D Also appears in Figures 4 to 6B The same reference numerals in the drawings may denote the same constituent elements. Figures 4 to 6B in 7A to 7D The components are not described in detail.

[0078] refer to Figure 7A The word line WL21 may extend along the third direction D3. The word line WL21 may include a surrounding portion SWL and an extension portion EWL, each extending in the third direction D3 from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL21 may surround the channel layer CH of the active layer ACT. The extension portion EWL of the word line WL21 may not surround the channel layer CH of the active layer ACT.

[0079] The extension portion EWL of the word line WL21 may include a first portion E1, a second portion E2, and a third portion E3. The second portion E2 and the third portion E3 are respectively located on both sides of the first portion E1. The second portion E2 may be coupled to the surrounding portion SWL. The third portion E3, the first portion E1, and the second portion E2 may be arranged laterally in a third direction D3. The first portion E1, the second portion E2, and the third portion E3 may be integrated into a dog-bone shape. In the second direction D2, the width of the first portion E1 of the extension portion EWL may be smaller than the width of the second portion E2 and the width of the third portion E3. The length of the first portion E1 may be longer than each of the length of the second portion E2 and the length of the third portion E3. The lengths of the second portion E2 and the third portion E3 may be the same.

[0080] The surrounding portion SWL of the word line WL21 and the second and third portions E2 and E3 of the extension portion EWL may have the same width in the second direction D2 .

[0081] The surrounding portion SWL and the extension portion EWL of the word line WL21 may have the same length in the third direction D3 .

[0082] refer to Figure 7BThe word line WL22 may extend along the third direction D3. The word line WL22 may include a surrounding portion SWL and an extension portion EWL, each extending from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL22 may surround the channel layer CH of the active layer ACT. The extension portion EWL of the word line WL22 may not surround the channel layer CH of the active layer ACT.

[0083] The extended portion EWL of the word line WL22 may include a first portion E1, a second portion E2, and a third portion E3. The second portion E2 and the third portion E3 are respectively located on either side of the first portion E1. The second portion E2 may be coupled to the surrounding portion SWL. The third portion E3, the first portion E1, and the second portion E2 may be arranged laterally in a third direction D3. The first portion E1, the second portion E2, and the third portion E3 may be integrated into a dog-bone shape. In the second direction D2, the width of the first portion E1 of the extended portion EWL may be smaller than the widths of the second portion E2 and the third portion E3.

[0084] The second and third portions E2 and E3 of the extension portion EWL may have the same width in the second direction D2 , and may have widths smaller than that of the surrounding portion SWL of the word line WL22 in the second direction D2 .

[0085] The surrounding portion SWL and the extension portion EWL of the word line WL22 may have the same length in the third direction D3. The length of the first portion E1 may be longer than each of the lengths of the second portion E2 and the third portion E3. The lengths of the second portion E2 and the third portion E3 may be the same.

[0086] refer to Figure 7C The word line WL23 may extend along the third direction D3. The word line WL23 may include a surrounding portion SWL and an extension portion EWL, each extending in the third direction D3 from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL23 may surround the channel layer CH of the active layer ACT. The extension portion EWL of the word line WL23 may not surround the channel layer CH of the active layer ACT.

[0087] The extended portion EWL of the word line WL23 may include a first portion E1, a second portion E2, and a third portion E3. The second portion E2 and the third portion E3 are respectively located on either side of the first portion E1. The second portion E2 may be coupled to the surrounding portion SWL. The third portion E3, the first portion E1, and the second portion E2 may be arranged laterally in a third direction D3. The first portion E1, the second portion E2, and the third portion E3 may be integrated into a dog-bone shape. In the second direction D2, the width of the first portion E1 of the extended portion EWL may be smaller than the widths of the second portion E2 and the third portion E3.

[0088] The second and third portions E2 and E3 of the extension portion EWL may have the same width in the second direction D2. The second and third portions E2 and E3 of the extension portion EWL may have the same width as the surrounding portion SWL of the word line WL23 in the second direction D2.

[0089] The surrounding portion SWL and the extension portion EWL of the word line WL23 may have the same length in the third direction D3. In the first direction D1, the height of the extension portion EWL of the word line WL23 may be lower than that of the surrounding portion SWL. In the first direction D1, the heights of the first portion E1, the second portion E2, and the third portion E3 of the extension portion EWL may be lower than that of the surrounding portion SWL.

[0090] refer to Figure 7D The word line WL24 may extend along the third direction D3. The word line WL24 may include a surrounding portion SWL and an extension portion EWL, each extending in the third direction D3 from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL24 may surround the channel layer CH of the active layer ACT. The extension portion EWL of the word line WL24 may not surround the channel layer CH of the active layer ACT.

[0091] The extended portion EWL of the word line WL24 may include a first portion E1 and a second portion E2 and a third portion E3 located on either side of the first portion E1. The second portion E2 may be coupled to the surrounding portion SWL. The third portion E3, the first portion E1, and the second portion E2 may be arranged laterally in a third direction D3. The first portion E1, the second portion E2, and the third portion E3 may be integrated into a dog-bone shape. In the second direction D2, the width of the first portion E1 of the extended portion EWL may be smaller than the widths of the second portion E2 and the third portion E3.

[0092] The second and third portions E2 and E3 of the extension portion EWL may have the same width in the second direction D2 . The widths of the second and third portions E2 and E3 of the extension portion EWL may be smaller than the width of the surrounding portion SWL of the word line WL24 in the second direction D2 .

[0093] The surrounding portion SWL and the extension portion EWL of the word line WL24 may have the same length in the third direction D3. In the first direction D1, the height of the extension portion EWL of the word line WL24 may be lower than that of the surrounding portion SWL. In the first direction D1, the heights of the first portion E1, the second portion E2, and the third portion E3 of the extension portion EWL may be lower than that of the surrounding portion SWL.

[0094] Figures 8A to 8C An active layer according to another embodiment of the present invention is shown. Figure 8B It is along Figure 8A A cross-sectional view taken along line A13-A13'. Figure 8C is based on Figure 8A Layout diagram of line A14-A14'.

[0095] refer to Figures 8A to 8C The active layer ACT may have a cross shape. The active layer ACT may include a cross-shaped channel layer CH11. The cross-shaped channel layer CH11 may include a central portion C1 and branch portions C2 and C3 on either side of the central portion C1. The central portion C1 may refer to a portion extending in the second direction D2. The branch portions C2 and C3 may refer to portions extending from the central portion C1 in the third direction D3. The cross shape may be defined by the central portion C1 and the branch portions C2 and C3.

[0096] The word line WL may surround the cross-shaped channel layer CH11. A gap filler material GM may be embedded in the active layer ACT. The gap filler material GM may have a cross shape. The active layer ACT may further include a first source / drain region SD1 and a second source / drain region SD2 on both sides of the cross-shaped channel layer CH11. The length L' of the cross-shaped channel layer CH11 of the active layer ACT in the third direction D3 may be greater than Figure 4 The length L of the channel layer CH.

[0097] The word line WL may extend along a third direction D3. The word line WL may include a surrounding portion SWL and an extension portion EWL extending in the third direction D3 from both sides of the surrounding portion SWL. The surrounding portion SWL of the word line WL may surround the cross-shaped channel layer CH11 of the active layer ACT. The extension portion EWL of the word line WL24 may not surround the cross-shaped channel layer CH11 of the active layer ACT.

[0098] According to the height of the cross-type channel layer CH11, the word line WL can be divided into an upper portion WLU, intermediate connectors WLM1 and WLM2, and a lower portion WLL. The upper portion WLU can be located at a higher level than the cross-type channel layer CH11, and the lower portion WLL can be located at a lower level than the cross-type channel layer CH11. The intermediate connectors WLM1 and WLM2 can be located between the upper portion WLU and the lower portion WLL, and they can have the same height as the cross-type channel layer CH11. The intermediate connectors WLM1 and WLM2 can be located on both sides of the cross-type channel layer CH11 in the third direction D3, respectively. The upper portion WLU and the lower portion WLL can be extended in the third direction D3. Figure 8C As shown, when viewed from above, the mid-level connectors WLM1 and WLM2 may surround sides of the branch portions C2 and C3 of the cross-type channel layer CH11 .

[0099] Figure 9A is a perspective view showing a memory cell array. Figure 9B It is along Figure 9A The cross-sectional view is taken along the line A21-A21' shown. Figure 9A and Figure 9B Also appears in Figures 1 to 8C The reference numerals in the same figure may represent the same component. Figures 1 to 8C in Figure 9A and Figure 9B The components are not described in detail.

[0100] refer to Figure 9A and Figure 9B , the memory device may include a memory cell array MCA, and the memory cell array MCA may include a stack of memory cells MC. The memory cell array MCA may include a 3D array of memory cells MC. The memory cell array MCA may include a DRAM memory cell array. The memory cells MC may be vertically stacked on a substrate LS in a first direction D1. The vertically stacked memory cells MC may share a bit line BL and a plate line PL. The memory cells MC may be laterally arranged in a third direction D3. The laterally arranged memory cells MC may share a word line WL and a plate line PL. Each memory cell MC may be one of the memory cells described in the above-mentioned embodiments of the present invention. For the description of each memory cell MC, reference may be made to the above-mentioned embodiments.

[0101] Each memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR and the capacitor CAP may be positioned in a lateral arrangement LA in the second direction D2 between the bit line BL and the plate line PL. Each memory cell MC may also include a word line WL, and the word line WL may extend in a third direction D3 along its length. The active layer ACT and the word line WL may include the active layer ACT and the word line WL according to the above-described embodiments of the present invention. The active layer ACT may include a channel layer CH, a first source / drain region SD1, and a second source / drain region SD2. A gap filler material GM may be embedded within the active layer ACT. One end of one side of the gap filler material GM may be coupled to the bit line. The word line WL may surround at least the channel layer CH. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The bit line BL may be coupled to a peripheral circuit portion PC, and the peripheral circuit portion PC may be disposed on the substrate LS.

[0102] For the active layer ACT and word line WL, please refer to Figures 3A to 8C .

[0103] Figure 10 1 is a perspective view showing a mirror-type memory cell array MCA1 that shares a plate line. Figure 11 1 is a perspective view showing a mirror-type memory cell array MCA2 that shares bit lines.

[0104] refer to Figure 10 , the memory cells of the memory cell array MCA1 may be arranged in a mirror type structure in which the memory cells share one plate line PL1.

[0105] refer to Figure 11 , the memory cells of the memory cell array MCA2 can be arranged in a mirror-type structure in which the memory cells share one bit line BL1 and BL2. For example, the memory cells sharing the bit line BL1 can be coupled to different plate lines PL1 and PL2. The memory cells sharing the bit line BL2 can be coupled to different plate lines PL1 and PL2.

[0106] exist Figure 9A 、 Figure 9B 、 Figure 10 and Figure 11 For the description of the active layer ACT and the word line WL in the memory cell arrays MCA, MCA1 and MCA2, please refer to Figures 3A to 8C .

[0107] Figure 12 and Figure 13 is a layout diagram showing an example of word lines of a memory cell array.

[0108] refer to Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 12 and Figure 13 Each memory cell array MCA3 and MCA4 may include a word line WL, and the word line WL may extend in the third direction D3 while surrounding the cross-shaped channel layer CH11 of the cross-shaped active layer ACT. Memory cells MC arranged laterally in the third direction D3 may share the word line WL.

[0109] The word line WL may include an upper portion WLU, an intermediate connector WLM, and a lower portion WLL. The upper portion WLU may be located at a level higher than the cross-type channel layer CH, and the lower portion WLL may be located at a level lower than the cross-type channel layer CH11. The intermediate connector WLM may be located between the upper portion WLU and the lower portion WLL, and may have the same height as that of the cross-type channel layer CH11. The intermediate connector WLM may be located between the cross-type channel layers CH11 that are laterally arranged in the third direction D3. The upper portion WLU and the lower portion WLL may extend in the third direction D3. The intermediate connector WLM may surround the side of the branch portion of the cross-type channel layer CH11 (refer to Figure 8C 'C2 and C3' in the .

[0110] Figure 12 and Figure 13 The intermediate-level connector WLM may be formed such that the intermediate-level connectors between the cross-type active layers CH11 arranged in the third direction D3 are coupled to each other. For example, between adjacent cross-type channel layers CH11 in the third direction D3, the intermediate-level connectors may be coupled to form an 'H'-shaped intermediate-level connector. Figure 13 The intermediate connection member WLM can have a 'modified H-shape' and it can be Figure 12 The central portion of the H-shape shown is formed by being thinned in the second direction D2.

[0111] exist Figure 12 and Figure 13 In the embodiment, an isolation material (not shown) such as silicon oxide may be formed between the bit lines BL adjacent to each other in the third direction D3. The isolation material may extend to be located on both sides of the mid-level connector WLM.

[0112] Figure 9A 、 Figure 10 and Figure 11 The memory cell arrays MCA, MCA1, and MCA2 may be located on a substrate LS including a peripheral circuit portion PC. Accordingly, the memory cell arrays MCA, MCA1, and MCA2 may have a peripheral under cell (PUC) structure. In the PUC structure, the bit lines BL may be oriented vertically upward from the substrate LS.

[0113] According to another embodiment of the present invention, the memory cell arrays MCA, MCA1, and MCA2 may be located below the substrate LS including the peripheral circuit unit PC, which may be referred to as a cell-under-periphery (CUP) structure or a periphery-on-cell (POC) structure. In the CUP structure, the bit lines may be oriented vertically downward from the substrate LS.

[0114] The memory cell arrays MCA, MCA1, and MCA2 according to the above-described embodiments of the present invention may provide a 3D DRAM cell array in which memory cells including one transistor and one capacitor are stacked in a vertical direction.

[0115] Although not shown, according to another embodiment of the present invention, a memory device may include a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate. A memory cell array may be formed on the first semiconductor substrate, and a peripheral circuit portion may be formed on the second semiconductor substrate. Each of the first semiconductor substrate and the second semiconductor substrate may include a conductive bonding pad, and the first semiconductor substrate and the second semiconductor substrate may be bonded via the conductive bonding pad. Thus, the memory cell array and the peripheral circuit portion may be electrically connected.

[0116] According to another embodiment of the present invention, Figure 9B As shown, the memory device may include: a substrate LS, which includes a peripheral circuit portion PC; an active layer ACT, which includes a nanowire channel CH spaced apart from the substrate LS and laterally oriented in a second direction D2; a word line WL, which is laterally oriented in a third direction D3 crossing the second direction while surrounding the nanowire channel CH; a bit line BL, which is coupled to an end portion of one side of the active layer ACT and vertically oriented in a first direction D1 starting from the peripheral circuit portion PC; and a lateral capacitor CAP, which is coupled to an end portion of the other side of the active layer ACT and spaced apart from the substrate LS.

[0117] According to another embodiment of the present invention, Figures 4 to 7D As shown, the surrounding portion SWL may be referred to as a gate, and the extension portions EWL and EWL' may be referred to as lateral word lines. Figure 14 Describe this.

[0118] Figure 14 FIG. 1 is a diagram showing a layout of a memory cell array MCA5 according to another embodiment of the present invention.

[0119] refer to Figure 14, the memory cell array MCA5 may include a plurality of memory cells MC. Each memory cell MC may include: a gate-around transistor GAA_TR; a bit line BL coupled to a first source / drain region SD1 of the gate-around transistor GAA_TR; a capacitor CAP coupled to a second source / drain region SD2 of the gate-around transistor GAA_TR; and a lateral word line L_WL coupled to the gate GAA_S of the gate-around transistor GAA_TR. The gates GAA_S of the gate-around transistors GAA_TR located at the same level in the third direction D3 may be coupled to one lateral word line L-WL. The bit line BL may be vertically oriented in the first direction D1, and the active layer ACT including the cross-type channel layer CH11 of the gate-around transistor GAA_TR may be laterally oriented in the second direction D2. The lateral word line L-WL may include an intermediate-level connector WLM for coupling adjacent gates GAA_S to each other. The intermediate-level connector WLM may have an 'H' shape.

[0120] According to an embodiment of the present invention, the integration density of a 3D memory device may be improved by three-dimensionally stacking transistors and capacitors over a substrate.

[0121] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A storage device comprising: substrate; an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction parallel to the substrate, and comprising an open first side, a closed second side, and a channel layer between the first side and the closed second side; a word line surrounding the channel layer and laterally oriented in a second direction intersecting the first direction; and a bit line coupled to the open first side of the active layer and oriented vertically relative to the substrate; Wherein, the active layer comprises: a gap-filling material extending along the first direction and comprising a dielectric material; and source / drain regions surrounding the gap-fill material, The gap-fill material includes a first side directly coupled to the bit line, and a second side facing the first side and directly coupled to the source / drain region.

2. The memory device according to claim 1, further comprising: A capacitor is coupled to the enclosed second side of the active layer.

3. The memory device according to claim 1, wherein The active layer has a laterally oriented cylindrical shape.

4. The memory device according to claim 1, wherein The source / drain region includes: a first source / drain region surrounding an end portion of one side of the gap-fill material; and A second source / drain region surrounds an end portion of the other side of the gap-fill material.

5. The memory device according to claim 1, wherein The active layer includes a silicon layer, InGaZnO x 、InSnZnO x 、ZnSnO x , MoS2, WS2 or MoSe2.

6. The memory device according to claim 1, wherein The word line includes: a surrounding portion that surrounds the channel layer; and The extending portions extend in the second direction from both sides of the surrounding portion.

7. The memory device according to claim 1, wherein The word line includes: an upper portion located at a higher level than the channel layer; a lower level portion located at a lower level than the channel layer; and An intermediate-level connector is located between the upper-level portion and the lower-level portion and is located at the same level as the channel layer.

8. A storage device comprising: a plurality of cylindrical active layers spaced apart from each other along a first direction over the substrate, the cylindrical active layers each being laterally oriented in a second direction intersecting the first direction and comprising a channel layer; and a word line surrounding the channel layer of the cylindrical active layer and extending horizontally, Wherein, the word line includes: an upper portion located at a higher level than the channel layer; a lower level portion located at a lower level than the channel layer; an intermediate-level connector located between the upper-level portion and the lower-level portion and at the same level as the channel layer; and a bit line extending vertically and coupled to the substrate; Wherein, each of the cylindrical active layers comprises: a gap-filling material extending along the second direction and comprising a dielectric material; and source / drain regions surrounding the gap-fill material, The gap-fill material includes a first side directly coupled to the bit line, and a second side facing the first side and directly coupled to the source / drain region.

9. The memory device according to claim 8, wherein the channel layer including a plurality of outer sides surrounding the gap-filling material; Wherein, the source / drain region includes: a first source / drain region surrounding an end portion of one side of the gap-fill material; and A second source / drain region surrounds an end portion of the other side of the gap-fill material.

10. The memory device according to claim 8, wherein Each of the cylindrical active layers is laterally oriented in a direction crossing the word lines.

11. The memory device according to claim 8, wherein The active layer includes a silicon layer, InGaZnO x 、InSnZnO x 、ZnSnO x , MoS2, WS2 or MoSe2.

12. The memory device according to claim 8, further comprising: a bit line coupled to one side of the active layer and oriented vertically in a vertical direction from the substrate; and A capacitor is coupled to the other side of the active layer.

13. A storage device comprising: a substrate including a peripheral circuit portion; an active layer comprising a nanowire channel spaced apart from the substrate and laterally oriented in a first direction parallel to the substrate; a word line surrounding the nanowire channel and laterally oriented in a direction crossing the nanowire channel; a bit line coupled to an end portion of one side of the active layer and vertically oriented from the peripheral circuit portion; and a lateral capacitor coupled to the other end of the active layer and spaced apart from the substrate; Wherein, the active layer comprises: a gap-filling material extending along the first direction and comprising a dielectric material; and source / drain regions surrounding the gap-fill material, The gap-fill material includes a first side directly coupled to the bit line, and a second side facing the first side and directly coupled to the source / drain region.

14. The memory device according to claim 13, wherein The source / drain region includes a first source / drain region and a second source / drain region, wherein the first source / drain region and the second source / drain region are located on both sides of the nanowire channel, and The first source / drain region and the second source / drain region surround the gap filling material.

15. The memory device according to claim 13, wherein The active layer includes polysilicon nanowires, oxide semiconductor nanowires or transition metal and chalcogen compound nanowires.

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