Semiconductor device and method of manufacturing the same and one-time programmable memory device

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device according to the present disclosure includes a gate structure, a source / drain component, a dielectric layer, a gate contact, and a source / drain contact. The source / drain component is adjacent to the gate structure. The dielectric layer is disposed on the gate structure and the source / drain component. The gate contact is disposed in the dielectric layer and on the gate structure. The source / drain contact is disposed in the dielectric layer and on the source / drain component. The dielectric layer is doped with a dopant, and the dopant includes germanium or tin.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and a one-time programmable memory device. BACKGROUND

[0002] Among semiconductor memory devices, non-volatile memory (NVM) devices can be used to store data even when the memory device is powered off. In various examples, non-volatile memory devices can include read only memory (ROM), magnetic memory, optical memory, or flash memory, which can exist in different kinds of non-volatile memory devices. Non-volatile memory devices include multi-time programmable (MTP) memory devices, few-time programmable (FTP) memory devices, and one-time programmable (OTP) memory devices. As the name implies, OTP NVM devices can only be programmed successfully once, but MTP NVM devices can be programmed successfully many times. Compared with MTP NVM devices, OTP NVM devices have simpler construction and smaller footprint. OTP NVM devices are often used in embedded NVM applications due to compatibility with existing processes, scalability, reliability, and security. Depending on the target application, device requirements, and manufacturing requirements, floating gate, E-fuse, or antifuse technologies can be used to implement OTP NVM devices.

[0003] OTP NVM devices using antifuse technology can be programmed by electrically shorting both the gate and the source of a transistor. In an example programming process, a programming voltage exceeding the breakdown voltage of the gate dielectric layer is applied to the gate, causing avalanche breakdown of the gate dielectric layer. Avalanche breakdown of the gate dielectric layer will cause the gate to be shorted to the source. However, conventional OTP NVM devices are typically only suitable for their original design purposes and cannot meet all aspects. SUMMARY

[0004] In some embodiments, the disclosure provides a semiconductor device, comprising: a gate structure; a source / drain component adjacent to the gate structure; a dielectric layer disposed over the gate structure and the source / drain component; a gate contact disposed in the dielectric layer and over the gate structure; a source / drain contact disposed in the dielectric layer and over the source / drain component; wherein the dielectric layer is doped with a dopant; wherein the dopant comprises germanium or tin.

[0005] In some embodiments, the disclosure provides a One-Time Programmable (OTP) memory device, comprising: an active region; a first gate structure and a second gate structure over the active region; a dielectric layer disposed over the first gate structure and the second gate structure; a first source / drain contact disposed between the first gate structure and the second gate structure; a second source / drain contact separated from the first source / drain contact by the second gate structure; a first gate contact disposed over the first gate structure and electrically coupled to the first gate structure; wherein a portion of the first source / drain contact, a portion of the second source / drain contact, and the first gate contact are disposed within the dielectric layer; wherein the dielectric layer is doped with a dopant; wherein the dopant comprises germanium or tin.

[0006] In some embodiments, the disclosure provides a method of manufacturing a semiconductor device, comprising: receiving a workpiece, wherein the workpiece comprises a dielectric layer, a gate contact disposed in the dielectric layer, and a source / drain contact disposed in the dielectric layer adjacent to the gate contact; and after receiving the workpiece, implanting the dielectric layer with a dopant. BRIEF DESCRIPTION OF DRAWINGS

[0007] The embodiments of the disclosure can be understood more readily by reference to the following detailed description of the embodiments and the Examples and by reference to the various figures and their previous and following description.

[0008] Figure 1 is a circuit diagram showing an equivalent circuit of a portion of an OTP NVM device according to one or more aspects of the disclosure.

[0009] Figure 2 is a flowchart showing a method of manufacturing a semiconductor device according to one or more aspects of the disclosure.

[0010] Figure 3 is a layout diagram showing a semiconductor device according to one or more aspects of the disclosure.

[0011] Figure 4 is a partial cross-sectional view showing a portion of a semiconductor device that has undergone an implantation procedure in accordance with one or more aspects of the present disclosure. Figure 3

[0012] Figure 5 is a partial cross-sectional view showing a portion of a semiconductor device that has undergone an implantation procedure in accordance with one or more aspects of the present disclosure.

[0013] Figure 6 is a layout view showing a semiconductor device that has undergone an implantation procedure in accordance with one or more aspects of the present disclosure. Figure 5

[0014] Figure 7 is a partial cross-sectional view showing a portion of a semiconductor device that has undergone an implantation procedure in accordance with one or more aspects of the present disclosure. Figure 5

[0015] Figure 8 is a partial cross-sectional view showing a portion of a semiconductor device that has undergone an implantation procedure in accordance with one or more aspects of the present disclosure.

[0016] Wherein the reference signs are explained as follows:

[0017] 10: circuit diagram

[0018] 100: method

[0019] 102, 104, 106: operation

[0020] 1000: first leakage path

[0021] 200: workpiece

[0022] 202: substrate

[0023] 204: active region

[0024] 206-1: first gate structure

[0025] 206-2: second gate structure

[0026] 206-3: third gate structure

[0027] 206-4: fourth gate structure

[0028] 208-1: first source / drain contact

[0029] 208-2: first source / drain contact

[0030] 208-3: first source / drain contact

[0031] ​​​210-1: first gate contact

[0032] 210-2: second gate contact

[0033] 210-3: third gate contact

[0034] 210-4: fourth gate contact

[0035] 212: OTP memory device

[0036] 214: source / drain contact via

[0037] 216: first dielectric layer

[0038] 218-1: first program word line

[0039] 218-2: second program word line

[0040] 220-1: first read word line

[0041] 220-2: second read word line

[0042] 222-1: first bit line

[0043] 222-2: second bit line

[0044] 222-3: third bit line

[0045] 224-1: first isolation structure

[0046] 224-2: second isolation structure

[0047] 226: source / drain component

[0048] 228: gate dielectric layer

[0049] 230: gate electrode

[0050] 232: gate spacer

[0051] 234: contact etch stop layer

[0052] 2000: second leakage path

[0053] 2160: second dielectric layer

[0054] 300: injection procedure

[0055] 3000: leakage component

[0056] BL: bit line

[0057] I cell : cell current

[0058] SEL: select node

[0059] T1: first transistor

[0060] T2: second transistor

[0061] T3: third transistor

[0062] V pp : programming voltage

[0063] WLP: program word line

[0064] WLR: read word line

[0065] X: X-axis

[0066] Y: Y-axis

[0067] Z: Z-axis DETAILED DESCRIPTION

[0068] The following detailed description is presented to enable any person skilled in the art to make and use the application. Descriptions of specific embodiments are included to provide a sufficient understanding of the application. However, it will be clear to those skilled in the art that various modifications, combinations, sub-combinations and equivalents can be used, and that the scope of the application extends beyond the specific embodiments described herein. For the purpose of this disclosure, the terms "coupled" and "connected," along with their derivatives, can be used to describe functional relationships between elements. It should be understood that these terms are not intended to limit the scope of the application to the precise structural relationships depicted in the drawings. It should be further understood that these terms are intended to encompass not only direct connections between elements, but indirect connections requiring one or more intermediate elements. In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0069] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0070] Further, when describing a numerical value or a range of numerical values with words such as "about," "approximately," and the like, the words are intended to encompass values in a reasonable range of the value as understood by those of ordinary skill in the art, taking into account various variations that can occur in the manufacturing process. For example, based on known manufacturing tolerances, and manufacturing characteristics associated with the values, the value or range can encompass a reasonable range of the value, such as + / - 10% of the value. For example, if those of ordinary skill in the art know that a manufacturing tolerance associated with depositing a layer of material is + / - 15%, then a layer of material having a thickness of "about 5 nm" can include a range of sizes from 4.25 nm to 5.75 nm. Still further, the specification can refer to various examples in the singular or / and plural. This is done simply for ease of reference and does not imply a relationship between the various examples or / and configurations.

[0071] Among semiconductor memory devices, non-volatile memory (NVM) devices can be used to store data even when the memory device is powered off. Non-volatile memory devices include multi-time programmable (MTP) memory devices, few-time programmable (FTP) memory devices, and one-time programmable (OTP) memory devices. As the name implies, OTP NVM devices can only be successfully programmed once, but MTP NVM devices can be successfully programmed many times. Compared to MTP NVM devices, OTP NVM devices have a simpler construction and a smaller footprint. OTP NVM devices are often used for embedded NVM applications due to compatibility with existing processes, scalability, reliability, and security. Depending on the target application, device requirements, and fabrication requirements, a floating gate, e-fuse, or antifuse technology can be used to implement an OTP NVM device.

[0072] Floating-gate based OTP NVM devices include a floating gate that is isolated by an oxide layer. Programming a floating-gate OTP NVM device involves applying a high voltage to trap charge on the floating gate. Erasing a floating-gate OTP NVM device involves depleting the charge trapped on the floating gate. Electron-fuse based OTP NVM devices include a narrow width fuse. Programming an electron-fuse OTP NVM device involves applying a high voltage across the fuse. The high voltage induces a high current density through the fuse, and the fuse is blown by accelerated electro-migration. Since the mechanism of fuse blowing is irreversible, programming an electron-fuse OTP NVM device cannot be erased. Reverse-fuse based OTP NVM devices include a dielectric layer with a relatively low breakdown voltage. In some conventional technologies, a reverse-fuse OTP NVM device includes a thinner gate dielectric layer (i.e., a core gate dielectric layer) for some transistors, and a thicker gate dielectric layer (i.e., an Input / Output (I / O) gate dielectric layer) for other transistors. When a high programming voltage is applied, the thinner gate dielectric layer breaks down and forms a conductive path to allow a cell current (I cell ) to pass through. Compared to floating-gate OTP NVM devices and electron-fuse OTP NVM devices, reverse-fuse OTP NVM devices can be more scaled down, and their implementation requires little or even no charge for the structure or process.

[0073] The operation of a reverse-fuse OTP NVM device will be further described in Figure 1 . Figure 1 is a circuit diagram 10 showing the equivalent circuit of a portion of a reverse-fuse OTP NVM device. As shown in Figure 1 , the circuit diagram 10 includes a first transistor T1, a second transistor T2, and a third transistor T3. The gate of the first transistor T1 is coupled to a programming word line (WLP) that can be used to apply a programming voltage (V pp ) to program the OTP NVM device. The gate of the second transistor T2 is coupled to a read word line (WLR). The gate of the third transistor T3 is coupled to a select (SEL) node. The source / drain of the third transistor T3 is coupled to a bit line (BL). When the programming voltage (V pp) has not been applied, and both the second transistor T2 and the third transistor T3 are turned on, only a leakage current will flow from the first transistor Tl, through the second transistor T2 and the third transistor T3 to the bit line, which results in a small cell current (I cell ) and the bit line (BL) can read out "0". In an ideal case, when the program voltage (V pp ) is applied to the program word line (WLP), the program voltage (V pp ) will be high enough to cause the gate dielectric of the first transistor Tl to break down and a larger cell current (I cell ) to flow through this new leakage path. When both the second transistor T2 and the third transistor T3 are turned on, a larger cell current (I cell ) can flow from the first transistor Tl, through the second transistor T2 and the third transistor T3 to the bit line, which results in and the bit line can read out "1". If, due to any process variation, the program voltage (V pp ) is not high enough to cause the gate dielectric of the first transistor Tl to break down, the program operation of the antifuse OTP NVM device can fail. In some examples, this program operation can be retried once.

[0074] Traditionally, the selected program voltage (V pp ) is higher than the breakdown voltage of the gate dielectric of the first transistor Tl. Since the first transistor Tl is not special and the rest of the core transistors share the same gate dielectric thickness, the program voltage (V pp ) can be between 4.5V and 5.5V. Since this program voltage can be higher than the supply voltage provided by the input / output device or the control circuit, a structural change can be needed. In some examples where successful programming is desired, a higher program voltage (V pp ) can be needed to implement to accommodate various possible process variations. For example, when the gate dielectric of the transistors in the OTP NVM device has different thicknesses, the program voltage must reliably cause all the gate dielectrics that should break down to break down. As the program voltage (V pp ) is increased, the supply voltage and the power consumption of the OTP NVM device will also increase. In some examples, structural changes such as deep n-type well are proposed to withstand the high supply voltage. Such structural changes can complicate the manufacturing process and reduce the yield, which can offset the benefits of the antifuse OTP NVM device described above.

[0075] A process is presented to form a leakage path with a low breakdown voltage in an OTP NVM device. In an example process, a workpiece including an OTP NVM device can be received. The workpiece includes a gate contact and a source / drain contact, where the source / drain contact is adjacent to the gate contact. The gate contact and the source / drain contact are embedded in a dielectric layer. In an example process, a dopant species such as germanium or tin can be implanted into the workpiece to introduce impurities and defects in the dielectric layer. The defects in the dielectric layer will lower the breakdown voltage of the dielectric layer between the gate contact and the source / drain contact, which can be lowered to about 2V to 3V, for example, 2.5V. Thus, a lower programming voltage, for example, between about 2V to 3V, is needed for programming the OTP NVM device. In some embodiments, the breakdown of the dielectric layer between the gate contact and the source / drain contact can create a leakage path (or a conduction path) that can physically extend between the gate contact and the source / drain contact. The leakage path (or conduction path) can include materials from the gate contact and the source / drain contact. By lowering the programming voltage, embodiments of the disclosure can reduce the power consumption of an OTP NVM device by as much as 90%.

[0076] Various aspects of the disclosure will now be described in Figures 2-8 greater detail. Figure 2 A flow diagram in accordance with one or more aspects of the disclosure is shown in FIG. 1, which can illustrate a method 100 of forming a semiconductor device or a portion thereof from a workpiece. The method 100 is merely an example and is not intended to limit the disclosure to anything that is specifically shown in the method 100. Other operations can be provided before, during, and after the method 100, and some of the described operations can be replaced, eliminated, or moved to a different position. For the sake of brevity, not every operation is described in detail. The method 100 is described below in conjunction with partial cross-sectional or layout views of a workpiece 200 at different stages of fabrication, as shown in FIGS. 2-8, in accordance with embodiments of the method 100. For the avoidance of doubt, in all of the figures, the X-direction is perpendicular to the Y-direction, and the Z-direction is perpendicular to both the X-direction and the Y-direction. It must be noted that because the workpiece 200 can be fabricated into a semiconductor device, the workpiece 200 can also be referred to as a semiconductor device 200, as needed in context.

[0077] Reference is made to Figure 2 , Figure 3 , Figure 4The method 100 includes an operation 102 in which a workpiece 200 has been received. Figure 3 is a layout view of the workpiece 200. As Figure 3As shown, the features whose views are obstructed by other features can be considered as a perspective top view of the workpiece 200. The workpiece 200 includes a substrate 202 and an OTP memory device 212, where the OTP memory device 212 is disposed on the substrate 202. The OTP memory device 212 can be an OTP NVM device and includes an active region 204, a first gate structure 206-1, a second gate structure 206-2, a third gate structure 206-3, a fourth gate structure 206-4, a first source / drain contact 208-1, a second source / drain contact 208-2, a third source / drain contact 208-3, a first program word line (WLP0) 218-1, a second program word line (WLP1) 218-2, a first read word line (WLR0) 220-1, a second read word line (WLR1) 220-2, a first bit line 222-1, a second bit line 222-2, a third bit line 222-3, a first isolation structure 224-1, and a second isolation structure 224-2. The first gate structure 206-1 is electrically coupled to the first program word line (WLP0) 218-1 through a first gate contact 210-1. The second gate structure 206-2 is electrically coupled to the first read word line (WLR0) 220-1 through a second gate contact 210-2. The third gate structure 206-3 is electrically coupled to the second read word line (WLR1) 220-2 through a third gate contact 210-3. The fourth gate structure 206-4 is electrically coupled to the second program word line (WLP1) 218-2 through a fourth gate contact 210-4. The second source / drain contact 208-2 is electrically coupled to the first bit line 222-1, the second bit line 222-2, and the third bit line 222-3 through source / drain contact vias 214. The first gate contact 210-1, the second gate contact 210-2, the third gate contact 210-3, the fourth gate contact 210-4, the first source / drain contact 208-1, the second source / drain contact 208-2, the third source / drain contact 208-3, and the source / drain contact vias 214 can be disposed / embedded in a first dielectric layer 216. The first dielectric layer 216 can be disposed on the substrate 202 and can include being disposed on the first gate structure 206-1, the second gate structure 206-2, the third gate structure 206-3, and the fourth gate structure 206-4.

[0078] In one embodiment, the substrate 202 can be a silicon (Si) substrate. In some other embodiments, the substrate 202 can include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. For example, the III-V semiconductor materials can include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 can also include an insulating layer, such as a silicon oxide layer, to provide a silicon-on-insulator (SOI) structure. In some embodiments, the substrate 202 can include one or more wells, such as an n-well doped with n-type dopants (i.e., phosphorus (P) or arsenic (As)) or a p-well doped with p-type dopants (i.e., boron (B) or gallium (Ga)) to form different types of devices. The doping of the n-well and the p-well can be formed by using ion implantation or thermal diffusion.

[0079] The active region 204 can include a fin structure raised above the substrate 202. When the active region 204 includes a fin structure, the transistors in the semiconductor device 200 can be fin-type field effect transistors (FinFETs). The active region 204 can be formed by patterning the substrate 202 or an epitaxial layer deposited on the substrate 202. Although not explicitly shown in the figures, a base portion of the active region 204 can be surrounded by an isolation feature to isolate the active region 204 from a neighboring active region. The isolation feature can be a shallow trench isolation (STI) feature. The isolation feature can be composed of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, a combination thereof, and / or other suitable materials known in the art.

[0080] The first gate structure 206-1, the second gate structure 206-2, the third gate structure 206-3, and the fourth gate structure 206-4 can be disposed on the active region 204. More specifically, the first gate structure 206-1, the second gate structure 206-2, the third gate structure 206-3, and the fourth gate structure 206-4 can be disposed on the channel region of the active region 204. Figure 3 In the illustrated embodiment, the active region 204 extends lengthwise along the X-axis, while the first gate structure 206-1, the second gate structure 206-2, the third gate structure 206-3, and the fourth gate structure 206-4 extend lengthwise along the Y-axis, which is perpendicular to the X-axis. Figure 3 In this configuration, each intersection of the gate structure and the active region 204 defines a separate transistor in the OTP memory device 212. Each of the first gate structure 206-1, the second gate structure 206-2, the third gate structure 206-3, and the fourth gate structure 206-4 includes a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is located above the active region 204, and the gate electrode is located above the gate dielectric layer. (See reference...) Figure 4 This example illustrates how each gate structure is constructed. Figure 4 As shown, the first gate structure 206-1 includes a gate dielectric layer 228 and a gate electrode 230, wherein the gate dielectric layer 228 is located above the active region 204, and the gate electrode 230 is located above the gate dielectric layer 228. The remaining gate structures (second gate structure 206-2, third gate structure 206-3, and fourth gate structure 206-4) have similar construction methods, and their details are omitted here.

[0081] The gate dielectric layer 228 includes an interfacial layer on the active region 204 and a high-k dielectric layer on the interfacial layer. In some embodiments, the interfacial layer can include a silicon oxide layer (SiO2), a silicon oxynitride layer (SiON), or a hafnium silicate layer (HfSiO). In one embodiment, the high-k dielectric layer can include a hafnium oxide layer (HfO2). Alternatively, the high-k dielectric layer can include other high-k dielectrics such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3(STO), BaTiO3(BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3(BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. In various embodiments, the gate electrode 230 can be a multi-layer structure including at least one work function layer and a metal fill layer. For example, the at least one work function layer can include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum cyanide (TaCN), or tantalum carbide (TaC). The metal fill layer can include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials, or combinations thereof. In Figure 4 In some embodiments, the sidewall of the first gate structure 206-1 is lined by a gate spacer 232. The gate spacer 232 can include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. Similarly, the other gate structures (second gate structure 206-2, third gate structure 206-3, and fourth gate structure 206-4) can also be lined by the gate spacer 232.

[0082] Referring again to Figure 1The first gate contact 210-1 is disposed on the first gate structure 206-1 and extends into the first dielectric layer 216. The second gate contact 210-2 is disposed on the second gate structure 206-2 and extends into the first dielectric layer 216. The third gate contact 210-3 is disposed on the third gate structure 206-3 and extends into the first dielectric layer 216. The fourth gate contact 210-4 is disposed on the fourth gate structure 206-4 and extends into the first dielectric layer 216. Each of the first gate structure 206-1, the second gate structure 206-2, the third gate structure 206-3, and the fourth gate structure 206-4 is disposed on a channel region in the active region 204. A source / drain feature 226 is disposed in the source / drain region adjacent to the channel region. Referring again to Figure 4 , which illustrates an association of a source / drain feature 226 with its adjacent structures. As shown in Figure 4 , the first source / drain contact 208-1 is disposed on the source / drain feature 226, which can be disposed between two channel regions overlapping the first gate structure 206-1 and the second gate structure 206-2. As shown in Figure 4 , the source / drain feature 226 is adjacent to the first gate structure 206-1 and the second gate structure 206-2. In some embodiments, the first source / drain contact 208-1 can be in direct contact with the source / drain feature 226. In some embodiments not explicitly shown in the figures, a silicide layer can be sandwiched between the first source / drain contact 208-1 and the source / drain feature 226. Such a silicide layer can include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). Each source / drain contact is disposed between two gate structures.

[0083] As shown in Figure 4As shown, the first source / drain contact 208-1 is disposed between the first gate structure 206-1 and the second gate structure 206-2 and extends into the dielectric layer. Each source / drain contact can be separated from the gate spacer 232 by a contact etch stop layer (CESL) 234. The contact etch stop layer 234 can include silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The source / drain contact via 214 is disposed on the second source / drain contact 208-2 and in the first dielectric layer 216. The first gate contact 210-1, the second gate contact 210-2, the third gate contact 210-3, the fourth gate contact 210-4, the first source / drain contact 208-1, the second source / drain contact 208-2, the third source / drain contact 208-3, and the source / drain contact via 214 can include copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), nickel (Ni), cobalt (Co), or other suitable metals or metal alloys. Additionally, although not shown, a barrier layer can separate the sidewalls of each of the first gate contact 210-1, the second gate contact 210-2, the third gate contact 210-3, the fourth gate contact 210-4, the first source / drain contact 208-1, the second source / drain contact 208-2, the third source / drain contact 208-3, and the source / drain contact via 214 from the first dielectric layer 216. Figure 4 As shown, the first source / drain contact 208-1 is disposed between the first gate structure 206-1 and the second gate structure 206-2 and extends into the dielectric layer. Each source / drain contact can be separated from the gate spacer 232 by a contact etch stop layer (CESL) 234. The contact etch stop layer 234 can include silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The source / drain contact via 214 is disposed on the second source / drain contact 208-2 and in the first dielectric layer 216. The first gate contact 210-1, the second gate contact 210-2, the third gate contact 210-3, the fourth gate contact 210-4, the first source / drain contact 208-1, the second source / drain contact 208-2, the third source / drain contact 208-3, and the source / drain contact via 214 can include copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), nickel (Ni), cobalt (Co), or other suitable metals or metal alloys. Additionally, although not shown, a barrier layer can separate the sidewalls of each of the first gate contact 210-1, the second gate contact 210-2, the third gate contact 210-3, the fourth gate contact 210-4, the first source / drain contact 208-1, the second source / drain contact 208-2, the third source / drain contact 208-3, and the source / drain contact via 214 from the first dielectric layer 216.

[0084] The first dielectric layer 216 can be an interlayer dielectric (ILD) layer and can include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG). See, e.g., U.S. Patent No. 6,309,745, which is incorporated herein by reference in its entirety. Figure 4The shortest distance between the first gate contact 210-1 and the first source / drain contact 208-1 is greater than the thickness of the gate dielectric layer 228. For example, the shortest distance between the first gate contact 210-1 and the first source / drain contact 208-1 can be approximately between 5 nm to 10 nm, but the thickness of the gate dielectric layer 228 can be approximately between 1 nm to 3 nm. As such, when a programming voltage is applied to the first gate contact 210-1, the gate dielectric layer 228 can breakdown, but the dielectric layer does not. The breakdown of the gate dielectric layer 228 can create a first leakage path 1000, which can be from the gate electrode 230, through the active region 206 and the source / drain component 226, to the first source / drain contact 208-1. It can be observed that the breakdown of the gate dielectric layer 228 can require a programming voltage between 4.5 V to 5.5 V. As previously mentioned, such a high programming voltage (approximately between 4.5 V to 5.5 V) can result in increased power consumption, and can require additional components and structures to boost the supply voltage.

[0085] The first programming word line (WLP0) 218-1, the second programming word line (WLP1) 218-2, the first read word line (WLR0) 220-1, the second read word line (WLR1) 220-2, the first bit line 222-1, the second bit line 222-2, and the third bit line 222-3 can all be metal lines (Metal Lines) that can be formed in a Metal-0 (M0) Interconnection Layer. These metal lines can include copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), nickel (Ni), cobalt (Co), or other suitable metals or metal alloys that can extend longitudinally along the X-axis direction. The first isolation structure 224-1 and the second isolation structure 224-2 can be dummy fins or dielectric fins formed from one or more dielectric materials, such as silicon oxide, silicon nitride, or silicon oxynitride. The first isolation structure 224-1 and the second isolation structure 224-2 can also extend longitudinally along the X-axis direction.

[0086] Referring to Figure 2 , Figure 5 , Figure 6 , Figure 7 . The method 100 includes an operation 104 in which an implantation processor 300 is applied to the first dielectric layer 216. In Figure 5In some embodiments, the implantation procedure 300 can be used to introduce impurities and defects in the first dielectric layer 216. In some embodiments, the implantation procedure 300 can implant dopants in Group 4A of the Periodic Table, such as germanium (Ge) or tin (Sn), to introduce defects and impurities in the first dielectric layer 216. In some other embodiments, the implantation procedure can implant inert gases, such as xenon or argon, to introduce defects and vacancies in the first dielectric layer 216. The implantation procedure 300 can include an implantation dosage of about 5 x 1011 atoms per square centimeter to about 1 x 1012 atoms per square centimeter. In some embodiments, the implantation procedure 300 can include an ion implantation energy of about 5 keV to 30 keV. Reference can be made to FIGS. 6 and 7. For ease of reference, the first dielectric layer 216 that has been implanted by the implantation procedure 300 can be referred to as a second dielectric layer 2160. It can be observed that the defects, impurities, and vacancies caused by the implantation procedure 300 can trap charges and contribute to a percolation process that causes the second dielectric layer 2160 to breakdown. In other words, the implantation procedure 300 in operation 104 effectively lowers the breakdown voltage of the dielectric layer. According to the present disclosure, as a result of the implantation procedure 300, the breakdown voltage of the second dielectric layer 2160 between the first gate contact 210-1 and the first source / drain contact 208-1 can be lower than the breakdown voltage of the gate dielectric layer 228. 14 15 In some embodiments, the implantation procedure 300 can be used to introduce impurities and defects in the first dielectric layer 216. In some embodiments, the implantation procedure 300 can implant dopants in Group 4A of the Periodic Table, such as germanium (Ge) or tin (Sn), to introduce defects and impurities in the first dielectric layer 216. In some other embodiments, the implantation procedure can implant inert gases, such as xenon or argon, to introduce defects and vacancies in the first dielectric layer 216. The implantation procedure 300 can include an implantation dosage of about 5 x 1011 atoms per square centimeter to about 1 x 1012 atoms per square centimeter. In some embodiments, the implantation procedure 300 can include an ion implantation energy of about 5 keV to 30 keV. Reference can be made to FIGS. 6 and 7. For ease of reference, the first dielectric layer 216 that has been implanted by the implantation procedure 300 can be referred to as a second dielectric layer 2160. It can be observed that the defects, impurities, and vacancies caused by the implantation procedure 300 can trap charges and contribute to a percolation process that causes the second dielectric layer 2160 to breakdown. In other words, the implantation procedure 300 in operation 104 effectively lowers the breakdown voltage of the dielectric layer. According to the present disclosure, as a result of the implantation procedure 300, the breakdown voltage of the second dielectric layer 2160 between the first gate contact 210-1 and the first source / drain contact 208-1 can be lower than the breakdown voltage of the gate dielectric layer 228.

[0087] ​In some embodiments, a programming voltage between approximately 2V and 3V is sufficient to cause the second dielectric layer 2160 between the first gate contact 210-1 and the first source / drain contact 208-1 to collapse. Because a programming voltage between approximately 2V and 3V is insufficient to cause the gate dielectric layer 228 to collapse, the gate dielectric layer 228 will remain intact. Therefore, when a programming voltage between approximately 2V and 3V is applied to the first gate contact 210-1, the gate dielectric layer 228 may collapse along a second leakage path 2000, but the dielectric layer will not. The second leakage path 2000 can pass through the second dielectric layer 2160 between the first gate contact 210-1 and the first source / drain contact 208-1. To ensure that the implantation process 300 reaches the region between the first gate contact 210-1 and the first source / drain contact 208-1, the implantation process 300 includes ion implantation energies between approximately 5 keV and 30 keV. To ensure that the programming voltage falls within the range of 2V to 3V, the implantation process 300 includes a concentration of approximately 5 × 10⁻⁶ ions. 14 atoms / square centimeter and 1×10 15 Injection dose between atoms per square centimeter. When the dose is below 5 × 10⁻⁶ 14 At a dose of atoms per square centimeter, the implantation procedure 300 is insufficient to reduce the breakdown voltage of the second dielectric layer 2160 to the required level. When the dose is higher than 1 × 10⁻⁶, 15 At a dose of atoms per square centimeter, the implantation procedure 300 may cause the breakdown voltage of the second dielectric layer 2160 to inappropriately decrease to a level where the OTP memory device is prone to failure. For example, when the dose is higher than 1 × 10⁻⁶, 15 When the density is 1 atom / square centimeter, the second gate contact point 210-2 (e.g.) Figure 6 The second dielectric layer 2160 between the first source / drain contact 208-1 (shown) and the second gate contact 210-2 may break down during a read operation of the OTP memory device 212. During the read operation, a read voltage between approximately 0.5V and 1.5V may be applied to the second gate contact 210-2. After implantation procedure 300, the second dielectric layer 2160 may include a dielectric layer between 5×10⁻⁶ and 10⁻⁶ ohms. 14 atoms / square centimeter and 1×10 15 Dopant concentration per atom / square centimeter, as described above, wherein the dopant may include germanium or tin.

[0088] Please refer to Figure 2 , Figure 8Method 100 includes an operation 106 in which a program voltage is applied to OTP memory device 212. In operation 106, a program voltage of approximately between 2V and 3V is applied to first program word line (WLP0) 218-1 and second program word line (WLP1) 218-2. The program voltage can be applied to first gate structure 206-1 and fourth gate structure 206-4 through first gate contact 210-1 and fourth gate contact 210-4, respectively. Because the program voltage of approximately between 2V and 3V is not sufficient to cause breakdown of gate dielectric layer 228, gate dielectric layer 228 will remain intact. However, as previously described, the program voltage of approximately between 2V and 3V is sufficient to cause breakdown of second dielectric layer 2160 between first gate contact 210-1 and first source / drain contact 208-1, and sufficient to cause breakdown of second dielectric layer 2160 between fourth gate contact 210-4 and third source / drain contact 208-3.

[0089] Experiments and microscopy images show that the application of the program voltage can create a leakage feature due to electromigration. Figure 8 A leakage feature 3000 between first gate contact 210-1 and first source / drain contact 208-1 is shown. Leakage feature 3000 includes material of first gate contact 210-1 and first source / drain contact 208-1. For example, leakage feature 3000 can include copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), nickel (Ni), cobalt (Co), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), nickel nitride (NiN), or cobalt nitride (CoN).

[0090] Various embodiments described herein provide several advantages over the prior art. It will be appreciated that not necessarily all advantages are discussed herein and that some embodiments can provide different advantages to different embodiments. As an example, the methods of the present disclosure can shift a programming leakage path of an OTP memory device from a gate dielectric layer of a gate structure to an interlayer dielectric layer (ILD layer) between a gate contact and a source / drain contact. By implanting the ILD layer with a dopant such as germanium or tin, the methods of the present disclosure can lower the breakdown voltage of the ILD layer to a level lower than the breakdown voltage of the gate dielectric layer. The leakage path of the ILD layer between the gate contact and the source / drain contact can allow a programming voltage of about between 2V and 3V. The use of a lower programming voltage by the present disclosure can reduce power consumption and increase yield as compared to the higher programming voltage required for breakdown of the gate dielectric layer. Additionally, a leakage component can be formed in the ILD layer between the gate contact and the source / drain contact upon application of the programming voltage. The leakage component can include materials found in the gate contact or the source / drain contact.

[0091] Accordingly, in an aspect, the present disclosure provides a semiconductor device, comprising: a gate structure; a source / drain component adjacent to the gate structure; a dielectric layer disposed over the gate structure and the source / drain component; a gate contact disposed in the dielectric layer and over the gate structure; a source / drain contact disposed in the dielectric layer and over the source / drain component; wherein the dielectric layer is doped with a dopant; wherein the dopant comprises germanium or tin.

[0092] In some embodiments, the concentration of the dopant in the dielectric layer is about between 5 x 1019atoms / cubic centimeter and 1 x 1021atoms / cubic centimeter. 14 1 x 1021atoms / cubic centimeter. 15between 2V and 3V. In some embodiments, the gate structure includes a gate dielectric layer; a breakdown voltage of the gate dielectric layer is greater than a breakdown voltage of the dielectric layer between the gate contact and the source / drain contact. In some embodiments, the semiconductor device further includes a leakage path between the gate contact and the source / drain contact, wherein the leakage path electrically couples the gate contact and the source / drain contact. In some embodiments, the leakage path physically extends through a portion of the dielectric layer. In some embodiments, the leakage path includes a material of the gate contact or a material of the source / drain contact. In some embodiments, the dielectric layer includes Tetraethyl orthosilicate (TEOS) oxide, Undoped Silicate Glass (USG), Borophosphosilicate Glass (BPSG), Fluorosilicate Glass (FSG), Phosphosilicate Glass (PSG), or Boron Doped Silicon Glass (BSG).

[0093] In another aspect, the disclosure provides a One-Time Programmable (OTP) memory device, comprising: an active region; a first gate structure and a second gate structure over the active region; a dielectric layer over the first gate structure and the second gate structure; a first source / drain contact between the first gate structure and the second gate structure; a second source / drain contact separated from the first source / drain contact by the second gate structure; a first gate contact over the first gate structure and electrically coupled to the first gate structure; wherein a portion of the first source / drain contact, a portion of the second source / drain contact, and the first gate contact are disposed within the dielectric layer; wherein the dielectric layer is doped with a dopant; wherein the dopant includes germanium or tin.

[0094] In some embodiments, a concentration of the dopant in the dielectric layer is between 5x10 14 between 1x10 15between about 2 V and 3 V. In some embodiments, the second source / drain contact is coupled to a bit line by a source / drain contact via. In some embodiments, the memory device further includes a leakage path between the first gate contact and the first source / drain contact, and a second gate contact disposed over the second gate structure and electrically coupled to the second gate structure, wherein the second gate contact is disposed within the dielectric layer, and wherein a portion of the dielectric layer between the second gate contact and the first source / drain contact does not include a leakage path. In some embodiments, the first gate contact is coupled to a program bit line, the second gate contact is coupled to a read bit line, the first gate structure and the second gate structure extend longitudinally along a first direction, and the program bit line and the read bit line extend longitudinally along a second direction, wherein the second direction is perpendicular to the first direction.

[0095] In another aspect, the disclosure provides a method of manufacturing a semiconductor device, including the operations of receiving a workpiece, wherein the workpiece includes a dielectric layer, a gate contact disposed in the dielectric layer, and a source / drain contact disposed in the dielectric layer adjacent to the gate contact, and after receiving the workpiece, implanting the dielectric layer with a dopant.

[0096] In some embodiments, the dopant is an element from Group 4A of the periodic table. In some embodiments, the dopant includes germanium or tin. In some embodiments, the implantation procedure of the dielectric layer reduces a breakdown voltage of the dielectric layer between the gate contact and the source / drain contact. In some embodiments, the dopant concentration of the dielectric layer is between about 5 x 1019 atoms / cm2and 1 x 1021atoms / cm2. 14 and 1 x 1021atoms / cm2. 15 In some embodiments, the implantation procedure of the dielectric layer includes an implantation energy between about 5 keV and 30 keV.

[0097] The foregoing outlines features of many embodiments so that those skilled in the art can better understand the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a gate structure; a source / drain component adjacent to the gate structure; a dielectric layer disposed over the gate structure and the source / drain component; a gate contact disposed in the dielectric layer and over the gate structure; a source / drain contact disposed in the dielectric layer and over the source / drain component; and a leakage path between the gate contact and the source / drain contact, wherein the leakage path electrically couples the gate contact and the source / drain contact; wherein the dielectric layer is doped with a dopant; wherein the dopant comprises germanium or tin.

3. The semiconductor device of claim 1, wherein a breakdown voltage of the dielectric layer between the gate contact and the source / drain contact is approximately between 2V and 3V.

2. The semiconductor device of claim 1, wherein the concentration of the dopant in the dielectric layer is between about 5 x 1010 atoms / cm3 and 1 x 1011 atoms / cm3. 14 15 atoms / cm3.​ 4. The semiconductor device of claim 1, wherein: the gate structure comprises a gate dielectric layer; a breakdown voltage of the gate dielectric layer is greater than a breakdown voltage of the dielectric layer between the gate contact and the source / drain contact.

5. The semiconductor device of claim 1, wherein the leakage path physically extends through a portion of the dielectric layer.

6. The semiconductor device of claim 1, wherein the leakage path comprises a material of the gate contact or a material of the source / drain contact.

7. The semiconductor device of claim 1, wherein the dielectric layer comprises tetraethyl orthosilicate oxide, undoped silicate glass, borophosphosilicate glass, fluorosilicate glass, phosphosilicate glass, or borosilicate glass.

8. A one-time programmable memory device, comprising: an active region; a first gate structure and a second gate structure over the active region; a dielectric layer disposed over the first gate structure and the second gate structure; a first source / drain contact disposed between the first gate structure and the second gate structure; a second source / drain contact separated from the first source / drain contact by the second gate structure; a first gate contact disposed over the first gate structure and electrically coupled to the first gate structure; and a leakage path between the first gate contact and the first source / drain contact, wherein the leakage path electrically couples the first gate contact and the first source / drain contact; wherein a portion of the first source / drain contact, a portion of the second source / drain contact, and the first gate contact are disposed within the dielectric layer; wherein the dielectric layer is doped with a dopant; wherein the dopant comprises germanium or tin.

10. The one-time programmable memory device of claim 8, wherein a breakdown voltage of the dielectric layer between the first gate contact and the first source / drain contact is approximately between 2V and 3V.

11. The one-time programmable memory device of claim 8, wherein the second source / drain contact is coupled to a bit line by a source / drain contact via.

9. The one-time programmable memory device of claim 8, wherein the concentration of the dopant in the dielectric layer is between about 5 x 1016 atoms per cubic centimeter and 1 x 1018 atoms per cubic centimeter. 14 15 atoms per cubic centimeter and 1 x 1018 atoms per cubic centimeter.​ 12. The one-time programmable memory device of claim 8, further comprising: ​ ​ a second gate contact disposed over the second gate structure and electrically coupled to the second gate structure; wherein the second gate contact is disposed within the dielectric layer; wherein a portion of the dielectric layer between the second gate contact and the first source / drain contact does not include a leakage path.

13. The one-time programmable memory device of claim 12, wherein: the first gate contact is coupled to a program word line; the second gate contact is coupled to a read word line; the first gate structure and the second gate structure extend longitudinally along a first direction; the program word line and the read word line extend longitudinally along a second direction, wherein the second direction is perpendicular to the first direction.

14. A method of fabricating a semiconductor device, comprising operations of: receiving a workpiece, wherein the workpiece comprises: a gate structure comprising a gate dielectric layer; a dielectric layer over the gate structure; a gate contact disposed in the dielectric layer, the gate contact physically and electrically coupled to the gate structure; and a source / drain contact adjacent to the gate contact and disposed in the dielectric layer; after receiving the workpiece, implanting a dopant into the dielectric layer; and applying a voltage to the gate contact to form a leakage path through the dielectric layer, wherein the leakage path is between the gate contact and the source / drain contact and electrically couples the gate contact and the source / drain contact.

15. The method of claim 14, wherein the dopant is an element of Group 4A of the periodic table.

16. The method of claim 14, wherein the dopant comprises germanium or tin.

17. The method of claim 14, wherein the implanting procedure of the dielectric layer reduces a breakdown voltage of the dielectric layer between the gate contact and the source / drain contact.

18. The method of claim 14, wherein the doping concentration of the dielectric layer is between about 5 x 1010 atoms / cm3 and 1 x 1011 atoms / cm3. 14 15 atoms / cm3 and 1 x 1011 atoms / cm3.​ 19. The method of claim 14, wherein the implanting procedure of the dielectric layer comprises an implant energy between about 5 keV and 30 keV.

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