A subthreshold boost circuit based on positive and negative clock generation circuit

Abstract

The present invention discloses a subthreshold boost circuit based on a positive and negative clock generating circuit, which is composed of a ring oscillator, a buffer differential circuit, two positive and negative clock generating circuits, a charge pump and a rectifier circuit. In a conventional gate cross-coupled boost circuit, the clock signal output from the buffer differential circuit is directly used as the control clock of a three-stage cross-coupled charge pump. The present invention designs a positive and negative voltage clock generating circuit to dynamically bias the substrate of the NMOS tube in the charge pump when it is working and shutting down, and the substrate of the PMOS tube in the charge pump is biased by the output of the rectifier circuit, thereby reducing the loss of the transistor in forward conduction and reverse conduction, and improving the boost effect.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a subthreshold boosting circuit based on a positive and negative clock generating circuit. Background Art

[0002] The subthreshold boost circuit is a key module of the low-voltage self-starting circuit in energy harvesting and an important prerequisite for the miniaturization and self-powering of wearable electronic devices. Miniaturization, low power consumption and self-powering are one of the important trends in the development of wearable electronic devices in the future. This requires not only breakthroughs in sensor technology, but also breakthroughs in self-powered energy harvesting technology when the battery capacity is limited. At the same time, self-powering may also become a way to replace battery power. Since most modules in current electronic devices require higher voltages to work properly, the subthreshold boost circuit has become one of the hot research directions in self-powered energy harvesting technology.

[0003] Common types of boost circuits in integrated circuits include switched capacitor boost circuits and switched inductor boost circuits. Compared with switched inductor boost circuits, switched capacitor boost circuits are a better choice due to their simple circuit principles, small layout area, and easy control circuit implementation. However, the gate cross-coupled charge pump commonly used in switched capacitor boost circuits currently requires multiple stages to boost to a higher voltage, which will increase the chip area and cost, so the boost effect needs to be improved urgently. Summary of the invention

[0004] The present invention aims to solve the problem that the currently commonly used gate cross-coupled charge pump requires multiple stages to boost to a higher voltage, which will lead to an increase in chip area and an increase in cost, and provides a subthreshold boost circuit based on a positive and negative clock generation circuit.

[0005] To solve the above problems, the present invention is achieved through the following technical solutions:

[0006] A subthreshold boost circuit based on a positive and negative clock generating circuit comprises a subthreshold boost circuit body, wherein the subthreshold boost circuit is composed of a ring oscillator, a buffer differential circuit, two positive and negative clock generating circuits, a charge pump and a rectifier circuit; the first positive and negative clock generating circuit is composed of a PMOS tube MP1, a capacitor C1, a PMOS tube MP11 and an NMOS tube MN7; the second positive and negative clock generating circuit is composed of a PMOS tube MP2, a capacitor C2, a PMOS tube MP12 and an NMOS tube MN8; the output terminal OUT of the ring oscillator is connected to the input terminal of the buffer differential circuit. The differential clock output terminal CLKA of the buffer differential circuit is connected to the gate of the PMOS tube MP1 of the first positive and negative clock generating circuit, the gate of the PMOS tube MP11 and the gate of the NMOS tube MN7, and the upper plate of the capacitor C2 of the second positive and negative clock generating circuit; the differential clock output terminal CLKB of the buffer differential circuit is connected to the gate of the PMOS tube MP2 of the second positive and negative clock generating circuit, the gate of the PMOS tube MP12 and the gate of the NMOS tube MN8, and the upper plate of the capacitor C1 of the first positive and negative clock generating circuit; the source of the PMOS tube MP11 is connected to the substrate The power supply VDD, the source and substrate of the PMOS tube MP1 are grounded; the lower plate of the capacitor C1 is connected to the drain of the PMOS tube MP1, and the source and substrate of the NMOS tube MN7; the drain of the PMOS tube MP11 and the drain of the NMOS tube MN7 are connected and then connected as the output end of the first positive and negative clock generating circuit to the substrate input end Nbulk1 and the clock input end UPCLK of the charge pump; the source and substrate of the PMOS tube MP12 are connected to the power supply VDD, and the source and substrate of the PMOS tube MP2 are grounded; the lower plate of the capacitor C2 is connected to the drain of the PMOS tube MP2, and The source of the NMOS tube MN8 is connected to the substrate; the drain of the PMOS tube MP12 and the drain of the NMOS tube MN8 are connected and then connected to the substrate input terminal Nbulk2 and the clock input terminal DOWNCLK of the charge pump as the output terminal of the second positive and negative clock generating circuit; the input terminal CPIN of the charge pump is connected to the power supply VDD; the output terminals CPOUT1 and CPOUT2 of the charge pump are respectively connected to the input terminals IN1 and IN2 of the rectifier circuit; the output terminal OUT of the rectifier circuit is connected to the substrate input terminal Pbulk of the charge pump and serves as the output terminal of the subthreshold boost circuit body.

[0007] In the above scheme, the ring oscillator adopts a stacked inverter circuit.

[0008] In the above scheme, the buffer differential circuit is composed of a buffer chain module and a differential clock module; the input end of the buffer chain module serves as the input end IN of the buffer differential circuit, the output end of the buffer chain module is connected to the input end of the differential clock module, and the two output ends of the differential clock module serve as the differential clock output ends CLKA and CLKB of the buffer differential circuit respectively.

[0009] In the above scheme, the differential clock signals outputted from the output terminals CLKA and CLKB of the buffer differential circuit have opposite phases and equal amplitudes.

[0010] In the above scheme, the charge pump is formed by cascading three-stage charge pump modules; the first-stage charge pump module is composed of NMOS tube MN1, NMOS tube MN2, PMOS tube MP3, PMOS tube MP4, capacitor C3 and capacitor C4; the second-stage charge pump module is composed of NMOS tube MN3, NMOS tube MN4, PMOS tube MP5, PMOS tube MP6, capacitor C5 and capacitor C6; the third-stage charge pump module is composed of NMOS tube MN5, NMOS tube MN6, PMOS tube MP7, PMOS tube MP8, capacitor C7 and capacitor C8; the substrate of NMOS tube MN1, the substrate of NMOS tube MN3 and the substrate of NMOS tube MN5 are connected and serve as the substrate input terminal Nbul of the charge pump. k1; the substrates of the NMOS tube MN2, the NMOS tube MN4 and the NMOS tube MN6 are connected as the substrate input terminal Nbulk2 of the charge pump; the substrates of the PMOS tube MP3, the PMOS tube MP4, the PMOS tube MP5, the PMOS tube MP6, the PMOS tube MP7 and the PMOS tube MP8 are connected as the substrate input terminal Pbulk of the charge pump; the upper plate of the capacitor C3, the upper plate of the capacitor C5 and the upper plate of the capacitor C7 are connected as the clock input terminal UPCLK of the charge pump; the lower plate of the capacitor C4, the lower plate of the capacitor C6 and the lower plate of the capacitor C8 are connected as the clock input terminal DOWNCLK of the charge pump; The source of the OS transistor MN1 is connected to the source of the NMOS transistor MN2 and serves as the input terminal CPIN of the charge pump; the lower plate of the capacitor C3, the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3, the gate of the NMOS transistor MN2 and the gate of the PMOS transistor MP4 are connected; the upper plate of the capacitor C4, the drain of the NMOS transistor MN2, the drain of the PMOS transistor MP4, the gate of the NMOS transistor MN1 and the gate of the PMOS transistor MP3 are connected; the source of the PMOS transistor MP3, the source of the PMOS transistor MP4, the source of the NMOS transistor MN3 and the source of the NMOS transistor MN4 are connected; the lower plate of the capacitor C5, the drain of the NMOS transistor MN3, the drain of the PMOS transistor MP5, the NMOS transistor MN The gate of capacitor C4 is connected to the gate of PMOS tube MP6; the upper plate of capacitor C6, the drain of NMOS tube MN4, the drain of PMOS tube MP6, the gate of NMOS tube MN3 and the gate of PMOS tube MP5 are connected; the source of PMOS tube MP5, the source of PMOS tube MP6, the source of NMOS tube MN5 and the source of NMOS tube MN6 are connected; the lower plate of capacitor C7, the drain of NMOS tube MN5, the drain of PMOS tube MP7, the gate of NMOS tube MN6 and the gate of PMOS tube MP8 are connected; the upper plate of capacitor C8, the drain of NMOS tube MN6, the drain of PMOS tube MP8, the gate of NMOS tube MN5 and the gate of PMOS tube MP7 are connected;The source of the PMOS tube MP7 serves as the output terminal CPOUT1 of the charge pump; the source of the PMOS tube MP8 serves as the output terminal CPOUT2 of the charge pump.

[0011] In the above scheme, the rectifier circuit is composed of a PMOS tube MP9 and a PMOS tube MP10; the gate of the PMOS tube MP10 and the source of the PMOS tube MP9 are connected to the substrate and serve as the input terminal IN1 of the rectifier circuit; the gate of the PMOS tube MP9 and the source of the PMOS tube MP10 are connected to the substrate and serve as the input terminal IN2 of the rectifier circuit; the drain of the PMOS tube MP9 and the drain of the MOS tube MP10 are connected and serve as the output terminal OUT of the rectifier circuit.

[0012] Compared with the prior art, the present invention has the following characteristics:

[0013] 1. The positive and negative clock generating circuits are combined with the charge pump, the clock voltage of the charge pump is increased by the positive and negative clock generating circuits, and the loss is reduced by biasing the positive and negative clock generating circuits to the substrate. Compared with the traditional three-stage gate cross-coupled charge pump, the present invention can obtain a higher output voltage.

[0014] 2. The positive and negative clock generation circuits are combined with the charge pump to achieve the same output voltage. The traditional gate cross-coupled charge pump requires five stages in series, while the present invention only requires three stages, which is more energy efficient and saves chip layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The schematic diagram is a principle block diagram of a subthreshold boost circuit based on a positive and negative clock generation circuit.

[0016] Figure 2 The figure is a transistor-level implementation schematic diagram of a subthreshold boost circuit based on a positive and negative clock generation circuit.

[0017] Figure 3 This is a comparison diagram of the boosting effect of the boosting circuit proposed by the present invention and the traditional gate cross-coupled boosting circuit. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0019] A subthreshold boost circuit based on a positive and negative clock generating circuit, such as Figure 1As shown, it is composed of a ring oscillator, a buffer differential circuit, two positive and negative clock generating circuits, a charge pump and a rectifier circuit. The power supply is connected to the power supply terminal VDD of the ring oscillator, the power supply terminal VDD of the buffer differential circuit, the power supply terminal VDD of the first positive and negative clock generating circuit, the power supply terminal VDD of the second positive and negative clock generating circuit and the input terminal CPIN of the charge pump. The output OUT of the ring oscillator is connected to the input terminal IN of the buffer differential circuit. The output terminals CLKA and CLKB of the buffer differential circuit generate a pair of differential clock signals CLKA and CLKB with opposite phases and equal amplitudes. The differential clock signal CLKA is connected to the gate of the PMOS tube MP1 in the first positive and negative clock generating circuit, the gate of the PMOS tube MP11 and the NMOS tube MN7, and the upper plate of the capacitor C2 in the second positive and negative clock generating circuit. The differential clock signal CLKB is connected to the gate of the PMOS tube MP2 in the second positive and negative clock generating circuit, the gate of the PMOS tube MP12 and the NMOS tube MN8, and the upper plate of the capacitor C1 in the first positive and negative clock generating circuit. The lower plate of capacitor C1 in the first positive and negative clock generating circuit is connected to the drain of PMOS tube MP1, and generates a first square wave signal with a low level of -VDD and a high level of 0, and the first square wave signal is sent to the source and substrate of NMOS tube MN7. The drain of PMOS tube MP11 in the first positive and negative clock generating circuit is connected to the drain of NMOS tube MN7 and serves as the output end of the first positive and negative clock generating circuit, and the output end is connected to the substrate input end Nbulk1 of the charge pump and the clock input end UPCLK of the charge pump. The lower plate of capacitor C2 in the second positive and negative clock generating circuit is connected to the drain of PMOS tube MP2, and generates a second square wave signal with a low level of -VDD and a high level of 0, and the second square wave signal is sent to the source and substrate of NMOS tube MN8. The drain of PMOS tube MP12 in the second positive and negative clock generating circuit is connected to the drain of NMOS tube MN8 and serves as the output end of the second positive and negative clock generating circuit, and the output end is connected to the substrate input end Nbulk2 of the charge pump and the clock input end DOWNCLK. The output terminals CPOUT1 and CPOUT2 of the charge pump are connected to the input terminals IN1 and IN2 of the rectifier circuit respectively. The output terminal OUT of the rectifier circuit is connected to the substrate input terminal Pbulk of the charge pump. The output terminal OUT of the rectifier circuit is also the final output of the boost circuit.

[0020] The ring oscillation circuit provides a clock signal, and the clock signal passes through a buffer differential circuit to generate a pair of clock signals with opposite phases and equal amplitudes as control signals for the positive and negative clock generation circuits. The control signal acts on the positive and negative clock generation circuits to generate corresponding positive and negative clock bias voltages. The charge pump uses the bias voltage as the clock signal and the substrate bias voltage to complete the voltage boost, and finally the boosted voltage is output through the rectifier circuit. When the first positive and negative clock generation circuit is working, the PMOS tube is turned on, the lower plate of the capacitor C1 is grounded, and the upper plate of the capacitor C1 is charged to the high level of the clock signal. At this time, Vc=V 上 -V 下 = VDD. In the off phase of the PMOS tube, the upper plate of the capacitor is connected to the low level of the clock signal. Since the voltage across the capacitor C1 will not change suddenly, the voltage of the lower plate of the capacitor C1 is V 下 =V 上 -Vc = -VDD, thus generating negative voltage. At the same time, due to the periodic on and off of the PMOS tube, the negative voltage is a square wave signal. The generated negative voltage square wave signal and VDD are respectively input into the selection circuit of the inverter structure composed of MN7 and MP11, and a positive and negative voltage square wave with the same sequence as CLKA / CLKB can be obtained. In the positive and negative clock generation circuit, the gate of the NMOS tube is connected to the gate of the PMOS tube and is connected to the corresponding clock signal, the drain of the NMOS tube is connected to the drain of the PMOS tube, the source of the PMOS tube is connected to VDD, and the source of the NMOS tube is connected to the output of the negative voltage circuit. When the clock signal of the gate is high, the NMOS tube is turned on and the PMOS tube is turned off, and the negative voltage is output; when the clock signal of the gate is low, the PMOS tube is turned on and the NMOS tube is turned on, and VDD is output. The working principle of the second positive and negative clock signal generation circuit is similar to that of the first positive and negative clock generation circuit. In the traditional gate cross-coupled boost circuit, the clock signal output from the buffer differential circuit is directly used as the control clock of the three-stage cross-coupled charge pump. The present invention designs a positive and negative voltage clock generating circuit to dynamically bias the substrate of the NMOS tube in the charge pump when it is working and shutting down. The substrate of the PMOS tube in the charge pump is biased by the output of the rectifier circuit, thereby reducing the forward conduction and reverse conduction losses of the transistor and improving the boosting effect.

[0021] Figure 2 The invention is a transistor-level implementation schematic diagram of a subthreshold boost circuit based on a positive and negative clock generation circuit, including a ring oscillator, a buffer differential circuit, two positive and negative clock generation circuits, a charge pump and a rectifier circuit.

[0022] The ring oscillator adopts a stacked inverter circuit. The power supply terminal of the ring oscillator is connected to the power supply VDD, and the ground terminal is connected to the ground GND.

[0023] The buffer differential circuit consists of two modules: a buffer chain and a differential clock. The power supply end of the buffer chain module and the differential clock module is connected to the power supply VDD, and the ground end is connected to the ground GND. The output end of the ring oscillator is connected to the input end of the buffer chain module, and the input end of the buffer chain module serves as the input end IN of the buffer differential circuit. The output end of the buffer chain module is connected to the input end of the differential clock module. The 2 output ends of the differential clock module serve as the differential clock output ends CLKA and CLKB of the buffer differential circuit, generating a pair of differential clock signals CLKA and CLKB with opposite phases and equal amplitudes.

[0024] The first positive and negative clock generating circuit is composed of a PMOS tube MP1, a capacitor C1, a PMOS tube MP11 and an NMOS tube MN7. The gate of the PMOS tube MP1 is connected to the CLKA signal. The source and substrate of the PMOS tube MP1 are connected to the ground GND. The drain of the PMOS tube MP11, the lower plate of C1 and the drain of the PMOS tube MP1 are connected to generate a first square wave signal with a low level of -VDD and a high level of 0, and the first square wave signal is sent to the source and substrate of the NMOS tube MN7. The differential clock output terminal CLKB of the buffer differential circuit is connected to the upper plate of the capacitor C1 in the first positive and negative clock circuit. The gate of the PMOS tube MP11 is connected to the gate of the NMOS tube MN7 and connected to the differential clock output terminal CLKA. The source and substrate of the PMOS tube MP11 are connected to the power supply. The drain of the PMOS tube MP11 is connected to the drain of the NMOS tube MN7 and serves as the output terminal of the first positive and negative clock generating circuit, and the output terminal is connected to the input terminal Nbulk1 and the input terminal UPCLK of the charge pump.

[0025] The second positive and negative clock generating circuit is composed of a PMOS tube MP2, a capacitor C2, a PMOS tube MP12 and an NMOS tube MN8. The output CLKB of the differential clock is connected to the gate of the PMOS tube MP2. The source and substrate of the PMOS tube MP2 are connected to the ground GND. The drain of the PMOS tube MP2, the lower plate of C2 and the drain of the PMOS tube MP2 are connected to generate a second square wave signal with a low level of -VDD and a high level of 0 (opposite to the phase of the first square wave signal), and the second square wave signal is sent to the source and substrate of the NMOS tube MN8. The differential clock output terminal CLKA of the buffer differential circuit is connected to the upper plate of the capacitor C2 in the second positive and negative clock circuit. The gate of the PMOS tube MP12 is connected to the gate of the NMOS tube MN8 and is connected to the differential clock output terminal CLKB. The source of the PMOS tube MP12 is connected to the substrate and is connected to the power supply VDD. The drain of the PMOS tube MP12 and the drain of the NMOS tube MN8 are connected to serve as the output end of the second positive and negative clock generating circuit, and the output end is connected to the substrate input end Nbulk2 of the charge pump and the clock input end DOWNCLK.

[0026] The charge pump is formed by cascading three-stage charge pump modules. The first-stage charge pump module is composed of NMOS tube MN1, NMOS tube MN2, PMOS tube MP3, PMOS tube MP4, capacitor C3 and capacitor C4. The second-stage charge pump module is composed of NMOS tube MN3, NMOS tube MN4, PMOS tube MP5, PMOS tube MP6, capacitor C5 and capacitor C6. The third-stage charge pump module is composed of NMOS tube MN5, NMOS tube MN6, PMOS tube MP7, PMOS tube MP8, capacitor C7 and capacitor C8. The substrate of NMOS tube MN1, the substrate of NMOS tube MN3 and the substrate of NMOS tube MN5 are connected to serve as the substrate input terminal Nbulk1 of the charge pump. The substrate of NMOS tube MN2, the substrate of NMOS tube MN4 and the substrate of NMOS tube MN6 are connected to serve as the substrate input terminal Nbulk2 of the charge pump. The substrate of the PMOS tube MP3, the substrate of the PMOS tube MP4, the substrate of the PMOS tube MP5, the substrate of the PMOS tube MP6, the substrate of the PMOS tube MP7, and the substrate of the PMOS tube MP8 are connected to serve as the substrate input terminal Pbulk of the charge pump. The upper plate of the capacitor C3, the upper plate of the capacitor C5, and the upper plate of the capacitor C7 are connected to serve as the clock input terminal UPCLK of the charge pump. The lower plate of the capacitor C4, the lower plate of the capacitor C6, and the lower plate of the capacitor C8 are connected to serve as the clock input terminal DOWNCLK of the charge pump. The source of the NMOS tube MN1 and the source of the NMOS tube MN2 are connected to serve as the input terminal CPIN of the charge pump. The lower plate of the capacitor C3, the drain of the NMOS tube MN1, the drain of the PMOS tube MP3, the gate of the NMOS tube MN2, and the gate of the PMOS tube MP4 are connected. The upper plate of capacitor C4, the drain of NMOS tube MN2, the drain of PMOS tube MP4, the gate of NMOS tube MN1 and the gate of PMOS tube MP3 are connected. The source of PMOS tube MP3, the source of PMOS tube MP4, the source of NMOS tube MN3 and the source of NMOS tube MN4 are connected. The lower plate of capacitor C5, the drain of NMOS tube MN3, the drain of PMOS tube MP5, the gate of NMOS tube MN4 and the gate of PMOS tube MP6 are connected. The upper plate of capacitor C6, the drain of NMOS tube MN4, the drain of PMOS tube MP6, the gate of NMOS tube MN3 and the gate of PMOS tube MP5 are connected. The source of PMOS tube MP5, the source of PMOS tube MP6, the source of NMOS tube MN5 and the source of NMOS tube MN6 are connected. The lower plate of capacitor C7, the drain of NMOS tube MN5, the drain of PMOS tube MP7, the gate of NMOS tube MN6 and the gate of PMOS tube MP8 are connected. The upper plate of capacitor C8, the drain of NMOS tube MN6, the drain of PMOS tube MP8, the gate of NMOS tube MN5 and the gate of PMOS tube MP7 are connected.The source of the PMOS transistor MP7 serves as the output terminal CPOUT1 of the charge pump. The source of the PMOS transistor MP8 serves as the output terminal CPOUT2 of the charge pump.

[0027] The rectifier circuit is composed of a PMOS tube MP9 and a PMOS tube MP10. The gate of the PMOS tube MP10 and the source of the PMOS tube MP9 are connected to the substrate as the input terminal IN1 of the rectifier circuit; the gate of the PMOS tube MP9 and the source of the PMOS tube MP10 are connected to the substrate as the input terminal IN2 of the rectifier circuit; the drain of the PMOS tube MP9 and the drain of the MOS tube MP10 are connected as the output terminal OUT of the rectifier circuit.

[0028] The working principle of the present invention is:

[0029] The 200mV DC power supply voltage generated by environmental energy new energy batteries such as wearable solar cells and thermoelectric batteries is connected to the power supply end of the ring oscillator, and the differential clock signals CLKA and CLKB are generated through the buffer differential circuit. The two clock signals are then sent to the positive and negative clock generation circuit to generate square wave differential clock signals UPCLK and DOWNCLK with a high level of VDD and a low level of -VDD / 2. The two inverted clock control gates are cross-coupled to work with the charge pump, so that the output end VOUT voltage of the three-stage charge pump is 1.2V. In the present invention, a stacked inverter structure is used to ensure that the ring oscillator works normally at a power supply voltage as low as 200mV. At a low power supply voltage, a larger output swing is obtained at the cost of reducing the switching speed.

[0030] In the traditional gate cross-coupled boost circuit, the clock signal output from the buffer differential circuit is directly used as the control clock of the three-stage cross-coupled charge pump. Now let's analyze the first stage of the cross-coupled charge pump in detail. Initially, there is no charge accumulation in capacitor C3, and the voltage difference across the capacitor is zero. ① When CLKA is low, CLKB is high, NMOS tube MN1 is turned on, and PMOS tube MP3 is turned off; the conduction of MN1 will transfer charge from the input end to the C3 capacitor, and the voltage difference across the capacitor plate is an input voltage Vin = 200mV② When CLKA is high and CLKB is low. MN1 is turned off and MP3 is turned on; the voltage on the upper plate of capacitor C3 is 200mV, and capacitor C3 has no discharge path, so the voltage cannot change suddenly, so the voltage on the lower plate of the capacitor becomes Vin plus a clock signal amplitude ΔVDD (Vin+ΔVDD). At the same time, because M17 is turned on, the lower plate of C3 (400mV at this time) is transmitted to the next stage through MP3 to charge the subsequent circuit. In the 180nm CMOS process simulation experiment, after the cross-coupling of the upper and lower parts, the voltage at the first-stage output (i.e., the second-stage input) is 400mV. Finally, after three stages of step-by-step voltage boosting, the charge pump output VOUT is 787mV, close to the theoretical value of 800mV.

[0031] On this basis, the losses caused by the cross-coupled charge pump are analyzed. The losses mainly include reverse feedthrough loss and conduction loss caused by the back-gate effect of the actual MOS tube. (1) The reverse feedthrough loss is because the low level on the gate is not strictly zero voltage in the stage when the MOS tube should be turned off, which will cause subthreshold current leakage in the MOS tube and not completely turn off. There is leakage current and leakage voltage between the source and the drain, causing the charge to flow back to the previous level. This loss becomes weaker and the loss becomes greater as the number of charge pump levels increases. (2) Due to the back-gate effect of the actual MOS tube, there is a difference between the substrate voltage and the source voltage in the MOS tube, which causes losses to the circuit. For example, in the common process, the substrate of the NMOS tube is a P-type semiconductor material. Assuming that the source-drain voltage is 0, and in the present invention, the MOS tube operates under subthreshold conditions, the gate-source voltage V GS If the voltage is less than the threshold voltage Vth, a depletion layer will be formed at the interface below the gate SiO2. The size of the substrate voltage will affect the characteristics of the depletion layer, thereby affecting the threshold voltage. According to the threshold voltage formula:

[0032]

[0033] It can be seen that Q dep It is one of the important factors affecting Vt, and the PMOS tube also has a similar phenomenon. In the usual MOS integrated circuit design and application, considering the circuit symmetry and back gate effect, the NMOS substrate is often connected to each input level, and the PMOS is connected to each output level.

[0034] According to the above analysis, the present invention designs a positive and negative voltage clock generation circuit to dynamically bias the substrate of the NMOS tube in the charge pump when it is working and shutting down. When the NMOS tube needs to work logically, a voltage greater than 0 is input to the substrate to reduce the voltage difference between the substrate and the source, thereby reducing the threshold voltage of the NMOS tube and reducing the forward conduction loss; when the NMOS tube needs to be shut down logically, a voltage less than 0 is input to the substrate to increase the voltage difference between the substrate and the source, thereby increasing its threshold voltage and reducing the loss caused by reverse conduction. All PMOS substrates are connected to the highest potential in the circuit, that is, connected to the output of the rectifier circuit in the present invention. The positive and negative clock generation circuit includes a negative voltage circuit module, the negative voltage circuit module of the first positive and negative clock generation circuit is composed of a PMOS tube MP1 and a capacitor C1, and the negative voltage circuit module of the second positive and negative clock generation circuit is composed of a PMOS tube MP2 and a capacitor C2. The gate of the PMOS tube of the negative voltage circuit module is connected to one of the clock signals, the source and drain of the PMOS tube are connected to the ground and the lower plate of the capacitor respectively, and the upper plate of the capacitor is connected to a signal that is inverted to the above clock signal. When the negative voltage circuit module is working, the PMOS tube is turned on, the lower plate of the capacitor is grounded, and the upper plate of the capacitor is charged to the high level of the clock signal. At this time, Vc=V 上 -V 下 = VDD. In the off phase of the PMOS tube, the upper plate of the capacitor is connected to the low level of the clock signal. Since the voltage across the capacitor will not change suddenly, the voltage of the lower plate of the capacitor is V 下 =V 上-Vc=-VDD, thus generating negative voltage. At the same time, due to the periodic on and off of the PMOS tube, the negative voltage is a square wave signal. The negative voltage square wave signal generated by the first positive and negative clock generation circuit and VDD are respectively input into the selection circuit of the inverter structure composed of MN7 and MP11, and the positive and negative voltage square waves with the same sequence as CLKA and CLKB can be obtained. The negative voltage square wave signal generated by the second positive and negative clock generation circuit and VDD are respectively input into the selection circuit of the inverter structure composed of MN8 and MP12, and the positive and negative voltage square waves with the same sequence as CLKA and CLKB can be obtained. This signal has the same clock cycle as CLKA and CLKB, so it can be used as the control clock of the cross-coupled electric pump at the same time. In the traditional circuit without dynamic substrate bias, the three-stage traditional cross-coupled charge pump circuit directly uses the clock of the buffer differential circuit for control, and can only output 787mV voltage; the three-stage traditional cross-coupled charge pump circuit uses the buffer differential circuit and the positive and negative clock generation circuit for clock control, but does not perform substrate dynamic bias, and can only obtain an output of 984mV. After combining with dynamic substrate bias, it can be seen from the simulation results that, with the same three-stage cross-coupled charge pump, the circuit of the present invention can finally generate an output voltage of 1.19V. The traditional gate cross-coupled charge pump needs 5-stage charge pumps to increase the voltage to 1.19V. The present invention saves layout area and greatly improves the boosting effect. Figure 3 This is a comparison diagram of the boosting effect of the boosting circuit proposed by the present invention and the traditional gate cross-coupled boosting circuit.

[0035] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A subthreshold boost circuit based on a positive and negative clock generating circuit, comprising a subthreshold boost circuit body, characterized in that: The subthreshold boost circuit is composed of a ring oscillator, a buffer differential circuit, two positive and negative clock generating circuits, a charge pump and a rectifier circuit; the first positive and negative clock generating circuit is composed of a PMOS tube MP1, a capacitor C1, a PMOS tube MP11 and an NMOS tube MN7; the second positive and negative clock generating circuit is composed of a PMOS tube MP2, a capacitor C2, a PMOS tube MP12 and an NMOS tube MN8; The output terminal OUT of the ring oscillator is connected to the input terminal IN of the buffer differential circuit; The differential clock output terminal CLKA of the buffer differential circuit is connected to the gate of the PMOS transistor MP1, the PMOS transistor MP11 and the gate of the NMOS transistor MN7 of the first positive and negative clock generating circuit, and the upper plate of the capacitor C2 of the second positive and negative clock generating circuit; The differential clock output terminal CLKB of the buffer differential circuit is connected to the gate of the PMOS transistor MP2, the PMOS transistor MP12 and the gate of the NMOS transistor MN8 of the second positive and negative clock generating circuit, and the upper plate of the capacitor C1 of the first positive and negative clock generating circuit; The source and substrate of the PMOS tube MP11 are connected to the power supply VDD, and the source and substrate of the PMOS tube MP1 are grounded; the lower plate of the capacitor C1 is connected to the drain of the PMOS tube MP1, and the source and substrate of the NMOS tube MN7; the drain of the PMOS tube MP11 and the drain of the NMOS tube MN7 are connected and then connected as the output end of the first positive and negative clock generating circuit to the substrate input end Nbulk1 and the clock input end UPCLK of the charge pump; The source and substrate of the PMOS tube MP12 are connected to the power supply VDD, and the source and substrate of the PMOS tube MP2 are grounded; the lower plate of the capacitor C2 is connected to the drain of the PMOS tube MP2, and the source and substrate of the NMOS tube MN8; the drain of the PMOS tube MP12 and the drain of the NMOS tube MN8 are connected and then connected as the output end of the second positive and negative clock generating circuit to the substrate input end Nbulk2 and the clock input end DOWNCLK of the charge pump; The input terminal CPIN of the charge pump is connected to the power supply VDD; the output terminals CPOUT1 and CPOUT2 of the charge pump are respectively connected to the input terminals IN1 and IN2 of the rectifier circuit; the output terminal OUT of the rectifier circuit is connected to the substrate input terminal Pbulk of the charge pump and serves as the output terminal of the subthreshold boost circuit body.

2. A subthreshold boost circuit based on a positive and negative clock generating circuit according to claim 1, characterized in that: The ring oscillator uses a stacked inverter circuit.

3. The subthreshold boost circuit based on a positive and negative clock generating circuit according to claim 1, characterized in that: The buffer differential circuit is composed of a buffer chain module and a differential clock module; The input end of the buffer chain module serves as the input end IN of the buffer differential circuit, the output end of the buffer chain module is connected to the input end of the differential clock module, and the two output ends of the differential clock module serve as the differential clock output ends CLKA and CLKB of the buffer differential circuit respectively.

4. A subthreshold boost circuit based on a positive and negative clock generating circuit according to claim 1 or 3, characterized in that: The differential clock signals outputted from the output terminals CLKA and CLKB of the buffer differential circuit have opposite phases and equal amplitudes.

5. The subthreshold boost circuit based on a positive and negative clock generating circuit according to claim 1, characterized in that: The charge pump is formed by cascading three-stage charge pump modules; the first-stage charge pump module is composed of NMOS tube MN1, NMOS tube MN2, PMOS tube MP3, PMOS tube MP4, capacitor C3 and capacitor C4; the second-stage charge pump module is composed of NMOS tube MN3, NMOS tube MN4, PMOS tube MP5, PMOS tube MP6, capacitor C5 and capacitor C6; the third-stage charge pump module is composed of NMOS tube MN5, NMOS tube MN6, PMOS tube MP7, PMOS tube MP8, capacitor C7 and capacitor C8; The substrates of the NMOS tube MN1, the NMOS tube MN3 and the NMOS tube MN5 are connected to serve as the substrate input terminal Nbulk1 of the charge pump; the substrates of the NMOS tube MN2, the NMOS tube MN4 and the NMOS tube MN6 are connected to serve as the substrate input terminal Nbulk2 of the charge pump; The substrates of the PMOS tube MP3, the PMOS tube MP4, the PMOS tube MP5, the PMOS tube MP6, the PMOS tube MP7, and the PMOS tube MP8 are connected to serve as the substrate input terminal Pbulk of the charge pump; The upper plate of capacitor C3, the upper plate of capacitor C5 and the upper plate of capacitor C7 are connected to serve as the clock input terminal UPCLK of the charge pump; the lower plate of capacitor C4, the lower plate of capacitor C6 and the lower plate of capacitor C8 are connected to serve as the clock input terminal DOWNCLK of the charge pump; The source of the NMOS tube MN1 and the source of the NMOS tube MN2 are connected to serve as the input terminal CPIN of the charge pump; The lower plate of capacitor C3, the drain of NMOS tube MN1, the drain of PMOS tube MP3, the gate of NMOS tube MN2 and the gate of PMOS tube MP4 are connected; the upper plate of capacitor C4, the drain of NMOS tube MN2, the drain of PMOS tube MP4, the gate of NMOS tube MN1 and the gate of PMOS tube MP3 are connected; The source of the PMOS tube MP3, the source of the PMOS tube MP4, the source of the NMOS tube MN3 and the source of the NMOS tube MN4 are connected; The lower plate of capacitor C5, the drain of NMOS tube MN3, the drain of PMOS tube MP5, the gate of NMOS tube MN4 and the gate of PMOS tube MP6 are connected; the upper plate of capacitor C6, the drain of NMOS tube MN4, the drain of PMOS tube MP6, the gate of NMOS tube MN3 and the gate of PMOS tube MP5 are connected; The source of the PMOS tube MP5, the source of the PMOS tube MP6, the source of the NMOS tube MN5, and the source of the NMOS tube MN6 are connected; The lower plate of capacitor C7, the drain of NMOS tube MN5, the drain of PMOS tube MP7, the gate of NMOS tube MN6 and the gate of PMOS tube MP8 are connected; the upper plate of capacitor C8, the drain of NMOS tube MN6, the drain of PMOS tube MP8, the gate of NMOS tube MN5 and the gate of PMOS tube MP7 are connected; The source of the PMOS tube MP7 serves as the output terminal CPOUT1 of the charge pump; the source of the PMOS tube MP8 serves as the output terminal CPOUT2 of the charge pump.

6. The subthreshold boost circuit based on a positive and negative clock generating circuit according to claim 1, characterized in that: The rectifier circuit is composed of a PMOS tube MP9 and a PMOS tube MP10; The gate of the PMOS tube MP10 and the source of the PMOS tube MP9 are connected to the substrate and serve as the input terminal IN1 of the rectifier circuit; the gate of the PMOS tube MP9 and the source of the PMOS tube MP10 are connected to the substrate and serve as the input terminal IN2 of the rectifier circuit; the drain of the PMOS tube MP9 and the drain of the MOS tube MP10 are connected to serve as the output terminal OUT of the rectifier circuit.

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