A Single-Cycle Full-Data A / D Sampling Method for Eliminating Waiting Time

Abstract

The present invention provides a method for eliminating waiting time in single-cycle full-data A / D sampling, comprising the following steps: S1: Start the processor; S2: Begin the tasks of the current cycle; S3: After assigning the input signal of the i-th analog quantity to 0, select the input signal of the i-th analog quantity and wait for the analog signal to be fully established; S4: Increment i by x; S5: Start the conversion; S6: Parallel process the address selection of the input signal of the (i + x)-th analog quantity and the conversion judgment of the i-th analog quantity; S7: Judge the magnitude relationship between i + x and the total number N of all analog quantity inputs. If i + x is less than N, return to S4. If i + x is equal to N, proceed to the next step; S8: Assign 0 to i, perform other tasks of the current cycle, and after completion, return to S2 to start again; where x is a natural number with a minimum value of 1 and a maximum value of N - i. This method fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time during the A / D conversion sampling process.

Description

Technical Field

[0001] The present invention belongs to the field of airborne computers, and particularly relates to a method for eliminating waiting time in single-cycle full-data A / D sampling. Background Art

[0002] The basic circuit model for an airborne embedded computer to perform analog-to-digital conversion on external multi-channel analog input signals is as Figure 3 shown. Among them, a multiplexer is used to select and connect a certain channel of analog signal to the subsequent A / D conversion circuit. Inside the A / D conversion circuit, after sampling and holding the signal, the analog-to-digital conversion is performed. The processor can obtain digital quantity information through the bus interface circuit of the A / D conversion circuit. Based on this hardware structure, the classic A / D conversion sampling method is as Figure 4 shown in the flow. The characteristic of this flow is that when performing the A / D conversion sampling task in this cycle, the digital quantity information of all complete analog signals is obtained within this cycle. The biggest drawback of this method is that it requires a large amount of waiting time. It takes time for the multiplexer to select data, waiting time is required for the establishment after the signal is selected, waiting time is required for sampling and holding, and waiting time is required for A / D conversion. The multiple concentrated accumulations of these times will severely restrict the performance of the real-time characteristics of the embedded computer and will affect the timely execution of other tasks in the current cycle. Summary of the Invention

[0003] In order to solve the above problems, the present invention provides a single-cycle full-data A / D conversion sampling method, which fully improves the operation efficiency of the processor and effectively reduces the ineffective waiting time in the A / D conversion sampling process.

[0004] The purpose of the present invention is to provide a method for eliminating waiting time in single-cycle full-data A / D sampling, which is characterized in that the method includes the following steps:

[0005] S1: Start the processor;

[0006] S2: Start the tasks of this cycle;

[0007] S3: After assigning the i-th analog input signal to 0, select the i-th analog input signal and wait for the analog signal to be fully established;

[0008] S4: Increment i by x;

[0009] S5: Start the conversion;

[0010] S6: Parallel process the address selection of the (i + x)-th analog input signal and the conversion judgment of the i-th signal;

[0011] S7: Determine the magnitude relationship between i + x and the total number N of all analog inputs. If i + x is less than N, return to S4. If i + x equals N, proceed to the next step;

[0012] S8: Assign 0 to i, perform other tasks in this cycle, and after completion, return to S2 to start over;

[0013] Among them, x is a natural number with a minimum value of 1 and a maximum value of N - i.

[0014] The single-cycle full-data A / D sampling method for eliminating waiting time provided by the present invention also has the following feature: In S3, the gating of the i-th analog input signal is performed through a multiplexer.

[0015] The single-cycle full-data A / D sampling method for eliminating waiting time provided by the present invention also has the following feature: S6 includes the following steps:

[0016] S6.1: Determine the magnitude relationship between i + x and N. If it is less, proceed to the next step. If i + x equals N, directly proceed to step S6.4;

[0017] S6.2: Wait for the sampling and holding circuit signal to be ready;

[0018] S6.3: Gate the address of i + x and gate the data labeled i + x;

[0019] S6.4: Perform a conversion judgment on the i-th data to determine whether the conversion is completed. If completed, proceed to S7. If not completed, repeat step S6.4.

[0020] The single-cycle full-data A / D sampling method for eliminating waiting time provided by the present invention also has the following feature: The steps of the conversion judgment in S6.4 are as follows:

[0021] S6.4.1: Start and enter the "conversion completed" discrimination process;

[0022] S6.4.2: Assign 0 to c, and c is used for loop counting;

[0023] S6.4.3: Determine whether the value of c is less than M. If it is less than M, perform S6.4.5 in the next step. Otherwise, perform S6.4.4 in the next step, where M is the counting threshold value;

[0024] S6.4.4: Fault handling, and perform S6.4.7 in the next step;

[0025] S6.4.5: Determine whether the "A / D conversion completed signal indication" is in the completed state. If completed, perform S6.4.7 in the next step. Otherwise, perform S6.4.6 in the next step:

[0026] S6.4.6: Increment i by 1, that is, increase the value of i by 1, and then execute S6.4.3 in the next step;

[0027] S6.4.7: Assign 0 to c;

[0028] S6.4.8: Exit, and the "conversion completed" discrimination process is completed.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] The present invention provides a single-cycle full-data A / D sampling method for eliminating waiting time consumption, which fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time consumption during the A / D conversion sampling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 The flowchart of the single-cycle full-data A / D sampling method for eliminating waiting time consumption provided by the embodiment of the present invention;

[0033] Figure 2 The flowchart of the conversion completion step in the method provided by the embodiment of the present invention;

[0034] Figure 3 The basic model of the A / D conversion sampling circuit;

[0035] Figure 4 The single-cycle full-data A / D conversion sampling method in the prior art. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] In order to make the technical means, creative features, achieved purposes and effects of the present invention easy to understand, the following embodiments will specifically describe the single-cycle full-data A / D sampling method for eliminating waiting time consumption provided by the present invention in conjunction with the drawings.

[0037] In the description of the embodiments of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0038] In addition, the terms "first", "second", "third", etc. are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0039] The terms "mounted", "connected", and "coupled" should be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] As Figure 1 shown, the present invention provides a single-cycle full-data A / D sampling method for eliminating waiting time-consuming, and the method includes the following steps:

[0041] S1: Start the processor;

[0042] S2: Start the tasks of this cycle;

[0043] S3: After assigning the i-th analog input signal to 0, select the i-th analog input signal and wait for the analog signal to be fully established;

[0044] S4: Increment i by x;

[0045] S5: Start the conversion;

[0046] S6: Parallel process the address selection of the (i + x)-th analog input signal and the conversion judgment of the i-th;

[0047] S7: Judge the magnitude relationship between i + x and the total number N of all analog inputs. If i + x is less than the total number N of all analog inputs, return to S4. If i + x is equal to N, proceed to the next step;

[0048] S8: Assign 0 to i, perform other tasks of this cycle, and after completion, return to S2 to start again;

[0049] Wherein, x is a natural number with a minimum value of 1 and a maximum value of N - i.

[0050] In some embodiments, the selection of the i-th analog input signal in S3 is performed through a multiplexer.

[0051] In some embodiments, S6 includes the following steps:

[0052] S6.1: Determine the magnitude relationship between i + x and N. If it is less than N, proceed to the next step. If i + x is equal to N, directly proceed to step S6.4;

[0053] S6.2: Wait for the sampling and holding circuit signal to be ready;

[0054] S6.3: Select the address of i + x and select the data labeled i + x;

[0055] S6.4: Perform a conversion judgment on the i-th data to determine whether the conversion is completed. If it is completed, proceed to S7. If it is not completed, repeat step S6.4.

[0056] In some embodiments, as Figure 2 shown, the steps of the conversion judgment in S6.4 are as follows:

[0057] S6.4.1: Start and enter the "conversion completed" discrimination process;

[0058] S6.4.2: Assign 0 to c, where c is used for loop counting;

[0059] S6.4.3: Determine whether the value of c is less than M. If it is less than M, proceed to S6.4.5 in the next step. Otherwise, proceed to S6.4.4 in the next step, where M is the counting threshold value;

[0060] S6.4.4: Fault handling, and proceed to S6.4.7 in the next step;

[0061] S6.4.5: Determine whether the "A / D conversion completed signal indication" is in the completed state. If it is completed, proceed to S6.4.7 in the next step. Otherwise, proceed to S6.4.6 in the next step:

[0062] S6.4.6: Increment i by 1, that is, increase the value of i by 1, and proceed to S6.4.3 in the next step;

[0063] S6.4.7: Assign 0 to c;

[0064] S6.4.8: Exit, and the "conversion completed" discrimination process is completed.

[0065] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention. The above is only the preferred implementation manner of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principles of the present invention, several improvements and modifications can still be made, and these improvements and modifications should also be regarded as within the protection scope of the present invention.

Claims

1. A method for eliminating waiting time in single-cycle full-data A / D sampling, characterized in that The method includes the following steps: S1: Start the processor; S2: Start the tasks of this cycle; S3: After assigning the i-th analog input signal to 0, select the i-th analog input signal and wait for the analog signal to be fully established; S4: Increment i by x; S5: Start the conversion; S6: Parallel process the address selection of the (i + x)-th analog input signal and the conversion judgment of the i-th signal; S7: Judge the magnitude relationship between i + x and the total number N of all analog inputs. If i + x is less than N, return to S4. If i + x is equal to N, proceed to the next step; S8: Assign 0 to i, perform other tasks of this cycle, and after completion, return to S2 to start over; where x is a natural number with a minimum value of 1 and a maximum value of N - i, The said S6 includes the following steps: S6.1: Judge the magnitude relationship between i + x and N. If it is less, proceed to the next step. If i + x is equal to N, directly proceed to step S6.4; S6.2: Wait for the sampling and holding circuit signal to be ready; S6.3: Select the address of i + x and select the data labeled i + x; S6.4: Perform a conversion judgment on the i-th data to determine whether the conversion is completed. If completed, proceed to S7. If not completed, repeat step S6.4; The steps of the conversion judgment in the said S6.4 are as follows: S6.4.1: Start and enter the "conversion completed" discrimination process; S6.4.2: Assign 0 to c, where c is used for loop counting; S6.4.3: Judge whether the value of c is less than M. If less than M, the next step is to execute S6.4.

5. Otherwise, the next step is to execute S6.4.4, where M is the counting threshold value; S6.4.4: Fault handling, and the next step is to execute S6.4.7; S6.4.5: Check whether the "A / D conversion completed signal indication" is in the completed state. If completed, the next step is to execute S6.4.

7. Otherwise, the next step is to execute S6.4.6: S6.4.6: Increment i by 1, that is, add 1 to the value of i, and the next step is to execute S6.4.3; S6.4.7: Assign 0 to c; S6.4.8: Exit, and the "conversion completed" discrimination process is completed.

2. The single-cycle full-data A / D sampling method for eliminating waiting time consumption according to claim 1, wherein The selection of the i-th analog input signal in the said S3 is performed through a multiplexer.

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