Memory Controller and Memory Device

Abstract

The present invention discloses a memory device and a memory controller. The memory controller includes a control unit, a storage unit, and a plurality of encoder units. The storage unit is coupled to the control unit and includes a plurality of storage areas. Each storage area is represented by a memory address and stores one of a plurality of parts of a generator matrix. The encoder units are coupled to the control unit and the storage unit and are coupled to the memory chips one-to-one, many-to-one, or one-to-many. The encoder units are based on a low density parity check (LDPC) code, and the LDPC code is based on the generator matrix.

Description

Technical Field

[0001] The present invention relates to a memory controller and a memory device. Background Art

[0002] A memory device may include multiple memory chips. For each memory chip, the memory controller of the memory device needs to configure an error correction circuit, which includes an encoder unit and a decoder unit to perform: (1) encoding user data from a host controller for writing to the corresponding memory chip, and (2) decoding data read from the corresponding memory chip for transmission to the host controller. In some implementations, these encoder units are based on Low-density parity-check code (LDPC). Under the LDPC-based architecture, when performing the operation of encoding user data from the host controller, the encoder in the encoder unit multiplies the user data by a generator matrix to generate multiple parity-check digits. In one implementation of the prior art, for each encoder unit, a storage unit can be configured in the memory controller to store the generator matrix, that is, N encoder units will be configured with N storage units, and these storage units store the same generator matrix. This approach increases the area and cost of the memory controller. In another implementation of the prior art, for all encoder units, a storage unit can be configured in the memory controller to store the generator matrix, that is, N encoder units share one storage unit in turn. This approach saves area and cost, but reduces the data throughput. Summary of the Invention

[0003] One aspect of the present invention discloses a memory device. The memory device includes multiple memory chips and a memory controller. The memory controller is coupled to the memory chips. The memory controller includes a control unit, a storage unit, and multiple encoder units. The storage unit is coupled to the control unit and includes multiple storage areas. Each storage area is represented by a memory address and stores one of multiple parts of a generator matrix. The encoder units are coupled to the control unit and the storage unit, and are coupled to the memory chips one-to-one, many-to-one, or one-to-many. The encoder units are encoded based on a Low-density parity-check code (LDPC), and the LDPC encoding is based on the generator matrix.

[0004] Another aspect of the present invention discloses a memory controller. The memory controller includes a control unit, a storage unit, and a plurality of encoder units. The storage unit is coupled to the control unit and includes a plurality of storage areas. Each storage area is represented by a memory address and stores one of a plurality of parts of a generator matrix. The encoder units are coupled to the control unit and the storage unit and are coupled to the memory chips one-to-one, many-to-one, or one-to-many. The encoder units are based on a low density parity check (LDPC) code, and the LDPC code is based on the generator matrix.

[0005] In order to have a better understanding of the above and other aspects of the present invention, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. shows a block diagram of a memory device according to an embodiment of the present invention.

[0007] Figure 2 FIG. shows a block diagram of a memory controller according to an embodiment of the present invention.

[0008] Figure 3 FIG. shows a schematic diagram of calculating a parity check code according to an embodiment of the present invention.

[0009] Figures 4A to 4B FIG. shows a flowchart of an operation method of a memory controller according to an embodiment of the present invention.

[0010] Figure 5 FIG. shows a timing diagram of a memory device calculating a parity check code according to an embodiment of the present invention.

[0011] SYMBOL DESCRIPTION

[0012] 10: Memory device

[0013] 102-1 to 102-x: Memory chips

[0014] 104: Memory controller

[0015] 1041: Control unit

[0016] 1043: Storage unit

[0017] 1045-1 to 1045-x: Encoder units DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0019] Please refer to Figure 1 , Figure 1FIG. is a block diagram of a memory device according to an embodiment of the present invention. The memory device 10 includes a plurality of memory chips 102-1 to 102-x and a memory controller 104, where x is a positive integer greater than 1. Each of the memory chips 102-1 to 102-x may include a memory array and control circuits (such as input / output circuits, sense amplifier circuits, etc.) for operating the memory array. The memory array may be a NAND flash memory array, a NOR flash memory array, a phase change memory array, or any available memory array.

[0020] The memory controller 104 is coupled to a host controller 90 and the memory chips 102-1 to 102-x. The memory controller 104 is configured to receive one or more write commands from the host controller 90 and one or more pieces of user data corresponding to the one or more write commands. The memory controller 104 writes the one or more pieces of user data into the memory chips 102-1 to 102-x in response to the one or more write commands. For details of the memory controller 104, please further refer to Figure 2 FIG. is a block diagram of a memory controller according to an embodiment of the present invention. The memory controller 104 includes a control unit 1041, a storage unit 1043, and a plurality of encoder units 1045-1 to 1045-x. In this embodiment, the number of encoder units 1045-1 to 1045-x is the same as the number of memory chips. The storage unit 1043 is coupled to the control unit 1041. The storage unit 1043 may be an embedded read only memory or a static random access memory. The encoder units 1045-1 to 1045-x are coupled to the control unit 1041, the storage unit 1043, and the memory chips 102-1 to 102-x. Each of the encoder units 1045-1 to 1045-x corresponds to one of the memory chips 102-1 to 102-x in a one-to-one manner. For example, the encoder unit 1045-1 corresponds to and is coupled to the memory chip 102-1, the encoder unit 1045-2 corresponds to and is coupled to the memory chip 102-2, and so on. Each of the encoder units 1045-1 to 1045-x is, for example, an encoder based on a Low-density parity-check code (LDPC) encoding.

[0021] It should be noted that, in other embodiments, the number of encoder units may also be different from the number of memory chips. That is, the encoder units may also be coupled to the memory chips in a one-to-many or many-to-one manner.

[0022] To more easily understand the content of the present invention, a brief description of LDPC coding is given here. A piece of user data D with a length of k bits can generate a codeword C with a length of n bits according to a generation matrix G with a dimension of k×n, where k and n are positive integers, and can be expressed mathematically as: C = DG. The generation matrix G can be decomposed into an identity matrix I with a dimension of k×k and a matrix P with a dimension of k×p, where p is a positive integer and k + p = n, and can be expressed mathematically as: G = I + P. Thus, the codeword C can be expressed mathematically as: C = D + Q, where Q is a parity check code with a length of p bits.

[0023] Please refer to Figure 3 , Figure 3 FIG. showing a schematic diagram of calculating a parity check code according to an embodiment of the present invention. In this embodiment, the generation matrix G may include a plurality of sub-matrices g 0，0 ~g 2，5 , where the dimension of the sub-matrix g 0，0 ~g 2，5 is m×m, and m is a positive integer. More specifically, the generation matrix P can be regarded as being composed of the sub-matrices g 0，0 ~g 2，5 . The user data D can be regarded as being composed of six sub-sequences d0~d5 with a length of m, that is, D = d0d1d2d3d4d5. When calculating the parity check code, it can be calculated according to the Figure 3 way shown on the right, where the parity check code Q can be expressed as Q = P0P1P2, and XOR is the "exclusive OR" operation. In this embodiment, the generation matrix is divided into six parts, where the first part includes the sub-matrices g 0，0 , g 1，0 , g 2，0 , the second part includes the sub-matrices g 0，1 , g 1，1 , g 2，1 , the third part includes the sub-matrices g 0，2 , g 1，2 , g 2，2 , the fourth part includes the sub-matrices g 0，3 , g 1，3 , g 2，3 , the fifth part includes the sub-matrices g 0，4 , g 1，4 , g 2，4 , and the sixth part includes the sub-matrices g 0，5 , g 1，5 , g 2，5 . These six parts of the generation matrix can be respectively stored in six storage areas of the storage unit 1043 represented by the memory addresses A1~A5. For example, the sub-matrices g 0，0 , g 1，0 , g 2，0The elements of can be stored in the first storage area represented by the memory address A1 in the storage unit 1043, and the sub-matrix g of the second part 0，1 、g 1，1 、g 2，1 The elements of can be stored in the second storage area represented by the memory address A2 in the storage unit 1043, and so on. For a piece of user data, the encoder unit can use six frequency cycles to calculate the parity check code. For example, in the first frequency cycle C1, according to the first subsequence d0 of the user data and the sub-matrix g of the first part 0，0 、g 1，0 、g 2，0 calculate the parity check code, and in the second frequency cycle C2, according to the second subsequence d1 of the user data and the sub-matrix g of the second part 0，1 、g 1，1 、g 2，2 calculate the parity check code. It is worth mentioning that the operation order of the first frequency cycle C1 to the sixth frequency cycle C6 can be arranged arbitrarily, that is, it is allowed to calculate the operation of the first frequency cycle C1 after calculating the operation of the second frequency cycle C2.

[0024] Return to Figure 2 , and please also refer to Figures 4A to 4B the flowchart of the operation method of the memory controller according to an embodiment of the present invention shown in the figure, where Figure 4A the process is executed by each encoder unit, Figure 4B is executed by the control unit. It should be noted that in this embodiment, the generating matrix is taken as an example including six parts, however, the present invention is not limited thereto. That is to say, in practical applications, the generating matrix can be divided into multiple parts (i.e., can include multiple parts), and the storage unit can include multiple storage areas, each storage area can be represented by a memory address, and store one of these parts of the generating matrix.

[0025] First, Figure 4A, in step S401, each encoder unit 1045-1 to 1045-x respectively determines whether it has received a complete user data. The main controller 90 can transmit one or more pieces of user data to the memory controller 104. For example, the main controller 90 can successively transmit the first user data, the second user data, and the third user data. The first user data can be transmitted to the encoder unit 1045-1, the second user data can be transmitted to the encoder unit 1045-2, and the third user data can be transmitted to the encoder unit 1045-3. In an example where the length of the user data is set to k bits, the encoder units 1045-1 to 1045-3 can respectively determine that they have received a complete user data according to the length of the received user data reaching k bits. When an encoder unit confirms that it has received a complete user data, it executes S403; otherwise, it returns to step S401.

[0026] In step S403, the encoder unit that has confirmed receiving a complete user data sets its own state to ready and transmits a ready signal to the control unit 1041. The ready signal can include an identifier of the encoder unit that transmits this ready signal. That is to say, the ready signal can be used to notify the control unit 1041 which encoder unit is in the ready state.

[0027] Jump to Figure 4B , in step S411, the control unit 1041 determines whether it has received a ready signal. When the control unit 1041 receives a ready signal, it executes step S413; otherwise, it executes step S423.

[0028] In step S413, in response to the ready signal, the control unit 1041 determines an end address ready signal according to a current address. The current address and the end address are selected and set from the memory addresses in the storage unit that represent the storage areas storing these parts of the generating matrix.

[0029] In step S415, the control unit 1041 transmits the current address to the encoder unit whose state is ready.

[0030] In step S417, the control unit 1041 transmits the current address to the storage unit 1043 and instructs the storage unit 1043 to output the part of the generating matrix stored in the storage area corresponding to the current address to the encoder unit whose state is ready.

[0031] In step S419, the control unit 1041 determines whether an end condition has been reached. The end condition is, for example, that the current address is equal to the end address. If so, this process ends; if not, it executes step S421.

[0032] In step S421, the control unit 1041 updates the current address. For example, it sets the next memory address of the current address as the new current address.

[0033] In step S423, the control unit 1041 determines whether at least one ready signal has been received. If so, step S413 is executed; if not, step S411 is executed. The control unit 1041 can determine whether at least one ready signal has been received by setting a flag. For example, when the first ready signal is received after the start of this process, the control unit 1041 can set the flag value from 0 to 1; when the process ends, the flag is set from 1 to 0.

[0034] Then jump back Figure 4A , in step S405, the encoder unit with the ready state receives the current address from the control unit and the part of the generating matrix corresponding to the current address from the storage unit.

[0035] In step S407, the encoder unit with the ready state calculates / updates the parity check code (i.e., the generated code) corresponding to the user data according to the subsequence corresponding to the current address in the user data and the received part of the generating matrix corresponding to the current address.

[0036] In step S409, the encoder unit with the ready state determines whether the parity check code has been calculated. If so, the state is set to operation completed and this process ends; if not, step S405 is executed. In one embodiment, when each subsequence in the user data has performed the operation of step S407, the encoder unit can determine that the parity check code corresponding to this user data has been calculated. In another embodiment, the encoder unit can be configured with a counter. When the value of the counter reaches a threshold, it can be determined that the parity check code corresponding to this user data has been calculated. Taking Figure 3 the embodiment as an example, the value of the counter can be preset to 0, the threshold can be set to 6, and the value of the counter increases by 1 each time step S407 is executed. When the value of the counter reaches 6, it means that after six frequency cycles of operation, the six subsequences of the user data have all completed the operation with the corresponding parts of the generating matrix.

[0037] In one embodiment, when the encoder unit determines that the parity check code has been calculated, the encoder unit transmits a completion signal to the control unit 1041, where the completion signal can include the identification code of the encoder unit. That is to say, the completion signal can be used to notify the control unit 1041 which encoder unit's state has been changed from ready to operation completed. In such an embodiment, the control unit 1041 can determine whether the end condition is reached by recording whether all the encoder units that have transmitted the ready signal have transmitted the completion signal.

[0038] For a clearer understanding of the present invention, please refer to Figure 5 the timing diagram showing the calculation of parity check codes by a memory device according to an embodiment of the present invention. Figure 5 It is Figure 2 the memory controller 104 of Figure 3 calculating the timing of the parity check code according to the calculation method of the parity check code of

[0039] At time T0, the encoder unit 1041-1 confirms receiving a complete user data and transmits a ready signal to the control unit; at this time, in the record of the control unit, the current address is A0 (initial set value). Since the encoder unit 1045-1 needs to perform a complete operation of the generator matrix and read the memory addresses A0 to A5 once, the end address is set to A5, the current address A0 is notified to the encoder unit 1045-1, and the storage unit 1043 is instructed to transmit the part of the generator matrix stored at the memory address A0 to the encoder unit 1045-1. At time T1, the encoder unit 1045-2 also receives a complete user data and transmits a ready signal to the control unit; at this time, in the record of the control unit, the current address is A2 (after two frequency cycles starting from T0). Since the encoder unit 1045-2 needs to perform a complete operation of the generator matrix and read the memory addresses A0 to A5 once, the end address is set to A1, the current address A2 is notified to the encoder units 1045-1 and 1045-2, and the storage unit 1043 is instructed to transmit the part of the generator matrix stored at the memory address A2 to the encoder units 1045-1 and 1045-2. The same applies to times T2 and T3. Figure 5 In 0，0 D Figure 3 represents the encoder unit 1045-1 performing the calculation of the first frequency cycle C1 as shown in 0，1 according to the received user data D0, D Figure 3 represents the encoder unit 1045-1 performing the calculation of the second frequency cycle C2 as shown in 1，2 according to the received user data D0, D Figure 3 represents the encoder unit 1045-2 performing the calculation of the third frequency cycle C3 as shown in

[0040] In summary, for the encoder units in the ready state according to the present invention, the control unit will instruct the storage unit to transmit the same part of the parity check code according to the current address. By the above method, it is not necessary to wait for one encoder unit to calculate the parity check code before the other encoder unit can calculate. In this way, the throughput of the memory controller can be improved.

[0041] The specific embodiments described above further elaborate on the object, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A memory device, wherein, Comprising: A plurality of memory chips; And A memory controller, coupled to these memory chips, and comprising: A control unit; A storage unit, coupled to the control unit, and comprising a plurality of storage areas, each of which is represented by a memory address and stores one of a plurality of parts of a generation matrix; and A plurality of encoder units, coupled to the control unit and the storage unit, and coupled to these memory chips one-to-one, one-to-many or many-to-one, Wherein these encoder units are encoded based on a low-density parity-check code, and the low-density parity-check code is encoded based on the generation matrix; Each of these encoder units is configured to perform: determining whether a complete user data is received; in response to the determination of receiving a complete user data, setting a status to ready and transmitting a ready signal to the control unit; The control unit is configured to perform: determining whether the ready signal is received; in response to the ready signal, determining an end address according to a current address, wherein the current address and the end address are selected from these memory addresses; transmitting the current address to one or more encoder units in the ready status; transmitting the current address to the storage unit, and instructing the storage unit to output the part of the generation matrix stored in the storage area corresponding to the current address to the one or more encoder units in the ready status according to the current address.

2. The memory device according to claim 1, wherein, Each of these encoder units is further configured to perform: Calculating one or more parity-check codes for one of a plurality of subsequences corresponding to the current address in the user data and the part of the generation matrix corresponding to the current address according to the current address.

3. The memory device according to claim 2, wherein, The control unit is further configured to perform: Determining whether an end condition is reached, and the end condition is that the current address is equal to the end address; and In response to a determination that the end condition is not reached, updating the current address.

4. A memory controller, wherein, Comprising: A control unit; A storage unit, coupled to the control unit, and comprising a plurality of storage areas, each of which is represented by a memory address and stores one of a plurality of parts of a generation matrix; And A plurality of encoder units, coupled to the control unit and the storage unit, and coupled to a plurality of memory chips one-to-one, one-to-many or many-to-one, Wherein these encoder units are encoded based on a low-density parity-check code, and the low-density parity-check code is encoded based on the generation matrix; Each of these encoder units is configured to perform: determining whether a complete user data is received; in response to the determination of receiving a complete user data, setting a status to ready and transmitting a ready signal to the control unit; The control unit is configured to perform: determining whether the ready signal is received; in response to the ready signal, determining an end address according to a current address, wherein the current address and the end address are selected from these memory addresses; transmitting the current address to one or more encoder units in a ready state; transmitting the current address to the storage unit, and instructing the storage unit to output the part of the generation matrix stored in the storage area corresponding to the current address to the one or more encoder units in a ready state according to the current address.

5. The memory controller according to claim 4, wherein, Each of the encoder units is further configured to perform: Calculating one or more parity check codes for one of the multiple subsequences corresponding to the current address in the user data and the part corresponding to the current address in the generation matrix according to the current address.

6. The memory controller according to claim 5, wherein, The control unit is further configured to perform: Determining whether an end condition has been reached, the end condition being that the current address is equal to the end address; and Updating the current address in response to a determination that the end condition has not been reached.

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