Etch stop layer

Abstract

Disclosed are methods for forming silicon nitride (SiN) only on the horizontal surfaces of a structure, such as a 3D NAND staircase. This allows for thicker landing pads for subsequent via formation. In some embodiments, the method involves depositing a SiN layer on the staircase, followed by a process to densify the SiN layer selectively on the horizontal surfaces relative to the sidewall surfaces. Next, a wet etch is performed to remove the SiN from the sidewall surfaces. The selective process results in a significantly different wet etch rate (WER) between the horizontal surfaces and the sidewalls.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit of or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] Semiconductor device manufacturing involves the fabrication of flash memory. As devices shrink, structures for creating efficient and multiple memory cells are being used to maximize the density of memory cells in memory devices. 3D NAND technology addresses the challenges associated with two-dimensional NAND technology by vertically stacking memory cells in layers.

[0004] The descriptions of background and context contained herein are provided solely for the purpose of presenting the context of the disclosure as a whole. Many of the present disclosures are the work of the inventors, and simply because such work is described in the background section or presented as context elsewhere in this document does not mean that it is admitted to be prior art. Summary of the Invention

[0005] One aspect of the present disclosure relates to a method comprising: providing a substrate having alternating oxide and nitride layers arranged in a staircase pattern, the staircase pattern including exposed horizontal nitride surfaces and exposed oxide and nitride sidewall surfaces; depositing a silicon nitride (SiN) layer on the alternating oxide and nitride layers; and processing the SiN layer to selectively densify the SiN layer deposited on the exposed horizontal nitride surface.

[0006] In some embodiments, the method further comprises wet etching the treated SiN layer to form a separate SiN pad. In some embodiments, the separate SiN pad is at least 10 nm away from the adjacent sidewall surface. In some embodiments, the separate SiN pad is at least 10 nm thick. In some embodiments, the method further comprises replacing the SiN pad with a tungsten landing pad. In some embodiments, the deposition and treatment operations are performed in the same chamber.

[0007] In some embodiments, depositing the SiN layer comprises a plasma enhanced chemical vapor deposition (PECVD) process.

[0008] In some embodiments, treating the SiN layer includes exposing the substrate to a capacitively coupled plasma, which may be generated from an inert gas.

[0009] In some embodiments, performing the depositing and treating operations includes performing a plurality of cycles of depositing a conformal portion of the SiN layer followed by treating the deposited portion.

[0010] In some embodiments, the conformal SiN layer comprises a plurality of sub-layers, wherein at least two sub-layers have different wet etch rates (WERs). In some embodiments, one of the plurality of sub-layers is an etch stop (ES) sub-layer, the ES sub-layer having a lower WER than one or more other sub-layers of the plurality of sub-layers. In some embodiments, the ES layer has an etch rate in the wet etchant of no more than In some embodiments, one of the plurality of sub-layers has a WER of at least / minute of the sublayer. In some embodiments, the ES sublayer is disposed between two sublayers, each of which is thicker than the ES sublayer and has a WER greater than the ES sublayer. In some embodiments, the ES sublayer is a top layer of the SiN layer. In some embodiments, the SiN film is deposited from silane (SiH4) and ammonia (NH3). In some embodiments, the SiH4 and NH3 are in a process gas that also includes nitrogen (N2). In some embodiments, the method further includes replacing the nitride layer with a tungsten wordline.

[0011] Another aspect of the present disclosure relates to a method comprising: providing a substrate having horizontal and sidewall surfaces; depositing a silicon nitride (SiN) layer on the horizontal and sidewall surfaces; and treating the SiN layer to selectively densify the conformal SiN layer deposited on the horizontal surfaces. In some embodiments, the method further comprises wet etching the treated layer to form a separate SiN pad.

[0012] Yet another aspect of the present disclosure relates to a method comprising: providing a substrate having horizontal and sidewall surfaces; performing one or more first cycles to form a first sublayer, each of the one or more first cycles comprising: depositing a quantity of SiN on the horizontal and sidewall surfaces by PECVD, and exposing the deposited quantity of SiN to a capacitively coupled plasma generated by an inert gas; performing one or more second cycles to form an etch stop sublayer, each of the one or more second cycles comprising: depositing a quantity of SiN on the first sublayer by PECVD, and exposing the deposited quantity of SiN to a capacitively coupled plasma generated by an inert gas using low frequency radio frequency (LFRF) power. In some embodiments, if LFRF power is present in the one or more first cycles, the LFRF power in the one or more second cycles is greater than the LFRF power in the one or more first cycles.

[0013] Another aspect of the present disclosure relates to an apparatus comprising a PECVD deposition chamber including a LFRF plasma generator and a HFRF plasma generator; and a controller containing instructions for performing the methods described herein.

[0014] These and other aspects of the disclosure are discussed in the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A is a process flow diagram depicting the operation of a method according to certain embodiments.

[0016] Figure 1B is a process flow diagram depicting operations used in a method for forming a 3D NAND structure.

[0017] Figure 2 、 3 and 4A are schematic diagrams of the substrate in the patterning scheme.

[0018] Figure 4B yes Figure 4A A partial view of the substrate is shown in FIG.

[0019] Figure 5A 、 6A , 7A, 8 and 9 are schematic diagrams of substrates in patterning schemes.

[0020] Figure 5B 、 6B and 7B respectively Figure 5A 、 6A and a side view of a schematic diagram of the substrate shown in 7A.

[0021] Figure 10is a process flow diagram depicting operations for a method, according to certain embodiments.

[0022] Figure 11-15 is a schematic diagram of the substrate in the patterning scheme.

[0023] Figure 16 Examples of various silicon nitride (SiN) stacks including sub-layers with different wet etch rates (WERs) are depicted.

[0024] Figure 17 Target spacing (S) and thickness (T) of SiN pads are depicted according to certain embodiments.

[0025] Figure 18 is a process flow diagram illustrating operations for a method according to certain embodiments.

[0026] Figure 19 Graphs showing pitch and remaining thickness versus etch time for forming a SiN pad, according to certain embodiments.

[0027] Figure 20 is a schematic diagram of an exemplary processing chamber for performing certain disclosed embodiments.

[0028] Figure 21 is a schematic diagram of an example processing tool for performing certain disclosed embodiments. DETAILED DESCRIPTION

[0029] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail to avoid obscuring the embodiments of the present disclosure. Furthermore, although the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that the specific embodiments are not intended to limit the embodiments of the present disclosure.

[0030] The implementation scheme disclosed below describes the deposition of materials on a substrate such as a wafer, substrate or other workpiece. The workpiece can be of various shapes, sizes and materials. In this application, the terms "wafer" and "substrate" are used interchangeably.

[0031] Semiconductor manufacturing often involves the fabrication of memory devices. One example is the fabrication of 3D NAND (also known as "vertical NAND" (VNAND)) structures. However, existing techniques for forming 3D NAND structures are limited by vertical scaling: the number of memory layers increases. To achieve the desired cost per bit scaling, it is important not to increase the number of processing steps proportionally with the number of layers.

[0032] In 3D NAND technology, an oxide fill is deposited on alternating oxide and nitride layers arranged in a staircase pattern. The nitride layer is then replaced by a metal film, typically comprising tungsten, to form the word lines. Vias are then formed in the oxide fill. The vias extend vertically to contact the tungsten word lines, which now form the steps of the stairs. Metal (e.g., tungsten) is deposited in the vias to form interconnects, which extend and contact the tungsten word lines. As 3D NAND scales, the stairs have more steps and become deeper. Furthermore, to reduce the overall height of the memory stack, the word lines need to be thinned. The word lines that form the steps of the stairs also serve as an etch stop for the via etching. For cost reasons, it is desirable to form the vias in a single masking and etching step. However, as the stairs become deeper and the word lines become thinner, as scaling requires, it becomes more difficult to retain the upper word lines after the long overetch required to reach the lower word lines. As a result, the contact surfaces of word lines located higher up the steps may be overetched relative to word lines toward the bottom of the staircase pattern. Consequently, etching may penetrate these word lines and reach other word lines below. Subsequently, when the vias are filled with metal, these word lines will short-circuit, resulting in yield loss.

[0033] Disclosed are methods and related equipment for forming silicon nitride (SiN) only on the horizontal surfaces of 3D NAND steps. This enables thicker landing pads to be used for subsequently formed through-holes. In some embodiments, the method involves depositing a SiN layer on the steps, followed by processing to selectively densify the SiN layer on the horizontal surfaces relative to the sidewall surfaces. Next, a wet etch is performed to remove the SiN from the sidewall surfaces. The selective processing results in a significantly different wet etch rate (WER) between the horizontal surfaces and the sidewalls. After the wet etch, the SiN layer is retained on the horizontal surfaces and removed from the sidewalls. When the SiN layer is replaced with tungsten (W) in subsequent processing, a thick W pad is formed. Although the following methods and tools are described in the context of forming a SiN pad on a nitride layer in a 3D NAND structure, they can be applied to any application where selective deposition of SiN on a horizontal surface is required.

[0034] In addition to SiN, the method described below can be applied to form silicon oxynitride (SiON) films. Furthermore, the pad can be formed from any suitable oxide, nitride, carbide, oxynitride, oxynitride carbide, or oxycarbide film.

[0035] Figure 1AA process flow diagram of operations performed according to the methods described herein is shown. First, in operation 103, a SiN layer is deposited on a structure having horizontal and vertical surfaces (also referred to as sidewall surfaces). According to various embodiments, operation 103 may involve plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or thermal atomic layer deposition (ALD). Other deposition techniques capable of conformal deposition may be used. For deposition on a stepped structure, the total thickness deposited may depend on one or more of the following objectives: 1) the thickness of the SiN remaining on the horizontal surfaces after wet etching (which determines the thickness of the tungsten landing pad); 2) the shortest distance between the SiN and the sidewalls of the stepped structure; and 3) no over-etching to achieve 1) and 2). According to various embodiments, the thickness may be between between.

[0036] The SiN film is deposited on both the horizontal and vertical surfaces of the structure. It is generally conformal to the structure, but depending on the deposition method, there may be some difference in thickness on the sidewalls compared to the thickness on the horizontal surfaces. It should be noted that the term "vertical" as used herein includes surfaces that are close to 90° relative to a plane as well as completely vertical. For example, a vertical surface can vary by + / -10°, or + / -5°, or + / -1°, or + / -0.5° from 90°. Similarly, a horizontal surface can vary by + / -5°, or + / -1°, or + / -0.5° relative to 180°.

[0037] PECVD can be used to provide relatively fast deposition. In some embodiments, silane (SiH4) and ammonia (NH3) can be reacted to form SiN during PECVD deposition. Nitrogen (N2) or an inert gas such as argon (Ar) or helium (He) can be used as a carrier gas. Other silicon-containing precursors can be used to deposit SiN, including but not limited to organosilanes. Similarly, other nitrogen-containing gases (e.g., N2) can be used as co-reactants as appropriate.

[0038] At operation 105, the silicon nitride film is treated to selectively densify the horizontal surfaces. In this article, selective densification refers to densifying the SiN film on the horizontal surfaces without densifying the SiN film on the vertical surfaces, or to a significantly lesser extent. Operation 105 may involve exposing the deposited film to an inert gas plasma. For PECVD reactions or PEALD reactions, this can be performed in a deposition chamber. In some embodiments, a bias can be applied to the substrate to improve the directionality of the plasma, however, the method can be performed without a bias. For example, capacitively coupled in-situ Ar plasma without substrate bias has been shown to selectively densify films on horizontal surfaces.

[0039] It should be noted that operations 103 and 105 can be performed in multiple interspersed stages. That is, a first amount of silicon nitride can be deposited and then processed, a second amount of silicon nitride can be deposited and then processed, and so on, until the full thickness of the SiN film is formed. This may be effective if the process has a limited penetration depth to ensure that the full thickness of the film is processed.

[0040] A wet etch is then performed in operation 107 to selectively remove the SiN film from the vertical surfaces. Dilute hydrofluoric acid (DHF) may be used, but other wet etchants such as phosphoric acid may also be used. As further described below, in some implementations, the SiN layer may have multiple sub-layers with different WERs.

[0041] Figure 1A The method may be performed as part of a method of forming a 3D NAND structure. Figure 1B A process flow diagram is shown according to operations performed in a method for forming a 3D NAND structure. In operation 182, a substrate is provided. In various embodiments, the substrate is a semiconductor substrate. The substrate can be a silicon wafer, such as a 200-mm wafer, a 300-mm wafer, a 450-mm wafer, or a wafer having one or more material layers (e.g., dielectric, conductive, or semiconductive materials) deposited thereon. The exemplary substrate 100 is formed in Figure 2 Provided as a schematic diagram.

[0042] It should be noted that although the following description primarily refers to a 3D NAND structure with tungsten wordlines and vias, other metals may be used. For example, molybdenum (Mo) may be deposited to form the wordlines and vias.

[0043] return Figure 1B In operation 184, a film stack of alternating oxide and nitride films is deposited on the substrate. In various embodiments, the deposited oxide layer is a silicon oxide layer. In various embodiments, the deposited nitride layer is a silicon nitride layer.

[0044] Each oxide layer and nitride layer can be deposited to approximately the same thickness, for example, between about 10 nm and about 100 nm, for example, in some embodiments, between about 25 nm and 35 nm. The oxide layer can be deposited at a deposition temperature between about room temperature and about 700° C. It should be understood that “deposition temperature” (or “substrate temperature”) as used herein refers to the temperature set by the pedestal that holds the substrate during deposition.

[0045] The oxide and nitride layers used to form the alternating oxide and nitride film stack can be deposited using any suitable technique, such as ALD, PEALD, chemical vapor deposition (CVD), PECVD, or sputtering. In various embodiments, the oxide and nitride layers are deposited by PECVD.

[0046] For example, a film stack may include between 48 and 512 alternating oxide and nitride layers, with more alternating layers possible. Each oxide or nitride layer constitutes one layer. A film stack including alternating oxide and nitride layers may be referred to as an oxide-nitride-oxide-nitride (ONON) stack.

[0047] Figure 3 An exemplary schematic diagram of a substrate 100 is shown on which alternating oxide 101 and nitride 102 films are deposited. Note that although Figure 3 The structure shown in shows that oxide is deposited first, followed by nitride, oxide, nitride, etc., but nitride may be deposited first and then oxide, nitride, oxide, etc., in sequence.

[0048] After depositing the ONON stack, refer to Figure 1B , in operation 186, a stair-like pattern is formed on the substrate. The "stair-like pattern" referred to herein depicts two or more steps, each step comprising an oxide layer and a nitride layer. It should be understood that the top layer of each set of oxide layers and nitride layers can be an oxide layer or a nitride layer for forming steps in the steps. In various embodiments, the stair-like pattern includes between 24 and 256 steps. The stair-like pattern can be formed using various patterning techniques. One technique includes depositing a sacrificial layer on the substrate and masking an area of ​​the substrate to etch each set of oxide layers and nitride layers to form steps. Other techniques include patterning a photoresist, etching, trimming the photoresist, and then repeating the etching and trimming operations until the photoresist is too thin to be used again.

[0049] Figure 4A An example of a substrate 100 is provided that includes a stair-step pattern of oxide layers 111 and nitride layers 112 with a hard mask 110 on the topmost nitride layer. Figure 4A Four steps of the staircase pattern are shown, but it should be understood that the staircase pattern can have any number of steps, for example, between 24 and 256 steps. Each step includes a nitride layer and an oxide layer. The area of ​​each step that extends outward from the edge of the step above the step can be referred to as the "exposed" area of ​​the step or the uppermost layer of the step, or the portion suitable for deposition thereon. As shown in the figure, this exposed area is nitride.

[0050] exist Figure 4B Shown in Figure 4A A view 199 of the staircase pattern shown in FIG. 2 is bisected, for example, along the width of the staircase, to highlight the layered structure of the staircase pattern. The oxide layer 111 is parallel to and located between the nitride layer 112. Each set of oxide layers 111 and subsequent nitride layers 112 is longer than the set immediately above, thereby forming a staircase pattern with exposed areas.

[0051] In some embodiments, Figure 1B In operation 188, an oxide is deposited on the substrate. The oxide may have the same or a different composition than the oxide deposited in the layers of the ONON stack. In various embodiments, the oxide deposited on the substrate is deposited at a deposition temperature that is the same as or different from the deposition temperature used to deposit the oxide layer in the ONON stack. The deposition temperature may be between room temperature and approximately 600° C. Vertical slits are then etched into the substrate after the oxide is deposited and planarized.

[0052] Figure 5A An exemplary substrate 100 is shown including an ONON step, a hard mask 110, and an oxide 122 deposited thereon. Figure 5B A side view of the substrate 100 is shown after etching the vertical slits 135 and removing the hard mask 110 .

[0053] In operation 190, the nitride is selectively etched relative to the oxide on the substrate. The etching can be performed using a selective dry etching process, for example, by exposing the substrate to any one or more of the following gases: chlorine (Cl2), oxygen (O2), nitrous oxide (N2O), tetrafluoromethane (CF4), sulfur tetrafluoride (SF4), carbon dioxide (CO2), fluoromethane (CH3F), nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), ammonia (NH3), methane (CH4), sulfur hexafluoride (SF6), argon (Ar), carbonyl sulfide (COS), carbon disulfide (CS2), hydrogen sulfide (H2S), and nitric oxide (NO). Operation 190 removes the nitride layer from the ONON stack, causing the etching species to flow into the vertical gaps formed in the stair-step pattern and selectively etch the nitride. It should be understood that selective etching involves etching the first material at a faster rate than the second material. For example, selectively etching the nitride relative to the oxide means etching the nitride at a faster rate than the oxide. The nitride can be selectively etched using a wet etch process, for example by exposing the substrate to phosphoric acid (H3PO4), diluted hydrofluoric acid ("DHF"), or a mixture of these solutions. However, selectively removing the nitride carries the risk of degradation and removal of oxide material at various interfaces, such as the oxide-oxide interface at the end of each step. This is further described below. Figure 6A describe.

[0054] Figure 6A An exemplary schematic diagram of substrate 100 is shown having a horizontal gap 132 formed by etching nitride layer 112. As shown in the enlarged view depicted in the circle at 170, a gap 134 is formed at the oxide-oxide interface as etching species flows into gap 132 and etches away the oxide during the etching operation. Figure 6B A side view of a cross section of the substrate is shown whereby gaps 132 are formed by selectively etching the nitride.

[0055] return Figure 1B In operation 192, tungsten is deposited into the gaps in the substrate to form tungsten wordlines. The tungsten may be deposited by any suitable technique, such as ALD, CVD, PEALD, and PECVD. One or more additional layers may be deposited prior to depositing the bulk tungsten. For example, an aluminum oxide (Al2O3) layer may be deposited as a barrier oxide, followed by a titanium nitride (TiN) barrier layer, and a tungsten nucleation layer.

[0056] Figure 7AAn example of a substrate 100 is shown including deposited tungsten wordlines 140. However, due to degradation of the oxide at the oxide-oxide interface, as shown in the magnified view at 170, tungsten fills in the gap at 141, thereby connecting the two wordlines 140, potentially causing a short circuit. Figure 7B A schematic diagram of a cross-section of the substrate of 7A in side view is shown, with tungsten 140 deposited in the gaps where the nitride previously was.

[0057] return Figure 1B The oxide is vertically etched to form vias in operation 194. The oxide may be etched by dry etching using exposure to an etchant, such as one or more of the following gases: O2, Ar, C4F6, C4F8, SF6, CHF3, and CF4. Figure 8 An exemplary substrate 100 including an ONON stack in a stair-like pattern is shown, whereby vias 137 are etched in oxide 122. However, due to the relative thinness of the tungsten wordline layer and the long etch duration used to ensure sufficient vertical etching to etch the deepest vias (e.g., 137b), etching species flow into the vias etched for the shallow portion of the oxide (e.g., 137a), thereby etching through the tungsten layer 136 and even through another oxide layer 138. As previously described, this phenomenon is generally undesirable and is referred to as "punch-through" or "breakthrough" with respect to layers located below the intended tungsten wordline contact or layer.

[0058] exist Figure 1B In operation 196, tungsten is deposited in the vias to form interconnects with the tungsten word lines. Figure 9 As shown, since the shallow vias break through to the underlying layers due to the duration used to etch the deep vias, tungsten fills the vias (see tungsten filled vias 142) and results in Figure 9 The vias can be formed by a short circuit in 172 turns of the circuit. The depth of the vias varies and can have a depth between about 1 micron and about 14 microns, or deeper. Shallow vias are at the top and can have a depth of less than 100 nm. Deep vias can have a depth greater than 3.0 microns. The critical dimension of the vias formed in the oxide can be between about 50 nm and about 500 nm. The vias can be etched using a dry etch process that can involve masking to pattern the oxide.

[0059] Challenges in forming 3D NAND structures include punch-through of tungsten wordlines when etching vias of varying depths. Extensive etching techniques, which use various chemistries and patterning to mask areas of the substrate to etch vias of varying depths, can reduce yield and lower process efficiency.

[0060] This article provides a method and apparatus for forming 3D NAND to address these challenges. The method involves depositing SiN on exposed horizontal portions of a staircase-shaped nitride layer to form SiN pads. A wet etch process is performed to etch the material deposited on the exposed nitride and oxide sidewall surfaces. The staircase-shaped nitride layer and the SiN pads formed on each nitride layer are selectively etched relative to the oxide layer to form horizontal gaps and blank areas corresponding to the positions of the SiN pads. Tungsten fills the horizontal gaps and blank areas to form tungsten wordlines and landing pads on the wordlines. Each landing pad has a sufficient thickness to serve as an etch stop layer or protective barrier layer to prevent interconnects from penetrating the tungsten wordlines.

[0061] Figure 10 is a process flow diagram of the operations of a method performed according to some embodiments. Figure 10 The method shown results in the formation of landing pads at operation 1014. The thickness of each landing pad provides continuous protection to prevent interconnects from punching through the word lines formed with the landing pads at operation 1014. In some embodiments, operations 1002 and 1004 can be respectively performed in conjunction with the previously described operations. Figure 1B Operation 1006 is similar to or the same as operation 182 and 184 presented in FIG. 1006 is similar to ... Figure 1B The operation 186 is the same or similar.

[0062] Before depositing oxide on the stair-shaped pattern in operation 1010, SiN is selectively formed on the exposed horizontal surface of the nitride layer of the stair-shaped pattern in each nitride layer in operation 1008 to form a SiN pad. Figure 1A Further examples of selective SiN formation are described below.

[0063] After operation 1008, an oxide (also referred to as an oxide filler) is deposited on the stair-step pattern, including the SiN pad formed on the nitride layer at operation 1010. In operation 1012, the nitride layer is selectively etched relative to the oxide layer and the oxide filler, the nitride layer having the SiN pad extending from each nitride layer to create a gap between the oxide layers in the stair-step pattern similar to Figure 6A and 6B The horizontal gap is then filled with tungsten in operation 1014 by a gap-fill operation to form a tungsten word line and replace the SiN pad with a tungsten landing pad. Figure 14 As shown, a landing pad is formed on the word line, for example, landing pad 180 is formed on word line 140. Figure 1BThis operation may be performed using any of the techniques or processing conditions described in operation 192. During the formation of the tungsten wordline, during operation 1018, the empty areas created by etching the SiN pads are filled with tungsten to form landing pads on the tungsten wordlines.

[0064] Then, in operation 1016, the oxide 122 is then etched to form a via. Figure 8 Similar to the example shown, vias are etched vertically through the oxide to contact and terminate at landing pads extending from the word lines. Thus, multiple vias extend to each of the landing pads formed on the staircase pattern. Forming longer vias near the bottom of the staircase pattern to contact the word lines may require a relatively longer etch duration compared to the time required to form shorter vias near the top of the staircase pattern to contact the word lines. Consequently, the extended etch duration used to form the long vias extending to the word lines near the bottom of the staircase pattern may cause the vias intended to contact the word lines at the top of the staircase pattern to punch through the word lines. Figure 10 The process shown in prevents such punch-through of the via through the word line by forming a landing pad on each word line. Each landing pad provides additional material to prevent punch-through prior to punching through the word line on which the landing pad is formed.

[0065] At operation 1018 , tungsten is deposited into the via to form an interconnect that extends through the oxide fill to contact the landing pad. In addition to providing protection from punch-through of the via through the word line, the landing pad also prevents punch-through of the interconnect through the word line at operation 1020 .

[0066] Figure 10 Operation 1008 is further shown and described in Figure 11-18In some embodiments, operation 1008 involves a PECVD process. A PECVD process is different from a high-density plasma chemical vapor deposition (HDP CVD) process. A PECVD process uses a capacitively coupled plasma (CCP); an HDP CVD process uses an inductively coupled plasma. The processing conditions for an inductively coupled HDP CVD process, and the resulting film, are different from those for a capacitively coupled PECVD process. In a CCP process, the plasma is ignited between two electrodes. In an ICP process, RF is applied to one end of a coil while the other end is maintained at ground. The current flowing through the coil assists in generating the plasma. Exemplary frequencies used in HDP reactors are a 400 kHz plasma frequency for the coil and a 13.56 MHz frequency for the susceptor (on which the wafer is placed). In a PECVD process, exemplary frequencies applied to either the showerhead or susceptor electrode can be as high as 100 MHz, such as 13.56 MHz or 27 MHz. A low frequency RF (e.g., 400 kHz) can be applied to the other of the showerhead or susceptor electrodes. In some implementations, RF power is pulsed during the PECVD process to improve step coverage.

[0067] The plasmas produced are different, with ion density and ion energy distribution being the main differences. For example, HDP reactors have more than 10 11 ions / cm 3 The plasma density is higher than that of PECVD reactors. HDP usually has a tighter ion energy distribution.

[0068] In a capacitively coupled plasma reactor, a plasma frequency of 13.56 MHz is used to generate the applied plasma. The ion energy in an HDP reactor can be greater than that in a PECVD reactor. Therefore, the composition and properties of the films deposited in an HDP CVD reactor differ from those deposited in a PECVD reactor.

[0069] As about Figure 10 As discussed in operation 1008 of FIG. 1 , SiN may be formed to be deposited to form a SiN pad on the exposed horizontal nitride surface by flowing a silicon-containing precursor and a nitrogen source into the PECVD chamber. Figure 11 An example of a conformal SiN layer 1120 deposited on a stepped structure is shown. Figure 11 In the example of FIG, the stepped structure includes multiple pairs of oxide / nitride layers. The method can also be applied to a stepped structure including a single pair of steps. Figure 12 The conformal SiN layer 1120 after treatment is shown, where the sidewall SiN 1122 has a higher WER than the horizontal surface of the SiN.

[0070] The SiN layer is conformal because it is deposited on both horizontal and vertical surfaces of the structure. High step coverage (e.g., the ratio of sidewall thickness to horizontal thickness) can promote good separation of the pad from the sidewall during subsequent etching. In some embodiments, the ratio of sidewall to horizontal thickness (as an average for the structure or a particular step) is at least 0.7 (70% step coverage) or 0.8 (80% step coverage). If an ALD process is used, the step coverage can approach or be 100%. For the PECVD process described herein, step coverage of at least 70% to 90% can be achieved.

[0071] Figure 13 A SiN pad 182 is shown extending from each nitride layer 112. Each SiN pad 182 is spaced apart from the oxide sidewall surface 128 such that each SiN pad forms a notch on the end of its nitride layer 112.

[0072] Next, refer to Figure 14 , the nitride layer 112 and the SiN pad 182 deposited thereon are etched relative to the oxide on the substrate. Figure 1B As shown, etching is performed substantially as described in operation 190 to remove the nitride layer 112 by passing an etchant species vertically through the slits in the ONON stack, such that the etchant species flows into the vertical slits and selectively etches the nitride. The nitride can be selectively etched using a wet etching process, such as by exposing the substrate to phosphoric acid (H3PO4) or dilute hydrofluoric acid ("DHF") or a mixture of these solutions. For example, Figure 6A An exemplary schematic diagram of a substrate 100 having a horizontal gap 132 formed by etching nitride is shown.

[0073] After selectively etching the nitride and SiN pads 182 found in the nitride layer 112, tungsten is deposited into the gaps in the substrate to form tungsten word lines 140 and landing pads 180, respectively. Figure 14 As shown. Horizontal gap (similar to Figure 6A The gap 132 shown is filled with tungsten to form a tungsten word line. Similarly, the gap created by etching the SiN pad 182 is filled with tungsten to form the landing pad 180. Figure 8 and 9 As generally shown and discussed, oxide 122 is vertically etched to form vias, which are then filled with tungsten to form interconnects 142, as shown. Figure 15 As shown. Figure 1B As described in operation 194 , the oxide 122 may be etched by dry etching by exposure to any one or more of the following gases: O 2 , Ar, C 4 F 6 , C 4 F 8 , SF 6 , CHF 3 , and CF 4 .

[0074] As mentioned above and Figure 14 As shown, the formation of landing pad 182 prevents Figure 9 The depth of the landing pad 182 on each word line 140 provides additional tungsten that the interconnect 142 must pass through before punching through to the underlying word line 140, as shown. Figure 15 Thus, the use of landing pads 182 greatly reduces the likelihood of a punch-through condition, thereby preserving the overall structural integrity of the ONON stack.

[0075] In some embodiments, the SiN layer may include two or more sub-layers. One of these sub-layers may have a very low WER (e.g., no more than / minute) and is referred to as an etch stop (ES) layer. Another of these sub-layers may have a higher etch rate (e.g., greater than 100 Å) for rapid sidewall removal and separation. / minute, greater than / minute, or more / minute). Figure 16 Examples of stacks including different sublayers. At 1610, a stack including sublayers 1601, 1602, 1603, and 1604 is shown. Sublayer 1602 is an ES layer, which has a lower WER than sublayers 1601, 1603, and 1604. At 1620, a stack includes layers 1601, 1602, and 1603, where sublayer 1602 is an ES layer. In some embodiments, the ES layer is the topmost layer shown at 1630 and 1640, where sublayer 1601 is an ES layer. The ES layer can be the bottom layer, however, it is advantageous to have non-ES layers make up the bulk of the remaining SiN thickness because they form faster.

[0076] The ES layer may represent a small fraction of the overall thickness of the deposited SiN layer. It can only be Use of such a sub-layer may enable higher WERs to be used for other layers in the stack to achieve fast sidewall removal and spacing from the sidewalls.

[0077] exist Figure 16, any two of the sublayers 1601, 1602, 1603, and 1604 may have the same or different WERs. Each sublayer may also be characterized by its refractive index (RI) at 633 nm. Different WERs and / or RIs may be achieved by appropriately varying the processing operations. A lower WER may be achieved by utilizing one or more of the following: a longer processing time and, for CCP processing, the addition of low frequency (LF) power to generate the processing plasma. The chamber pressure during processing may also be reduced to lower the WER. Deposition conditions may also be used to achieve a specific WER. For example, during PECVD deposition of SiN from SiH4 and NH3, lowering the temperature and reducing the N2 carrier gas flow rate may increase the WER. Thus, in one example, the stack shown at 1610 may be:

[0078] Sublayer 1604—greater than WER / minute;

[0079] Sublayers 1603 and 1601—greater than WER / minute;

[0080] Sublayer 1602 (ES)—less than WER / minute

[0081] In some embodiments, one or more sub-layers can be deposited without post-processing for high WER.

[0082] Differential etch rates can also be achieved by varying the gas composition, RF frequency, showerhead-pedestal gap, and temperature. Just like the total thickness (before etching), the WER of the SiN layer (or, if applicable, each sublayer) can be determined by the following goals: 1) the remaining SiN thickness on horizontal surfaces after wet etching (which determines the thickness of the tungsten landing pad); 2) the minimum distance of the SiN from the sidewalls of the step structure; and 3) the lack of overetching to achieve 1) and 2). Figure 17 An example of a SiN pad after deposition and processing is shown. The spacing (S) and thickness (T) are labeled. In some embodiments, S can be between 10 nm and 60 nm, while T can be between 10 nm and 40 nm. This can be achieved without overetching (i.e., without etching the SiN away from the top of the structure).

[0083] Figure 18 An example of forming a SiN layer having a three-layer structure, as shown at 1620, includes an ES layer sandwiched between two higher WER layers. A person skilled in the art will understand how to modify Figure 18The method begins at 1802 by depositing a first portion of a silicon nitride film. This first portion is typically thin enough so that it does not exceed the penetration depth of subsequent processing. Exemplary thicknesses may be between However, it should be understood that this thickness depends on the specific process. As described above, deposition conditions can be modified to achieve a specific WER. Deposition conditions include substrate temperature, chamber pressure, reactant and carrier gas composition and flow rates, and HF / LF power. For PECVD, exemplary temperatures can range from 100°C to 600°C; exemplary pressures can range from 5 Torr to 20 Torr (relatively high for PECVD); and exemplary deposition chemistries are SiH4 and NH3, with carrier gases of Ar, N2, and / or He.

[0084] The deposited film is then treated at 1804 using first processing conditions. For CCP plasma processing, the processing conditions may include processing time, chamber pressure, HF / LF power, and processing gas composition and flow rate. Exemplary processing time can be between 1-30 seconds, such as between 5-20 seconds; exemplary pressure can be between 1-20 Torr, such as between 3-10 Torr; exemplary HF power can be between 500W-1500W; exemplary LF power can be 0, or up to 500W in some cases; exemplary processing gases include Ar and He, each having a flow rate between 1000-10000 seem. It should be understood that the deposition and processing conditions may fall outside the above ranges. In some embodiments, there may be no post-deposition processing time for this layer.

[0085] In some embodiments, operation 1804 may be performed without LF power to achieve a relatively high WER. This may facilitate the final etching of the SiN pad. Exemplary process times may be between 5-10 seconds, inclusive. Operations 1802 and 1804 may be repeated multiple times to form the bottom sublayer. In an example, this may be repeated to deposit between If the deposition amount in operation 1802 is This can be achieved with 5-20 repetitions.

[0086] Next, in operation 1808, a portion of the silicon nitride film is deposited. The deposition conditions may be as described above with respect to operation 1802. Next, at 1810, the portion is treated using a second processing condition. The second processing condition is different from the first processing condition because the value of one or more conditions is changed to change the WER. In this example, operations 1808 and 1810 form a portion of the ES layer and reduce the WER. In some embodiments, this involves adding (or increasing) the LF power and increasing the processing time or both. The processing gas flow rate may also be reduced and / or the pressure may be reduced. An exemplary processing time may be between 15-25 seconds (inclusive). In operation 1812, operations 1808 and 1810 may be repeated one or more times to form the ES sublayer. In an example, this may be repeated to deposit between It should be noted that in this example the ES layer is significantly thinner than the bottom sublayer. In the case where the full thickness is deposited in operation 1808, operation 1812 is omitted.

[0087] Next, at 1814, a portion of the silicon nitride film is deposited. The deposition conditions may be as described above for operation 1802. Next, at 1816, the portion is treated using a third processing condition. The third processing condition differs from the second processing condition in that the values ​​of one or more conditions are changed to change the WER, but the values ​​of the one or more conditions may be the same as or different from the first processing condition. In some embodiments, the WER is relatively high to result in rapid removal and spacing from the sidewalls. Exemplary processing times may be between 1-30 seconds, such as between 5-20 seconds; exemplary pressures may be between 1-20 Torr, such as between 3-10 Torr; exemplary HF powers may be between 500W-1500W; exemplary LF powers may be 0, or as high as 500W in some cases; exemplary processing gases include Ar and He, each having a flow rate between 1000-10000sccm. Operations 1816 and 1818 are repeated multiple times to form the top sublayer. In one example, they may be repeated to deposit between The sublayers between.

[0088] In some embodiments, one or more sub-layers that are not ES layers can be deposited without post-deposition treatment. In such cases, the sub-layer deposition can be performed in a single step without cycling between deposition and treatment.

[0089] In some embodiments, the thickness of one or more sub-layers below the ES layer is at or near a target thickness. For example, for a target thickness of 20 nm, layer 1603 (at 1620 and 1630), or layers 1603 and 1604 (at 1610), can be a total of 20 nm thick or near 20 nm.

[0090] Example

[0091] PECVD deposition conditions were varied to change the WER in 100:1 DHF. Post-deposition treatment was held constant (10 seconds, 5.5 Torr, HF / LF 1000 / 0 Watts, 10,000 sccm Ar / 4,000 sccm He). For both deposition processes A and B, the chamber pressure was 9 Torr, HF / LF 575 / 0 Watts, with SiH4 and NH3 process gases.

[0092] Process A used a substrate temperature of 550°C and a carrier gas of 10,000 sccm Ar / 6,000 sccm N2. Process B used a substrate temperature of 510°C and a carrier gas of 10,000 sccm Ar / 3,000 sccm N2 / 3,000 sccm He (3,000 sccm He was added to maintain the same total flow as Process A). The WER of Process A was / min. The WER of treatment B is / minute.

[0093] Process B PECVD deposition was used to form the ES layer. The process time was increased to 20 seconds (two 10-second cycles) and the pressure was reduced to 4 Torr. The HF / LF power was 800 / 300 watts (LF power was added). The gas flow rate was reduced to 3000 sccm Ar / 2000 sccm He. The WER was / minute.

[0094] Figure 19 shows the pitch and remaining thickness versus etch time for a SiN stack comprising the above-described The ES layer is sandwiched between layers formed as described in Process B. The results indicate that the ES layer maintains a residual thickness as the spacing is rapidly generated.

[0095] equipment

[0096] Suitable apparatus for performing the disclosed methods generally include hardware for performing the processing operations and instructions for a system controller for controlling the processing operations according to the methods described above.

[0097] Figure 20A block diagram of an exemplary apparatus that can be used to practice the disclosed embodiments is provided. As shown, reactor 2000 includes a process chamber 2024 that surrounds the other components of the reactor and is used to contain a plasma generated by, for example, a capacitor-type system including a showerhead 2014 operating in conjunction with a grounded heater block 2020. A high-frequency RF generator 2002 (which is connected to a matching network 2006) and a low-frequency RF generator 2004 are connected to showerhead 2014. The power and frequency supplied by matching network 2006 are sufficient to generate a plasma from the process gas, for example, 400-700W of total power. In one embodiment, both the HFRF generator and the LFRF generator are used to process the ES layer, with only the HFRF generator being used for PECVD deposition and processing of the other layers. In typical processing, the high-frequency RF component is typically between about 2-60 MHz; in specific embodiments, the HF component is about 13.56 MHz or 27 MHz. The low frequency LF component is typically between about 250-400 kHz: and in a particular embodiment, the LF component is about 350 kHz.

[0098] Inside the reactor, a susceptor 2018 supports a substrate 2016. The susceptor typically includes a chuck, fork, or lift pins to hold and transport the substrate during and between deposition and / or plasma processing reactions. The chuck can be an electrostatic chuck, a mechanical chuck, or various other types of chucks used in industry and / or research.

[0099] Process gases are introduced through inlet 2012. Gas lines 2010 from multiple sources are connected to manifold 2008. The gases may or may not be premixed. Appropriate valves and mass flow control mechanisms are used to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. In the case where the chemical precursors are delivered in liquid form, liquid flow control mechanisms are used. Subsequently, while the liquid is transported through the manifold, it is heated above its vaporization point before reaching the deposition chamber to vaporize the liquid and mix with the other process gases.

[0100] The process gas leaves the chamber 2000 through an outlet 2022. A vacuum pump 2026 (e.g., a primary or secondary mechanical dry pump and / or a turbomolecular pump) is used to draw the process gas through a closed-loop controlled flow restriction (e.g., a throttle valve or a pendulum valve) and maintain a suitable low pressure within the reactor.

[0101] The method can be implemented on a multi-station or single-station tool. Vector available from Lam Research (Fremont California) TMThe tool has multiple stations. After each deposition and / or post-deposition plasma treatment, the wafer can be indexed until all depositions and treatments are complete; or multiple depositions and treatments can be performed at a single station before the wafer is indexed.

[0102] In some embodiments, Figure 20 The reactor shown is part of a tool for processing one or more wafers. Figure 21 Examples of tools comprising one or more reactors are provided in . Figure 21 is a block diagram of a processing system suitable for performing deposition processing according to the disclosed embodiments. The system 2100 includes a transport module 2103, such as a Vector ® ® ® ® ® ® , available from Lam Research Corporation (Fremont, California). TM Wafer Transfer System (WTS) used on the platform. The transfer module 2103 provides a clean, pressurized environment to minimize the risk of contamination of workpieces such as wafers as they move between various processing stages.

[0103] Mounted on the transport module 2103 is a chamber 2109 capable of performing PECVD processing. Chamber 2109 may include a plurality of stations 2111, 2113, 2115, and 2117, which may perform deposition or treatment operations sequentially. System 2100 also includes one or more (two in this example) wafer source modules 2101, which store wafers before and after processing. A load lock 2119 is located between the transport module 2103 and the wafer source module 2101. A device within the transport module 2103 (typically a robotic arm unit) moves wafers between modules mounted on the transport module 2103. Additional modules 2105 and 2107 may be mounted on the transport module. These may be, for example, deposition, etching, or treatment modules. Figure 21 Also depicted is an embodiment of a system controller 2150 that is employed to control the processing conditions and hardware states of the processing tool 2100. The system controller 2150 may provide program instructions for implementing the above-described processes. The program instructions may control various processing parameters, such as RF power levels, pressure, temperature, flow rates, etc.

[0104] In some implementations, the controller 2150 is part of a system, which can be part of the examples described above. Such a system can include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics can be referred to as a "controller" that can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the controller 2150 can be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transport in and out of tools and other transport tools and / or load locks connected to or interfaced with a particular system.

[0105] In general, the controller 2150 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions delivered to the controller or system in the form of various separate settings (or program files) that define operating parameters for performing a specific process on or for a semiconductor wafer. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to accomplish one or more process steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or the die of the wafer.

[0106] In some embodiments, the system controller 2150 controls all activities of the processing tool 2100. The system controller 2150 may include one or more memory devices 2156, one or more mass storage devices 2154, and one or more processors 2152. The processor 2152 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc. The system controller 2150 executes system control software 2158 stored in the mass storage device 2154, loaded into the memory device 2156, and executed on the processor 2152. Alternatively, the control logic may be hard-coded in the controller 2150. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays or FPGAs), etc. may be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally comparable hard-coded logic may be used therein. The system control software 2158 may include parameters for controlling the transport of wafers into and out of the processing chamber, the timing of gases, the mixing of gases, the amount of gas flow, chamber and / or station pressure, backside gas flow pressure, chamber and / or reactor temperature, wafer temperature, bias power, target power level, RF power level, pedestal, chuck and / or sensor position, and other parameters for the specific process performed by the process tool 2100. The system control software 2158 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components necessary to perform the various process tool processes. The system control software 2158 may be encoded in any suitable computer-readable programming language.

[0107] In some implementations, the controller 2150 can be part of or coupled to a computer that is integrated with, coupled to, or connected to the system via a network, or a combination thereof. For example, the controller 2150 can be in the "cloud" or all or part of a mainframe system in a wafer fab, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current process of a manufacturing operation, review the history of past manufacturing operations, review trends or performance metrics across multiple manufacturing operations, change parameters of a current process, set process steps to follow the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that allows for input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller 2150 receives instructions in the form of data that specify parameters for each process step to be performed during one or more operations. It should be understood that these parameters can be specific to the type of process to be performed and the type of tool with which the controller 2150 is configured to interface or control. Thus, as described above, the controller 2150 can be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common goal (e.g., processing and control as described herein). Examples of distributed controllers for these purposes can be one or more integrated circuits within the room that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the processing within the room.

[0108] In some embodiments, the system control software 2158 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on the mass storage device 2154 and / or the memory device 2156 associated with the system controller 2150 may be employed. Examples of programs or program segments used for this purpose include wafer positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0109] The wafer positioning program may include program code for process tool components that is used to load the wafer onto the susceptor 2118 and control the spacing between the wafer and other parts of the process tool 2100. The process gas control program may include code that is used to control gas composition (e.g., deposition gas, process gas, carrier gas, etc.) and flow rates, and optionally to flow gas into one or more process stations prior to deposition to stabilize the pressure in the process station. The pressure control program may include code that is used to control the pressure in the process station by adjusting, for example, a throttle valve in the exhaust system of the process station, the gas flow into the process station, or the like.

[0110] The heater control program may include code for controlling the flow of current to a heating element for heating a workpiece. Alternatively, the heater control program may control the delivery of a heat transfer gas (e.g., helium) to the wafer. According to embodiments herein, the plasma control program may include code for setting the RF power level applied to the process electrode and, if appropriate, the bias in one or more process stations. According to embodiments herein, the pressure control program may include code for maintaining the pressure in the reaction chamber.

[0111] In some embodiments, there may be a user interface associated with the system controller 2150. The user interface may include a display screen, a graphical software display of device and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0112] In some embodiments, the parameters regulated by the system controller 2150 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF power level), pressure, temperature, etc. These parameters may be provided to the user in the form of a recipe, which may be entered using the user interface.

[0113] Signals for monitoring the process can be provided from various process tool sensors via analog and / or digital input connections of the system controller 2150. Signals for controlling the process can be output via analog and / or digital output connections of the process tool 2100. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, and the like. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain process conditions.

[0114] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0115] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in the material transport of wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0116] in conclusion

[0117] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the embodiments. Therefore, the embodiments herein are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A method comprising: providing a substrate having alternating oxide and nitride layers arranged in a stair-step pattern, the stair-step pattern including exposed horizontal nitride surfaces and exposed oxide and nitride sidewall surfaces; depositing silicon nitride (SiN) layers on the alternating oxide and nitride layers by a plasma enhanced chemical vapor deposition (PECVD) process using plasma generated from a process gas containing a silicon-containing precursor; and treating the SiN layer to selectively densify the SiN layer deposited on the exposed horizontal nitride surface, The SiN layer includes a first sublayer, the first sublayer is disposed between two second sublayers, and each second sublayer has a higher wet etching rate (WER) than the first sublayer. 2 . The method according to claim 1 , further comprising wet etching the treated SiN layer to form a separate SiN pad. The method of claim 1 , wherein the deposition and treatment operations are performed in the same chamber.

4. The method of claim 1 , wherein processing the SiN layer comprises: The substrate is exposed to the generated capacitively coupled plasma.

5. The method of claim 1 , wherein performing the depositing and treating operations comprises: A plurality of cycles are performed of depositing a conformal portion of the SiN layer followed by processing the deposited portion. The method of claim 1 , wherein the first sub-layer has a WER of no more than 50 Å / min in a wet etchant. 7 . The method of claim 1 , wherein at least one of the two second sub-layers is a sub-layer having a WER of at least 100 Å / min in a wet etchant. The method of claim 6 , wherein each of the two second sub-layers is thicker than the first sub-layer.

9. The method of claim 1, wherein the SiN layer is deposited from silane SiH4 and ammonia NH3.

10. The method of claim 9, wherein the SiH4 and NH3 are in a process gas further comprising nitrogen (N2). The method of claim 2 , wherein the distance between the adjacent sidewall surface and the separated SiN pad is at least 10 nm.

12. The method of claim 2, wherein the separate SiN pad is at least 10 nm thick.

13. The method of claim 2, further comprising replacing the SiN pad with a tungsten landing pad. The method of claim 1 , wherein treating the SiN layer comprises exposing it to a low frequency plasma.

15. The method of claim 1, wherein a chamber pressure during the PECVD process is in a range of 5 to 20 Torr.

16. The method according to claim 1, wherein The SiN layer is processed at a lower pressure than when the SiN layer was deposited.

17. The method of claim 1, further comprising pulsing RF power during the PECVD process. The method of claim 17 , wherein the step coverage of the SiN layer is between 70% and 90%.

19. A method comprising: providing a substrate having alternating oxide and nitride layers arranged in a stair-step pattern, the stair-step pattern including exposed horizontal nitride surfaces and exposed oxide and nitride sidewall surfaces; depositing a silicon nitride (SiN) layer on the horizontal and sidewall surfaces by a plasma enhanced chemical vapor deposition (PECVD) process using a plasma generated from a process gas containing a silicon-containing precursor; as well as The SiN layer is processed to selectively densify the SiN layer deposited on the horizontal surface, wherein a chamber pressure of a chamber containing the substrate during the plasma enhanced chemical vapor deposition of the SiN layer is higher than a chamber pressure during the processing of the SiN layer.

20. The method of claim 19, further comprising wet etching the processed layer to form a separate SiN pad.

21. A method comprising: providing a substrate having a horizontal surface and a sidewall surface; One or more first cycles are performed to form a first sub-layer, each of the one or more first cycles comprising: depositing a certain amount of SiN on the horizontal and sidewall surfaces by PECVD, and exposing the deposited certain amount of SiN to a capacitively coupled plasma generated by an inert gas; performing one or more second cycles to form an etch stop sublayer, each of the one or more second cycles comprising: A certain amount of SiN is deposited on the first sub-layer by PECVD, and the deposited certain amount of SiN is exposed to a capacitively coupled plasma generated by an inert gas using low-frequency radio frequency (LFRF) power, wherein the low-frequency radio frequency power applied during the etching stop sub-layer formation is higher than the low-frequency radio frequency power applied during the formation of the first sub-layer if the low-frequency radio frequency power is applied during the formation of the first sub-layer.

22. The method of claim 21, wherein the LFRF power in the one or more second cycles is greater than the LFRF power in the one or more first cycles, if there is LFRF power in the one or more first cycles.

23. An apparatus comprising: a PECVD deposition chamber comprising an LFRF plasma generator and an HFRF plasma generator; and a controller comprising instructions for executing the method according to claim 1.

24. A method comprising: providing a substrate having alternating oxide and nitride layers arranged in a stair-step pattern, the stair-step pattern including exposed horizontal nitride surfaces and exposed oxide and nitride sidewall surfaces; depositing silicon nitride (SiN) layers on the alternating oxide and nitride layers by a plasma enhanced chemical vapor deposition (PECVD) process using plasma generated from a process gas containing a silicon-containing precursor; and treating the SiN layer to selectively densify the SiN layer deposited on the exposed horizontal nitride surface, wherein the conformal SiN layer comprises a plurality of sub-layers, wherein at least two of the plurality of sub-layers have different wet etch rates (WER), The plurality of sublayers include a first sublayer having a first WER and a second sublayer having a second WER, wherein the second sublayer is deposited on the first sublayer, and wherein the second WER is higher than the first WER.

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