Electronic circuits and bistable circuits

Abstract

An electronic circuit has: a cell array having a plurality of memory cells, each memory cell having a bistable circuit having a first inverter circuit and a second inverter circuit capable of switching between a first mode having a transfer characteristic substantially free of hysteresis and a second mode having a transfer characteristic with hysteresis, an output node and an input node of the first inverter circuit being connected to an input node and an output node, respectively, of the second inverter circuit; and a control circuit that, after powering off one or more first memory cells of the plurality of memory cells in which data can not be retained, sets the bistable circuits within one or more second memory cells of the plurality of memory cells remaining powered on to the second mode, provides a second supply voltage to the bistable circuits within the one or more second memory cells in a state maintaining the second mode, the second supply voltage being lower than a first supply voltage provided to the bistable circuits when reading and / or writing data, the second mode bistable circuits being capable of retaining data at the second supply voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to electronic circuits and bistable circuits, for example to a bistable circuit and an electronic circuit having a plurality of memory cells, wherein the memory cells contain the bistable circuit. BACKGROUND

[0002] There is known a technique (for example, Patent Literature 1) that enables a virtual nonvolatile SRAM (VNR-SRAM) to be configured using only a CMOS (Complementary Metal Oxide Semiconductor) inverter without using a nonvolatile element. In the VNR-SRAM, a dual-mode inverter that can switch between a Schmitt trigger (ST) mode in which an ultralow voltage (ULV) hold is possible and a boost inverter (BI) mode in which a circuit performance equivalent to that of an SRAM is realized at a normal voltage is used. The ULV hold can be used for power gating (PG).

[0003] There is known a memory circuit (for example, Patent Literature 2) that uses a memory cell (NV-SRAM) having a bistable circuit and a nonvolatile element. In the NV-SRAM, data of the bistable circuit is stored in the nonvolatile element, and data of the nonvolatile element is restored to the bistable circuit.

[0004] In the NV-SRAM, there is known a memory circuit (for example, Patent Literature 3) that performs an SRAM (Static Random Access Memory) operation of writing data to and reading data from the bistable circuit as in a normal SRAM, a sleep operation of reducing a power supply voltage and holding data, a storage operation of storing data of the bistable circuit in the nonvolatile element, an off operation of cutting off a power supply of the memory cell, and a restoration operation of rewriting data stored in the nonvolatile storage element to the bistable circuit. By using the storage operation, the off operation, and the restoration operation, it is possible to perform power gating (PG) by power-off without losing the storage contents of the cell.

[0005] There is known a memory circuit (for example, Patent Literature 4) that performs control of skipping storage (free storage operation) when data stored in the bistable circuit coincides with data stored in the nonvolatile element. There is known a technique (for example, Patent Literature 5) that divides a cell array into a plurality of blocks and cuts off power to a block in which the storage operation ends.

[0006] PRIOR ART DOCUMENTS

[0007] PATENT LITERATURE

[0008] Patent Literature 1: International Publication No. 2016 / 158691

[0009] Patent Literature 2: International Publication No. 2009 / 028298

[0010] Patent Literature 3: International Publication No. 2013 / 172066

[0011] Patent Literature 4: International Publication No. 2013 / 172065

[0012] Patent Literature 5: International Publication No. 2016 / 024527 SUMMARY

[0013] PROBLEMS TO BE SOLVED BY THE INVENTION

[0014] In the VNR-SRAM of Patent Literature 1, by performing ULV hold, it is possible to reduce the power during standby without losing the storage contents of the cells. Thereby, it is possible to suppress the power consumption. However, in the VNR-SRAM, after the PG, ULV hold is performed also on the data which is not needed. Therefore, the reduction rate of the energy consumption due to the leakage current at the time of the PG is limited. In addition, in the PG, the switching of the ST mode and the BI mode is performed on all the cells. Therefore, the time (latency) and the energy cost for the mode switching are generated. These leakage current and the energy consumption for the mode switching cause the break-even time (BET) to increase.

[0015] In addition, in the NV-SRAMs of Patent Literatures 4 and 5, by performing the storage-free operation, it is possible to avoid storing the data which is not needed. However, when the storage capacity of the cell array becomes large, the power consumption due to the leakage current generated in the block which is waiting for the storage operation causes the effect of the storage-free to be suppressed. In addition, in the storage-free operation, the storage operation is performed also on the data which has been rewritten at the time of the normal operation although the PG is not needed. Therefore, the unnecessary energy cost and the cost of the latency required for the storage are generated.

[0016] The present application has been achieved in view of the above-described problems, and an object thereof is to suppress the power consumption and the energy consumption.

[0017] MEANS FOR SOLVING THE PROBLEMS

[0018] The present application is an electronic circuit having: a cell array having a plurality of memory cells each having a bistable circuit having a first inverter circuit and a second inverter circuit capable of switching a transfer characteristic from a first mode having substantially no hysteresis and a second mode having a hysteresis, an output node and an input node of the first inverter circuit being connected to an input node and an output node of the second inverter circuit, respectively; and a control circuit which, after powering off one or more first memory cells in which data that can not be held among the plurality of memory cells, sets the bistable circuits in one or more second memory cells remaining among the plurality of memory cells to the second mode, supplies a second power supply voltage to the bistable circuits in the one or more second memory cells in a state in which the second mode is maintained, the second power supply voltage being lower than a first power supply voltage supplied to the bistable circuits at the time of reading and / or writing data, at which the bistable circuits of the second mode can hold data.

[0019] In the above structure, the following structure can also be employed: the cell array is divided into a plurality of blocks each containing at least two memory cells, the control circuit extracts one or more first blocks in which data that can not be held from among the plurality of blocks, and powers off the one or more first blocks, and sets the bistable circuits in one or more second blocks remaining among the plurality of blocks to the second mode, and supplies the second power supply voltage to the bistable circuits in the one or more second blocks in a state in which the second mode is maintained.

[0020] In the above structure, the following structure can also be employed: the control circuit, before setting the bistable circuits in the one or more second blocks to the second mode, supplies a third power supply voltage to the one or more second blocks, the third power supply voltage being lower than the first power supply voltage and higher than the second power supply voltage, at which the bistable circuits of the first mode can hold data.

[0021] In the above structure, the following structure can also be employed: the control circuit, in a state in which the third power supply voltage is supplied to the bistable circuits in the one or more second blocks, sets the bistable circuits in the one or more second blocks to the second mode.

[0022] In the above structure, the following structure can also be employed: the one or more second blocks are a plurality of second blocks, and the control circuit sets the bistable circuits in the one or more third blocks to the second mode in a state in which the third power supply voltage is supplied to the bistable circuits of the one or more third blocks out of the plurality of second blocks, supplies the second power supply voltage in a state in which the bistable circuits in the one or more third blocks are in the second mode, and thereafter sets the bistable circuits in one or more fourth blocks different from the one or more third blocks out of the plurality of second blocks to the second mode in a state in which the third power supply voltage is supplied to the bistable circuits of the one or more fourth blocks, supplies the second power supply voltage in a state in which the bistable circuits in the one or more fourth blocks are in the second mode.

[0023] In the above structure, the following structure can also be employed: the one or more second blocks are a plurality of second blocks, and the control circuit sets the bistable circuits in the plurality of second blocks to the second mode in a state in which the third power supply voltage is supplied to the bistable circuits in the plurality of second blocks, and thereafter supplies the second power supply voltage in a state in which the bistable circuits in the plurality of second blocks are in the second mode.

[0024] In the above structure, the following structure can also be employed: the electronic circuit has a storage circuit provided outside the cell array, which stores information received from an external circuit indicating a block of data that the storage can not hold, and the control circuit extracts the one or more first blocks of data that the storage can not hold in accordance with the information.

[0025] In the above structure, the following structure can also be employed: the first inverter circuit and the second inverter circuit each have a first FET of a first conductivity type whose source is connected to a first power supply line, whose drain is connected to an output node, and whose gate is connected to an input node; a second FET of a second conductivity type opposite to the first conductivity type whose source is connected to a second power supply line, whose drain is connected to an intermediate node, and whose gate is connected to the input node, wherein a power supply voltage is supplied between the second power supply line and the first power supply line; a third FET of the second conductivity type whose source is connected to the intermediate node, whose drain is connected to the output node, and whose gate is connected to the input node; and a fourth FET whose one of a source and a drain is connected to the intermediate node, whose other of the source and the drain is connected to a control node, a gate of the fourth FET of the first inverter circuit is connected to any one of the input node of the first inverter circuit, the output node of the first inverter circuit, the input node of the second inverter circuit, and the output node of the second inverter circuit, a gate of the fourth FET of the second inverter circuit is connected to any one of the input node of the second inverter circuit, the output node of the second inverter circuit, the input node of the first inverter circuit, and the output node of the first inverter circuit, the fourth FET of the first inverter circuit is a FET of the second conductivity type when the gate is connected to the output node of the first inverter circuit or the input node of the second inverter circuit, and is a FET of the first conductivity type when the gate is connected to the input node of the first inverter circuit or the output node of the second inverter circuit, the fourth FET of the second inverter circuit is a FET of the second conductivity type when the gate is connected to the output node of the second inverter circuit or the input node of the first inverter circuit, and is a FET of the first conductivity type when the gate is connected to the input node of the second inverter circuit or the output node of the first inverter circuit.

[0026] In the above structure, the following structure can also be employed: a constant bias voltage is applied to the control nodes of the first inverter circuit and the second inverter circuit, and the first inverter circuit and the second inverter circuit become the first mode when the first power supply voltage is supplied, and become the second mode when the second power supply voltage is supplied.

[0027] The invention is a bistable circuit having: a first inverter circuit and a second inverter circuit, the first inverter circuit and the second inverter circuit each having a first FET of a first conductivity type of channel, a second FET of a second conductivity type of channel opposite to the first conductivity type, a third FET of the second conductivity type of channel, and a fourth FET of the first conductivity type of channel, in the first FET, a source is connected to a first power line, a drain is connected to an output node, and a gate is connected to an input node, in the second FET, a source is connected to a second power line, a drain is connected to an intermediate node, and a gate is connected to the input node, in the third FET, a source is connected to the intermediate node, a drain is connected to the output node, and a gate is connected to the input node, in the fourth FET, one of a source and a drain is connected to the intermediate node, and the other of the source and the drain is connected to a control node, wherein a power supply voltage is supplied between the second power line and the first power line; a first storage node connected to the output node of the first inverter circuit and the input node of the second inverter circuit; and a second storage node connected to the input node of the first inverter circuit and the output node of the second inverter circuit, the gate of the fourth FET of the first inverter circuit is connected to the input node of the first inverter circuit or the output node of the second inverter circuit, and the gate of the fourth FET of the second inverter circuit is connected to the input node of the second inverter circuit or the output node of the first inverter circuit.

[0028] The invention is an electronic circuit having: the above-described bistable circuit; and a power supply circuit that supplies the power supply voltage by switching between a first voltage at which the bistable circuit is able to write and read data and a second voltage lower than the first voltage.

[0029] In the above-described structure, the following structure can also be employed: when the power supply circuit supplies either of the first voltage and the second voltage to the bistable circuit, a constant bias voltage is also supplied to the control node.

[0030] In the above-described structure, the following structure can also be employed: the constant bias voltage is a bias voltage between the voltage of the first power line when the first voltage is supplied and the voltage of the second power line.

[0031] In the above-described structure, the following structure can also be employed: the constant bias voltage is closer to the voltage of the second power line than to a voltage halfway between the voltage of the first power line when the first voltage is supplied and the voltage of the second power line.

[0032] In the above configuration, the following configuration can be employed: when the fourth FET is a P-channel FET, a low level is supplied to the control node when the power supply circuit supplies the first voltage, and a high level higher than the low level is supplied to the control node when the power supply circuit supplies the second voltage, and when the fourth FET is an N-channel FET, a high level is supplied to the control node when the power supply circuit supplies the first voltage, and a low level lower than the high level is supplied to the control node when the power supply circuit supplies the second voltage.

[0033] The present application is an electronic circuit having a bistable circuit and a power supply circuit, the bistable circuit having: a first inverter circuit and a second inverter circuit, the first inverter circuit and the second inverter circuit each having a first FET of a first conductivity type, a second FET of a second conductivity type opposite to the first conductivity type, a third FET of the second conductivity type, and a fourth FET, in the first FET, a source is connected to a first power supply line, a drain is connected to an output node, and a gate is connected to an input node, in the second FET, a source is connected to a second power supply line, a drain is connected to an intermediate node, and a gate is connected to the input node, in the third FET, a source is connected to the intermediate node, a drain is connected to the output node, and a gate is connected to the input node, and in the fourth FET, one of a source and a drain is connected to the intermediate node, and the other of the source and the drain is connected to a control node, wherein a power supply voltage is supplied between the second power supply line and the first power supply line; a first storage node connected to the output node of the first inverter circuit and the input node of the second inverter circuit; and a second storage node connected to the input node of the first inverter circuit and the output node of the second inverter circuit, in the bistable circuit, the gate of the fourth FET of the first inverter circuit is connected to any one of the input node of the first inverter circuit, the output node of the first inverter circuit, the input node of the second inverter circuit, and the output node of the second inverter circuit, and the gate of the fourth FET of the second inverter circuit is connected to any one of the input node of the second inverter circuit, the output node of the second inverter circuit, the input node of the first inverter circuit, and the output node of the first inverter circuit, the power supply circuit supplies the power supply voltage switched between a first voltage and a second voltage lower than the first voltage, at the first voltage, the bistable circuit is capable of writing and reading data, and at the second voltage, the bistable circuit is capable of holding data, and in the electronic circuit, when the power supply circuit supplies any voltage of the first voltage and the second voltage to the bistable circuit, a constant bias voltage is also supplied to the control node.

[0034] In the above structure, the following structure can also be employed: when switching the power supply voltage between the first voltage and the second voltage, the power supply circuit supplies a constant third voltage to the second power supply line, and the voltage supplied to the first power supply line is switched between a fourth voltage and a fifth voltage.

[0035] In the above structure, the following structure can also be employed: the constant bias voltage is a bias voltage between the third voltage and the fourth voltage.

[0036] In the above structure, the following structure can also be employed: the fourth FET of the first inverter circuit is a FET of which the channel is of the second conductivity type when the gate is connected to the output node of the first inverter circuit or the input node of the second inverter circuit, and is a FET of which the channel is of the first conductivity type when the gate is connected to the input node of the first inverter circuit or the output node of the second inverter circuit, and the fourth FET of the second inverter circuit is a FET of which the channel is of the second conductivity type when the gate is connected to the output node of the second inverter circuit or the input node of the first inverter circuit, and is a FET of which the channel is of the first conductivity type when the gate is connected to the input node of the second inverter circuit or the output node of the first inverter circuit.

[0037] The present application is an electronic circuit having: a cell array having a plurality of memory cells each having a bistable circuit that stores data on a volatile basis and a nonvolatile element that stores data stored in the bistable circuit on a nonvolatile basis and restores the data stored on a nonvolatile basis to the bistable circuit; and a control circuit that, when the cell array is powered off, powers off one or more first memory cells of the plurality of memory cells in which data that can not be stored on a nonvolatile basis is stored on a volatile basis regardless of whether or not the data is rewritten on a volatile basis, performs a storage operation of storing data stored in a bistable circuit on a volatile basis in the nonvolatile element in one or more second memory cells of the plurality of memory cells after the one or more first memory cells are powered off, and then powers off the one or more second memory cells.

[0038] In the above structure, the following structure can also be employed: the cell array is divided into a plurality of blocks, each block containing at least two memory cells, the control circuit extracts one or more first blocks in which data that can not be non-volatilely stored is volatilely stored regardless of whether or not the memory cells within the blocks are volatilely rewritten, from among the plurality of blocks, powers off the one or more first blocks, after the one or more first blocks are powered off, performs a storage operation in the memory cells within one or more second blocks remaining among the plurality of blocks, and powers off the second blocks after the storage operation is completed.

[0039] In the above structure, the following structure can also be employed: the control circuit performs a storage operation in the memory cells within the one or more second blocks after the one or more first blocks are all powered off.

[0040] In the above structure, the following structure can also be employed: the electronic circuit has a storage circuit provided outside the cell array, which stores information indicating the one or more first blocks received from an external circuit, and the control circuit extracts the one or more first blocks in accordance with the information.

[0041] In the above structure, the following structure can also be employed: the control circuit extracts, as the one or more first blocks, a block in which data that can not be non-volatilely stored is volatilely stored regardless of whether or not the memory cells within the block are volatilely rewritten and a block in which none of the memory cells within the block is volatilely rewritten, from among the plurality of blocks, powers off the one or more first blocks, after the one or more first blocks are powered off, performs a storage operation in the memory cells within one or more second blocks remaining among the plurality of blocks, and powers off the second blocks after the storage operation is completed.

[0042] Effects of Invention

[0043] According to the present invention, power consumption and energy consumption can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a circuit diagram of the memory cell of Example 1.

[0045] Figure 2 (a) of FIG. 1 and Figure 2 (b) of FIG. 1 is a graph showing voltages applied in each state of Example 1.

[0046] Figure 3 is a graph showing power consumption during each period of Example 1.

[0047] Figure 4 is a block diagram of the electronic circuit of Example 1.

[0048] Figure 5 is a block diagram of the subarray of Embodiment 1.

[0049] Figure 6 is a flowchart showing the operation of Embodiment 1.

[0050] Figure 7 (a) of is a flowchart showing the read / write operation of Embodiment 1, Figure 7 (b) of is a flowchart showing the setting of UDF of Embodiment 1.

[0051] Figure 8 is a flowchart showing the storage operation of Embodiment 1.

[0052] Figure 9 (a) to Figure 9 (d) of is a schematic diagram showing the cell array and the block of Embodiment 1.

[0053] Figure 10 (a) to Figure 10 (c) of is a schematic diagram showing the block of Embodiment 1.

[0054] Figure 11 (a) and Figure 11 (b) of is a diagram showing examples of the size of the cell array and the word address of Embodiment 1, respectively.

[0055] Figure 12 is a block diagram showing an example of the control circuit of Embodiment 1.

[0056] Figure 13 (a) to Figure 13 (e) of is a diagram showing the levels of the respective signals and the operation of the power switch of Embodiment 1.

[0057] Figure 14 is a timing chart of the control signal of Embodiment 1.

[0058] Figure 15 is a block diagram of another example of the control circuit 28 of Embodiment 1.

[0059] Figure 16 (a) to Figure 16 (c) of is a diagram showing the BET with respect to the SFBF storage-free ratio of Embodiment 1, Comparative Example 1-1, and Comparative Example 1-2, Figure 16 (d) to Figure 16 (f) of is a diagram showing the storage latency with respect to the SFBF storage-free ratio.

[0060] Figure 17 is a circuit diagram of the memory cell of Embodiment 2.

[0061] Figure 18 (a) andFigure 18 (b) is a graph showing the voltage applied in each state of Example 2.

[0062] Figure 19 (a) and Figure 19 (b) is a diagram showing the applied voltage for holding and closing in Embodiment 2.

[0063] Figure 20 This is a graph showing the power consumption during each period of Embodiment 2.

[0064] Figure 21 (a) and Figure 21 (b) is another example of the memory cell in Embodiment 2.

[0065] Figure 22 This is a block diagram showing the electronic circuit of Embodiment 2.

[0066] Figure 23 This is a block diagram of the subarray in Embodiment 2.

[0067] Figure 24 This is a flowchart illustrating the operation of Embodiment 2.

[0068] Figure 25 This is a flowchart illustrating type A of the holding action in Embodiment 2.

[0069] Figure 26 (a) to Figure 26 (e) is a schematic diagram showing the cell array of type A of the holding action in embodiment 2.

[0070] Figure 27 (a) to Figure 27 (e) is a schematic diagram showing the cell array and blocks of type A of the holding action in embodiment 2.

[0071] Figure 28 This is a flowchart illustrating type B of the holding action in Embodiment 2.

[0072] Figure 29 (a) to Figure 29 (e) is a schematic diagram showing the cell array of type B of the holding action in embodiment 2.

[0073] Figure 30 (a) to Figure 30 (e) is a schematic diagram showing the cell array and blocks of type B of the holding action in embodiment 2.

[0074] Figure 31 This is a flowchart illustrating type C of the holding action in Embodiment 2.

[0075] Figure 32 (a) to Figure 32(a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0076] Figure 33 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 33 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0077] Figure 34 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0078] Figure 35 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 35 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0079] Figure 36 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0080] Figure 37 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0081] Figure 38 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0082] Figure 39 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 39 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 39 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 39 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0083] Figure 40 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 40 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0084] Figure 41 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0085] Figure 42 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0086] Figure 43 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 43 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.

[0087] Figure 44 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation. Figure 44 (a) to (c) of FIG. 6 are diagrams showing the type C of the cell array of the hold operation.Figure 44 (c) and Figure 44 (d) is a graph showing the leakage power in ST mode.

[0088] Figure 45 This is a circuit diagram of the memory cell of type 2 PS·PDFB at the tail of embodiment 3.

[0089] Figure 46 This is a circuit diagram of the memory cell of type 1 PS·PUFB at the tail of embodiment 3.

[0090] Figure 47 This is a circuit diagram of the memory cell of type 2 PS·PUFB in embodiment 3.

[0091] Figure 48 This is a circuit diagram of the memory cell of the header PS·PUPDFB in Embodiment 3.

[0092] Figure 49 This is a circuit diagram of the memory cell of the tail PS·PUPDFB in Embodiment 3.

[0093] Figure 50 (a) to Figure 50 (f) is a diagram showing the configuration of the power switch connected to the unit.

[0094] Figure 51 (a) to Figure 51 (d) is a diagram showing the configuration of the driver connected to the unit.

[0095] Figure 52 (a) to Figure 52 (c) is a diagram showing the configuration of the driver connected to the unit.

[0096] Figure 53 (a) and Figure 53 (b) is a diagram showing the voltages of the head PS·PDFB·Type 1 and the tail PS·PUFB·Type 1, respectively.

[0097] Figure 54 This is a circuit diagram of the memory cell of type PS, PDFB, type 1 in embodiment 4.

[0098] Figure 55 This is a circuit diagram of the tail PS·PUFB·Type 1 memory cell of Embodiment 4.

[0099] Figure 56 This is a circuit diagram of the memory cell of type 1 on the head PS·PUPDFB·PD side in Embodiment 4.

[0100] Figure 57is a circuit diagram of a memory cell of the tail PS • PUPDFB • PU side type 1 type of Embodiment 4.

[0101] Figure 58 is a circuit diagram of an electronic circuit of Modification 1 of Embodiment 4.

[0102] Figure 59 (a) of FIG. 8 is a graph showing the butterfly curve of the flip-flop circuit, Figure 59 (b) of FIG. 8 is a graph showing the standby power.

[0103] Figure 60 (a) of FIG. 9 is a graph showing the SNM, Figure 60 (b) of FIG. 9 is a graph showing the standby power.

[0104] Figure 61 (a) of FIG. 10 is a conceptual diagram of a logic system simulated, Figure 61 (b) of FIG. 10 is a graph showing the normalized standby power of systems A and C. DETAILED DESCRIPTION

[0105] Hereinafter, embodiments will be described with reference to the drawings.

[0106] Embodiment 1

[0107] As in Patent Document 3, a storage operation is performed only on the memory cell that is rewritten at the time of normal SRAM operation (i.e., read / write operation). In this method, when the size of the cell array becomes large, the power consumption of the memory cell that waits for the storage operation due to the leakage current becomes large. Therefore, it is considered that the memory cell in which data is not rewritten is first turned off, and then the storage operation is performed on the memory cell that is rewritten. However, even if the data of the memory cell that is rewritten is data that is not needed after restoration, the storage operation is performed. Thereby, the power consumption and the latency increase.

[0108] Embodiment 1 aims at suppressing the power consumption and the energy consumption. Specifically, it aims at reducing the power consumption and the energy consumption at the time of PG (power gating) (at the time of power-off), during transition to PG, and during restoration from PG, and reducing the BET related to PG.

[0109] In Embodiment 1, the memory cell in which data that can not be stored is stored is first turned off regardless of whether it is rewritten, and then the storage operation is performed on the remaining memory cells. Thereby, it is possible to suppress the power consumption and the latency.

[0110] More specifically, the cell array is divided into a plurality of blocks. In a higher level than the storage level, it is determined whether each block is storage-free. At this time, even if there is rewriting in the usual SRAM operation, as long as it is data that is not needed, it is set as a storage-free block. The higher level generates a UDF (Useless Data Flag) that specifies a block in which data that is not needed after recovery exists. In the storage level, a closing and storage operation is performed on each block in accordance with the UDF. Thus, power consumption can be efficiently suppressed.

[0111] Hereinafter, a detailed example of Embodiment 1 will be described.

[0112] [Explanation of Memory Cell]

[0113] Figure 1 is a circuit diagram of the memory cell of Embodiment 1. As shown in Figure 1 , the memory cell 10 mainly has inverter circuits 14 and 16, spin transfer torque magnetic tunnel junction elements (STT-MTJ: hereinafter referred to as ferromagnetic tunnel junction elements) MTJ1 and MTJ2.

[0114] The inverter circuits 14 and 16 are connected in a ring shape, constituting a bistable circuit 12. The inverter circuit 14 has FETs (Field Effect Transistors) m1 and m2. The inverter circuit 16 has a FET m3 and a FET m4. The FETs m1 and m3 are P-channel MOSFETs, and the FETs m2 and m4 are N-channel MOSFETs. The sources of the FETs m1 and m3 are connected to a power supply line 15a to which a virtual power supply voltage VVDD is applied, and the sources of the FETs m2 and m4 are connected to a ground line 15b to which a ground voltage VGND is applied. Thus, a power supply voltage (VVDD-VGND) is supplied to the bistable circuit 12.

[0115] The nodes to which the inverter circuits 14 and 16 are connected are nodes Q and QB, respectively. The node Q and the node QB are complementary nodes. The bistable circuit 12 becomes a stable state by the node Q and the node QB becoming a high level and a low level, respectively, or the node Q and the node QB becoming a low level and a high level, respectively. The bistable circuit 12 is capable of storing data by becoming a stable state.

[0116] The nodes Q and QB are connected to bit lines BL and BLB via N-channel FETs m5 and m6, respectively. The gates of the FETs m5 and m6 are connected to a word line WL. A 6-transistor (FET) type SRAM is formed by the FETs m1 to m6.

[0117] FET m7 and a ferromagnetic tunnel junction element MTJ1 are connected between a node Q and a control line CTRL, and FET m8 and a ferromagnetic tunnel junction element MTJ2 are connected between a node QB and the control line CTRL. One of the source and drain of FET m7 and m8 is connected to the node Q and QB, respectively, and the other of the source and drain is connected to the ferromagnetic tunnel junction element MTJ1 and MTJ2, respectively. The gate of FET m7 and m8 is connected to a switch line SR. FET m7 and m8 can also be connected between the ferromagnetic tunnel junction element MTJ1 and MTJ2 and the control line CTRL, respectively. In addition, FET m7 and m8 can not be provided.

[0118] The ferromagnetic tunnel junction elements MTJ1 and MTJ2 each have a free layer 17, a tunnel insulating film 18, and a pinned layer 19. The free layer 17 and the pinned layer 19 are composed of a ferromagnetic substance. In a state in which the magnetization directions of the free layer 17 and the pinned layer 19 are parallel (parallel state), the resistance values of MTJ1 and MTJ2 become low. In a state in which the magnetization directions of the free layer 17 and the pinned layer 19 are anti-parallel (anti-parallel state), the resistance values of MTJ1 and MTJ2 are higher than in the parallel state. MTJ1 and MTJ2 store data by the resistance values of MTJ1 and MTJ2. In the virtual power supply mode described later, the free layer 17 is connected to the control line CTRL, and in the virtual ground mode, the pinned layer 19 is connected to the control line CTRL. In the virtual power supply mode, FET m7 and m8 are N-channel FETs, and in the virtual ground mode, FET m7 and m8 are P-channel FETs.

[0119] A power supply switch 30 is connected between the power supply line 15a and the power supply 15c. The power supply switch 30 includes power supply switches PS1 and PS2 connected in parallel between the power supply line 15a and the power supply 15c. The power supply switches PS1 and PS2 are, for example, a P-channel FET and an N-channel FET, respectively. The gates of the power supply switches PS1 and PS2 are supplied with PS control signals VPG1 and VPG2, respectively. The power supply switch 30 can also be provided between the ground line 15b and the ground terminal 15d. In this case, the voltage VDD of the power supply is applied to the power supply line 15a, and a virtual ground voltage VVGND higher than the ground voltage VGND is applied to the ground line 15b. This is referred to as the virtual ground mode. The power supply switch 30 can also be provided between both the power supply line 15a and the power supply 15c and the ground line 15b and the ground terminal 15d.

[0120] [Explanation of each state]

[0121] Figure 2 (a) of FIG. 6 and Figure 2 (b) of FIG. 6 are graphs showing the voltages applied in each state of Embodiment 1. As Figure 2As in (a), in the read / write state, VPG1 and VPG2 are at the low level L. The power switches PS1 and PS2 are turned on and off, respectively. Thus, the power supply voltage VVDD-VGND provided between the power supply line 15a and the ground line 15b is the voltage V2. The voltage V2 is, for example, 1.2 V.

[0122] In the sleep state, VPG1 and VPG2 are at the high level H. The power switches PS1 and PS2 are turned off and on, respectively. Thus, the power supply voltage VVDD-VGND is the voltage V1 which is lower than the voltage V2. The voltage V1 is, for example, 0.8 V.

[0123] In the off state, VPG1 and VPG2 are at the high level H and the low level L, respectively. The power switches PS1 and PS2 are turned off. The power supply voltage is not applied to the power supply line 15a. Thus, the power supply voltage VVDD-VGND is the voltage V0 which is lower than the voltage V1. The voltage V0 is, for example, substantially 0 V.

[0124] The period of the read / write state is a period in which the data of the bistable circuit 12 is rewritten as a normal SRAM, and the data is held in a volatile manner (this is referred to as "rewritten in a volatile manner"). The data is written to and read from the bistable circuit 12 as in the SRAM. That is, by setting the word line WL to the high level and setting the FETs m5 and m6 to the on state, the data of the bit lines BL and BLB can be written to the bistable circuit 12. In addition, by setting the bit lines BL and BLB to the floating state in which the potentials are equal, setting the word line WL to the high level, and setting the FETs m5 and m6 to the on state, the data of the bistable circuit 12 can be read to the bit lines BL and BLB. The power supply voltage VVDD-VGND is the voltage V2 at which the bistable circuit 12 can rewrite the data and can hold the data.

[0125] The period of the sleep state is a period in which the memory cell 10 is in the sleep mode. In the sleep state, the bistable circuit 12 can hold the data only, and cannot rewrite the data. The power supply voltage VVDD-VGND is the voltage V1 at which the bistable circuit 12 cannot rewrite the data but can hold the data. Since the voltage V1 is lower than the voltage V2, the power consumption can be suppressed.

[0126] In the read / write state and the sleep state, the control signals VCTRL and VSR in the control line CTRL and the switch line SR are at the low level, and the FETs m7 and m8 are turned off. By turning off the FETs m5 and m6, the data of the bistable circuit 12 is held. In addition, when the data is written to, read from, and held with respect to the bistable circuit 12, it is preferable to set the switch line SR to the low level and turn off the FETs m7 and m8. Thus, the current between the nodes Q and QB and the control line CTRL can be substantially cut off, stable operation can be achieved, and further the increase in the power consumption can be suppressed.

[0127] As Figure 2 The storage period is a period in which the storage operation is performed, and is a period in which the data stored in the bistable circuit 12 is stored in the ferromagnetic tunnel junction elements MTJl and MTJ2 and is held nonvolatile (referred to as "nonvolatile storage"). During the storage period, the power supply voltage VVDD-VGND is the voltage V2 which is the same as the readout / storage state. The control signal VSR is set to the high level.

[0128] During the H storage period, the control signal VCTRL is set to the low level. As a result, the MTJ corresponding to the node of the high level in the nodes Q and QB becomes high resistance. During the L storage period, the control signal VCTRL is set to the high level. As a result, the MTJl and MTJ2 corresponding to the nodes of the low level in the nodes Q and QB become low resistance. The order of the H storage period and the L storage period can also be reversed. In this way, the data of the bistable circuit 12 is stored in the ferromagnetic tunnel junction elements MTJl and MTJ2.

[0129] The period of the off state is a period in which the memory cell 10 is turned off. In the off state, the power supply voltage VVDD-VGND is set to the voltage V0 which is substantially 0 V. At this time, almost no current flows in the memory cell 10, and thus power consumption can be suppressed.

[0130] During the recovery period, the recovery is performed by raising the power supply voltage VVDD-VGND from the voltage V0 to the voltage V2 in a state in which the control signal VCTRL is set to the low level and the control signal VSR is set to the high level. The nodes Q and QB corresponding to the ferromagnetic tunnel junction elements MTJl and MTJ2 of high resistance become the high level. The nodes Q and QB corresponding to the MTJl and MTJ2 of low resistance become the low level. In this way, the data stored in the ferromagnetic tunnel junction elements MTJl and MTJ2 and held nonvolatile (referred to as "nonvolatile stored data") is recovered into the bistable circuit 12.

[0131] The high level of the control signals VCTRL and VSR is, for example, VDD or VVDD, and the low level is, for example, VGND. The high level of the control signal VCTRL can be a voltage higher than the low level, and the high level of the control signal VSR can be a voltage higher than the low level.

[0132] Figure 3 is a graph showing the power consumption of each period of Embodiment 1. The solid line indicates the case in which the ferromagnetic tunnel junction elements MTJl and MTJ2 are used, and the broken line indicates the case in which the magnetic tunnel junction elements MTJl and MTJ2 are used. Figure 1Power consumption (power) of the storage circuit of the illustrated memory cell 10 (NV-SRAM). The power consumption of the solid line includes the power due to the leakage current and the power used in the storage and the restoration, and does not include the power of the read and the write during the read / write. The dotted line indicates the power consumption of the storage circuit using a 6-transistor SRAM (6T-SRAM) cell in which the FETs m7, m8, MTJl, and MTJ2 are not provided. The broken line indicates the power consumption of the storage circuit using the 6T-SRAM cell during the read / write. The power consumption of the broken line and the dotted line includes the power due to the leakage current, and does not include the power of the read and the write during the read / write.

[0133] As Figure 3 illustrated, the operation period of the memory cell 10 has a sleep period (period in the sleep state), a read / write period (period in the read / write state), a storage period, an off period (period in the off state), and a restoration period. Let the length of the sleep period and the read / write period be τ NL . Let the length of the storage period, the off period, and the restoration period be τ 存储 , τ 关闭 , and τ 恢复 , respectively.

[0134] The power consumption of the sleep period and the read / write period of the NV-SRAM is P 休眠 and P NL , respectively. P 休眠 and P NL of the NV-SRAM are larger than the power consumption of the sleep period and the read / write period of the 6T-SRAM by ΔP NL . This is because the leakage current flows in the FETs m7 and m8 of the NV-SRAM.

[0135] In the NV-SRAM, the power for storage ΔP 存储 is generated in the storage period. The power consumption P 关闭 is generated in the off period. The power consumption P 关闭 is due to the leakage current. The power for restoration ΔP 恢复 is generated in the restoration period. In the 6T-SRAM, a period equivalent to the storage period, the off period, and the restoration period of the NV-SRAM is taken as the sleep period. Thus, the power consumption of the 6T-SRAM for these periods is P 休眠 - ΔP NL . The difference between the power consumption of the NV-SRAM and the 6T-SRAM in the off period is ΔP 关闭 .

[0136] The energy increase of the NV-SRAM cell with respect to the 6T-SRAM cell is based on ΔP NLthe sum of the energy increase ΔE NL based on ΔP 存储 during the storage period, the energy increase ΔE 存储 based on ΔP 恢复 during the recovery period, and the energy increase ΔE 恢复 The NV-SRAM cell saves the energy by turning off the energy decrease ΔE 关闭 based on ΔP 保存 during the turn-off period. This makes ΔE NL + ΔE 存储 + ΔE 恢复 equal to ΔE 保存 The τ 关闭 is BET (Break-even time). When the standby period during which no read / write of data is performed in the bistable circuit 12 is equal to or longer than the BET, it is set to the turn-off state, and when it is shorter than the BET, it is set to the sleep state. Thus, the energy can be reduced with extremely high efficiency.

[0137] [Explanation of electronic circuit]

[0138] Figure 4 is a block diagram showing the electronic circuit of Embodiment 1. As shown in Figure 4 , the electronic circuit 100 has a cell array 20 and a control circuit 28. The cell array 20 is divided into a plurality of sub-arrays 22. The storage capacity of the sub-array 22 is, for example, 8 kbytes. A plurality of memory cells 10 are arranged in a matrix form in the sub-array 22. The sub-array 22 is connected to a bus 25. The number of sub-arrays 22 can be designed as appropriate.

[0139] A power switch 30 and a peripheral circuit 38 are provided in the sub-array 22. The power switch 30 sets a power voltage for each sub-array 22. The peripheral circuit 38 performs a storage-free control for each sub-array 22.

[0140] The control circuit 28 has a SFBF (Store Free Block Flag) register 41 and a UDF (Useless Data Flag) register 40. The control circuit 28 generates the SFBF for each block in accordance with the address and stores it in the register 41. The control circuit 28 stores the UDF of each block received from the external circuit in the register 40. The control circuit 28 controls the power supply of each subarray 22 by controlling the power supply switch 30 of each subarray 22 using the PS control signal. In this way, the control circuit 28 functions as a power management unit. Further, the control circuit 28 controls the free store operation of each subarray 22 by controlling the peripheral circuit 38 of each subarray 22 using the store control signal. In this way, the control circuit 28 functions as a free store management unit. Also, the control circuit 28 inputs and outputs data with respect to the subarrays 22 via the bus 25. At least a part of the functions of the control circuit 28 can also be performed by a processor circuit such as a CPU (Central Processing Unit) in cooperation with software.

[0141] [Explanation of subarrays]

[0142] Figure 5 is a block diagram of the subarray of Embodiment 1. As shown in Figure 5 , the subarray 22 is divided into a plurality of blocks 24 (for example, 8) having memory cells 10. The storage capacity of the block 24 is, for example, 1 kbyte. The number of blocks 24 can be appropriately designed. A plurality of memory cells 10 are arranged in a matrix shape within the subarray 22. Within the subarray 22, the word line WL and the switch line SR extend in the row direction, and the bit line BL (corresponding to the bit lines BL and BLB of Figure 1 ) and the control line CTRL extend in the column direction. Each memory cell 10 is connected to the word line WL, the switch line SR, the bit line BL, the control line CTRL, the power supply line 15a, and the ground line 15b.

[0143] The power supply switch 30 and the peripheral circuit 38 are provided corresponding to each subarray 22. The control circuit 28 controls the power supply switch 30 and the peripheral circuit 38. The power supply switch 30 can set the power supply voltage VVDD-VGND to the voltages V2, V1, V0 for each block 24. The peripheral circuit 38 has a WL decoder 31, column decoders 32, 36, a precharge circuit 33, a read / write circuit 34, and an SR decoder 35.

[0144] During read / write, the WL decoder 31 selects the word line WL according to the row address. The column decoder 32 selects the bit line BL according to the column address. The precharge circuit 33 precharges the bit line BL. The read / write circuit 34 writes data to or reads data from the bistable circuit 12 of the memory cell 10 selected by the WL decoder 31 and the column decoder 32 and outputs to the bus 25.

[0145] During storage, the SR decoder 35 selects the switch line SR according to the row address. The column decoder 36 selects the control line CTRL according to the column address. In the memory cell 10 selected by the WL decoder 31 and the column decoder 32, the data of the bistable circuit 12 is nonvolatilely stored in the ferromagnetic tunnel junction elements MTJl and MTJ2.

[0146] [Explanation of the operation]

[0147] Figure 6 is a flowchart showing the operation of Embodiment 1. As shown in Figure 6 , the control circuit 28 turns on the power supply of the cell array 20 according to an instruction from an external circuit (step S10). For example, the control circuit 28 turns on the FETs m7 and m8 by setting the control signal VSR to the high level in all the blocks 24, and turns on the power supply switch PS1 and turns off the power supply switch PS2. Thereby, in each memory cell 10 within the cell array 20, the data within the ferromagnetic tunnel junction elements MTJl and MTJ2 is restored to the bistable circuit 12.

[0148] The control circuit 28 performs the read / write operation (step S12). The control circuit 28 determines whether an instruction to turn off the cell array 20 is received from the external circuit (step S14). When it is "No", the process returns to step S12. When it is "Yes", the control circuit 28 performs the storage operation and turns off (step S16). Then, the process returns to step S10.

[0149] [Explanation of the read / write operation]

[0150] The operation of step S12 of Figure 6 will be explained. Figure 7 (a) of Figure 7As shown in (a), control circuit 28 resets the SFBF corresponding to all blocks 24 in register 41 (step S20). For example, control circuit 28 sets the SFBF corresponding to all blocks 24 to a high level H. A write address is input to control circuit 28 (step S22). Control circuit 28 selects the block 24 to be written to (i.e., the block 24 containing the memory cell 10 to be written to) (step S24). Control circuit 28 sets the SFBF in register 41 corresponding to the block 24 selected using WL decoder 31 and column decoder 32 (step S26). For example, control circuit 28 sets the corresponding SFBF to a low level L. Control circuit 28 uses read-write circuit 34 to write data to the memory cell 10 within the selected block 24 (step S28). Control circuit 28 determines whether to end the operation (step S30). If "No", return to step S22. If "Yes", end.

[0151] [Explanation of UDF settings]

[0152] The action of setting a UDF is explained. A UDF is information indicating that the data in block 24 is data that can be left unstored (i.e., data that can be left unrecovered after closing). Figure 7 (b) is a flowchart illustrating the setting of the UDF in Example 1. Figure 7 As shown in (b), control circuit 28 resets the UDFs corresponding to all blocks 24 in register 40 (step S32). For example, control circuit 28 sets the UDFs corresponding to all blocks to a low level L. UDFs are input to control circuit 28 from an external circuit (step S34). The UDFs are input, for example, when data is written to block 24. Alternatively, UDFs are input periodically or irregularly, regardless of whether data is read or written. Control circuit 28 sets the UDF in register 40 corresponding to the block 24 specified by the UDF (step S36). For example, control circuit 28 sets the corresponding UDF to a high level H. Control circuit 28 determines whether to end the operation (step S38). If "No", it returns to step S34. If "Yes", it ends.

[0153] User-defined functions (UDFs) can be generated, for example, by software such as the operating system (OS) or programs within the CPU of an external circuit. Alternatively, part of the UDF generation can be performed by dedicated hardware circuitry. The algorithm for generating UDFs can also be installed on the compiler, allowing the compiler to automatically generate UDFs. Users can also specify the data to be used as a UDF in the program. Machine learning and other methods can also be used to learn the data to be used as a UDF and generate the UDF. Multiple methods for generating UDFs can also be combined. When the electronic circuit 100 is a cache memory, data that may not be stored includes, for example, data that has not been used for a long time, data with low usage frequency, or data written early.

[0154] [Description of storage action]

[0155] right Figure 6 The action of step S16 will be explained. Figure 8 This is a flowchart illustrating the storage operation of Embodiment 1.

[0156] Figure 9 (a) to Figure 9 (d) is a schematic diagram illustrating the cell array and blocks of Embodiment 1. Figure 9 (a) to Figure 9 In section (d), the cases where there are 3 × 3 = 9 subarrays 22 within the cell array 20, and 4 × 2 = 8 blocks 24 within one subarray 22, are explained. "Hibernate" indicates a block 24 in a hibernation state (i.e., all memory cells 10 within block 24 are in hibernation mode). "Storage" indicates a block 24 in the process of storage. "SFBF Closed" indicates a block 24 in a closed state based on SFBF (i.e., all memory cells 10 are closed), "UDF Closed" indicates a block 24 in a closed state based on UDF, and "Storage-After-Closed" indicates a block 24 in a closed state after the storage operation.

[0157] Figure 10 (a) to Figure 10 (c) is a schematic diagram showing the block of Embodiment 1. Figure 10 (a) to Figure 10 In (c), multiple rows 23 are set within block 24a. "Standby" refers to row 23 that is in a state of waiting to be stored. "Store" indicates row 23 that is in the process of being stored. Rows 23a to 23c represent specific rows among the multiple rows 23.

[0158] like Figure 8 As shown, when in Figure 6 In step S16, when the control circuit 28 begins the storage operation, it reads the UDF and SFBF corresponding to each block 24 from registers 40 and 41 respectively (step S40). The control circuit 28 extracts the block 24 for which at least one of the UDF and SFBF is set (e.g., set to high level H) as a storage-free block. The storage-free blocks are then turned off (step S42). For example, the control circuit 28 causes the power switch 30 to set the power supply voltage VVDD-VGND of the storage-free blocks to V0.

[0159] like Figure 9As shown in (a), the control circuit 28 simultaneously shuts down 36 of the 9×8=72 blocks 24 (9 subarrays 22, each subarray 22 having 8 blocks 24) (the sum of 17 blocks 24 with SFBF set and 19 blocks 24 with UDF set). The remaining 36 blocks 24 are put into sleep mode.

[0160] Control circuit 28 selects the first block 24a to perform the storage action (step S44). For example... Figure 9 As shown in (b), the control circuit 28 selects block 24a of subarray 22a and begins the storage operation.

[0161] As a storage operation for the selected block 24a, the control circuit 28 performs a storage operation on the selected block 24a row by row (step S46).

[0162] like Figure 10 As shown in (a), the control circuit 28 performs a storage operation on the first row 23a, causing the other rows 23 to wait. For example, the control circuit 28 turns on FETs m7 and m8 in row 23a and turns off FETs m7 and m8 in the waiting row 23. The control circuit 28 applies a storage operation voltage to the control line CTRL extending along the column direction. Thus, in the memory cells 10 where FETs m7 and m8 are turned on and the control line CTRL is energized, the data of the bistable circuit 12 is non-volatilely stored in the ferromagnetic tunnel junction elements MTJ1 and MTJ2. The voltage on the control line CTRL can be applied column by column or multiple columns simultaneously. The storage operation of row 23a ends when the storage operation of all memory cells 10 in row 23a is completed.

[0163] like Figure 10 As shown in (b), the control circuit 28 performs a storage operation on the next row 23b. Figure 10 As shown in (c), the control circuit 28 performs storage operations on row 23 sequentially, and performs a storage operation on the last row 23c. When the storage operations of all rows 23 are completed, the storage operation of block 24a is completed.

[0164] Control circuit 28 closes block 24a (step S48). Control circuit 28 determines whether the storage operation of the last block in the selected subarray 22 has ended (step S50). If it is "no", proceed to the next block 24b (step S52) and return to step S44.

[0165] like Figure 9 As shown in (c), in step S44, control circuit 28 selects block 24b, and in step S46, performs the storage operation of block 24b. In step S48, control circuit 28 closes block 24b. Then, steps S44 to S52 are repeated sequentially.

[0166] As Figure 9 indicated in (d) of FIG. 6, the storing operation of the last block 24 ends, and all the blocks 24 become the closed state. The control circuit 28 determines YES in step S50, and ends the storing operation.

[0167] [Example of Control Circuit]

[0168] Figure 11 (a) and Figure 11 (b) of FIG. 7 are diagrams each showing an example of the size of the cell array and the word address of Embodiment 1. As Figure 11 indicated in (a) of FIG. 7, as the size of the cell array 20, for example, 32 kbytes, 256 kbytes, and 2 Mbytes are set. If the size of one block 24 is set to 1 kbyte, and the number Nblock of the blocks 24 in one sub-array 22 is set to 8, the number NSA of the sub-arrays 22 is 4, 32, and 256, respectively. The number X of the bits of the address of the sub-array 22 is 2, 5, and 8, respectively. The number Y of the bits of the address of the block 24 is 3.

[0169] As Figure 11 indicated in (b) of FIG. 7, the word address is composed of the sub-array address X bits, the block address Y bits, and the row address in the block (for example, 7 bits when 1 kbyte) from the high-order bit.

[0170] Figure 12 is a block diagram showing an example of the control circuit of Embodiment 1. The control circuit 28 has a decoder 42, registers 40 and 41, a control circuit 43, and a PS control circuit 44. The number of bits of the registers 40 and 41 is NSA x Nblock or more, which is the number of the blocks 24. Blocks 24A to 24C of NSA x Nblock blocks 24 are described.

[0171] The UDF storage sections 40A to 40C are 1-bit latch circuits each corresponding to the blocks 24A to 24C. In Figure 7 step S32 of (b) of FIG. 8, all the storage sections 40A to 40C are reset to the low level L. When the UDF is input to the control circuit 28 in step S34, the memory cells 40A to 40C of the corresponding blocks 24A to 24C are set to the high level H in step S36.

[0172] The SFBF storage sections 41A to 41C are 1-bit latch circuits each corresponding to the blocks 24A to 24C. In Figure 7In step S20 of (a), the storage sections 41A to 41C are all reset to the high level H. In step S22, the address signal written is input to the decoder 42. In step S24, the corresponding block 24 is selected in accordance with the subarray address X and the block address Y. In step S26, the storage sections 40A to 40C of the corresponding block 24A to 24C are set to the low level L.

[0173] The control circuit 43 outputs the storage control signals a, b. The PS control circuit 44 controls the power supply switches PS1A to PS1C and the power supply switches PS2A to PS2C of the blocks 24A to 24C in accordance with the UDF and the SFBF held in the registers 40 and 41.

[0174] The PS control circuit 44 has the AND circuit 50, the NAND circuit 51, the OR circuit 52, the NOR circuit 53, the AND circuit 54, the AND circuit 55, the OR circuit 56, the OR circuit 57, the OR circuit 58, and the AND circuit 59 in the number same as the number of the blocks 24A to 24C.

[0175] The control signals a, b, ENNLB, and ENSLP input to the PS control circuit 44 are control signals common to the blocks 24A to 24C, and the control signals VCTRL and VSR are independent signals for each of the blocks 24A to 24C.

[0176] The output signals of the UDF storage sections 40A to 40C and the control signal ENNLB are input to the AND circuit 50. The output signals of the UDF storage sections 40A to 40C and the control signal ENNLB are input to the NAND circuit 51.

[0177] The output signals of the SFBF storage sections 41A to 41C and the control signal a are input to the OR circuit 52. The output signals of the SFBF storage sections 41A to 41C and the control signal b are input to the NOR circuit 53. The output signal of the OR circuit 52 and the control signal ENNLB are input to the AND circuit 54. The output signal of the NOR circuit 53 and the control signal ENNLB are input to the AND circuit 55. The output signal of the AND circuit 54 and the control signal ENSLP are input to the OR circuit 56. The output signal of the AND circuit 55 and the control signal ENSLP are input to the OR circuit 57.

[0178] The output signal of the AND circuit 50 and the output signal of the OR circuit 56 are input to the OR circuit 58. The PS control signals VPG1A to VPG1C are output from the OR circuit 58. The PS control signals VPG1A to VPG1C are input to the gates of the power supply switches PS1A to PS1C of the blocks 24A to 24C, respectively.

[0179] The output signal of the NAND circuit 51 and the output signal of the OR circuit 57 are input to the AND circuit 59. The PS control signals VPG2A to VPG2C are output from the AND circuit 59. The PS control signals VPG2A to VPG2C are input to the gates of the power switches PS2A to PS2C of the blocks 24A to 24C, respectively.

[0180] Figure 13 (a) to (e) of FIG. 8 are graphs showing the levels of the respective signals and the operation of the power switches in the case where the blocks 24A to 24C are in the read / write state. As shown in (a) of FIG. 8, during the read / write period, the control signals a, b, ENNLB, and ENSLP are all L. Assume that the UDFs of the blocks 24A to 24C are L, L, H, respectively. Assume that the SFBFs of the blocks 24A to 24C are L, H, L, respectively. At this time, VPG1A to VPG1C are L, and the power switches PS1A to PS1C are on. VPG2A to VPG2C are L, and the power switches PS2A to PS2C are off. Thus, during the read / write period, the power switches PS1A to PS1C are on, and the power switches PS2A to PS2C are off, regardless of the UDFs and the SFBFs. As a result, all of the blocks 24A to 24C are applied with the voltage V2 for read / write as the power supply voltage VVDD-VGND. Figure 13 Figure 13 As shown in (b) of FIG. 8, during the sleep period, the control signal ENSLP is H, and the control signals a, b, and ENNLB are L. VPG1A to VPG1C are H, and the power switches PS1A to PS1C are off. VPG2A to VPG2C are H, and the power switches PS2A to PS2C are on. Thus, during the sleep period, the power switches PS1A to PS1C are off, and the power switches PS2A to PS2C are on, regardless of the UDFs and the SFBFs. As a result, all of the blocks 24A to 24C are applied with the voltage V1 for sleep as the power supply voltage VVDD-VGND.

[0181] As shown in (c) of FIG. 8, during the sleep period, the control signal ENSLP is H, and the control signals a, b, and ENNLB are L. VPG1A to VPG1C are H, and the power switches PS1A to PS1C are off. VPG2A to VPG2C are H, and the power switches PS2A to PS2C are on. Thus, during the sleep period, the power switches PS1A to PS1C are off, and the power switches PS2A to PS2C are on, regardless of the UDFs and the SFBFs. As a result, all of the blocks 24A to 24C are applied with the voltage V1 for sleep as the power supply voltage VVDD-VGND. Figure 13 In step S42 of FIG. 8, the non-storage blocks 24B and 24C are set to the off state from the read / write state. As shown in (c) of FIG. 8, during the sleep period, the control signal ENSLP is H, and the control signals a, b, and ENNLB are L. VPG1A to VPG1C are H, and the power switches PS1A to PS1C are off. VPG2A to VPG2C are H, and the power switches PS2A to PS2C are on. Thus, during the sleep period, the power switches PS1A to PS1C are off, and the power switches PS2A to PS2C are on, regardless of the UDFs and the SFBFs. As a result, all of the blocks 24A to 24C are applied with the voltage V1 for sleep as the power supply voltage VVDD-VGND.

[0182] Figure 8 In step S42 of FIG. 8, the non-storage blocks 24B and 24C are set to the off state from the read / write state. As shown in (c) of FIG. 8, during the sleep period, the control signal ENSLP is H, and the control signals a, b, and ENNLB are L. VPG1A to VPG1C are H, and the power switches PS1A to PS1C are off. VPG2A to VPG2C are H, and the power switches PS2A to PS2C are on. Thus, during the sleep period, the power switches PS1A to PS1C are off, and the power switches PS2A to PS2C are on, regardless of the UDFs and the SFBFs. As a result, all of the blocks 24A to 24C are applied with the voltage V1 for sleep as the power supply voltage VVDD-VGND. Figure 13 Figure 13 ​​​Compared to (a), control signals a and ENLB change from L to H. Control signals b and ENSLP remain at L. VPG1A to VPG1C change from L to H, and power switches PS1A to PS1C change from ON to OFF. VPG2A changes from L to H, while VPG2B and VPG2C remain at L. Power switch PS2A changes from OFF to ON, while power switches PS2B and PS2C remain OFF. As a result, the power supply voltage VVDD-VGND of blocks 24B and 24C, where at least one of UDF and SFBF is H, becomes V0, and blocks 24B and 24C become OFF. The power supply voltage VVDD-VGND of block 24A, where both UDF and SFBF are L, becomes V1, and block 24A becomes sleep mode.

[0183] In step S46, the selected block 24A is from Figure 8 In step S42, the storage operation is performed in the state (let's say the period is T1). For example... Figure 13 As shown in (d), in steps S42 to S46, control signal a changes from H to L, and control signal b changes from L to H. Control signals ENLB and ENSLP maintain H and L respectively. VPG1A changes from H to L, and PS1A changes from off to on. VPG2A changes from H to L, and PS2A changes from on to off. PS1B, PS1C, PS2B, and PS2C remain off. The power supply voltage VVDD-VGND of block 24A becomes the waiting voltage V2, and the power supply voltage VVDD-VGND of blocks 24B and 24C is V0. Thus, block 24A enters the waiting state for storage operation, and blocks 24B and 24C remain in the off state. According to the storage control signal output from control circuit 43, control signals VCTRL and VSR are applied to block 24A. Thus, as Figure 10 (a) to Figure 10 As shown in (c), the storage operation on block 24A, which is the object, was performed. Let this period be T2.

[0184] exist Figure 8 In step S48, when the storage operation of block 24A ends, control signal a changes from L to H. Control signals b, ENLB, and ENSLP remain at H, H, and L respectively. VPG1A changes from L to H, and PS1A changes from ON to OFF. Consequently, the power supply voltage VVDD-VGND of block 24A changes from voltage V2 to voltage V0, and block 24A becomes closed. Let this period be T3. By executing... Figure 8 In the loop of steps S44 to S52, for block 24, which is the object of the storage action, the control signals (a, b) are set sequentially to (H, L) → (L, H) → (H, H). Thus, block 24, which is the object of the storage action, is sequentially executed with storage actions.

[0185] like Figure 13In the off state, the control signals a, b, ENNLB, and ENSLP are H, H, H, and L, respectively, as shown in (e). Regardless of the UDF and SFBF, the PS1A to PS1C and the PS2A to PS2C are open. Thus, the power supply voltage VVDD-VGND of all the blocks 24 is V0, and all the blocks 24 become the off state.

[0186] Figure 14 is a timing chart of the control signals of Embodiment 1. The control signals al to an are the control signals a corresponding to the blocks 24i to 24n, and the control signals bl to bn are the control signals b corresponding to the blocks 24i to 24n. The blocks 24i to 24k are the blocks that are the storage operation targets, and the blocks 24k+1 to 24n are the non-storage blocks.

[0187] As shown in (a), the period between the time t10 and the time t11 is the read / write period, and the control signals al to an, bl to bn, ENNLB, and ENSLP are L. The period between the time t11 and the time t12 is the sleep period, and the control signal ENSLP is H, and the other control signals are L. Figure 14

[0188] After the start of the storage operation, the control signals ENNLB and al to an become H at the time t13 (step S42 of (b)). Thus, the blocks 24i to 24k that are the storage operation targets become the sleep state for the period T1, and the non-storage blocks 24k+1 to 24n become the off state. This state is the period T1. Figure 8 At the time t14, the control signals al and bl corresponding to the block 24i become L and H, respectively. The period between the time t14 and the time t15 is the period T2 of the block 24i, and the storage operation is performed on the block 24i. At the time t15, the control signal al becomes H, and the control signal bl maintains H. The period from the time t15 onward is the period T3 of the block 24i, and the block 24i is in the off state. At the time t15, the control signals a2 and b2 corresponding to the block 24i become L and H, respectively. The period between the time t15 and the time t16 is the period T2 of the block 24i, and the storage operation is performed on the block 24i. At the time t16, the control signal a2 becomes H, and the control signal b2 maintains H. The period from the time t16 onward is the period T3 of the block 24i, and the block 24i is in the off state.

[0189]

[0190] ​​The steps S46 and S48 are sequentially performed on the blocks 24i-24k that are the storage operation objects. When the storage operation of all the blocks 24i-24k that are the storage operation objects ends at time t17, all the blocks 24i-24n are in the off state. When the control signals ai-an, bi-bn, ENNLB, and ENSLP become L at time t18, the read / write period is reached.

[0191] Thus, at time t13, the blocks 24i-24k are collectively in the sleep state (period T1), and the blocks 24k+1-24n are collectively in the off state. Thereafter, the blocks 24i-24k are sequentially subjected to the storage operation (period T2). The blocks whose storage operation ends are sequentially brought to the off state (period T3).

[0192] Figure 15 is a block diagram of another example of the control circuit 28 of Embodiment 1. As shown, by setting the control signal ENSLP to a signal for each of the blocks 24A-24C, it is possible to set each of the blocks 24A-24C to the sleep state. The other structures are the same as those of Figure 15 Embodiment 1, and the description is omitted. Figure 12

[0193] [Simulation]

[0194] The BET and the time lag of the storage operation of the electronic circuit of Embodiment 1 were simulated. Comparative Example 1-1 and Comparative Example 1-2 were also simulated. In Comparative Example 1-1, the collective cut-off of the subarray 22 and the blocks 24 was not performed, but the storage operation of the blocks 24 whose SFBF was set was sequentially skipped. In Comparative Example 1-2, the collective cut-off based on the UDF was not performed, but only the collective cut-off based on the SFBF was performed.

[0195] The simulation conditions were as follows. The voltage V2 of the power supply voltage VVDD-VGND during the read / write period, the storage period, and the recovery period was set to 1.2 V. The voltage V1 of the power supply voltage VVDD-VGND during the sleep period and the voltage of the control line CTRL were set to 0.8 V and 0 V, respectively. The voltage of the switch line SR during the storage period was set to 0.75 V. The voltages of the high level and the low level of the control line CTRL during the storage period were set to 0.45 V and 0 V, respectively. The storage capacities of the subarray 22 and the blocks 24 were set to 8 kbytes and 1 kbytes, respectively.

[0196] ​The ratio of the number of storage-free memory cells based on SFBF to the total number of memory cells in cell array 20 is used as the SFBF storage-free ratio. The ratio of the number of storage-free memory cells based on UDF to the total number of memory cells in cell array 20 is used as the UDF ratio. Considering that the memory cells 10 that are volatilely written to within cell array 20 are concentrated in specific subarrays 22 and blocks 24, the time spent on the storage operation is used as the storage latency. Simulations were performed for cell array 20 with storage capacities of 32KB, 256KB, and 2MB.

[0197] Figure 16 (a) to Figure 16 (c) is a graph showing the BET relative to the storage-free ratio of SFBF for Example 1, Comparative Example 1-1, and Comparative Example 1-2. Figure 16 (d) to Figure 16 (f) is a graph showing the storage latency relative to the storage-free ratio of SFBF. Figure 16 As shown in (a), in Comparative Example 1-1, at 32k bytes, the BET becomes shorter as the storage-free ratio increases.

[0198] like Figure 16 (b) and Figure 16 As shown in (c), when the storage capacity increases to 256 KB and 2 MB, the BET does not decrease even if the SFBF (Storage-Free Rate) increases. This is because, as the storage capacity increases, the number of blocks 24 waiting for storage actions increases. During the waiting period for storage actions, leakage current also flows in the memory cells 10. Therefore, the overall leakage current of the cell array 20 increases, and the BET does not decrease even if the storage-free rate increases.

[0199] like Figure 16 (d) to Figure 16 As shown in (f), in Comparative Example 1-1, the storage latency is constant and is independent of the storage-free ratio.

[0200] like Figure 16 (a) to Figure 16 As shown in (c), in Comparative Examples 1-2, regardless of the storage capacity, BET decreases as the storage-free ratio increases. Figure 16 (d) to Figure 16 As shown in (f), in Comparative Example 1-2, regardless of the storage capacity, the storage latency decreases as the proportion of storage-free storage increases. This is because in Comparative Example 1-2, storage-free block 24 is disabled first.

[0201] like Figure 16 (a) to Figure 16As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 16 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 16 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2.

[0202] As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 1 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 8 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2.

[0203] As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2.

[0204] As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 4 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 5 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 8 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 8 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 9 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 8 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 9 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 8 As shown in (c) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the BET becomes shorter as compared with Comparative Examples 1-2. As shown in (d) of FIG. 6, in Embodiment 1, as the proportion of UD becomes larger, the latency becomes shorter as compared with Comparative Examples 1-2. Figure 9As in (c), the control circuit 28 closes the second block after the storage operation ends.

[0205] Thus, since the first block in which the UDF is set is closed on a per block 24 basis, power consumption for performing the storage operation on the first block can be suppressed. In addition, the storage delay can be reduced. Furthermore, since the first block in which the UDF is set is closed first, power consumption due to leakage current while waiting for the storage operation can be reduced.

[0206] The control circuit 28 closes all of the extracted first blocks as in (a), and then performs a storage operation in the memory cells 10 in the remaining second blocks as in (b) to (d). Thus, power consumption while the first block in which the UDF is set is waiting to be closed can be reduced. Figure 9 Figure 9 The control circuit 28 closes all of the extracted first blocks as in (a), and then performs a storage operation in the memory cells 10 in the remaining second blocks as in (b) to (d). Thus, power consumption while the first block in which the UDF is set is waiting to be closed can be reduced. Figure 9

[0207] The register 40 (storage circuit) is provided outside the cell array 20, and stores the UDF (information indicating the first block in which data that can not be non-volatile stored is stored on a volatile basis) received from an external circuit. The control circuit 28 extracts the first block based on the UDF. Thus, compared to a method in which a storage circuit that stores the UDF is provided in each sub-array 22 or block 24, the UDF can be transmitted to the control circuit 28 without passing through the bus 25 or the like, and the control becomes simple.

[0208] As in step S40 of Figure 8 The control circuit 28 extracts the block in which the UDF is set and the block 24 in which the SFBF is set (i.e., a block in which any of the memory cells 10 has not been rewritten on a volatile basis) from among the plurality of blocks 24 as the first block. Thus, since the block in which the UDF is set and the block in which the SFBF is set are closed first, power consumption due to leakage current while waiting for the storage operation can be reduced. In addition, the storage delay can be reduced.

[0209] The register 41 (storage circuit) is provided outside the cell array 20. Thus, compared to a method in which the SFBF is stored in each sub-array 22 or block 24, the SFBF need not be transmitted to the control circuit 28 without passing through the bus 25 or the like, and the control becomes simple.

[0210] ​​In Embodiment 1, the case where MTJl and MTJ2 are connected to nodes Q and QB, respectively, is described, but as long as either of MTJl and MTJ2 is connected to node Q or QB. The memory cell can have only bistable circuit 12 and a nonvolatile element. As the nonvolatile element, an MTJ is described as an example, but as the nonvolatile element, a giant magnetoresistance (GMR) element, a variable resistance element used in ReRAM (Resistance Random Access Memory), or a phase change element used in PRAM (Phase change RAM) can be used.

[0211] Embodiment 2

[0212] In a case where the technology of Patent Document 5 is applied to a cell array, ULV hold of VNR-SRAM is performed by lowering a power supply voltage after switching a mode from a BI (boost inverter) mode to an ST (Schmitt trigger) mode. When the size of the cell array becomes large, power consumption due to a leakage current in a memory cell waiting for mode switching becomes large. Also, a delay increases due to a standby period. In addition, even if data of the memory cell is data that is not needed, hold is performed. Thus, power consumption and a delay increase.

[0213] Embodiment 2 aims at suppressing power consumption and energy consumption. Specifically, the aim is to reduce power consumption and energy consumption at the time of PG (hold time), during transition to PG, and during recovery from PG, and to reduce BET related to PG.

[0214] In Embodiment 2, when data is written to the cell array, or when data is processed, a memory cell having data that is not needed after a power supply is restored is closed, and hold is performed on the remaining memory cells. Thus, since mode switching is not needed for a memory cell storing data that is not needed to be held, it is possible to suppress power consumption and a delay.

[0215] More specifically, the cell array is divided into a plurality of blocks. A UDF is generated, which specifies a block having a memory cell having data that is not needed after a power supply is restored. At hold time, the block storing data that is not needed to be held is closed in accordance with the UDF. Then, hold is performed in the other blocks. Thus, since mode switching is not needed for the block storing data that is not needed to be held, it is possible to suppress power consumption and a delay. Furthermore, since the block storing data that is not needed to be held is closed, it is possible to further reduce power consumption.

[0216] Hereinafter, a detailed example of Embodiment 2 is described.

[0217] [Explanation of Memory Cell]

[0218] Figure 17 is a circuit diagram of the memory cell of Example 2. As shown in Figure 17 the memory cell 10 mainly has inverter circuits 14 and 16.

[0219] The inverter circuits 14 and 16 are connected in a ring shape, constituting a bistable circuit 12. The inverter circuit 14 has FETs ml, m2a, m2b, and m9. The inverter circuit 16 has FETs m3, m4a, m4b, and mlO. The FETs ml and m3 are P-channel MOSFETs, and the FETs m2a, m2b, m4a, m4b, m9, and mlO are N-channel MOSFETs. The sources of the FETs ml and m3 are connected to a power supply line 15a to which a virtual power supply voltage VVDD is applied, and the drains are connected to nodes Q and QB. The FETs m2a and m2b are connected in series between the node Q and a ground line 15b to which a ground voltage VGND is applied, the source of the FET m2b is connected to the ground line 15b, and the drain of the FET m2a is connected to the node Q. The FETs m4a and m4b are likewise connected between the node QB and the ground line 15b.

[0220] The input node of the inverter circuit 14 is a node Nl to which the FETs ml, m2a, and m2b are commonly connected, and the output node of the inverter circuit 14 is the node Q. The input node of the inverter circuit 16 is a node N3 to which the FETs m3, m4a, and m4b are commonly connected, and the output node of the inverter circuit 16 is the node QB. The input node and the output node of the inverter circuit 14 are connected to the output node and the input node of the inverter circuit 16, respectively.

[0221] One of the source and the drain of the FET m9 is connected to a node N2 between the FETs m2a and m2b, the other is connected to a control line CTRL, and the gate is connected to the node Q. One of the source and the drain of the FET mlO is connected to a node N4 between the FETs m4a and m4b, the other is connected to the control line CTRL, and the gate is connected to the node QB.

[0222] The inverter 26a is a driver 26 for the control line CTRL, inverts the control signal VCTRL, and outputs a control signal whose voltage is VSCTRL at a high level and whose voltage is VLCTRL at a low level. When the control signal VCTRL is at a high level, the control line CTRL becomes VLCTRL, and the inverter circuits 14 and 16 become the BI mode. When the control signal VCTRL is at a low level, the control line CTRL becomes VSCTRL, and the inverter circuits 14 and 16 become the ST mode.

[0223] The node Q and QB are connected to the bit lines BL and BLB via MOSFETs m5 and m6, respectively. The gates of the MOSFETs m5 and m6 are connected to the word line WL.

[0224] The BI mode is a mode in which the transfer characteristics of the inverter circuits 14 and 16 have substantially no hysteresis and are capable of high-speed operation. The ST mode is a mode in which the transfer characteristics of the inverter circuits 14 and 16 have hysteresis and operate slowly. In addition, substantially no hysteresis means that there is no intentional hysteresis as in the ST mode, and unintentional hysteresis is allowed.

[0225] In the BI mode, the memory cell 10 functions as a normal SRAM cell. In the ST mode, the data of the bistable circuit 12 can be held even if the power supply voltage (VVDD-VGND) is set to an ultra low voltage (ULV) of, for example, 0.2 V.

[0226] The power supply switch 30 has power supply switches PS1, PS2, and PS3. The power supply switches PS1 and PS2 are connected in parallel between the high-voltage power supply 15ch and the power supply line 15a. The power supply switches PS1 and PS2 are, for example, a P-channel FET and an N-channel FET, respectively. The gates of the power supply switches PS1 and PS2 are supplied with PS control signals VPG1 and VPG2, respectively. The substrate bias of the power supply switches PS1 and PS2 is, for example, VDDH and VGND, respectively.

[0227] The power supply switch PS3 and the FET m11 are connected in series between the low-voltage power supply 15cl and the power supply line 15a. The power supply switch PS3 and the FET m11 are a P-channel FET and an N-channel FET, respectively. The FET m11 functions as a load. The gate of the power supply switch PS3 is supplied with a PS control signal VPG3. The substrate bias of the power supply switch PS3 and the FET m11 is, for example, VDDL and VDDH, respectively. As in Embodiment 1, the power supply switch 30 can also be provided between the ground line 15b and the ground terminal 15d. The power supply switch 30 can also be provided between at least one of the power supply lines 15a and the power supplies 15ch and 15cl and between the ground line 15b and the ground terminal 15d.

[0228] [Explanation of each state]

[0229] Figure 18 (a) of FIG. 6 and Figure 18 (b) of FIG. 6 are graphs showing the voltages applied in each state of Embodiment 2. As Figure 18As shown in (a), in the standby state, VPG1, VPG2, and VPG3 are at low level L, low level L, and high level H, respectively. Power switches PS1, PS2, and PS3 are turned on, off, and off, respectively. Therefore, the power supply voltage VVDD-VGND becomes voltage V3. Voltage V3 is, for example, 1.2V.

[0230] In sleep mode, VPG1, VPG2, and VPG3 are H, H, and H, respectively. Power switches PS1, PS2, and PS3 are off, on, and off, respectively. Therefore, the power supply voltage VVDD-VGND becomes voltage V2, which is lower than voltage V3. Voltage V2 is, for example, 0.8V.

[0231] In the held state, VPG1, VPG2, and VPG3 are H, L, and L, respectively. Power switches PS1, PS2, and PS3 are open, closed, and on, respectively. Therefore, the power supply voltage VVDD-VGND becomes voltage V1, which is lower than voltage V2. Voltage V1 is, for example, 0.2V.

[0232] In the off state, VPG1, VPG2, and VPG3 are H, L, and H, respectively. Power switches PS1, PS2, and PS3 are open, open, and open, respectively. The power supply voltage VVDD-VGND becomes voltage V0, which is lower than voltage V1. Voltage V0 is approximately 0V.

[0233] like Figure 18 As shown in (b), in the standby state, the power supply voltage VVDD-VGND is voltage V3. There are two possible scenarios: when the control signal VCTRL is L, it is L; when VCTRL is H, memory cell 10 is in BI mode, and when VCTRL is L, it is in ST mode. The standby (BI) state is the same as the read / write state in Embodiment 1, and is a state where the data of the bistable circuit 12 can be rewritten, as is typical for SRAM. The power supply voltage VVDD-VGND is the voltage V3 at which the bistable circuit 12 can rewrite data and maintain the data.

[0234] In sleep mode, the power supply voltage VVDD-VGND is voltage V2, which is lower than voltage V3. There are two possible scenarios: when the control signal VCTRL is L, it is L; when VCTRL is H, memory cell 10 is in BI mode, and when VCTRL is L, it is in ST mode. The power supply voltage VVDD-VGND is voltage V2, which the bistable circuit 12 cannot overwrite but can retain. Because voltage V2 is lower than voltage V3, power consumption is suppressed.

[0235] In the holding state, the power supply voltage VVDD-VGND is a voltage VI lower than the voltage V2. The control signal VCTRL is L, and the memory cell 10 is in the ST mode. The power supply voltage VVDD-VGND is the voltage VI at which the bistable circuit 12 cannot hold data in the BI mode, but can hold data in the ST mode. In the holding state, the memory cell 10 is in a virtual nonvolatile state, and it is possible to make the voltage VI lower than the voltage V2, so it is possible to greatly suppress power consumption.

[0236] In the off state, the power supply voltage VVDD-VGND is a voltage V0 lower than the voltage VI. The control signal VCTRL is H, and the memory cell 10 is in the BI mode. In the off state, the power consumption of the memory cell 10 is substantially 0.

[0237] Figure 19 (a) of FIG. 6 and Figure 19 (b) of FIG. 6 are graphs showing the applied voltages in the holding and off states of Embodiment 2. As shown in Figure 19 (a) of FIG. 6, in the standby state, the power supply voltage VVDD-VGND is a voltage V3, and the control signal VCTRL is H, so it is in the BI mode. During the mode switching, first, VCTRL is set to L. Thereby, it becomes the ST mode. Thereafter, the power supply voltage VVDD-VGND is set to the voltage VI. Thereby, it becomes the holding state. Then, during the mode switching, the power supply voltage VVDD-VGND is set to the voltage V3. Thereafter, VCTRL is set to H. Thereby, it returns to the standby state. In this way, the mode switching is performed before and after the holding state is set.

[0238] As shown in Figure 19 (b) of FIG. 6, in the standby state, when the power supply voltage VVDD-VGND is made the voltage V0, it becomes the off state. At this time, VCTRL is maintained at H, and the BI mode is maintained. When the power supply voltage VVDD-VGND is made the voltage V3, it returns to the standby state.

[0239] Figure 20 is a graph showing the power consumption during each period of Embodiment 2. The solid line indicates the power consumption (power) of the memory circuit having the memory cell 10 (VNR-SRAM) shown in Figure 17 The dotted line indicates the power consumption of the memory circuit using a 6-transistor SRAM (6T-SRAM) cell.

[0240] As shown in Figure 20 , the operation period of the memory cell 10 has a standby period, a mode switching period, and a holding period. Let the length of the standby period be τ NL . Let the length of the mode switching period before the holding period be τ EXT . Let the length of the holding period be τ SDThe length of the mode switching period after the hold period is set to τ ENT .

[0241] The power consumption of the standby period of the VNR-SRAM is P larger than that of the 6T-SRAM LKG This is due to the drain current of FETs m9 and m10. In the VNR-SRAM, power consumption for mode switching is required during the mode switching period. During the hold period, the power consumption of the VNR-SRAM is P 保存 , the power consumption of the VNR-SRAM can be reduced by P 保存 .

[0242] The energy increase of the VNR-SRAM cell with respect to the 6T-SRAM cell is the sum of the energy increase E LKG based on P LKG of the standby period and the energy increase E EXT and E ENT of the mode switching period. The energy that can be saved by the VNR-SRAM cell during the hold period is the energy reduction E 保存 based on P 保存 . E LKG + E EXT + E ENT = P 保存 x BET. When the standby period during which the read / write of the bistable circuit 12 is not performed is BET or more, the hold state is set, and when it is less than BET, the standby state is set. Thus, the energy can be reduced with extremely high efficiency.

[0243] Figure 21 (a) of (b) of Figure 21 is another example of the memory cell of Embodiment 2. As shown in (a) of Figure 21 , the inverter circuit 14 has FETs ml a, ml b, m2, and m9a, and the inverter circuit 16 has FETs m3a, m3b, m4, and mlOa. The FETs ml a, ml b, m3a, m3b, m9a, and mlOa are P-channel FETs, and the FETs m2 and m4 are N-channel FETs. One of the source and drain of the FET m9a is connected to the node N2a between the FETs ml a and ml b, and one of the source and drain of the FET mlOa is connected to the node N4a between the FETs m3a and m3b.

[0244] Driver 26 has inverter 26c preceding inverter 26a. When VCTRL is L, inverter 26c outputs VDD, and inverter 26a outputs VLCTRL as CTRL, with inverter circuits 14 and 16 operating in BI mode. When VCTRL is H, inverter 26c outputs VGND, and inverter 26a outputs VSCTRL as CTRL, with inverter circuits 14 and 16 operating in ST mode. Other structures are similar to... Figure 17 Same as above, description omitted. Although the power supply voltage and ground voltage of inverter 26c are VDD and VGND, they can also be VSCTRL and VLCTRL, just like inverter 26a. Driver 26 can also be configured to use only inverter 26a instead of inverters 26a and 26c.

[0245] like Figure 21 As shown in (b), inverter circuit 14 has FETs m1a, m1b, m2a, m2b, m9, and m9a, and inverter circuit 16 has FETs m3a, m3b, m4a, m4b, m10, and m10a. FETs m1a, m1b, m3a, m3b, m9a, and m10a are P-channel FETs, and FETs m2a, m2b, m4a, m4b, m9, and m10 are N-channel FETs.

[0246] One of the source and drain terminals of FET m9a and FET m10a is connected to the control line CTRLLP, and the other of the source and drain terminals of FET m9 and FET m10 is connected to the control line CTRLN. Driver 26 has inverters 26a and 26b. Inverter 26a outputs a signal to the control line CTRLN. Inverter 26b inverts the output of inverter 26a and outputs it to the control line CTRLLP. Other structures are similar to... Figure 17 and Figure 21 (a) is the same, so the explanation is omitted.

[0247] like Figure 21 (a) and Figure 21 As in (b), in inverter circuits 14 and 16, at least one of the P-channel FETs m1a and m3a and the N-channel FETs m2 and m4 is connected in series. It is sufficient to provide at least one of the P-channel FETs m9a and m10a and the N-channel FETs m9 and m10.

[0248] [Explanation of Electronic Circuits]

[0249] Figure 22 This is a block diagram illustrating the electronic circuitry of Embodiment 2. (As shown...) Figure 22As shown, the electronic circuit 102 has a cell array 20 and a control circuit 28. The cell array 20 is divided into multiple subarrays 22. The storage capacity of the subarray 22 is, for example, 8 kilobytes. Multiple memory cells 10 are arranged in a matrix in the subarray 22. The subarray 22 is connected to a bus 25. The number of subarrays 22 can be appropriately designed.

[0250] A power switch 30 and peripheral circuitry 38 are provided in subarray 22. The power switch 30 sets the power supply voltage for each subarray 22. The peripheral circuitry 38 controls the mode of each memory cell 10 according to the mode control signal.

[0251] The control circuit 28 has a register 40. The control circuit 28 stores the UDF (User Data Function) of each block received from the external circuit in the register 40. The control circuit 28 uses the PS control signal to control the power switches 30 of each subarray 22. The control circuit 28 inputs and outputs data to the subarray 22 via the bus 25. At least some of the functions of the control circuit 28 can also be performed in cooperation with external processor circuits such as a CPU and software.

[0252] [Subarray Description]

[0253] Figure 23 This is a block diagram of the subarray in Embodiment 2. For example... Figure 23 As shown, subarray 22 is divided into multiple blocks 24 (e.g., eight) each containing memory cells 10. The storage capacity of block 24 is, for example, 1 kilobyte. The number of blocks 24 can be appropriately designed. Multiple memory cells 10 are arranged in a matrix within subarray 22. Within subarray 22, word lines WL and control lines CTRL extend along the row direction, and bit lines BL extend along the column direction. Each memory cell 10 is connected to word lines WL, bit lines BL, control lines CTRL, power lines 15a, and ground lines 15b.

[0254] A power switch 30 and peripheral circuits 38 are provided corresponding to each subarray 22. The control circuit 28 controls the power switch 30 and peripheral circuits 38.

[0255] The power switch 30 can set the power supply voltages VVDD-VGND to voltages V3, V2, V1, and V0 for each block 24. The peripheral circuitry 38 includes a WL decoder 31, a column decoder 32, a precharge circuit 33, and a read / write circuit 34.

[0256] During the waiting period, WL decoder 31 selects the word line WL based on the row address. Column decoder 32 selects the bit line BL based on the column address. Precharge circuit 33 precharges bit line BL. Read / write circuit 34 writes data to or reads data from the bistable circuit 12 of the memory cell 10 selected by WL decoder 31 and column decoder 32 and outputs it to bus 25.

[0257] During the holding period, the control circuit 28 sets one or more memory cells 10 to ST mode and sets VVDD to voltage V1. Thus, the memory cell 10 enters a holding state.

[0258] [Description of the action]

[0259] Figure 24 This is a flowchart illustrating the operation of Embodiment 2. For example... Figure 24 As shown, the control circuit 28 turns on the power supply of the cell array 20 according to the instruction from the external circuit (step S10). For example, the control circuit 28 sets all memory cells 10 of the block 24 to BI mode, turns on the power switch PS1, and turns off the power switches PS2 and PS3. As a result, all blocks 24 enter a waiting state.

[0260] The control circuit 28 performs read and write operations while in a waiting state (step S12). The control circuit 28 determines whether it has received an instruction to shut down the cell array 20 from an external circuit (step S14). If it is "no", it returns to step S12. If it is "yes", the control circuit 28 performs a hold operation and shuts down (step S17). Then, it ends and returns to step S10.

[0261] [Explanation of UDF settings]

[0262] Setting the UDF action is the same as in Example 1. Figure 7 (b) is the same, so the explanation is omitted.

[0263] [Explanation of Type A of the Hold Action]

[0264] As Figure 24 The action in step S17 is described in terms of type A of the holding action. Figure 25 This is a flowchart illustrating type A of the holding action in Embodiment 2. Figure 26 (a) to Figure 26 (e) is a schematic diagram showing the cell array of type A of the holding action in embodiment 2. Figure 27 (a) to Figure 27 (e) is a schematic diagram showing the cell array and blocks of type A of the holding action in embodiment 2. Figure 26 (a) to Figure 26 (e) is an example of holding the action according to each subarray 22. Figure 27 (a) to Figure 27 Example (e) is an example of holding the action per block 24. Whether holding the action is performed per subarray 22 or per block 24, the basic action is the same. The types of holding actions B and C are also the same.

[0265] In Figure 24 Step S17, the control circuit 28 starts the hold operation. At this time, as shown in (a) of Fig. 8, all the blocks 24 (or sub-arrays 22) are in the standby (ST) state. As shown in (a) of Fig. 8, all the blocks 24 are in the standby (ST) state. Figure 25 As shown in (a) of Fig. 8, all the blocks 24 are in the standby (ST) state. Figure 26 As shown in (a) of Fig. 8, all the blocks 24 are in the standby (ST) state. Figure 27 As shown in (a) of Fig. 8, all the blocks 24 are in the standby (ST) state.

[0266] The control circuit 28 reads out the UDFs corresponding to the blocks 24 (or sub-arrays 22) from the register 40 (step S56). The control circuit 28 extracts the blocks 24 (sub-arrays 22) whose UDFs are set (e.g., high level H), and turns them off all at once (step S58). For example, the control circuit 28 sets the power supply voltages VVDD-VGND of the corresponding blocks 24 (sub-arrays 22) to the voltage V0. As shown in (b) of Fig. 8, the control circuit 28 turns off all at once 4 of the 9 sub-arrays 22. As shown in (b) of Fig. 8, the control circuit 28 turns off all at once 28 of the 72 blocks 24. Figure 26 As shown in (b) of Fig. 8, the control circuit 28 turns off all at once 28 of the 72 blocks 24. Figure 27 As shown in (b) of Fig. 8, the control circuit 28 turns off all at once 28 of the 72 blocks 24.

[0267] The control circuit 28 selects the first block 24a (sub-array 22a) whose UDF is not set (i.e., is an object of holding) (step S60). The control circuit 28 sets the first block 24a (sub-array 22a) to the standby (ST) state (step S62). For example, the control circuit 28 sets the control signal VCTRL to L in the state where the power supply voltages VVDD-VGND of the block 24a (sub-array 22a) are set to the voltage V3. As shown in (c) of Fig. 8, the sub-array 22a becomes the standby (ST) state. As shown in (c) of Fig. 8, the block 24a becomes the standby (ST) state. Figure 26 As shown in (c) of Fig. 8, the sub-array 22a becomes the standby (ST) state. As shown in (c) of Fig. 8, the block 24a becomes the standby (ST) state. Figure 27 As shown in (c) of Fig. 8, the sub-array 22a becomes the standby (ST) state. As shown in (c) of Fig. 8, the block 24a becomes the standby (ST) state.

[0268] The control circuit 28 determines whether it is the last block 24 (sub-array 22) (step S64). When it is "No", it proceeds to the next block 24 (sub-array 22) (step S66), and returns to step S60. The blocks 24 (sub-arrays 22) which are objects of holding are sequentially set to the standby (ST) state. As shown in (d) of Fig. 8, all the sub-arrays 22 which are objects of holding become the standby (ST) state. As shown in (d) of Fig. 8, all the blocks 24 which are objects of holding become the standby (ST) state. Figure 26 As shown in (d) of Fig. 8, all the sub-arrays 22 which are objects of holding become the standby (ST) state. As shown in (d) of Fig. 8, all the blocks 24 which are objects of holding become the standby (ST) state. Figure 27 As shown in (d) of Fig. 8, all the sub-arrays 22 which are objects of holding become the standby (ST) state. As shown in (d) of Fig. 8, all the blocks 24 which are objects of holding become the standby (ST) state.

[0269] When the determination in step S64 is "Yes", the control circuit 28 sets all the blocks 24 (sub-arrays 22) as the holding targets to the holding state all at once or sets them to the holding state every multiple of blocks 24 (sub-arrays 22) (step S68). As shown in (e) of Fig. 14, all the sub-arrays 22 as the holding targets become the holding state. As shown in (e) of Fig. 15, all the blocks 24 as the holding targets become the holding state. After that, the process ends. Figure 26 Figure 27

[0270] [Explanation of Type B of Holding Action]

[0271] Type B of holding action will be explained. Figure 28 is a flowchart showing Type B of holding action of Embodiment 2. Figure 29 (a) to Figure 29 (e) are schematic diagrams showing the cell array of Type B of holding action of Embodiment 2. Figure 30 (a) to Figure 30 (e) are schematic diagrams showing the cell array and the block of Type B of holding action of Embodiment 2.

[0272] As shown in (a) of Fig. 14, the control circuit 28 sets each block 24 (or sub-array 22) to the sleep (ST) state (step S70). For example, the control circuit 28 sets the power supply voltage VVDD-VGND of each block 24 (sub-array 22) to the voltage V2 and sets the control signal VCTRL to L. As shown in (c) of Fig. 14, each sub-array 22 becomes the sleep (ST) state. As shown in (c) of Fig. 15, each block 24 becomes the sleep (ST) state. Figure 28 Figure 29 Figure 30

[0273] The control circuit 28 extracts the blocks 24 (sub-arrays 22) whose UDF is set (e.g., high level H) by the readout in step S56 and closes them all at once (step S58). As shown in (b) of Fig. 14, the control circuit 28 sets the four sub-arrays 22 to the closed state all at once. As shown in (b) of Fig. 15, the control circuit 28 sets the 28 blocks 24 to the closed state all at once. Figure 29 Figure 30

[0274] The control circuit 28 sets the first block 24a (sub-array 22a) selected in step S60 to the sleep (ST) state (step S72). For example, the control circuit 28 sets the power supply voltage VVDD-VGND of the block 24a (sub-array 22a) to the voltage V2 and sets the control signal VCTRL to L. As shown in (c) of Fig. 14, the sub-array 22a becomes the sleep (ST) state. As shown in (c) of Fig. 15, the block 24a becomes the sleep (ST) state. Figure 29 Figure 30 ​​​​​​​​(a) to (c) of FIG. 8, the first block 24a (or the subarray 22a) becomes the sleep (ST) state.

[0275] When the determination in step S64 is "No", steps S60 and S72 are performed on the next block 24 (subarray 22). As Figure 29 (d) of FIG. 8, all of the subarrays 22 as the holding objects become the sleep (ST) state. As Figure 30 (d) of FIG. 8, all of the blocks 24 as the holding objects become the sleep (ST) state.

[0276] When the determination in step S64 is "Yes", the control circuit 28 collectively sets all of the blocks 24 (subarrays 22) as the holding objects to the holding state (step S68). As Figure 29 (e) of FIG. 8, all of the subarrays 22 as the holding objects become the holding state. As Figure 30 (e) of FIG. 8, all of the blocks 24 as the holding objects become the holding state. After that, the process ends. The other actions are the same as those of the type A of the holding action.

[0277] [Explanation of the Type C of the Holding Action]

[0278] The type C of the holding action will be described. Figure 31 is a flowchart showing the type C of the holding action of Embodiment 2. Figure 32 (a) to Figure 32 (e) of FIG. 8 are schematic diagrams showing the type C of the holding action of the unit array. Figure 33 (a) to Figure 33 (e) of FIG. 8 are schematic diagrams showing the type C of the holding action of the unit array and the block.

[0279] As shown in Figure 31 , steps S70, S56, S58, S60, S72 are the same as those of the type B of the holding action, Figure 32 (a) to Figure 32 (c) of FIG. 8, and Figure 33 (a) to Figure 33 (c) of FIG. 8, respectively. Figure 29 (a) to Figure 29 (c) of FIG. 8, and Figure 30 (a) to Figure 30 (c) of FIG. 8 are the same as those of

[0280] The control circuit 28 sets the first block 24a (or the subarray 22a) as the holding object to the sleep (ST) state in step S72, and then sets the block 24a (or the subarray 22a) to the holding state (step S74). As Figure 32 (d) of FIG. 8, the subarray 22a becomes the holding state. As Figure 33 (d) of FIG. 8, the block 24a becomes the holding state.

[0281] Then, the block 24 (subarray 22) as the holding object is sequentially set to the dormant (ST) state (step S72), and then set to the holding state (step S74). When the determination in step S64 is "Yes", as in (e) of Figure 32 (e), all of the subarrays 22 as the holding object become the holding state. As in (e) of Figure 33 (e), all of the blocks 24 as the holding object become the holding state. Then, the process ends. The other actions are the same as those of the type B of the holding action.

[0282] [Example of the control circuit of the type B of the holding action]

[0283] Figure 34 is a block diagram showing an example of the control circuit of the type B of the holding action. The control circuit 28B has the register 40, the mode control circuit 45, and the PS control circuit 44. The number of bits of the register 40 is equal to or more than the number of the blocks 24, i.e., NSA x Nblock. Blocks 24A to 24B among the NSA x Nblock blocks 24 are described.

[0284] As in step S32 of (b) of the embodiment 1, Figure 7 As in step S32 of (b) of the embodiment 1,

[0285] The mode control circuit 45 outputs the mode control signal VCTRL. The PS control circuit 44 controls the power supply switches PS1A to PS1B, PS2A to PS2B, and PS3A to PS3B of the blocks 24A to 24B in accordance with the UDF held in the register 40.

[0286] The PS control circuit 44 has the OR circuit 60, the AND circuit 61, the OR circuit 62, the OR circuit 63, the NAND circuit 64, the AND circuit 65, the AND circuit 66, the OR circuit 67, the OR circuit 68, the OR circuit 69, the AND circuit 70, the AND circuit 71, the OR circuit 72, and the OR circuit 73, the number of which is the same as the number of the blocks 24A to 24B.

[0287] The output signals of the UDF storage sections 40A to 40B and the control signal ENNLB are input to an OR circuit 60. The output signal of the OR circuit 60 and the control signal ENNLB are input to an AND circuit 61. The output signal of the AND circuit 61 and the control signal ENSLP are input to an OR circuit 62. The PS control signals VPG1A to VPG1B are output from the OR circuit 62. The PS control signals VPG1A to VPG1B are input to the gates of the power switches PS1A to PS1B of the blocks 24A to 24B, respectively.

[0288] The output signals of the UDF storage sections 40A to 40B and the control signal ENRB are input to an OR circuit 63. The output signals of the UDF storage sections 40A to 40B and the control signal ENNLB are input to a NAND circuit 64. The output signal of the OR circuit 63 and the output signal of the NAND circuit 64 are input to an AND circuit 65. The output signal of the AND circuit 65 and the control signal ENNLB are input to an AND circuit 66. The output signal of the AND circuit 65 and the control signal ENSLP are input to an OR circuit 67. The PS control signals VPG2A to VPG2B are output from the OR circuit 67. The PS control signals VPG2A to VPG2B are input to the gates of the power switches PS2A to PS2B of the blocks 24A to 24B, respectively.

[0289] The output signals of the UDF storage sections 40A to 40B and the control signal ENRB are input to an OR circuit 68. The output signals of the UDF storage sections 40A to 40B and the control signal ENNLB are input to an OR circuit 69. The output signal of the OR circuit 68 and the output signal of the OR circuit 69 are input to an AND circuit 70. The output signal of the AND circuit 70 and the control signal ENNLB are input to an AND circuit 71. The output signal of the AND circuit 71 and the control signal ENSLP are input to an OR circuit 72. The output signal of the OR circuit 72 and the control signal ENRB are input to an OR circuit 73. The PS control signals VPG3A to VPG3B are output from the OR circuit 73. The PS control signals VPG3A to VPG3B are input to the gates of the power switches PS3A to PS3B of the blocks 24A to 24B, respectively.

[0290] Figure 35 (a) to (c) of FIG. 7 are graphs showing the levels of the respective signals and the operation of the power switch of the type B of the hold operation. As shown in (a) of FIG. 7, the output signal of the UDF storage section 40A and the control signal ENNLB are input to the OR circuit 60. The output signal of the OR circuit 60 and the control signal ENNLB are input to the AND circuit 61. The output signal of the AND circuit 61 and the control signal ENSLP are input to the OR circuit 62. The PS control signal VPG1A is output from the OR circuit 62. The PS control signal VPG1A is input to the gate of the power switch PS1A of the block 24A. Figure 35 (e) of FIG. 7 is a graph showing the levels of the respective signals and the operation of the power switch of the type B of the hold operation. As shown in (e) of FIG. 7, the output signal of the UDF storage section 40B and the control signal ENNLB are input to the OR circuit 60. The output signal of the OR circuit 60 and the control signal ENNLB are input to the AND circuit 61. The output signal of the AND circuit 61 and the control signal ENSLP are input to the OR circuit 62. The PS control signal VPG1B is output from the OR circuit 62. The PS control signal VPG1B is input to the gate of the power switch PS1B of the block 24B. Figure 35As shown in (a), in the standby (BI) state, the control signals ENRB, ENLB, ENSLP, and VCTRL are H, L, L, and H, respectively. Let the UDFs of blocks 24A and 24B be L and H, respectively. At this time, VPG1A to VPG1B are L, and power switches PS1A to PS1B are on. VPG2A to VPG2B are L, and power switches PS2A to PS2B are off. VPG3A to VPG3B are H, and power switches PS3A to PS3B are off. Thus, in the standby (BI) state, regardless of the UDF, power switches PS1A to PS1B are on, and power switches PS2A to PS2B and PS3A to PS3B are off. Therefore, the power supply voltage VVDD-VGND for all blocks 24A to 24B is voltage V3.

[0291] like Figure 35 As shown in (b), in the sleep (BI) state, the control signals ENRB, ENLB, ENSLP, and VCTRL are H, L, H, and H, respectively. VPG1A to VPG1B are H, and power switches PS1A to PS1B are off. VPG2A to VPG2B are H, and power switches PS2A to PS2B are on. VPG3A to VPG3B are H, and power switches PS3A to PS3B are off. Thus, in the sleep (BI) state, regardless of the UDF, power switches PS1A to PS1B and PS3A to PS3B are off, and power switches PS2A to PS2B are on. Therefore, the power supply voltage VVDD-VGND for all blocks 24A to 24B becomes voltage V2, thus entering the sleep (BI) state. Figure 28 In step S70, such as Figure 35 As in (b), all blocks become dormant (BI).

[0292] exist Figure 28 In steps S70, S56, and S58, block 24 with UDF H is set to a sleep (BI) state, and the block with UDF L is also cut off. Figure 35 As shown in (c), the control signal ENLB is from Figure 35 The waiting (BI) state of (a) changes from L to H. VPG1A to VPG1B change from L to H, and VPG2A changes from L to H. As a result, power switch PS2A changes from open to closed. Power switches PS1A and PS1B change from closed to open. Power switches PS2B, PS3A, and PS3B remain open. As a result, the power supply voltage VVDD-VGND of block 24A, which is being held, changes from voltage V3 to V2, and block 24A enters the sleep (BI) state. The power supply voltage VVDD-VGND of block 24B, where UDF is set, becomes voltage V0, and block 24B enters the off state.

[0293] existFigure 28 In step S72, the block 24A is switched from the sleep (BI) state to the sleep (ST) state. As shown in (d) of FIG. 7, the control signals ENRB, ENNLB, and ENSLP are maintained at the states of (c) of FIG. 7. The states of the power switches are not changed, and the power voltages VVDD-VGND of the blocks 24A and 24B are maintained at the voltages V2 and V0, respectively. The control signal VCTRL is changed from H to L. Thus, the mode of the block 24A as the object is switched from the BI mode to the ST mode. Thus, the block 24A becomes the sleep (ST) state. Figure 35 Figure 35 In step S72, the block 24A is switched from the sleep (BI) state to the sleep (ST) state. As shown in (d) of FIG. 7, the control signals ENRB, ENNLB, and ENSLP are maintained at the states of (c) of FIG. 7. The states of the power switches are not changed, and the power voltages VVDD-VGND of the blocks 24A and 24B are maintained at the voltages V2 and V0, respectively. The control signal VCTRL is changed from H to L. Thus, the mode of the block 24A as the object is switched from the BI mode to the ST mode. Thus, the block 24A becomes the sleep (ST) state.

[0294] By performing the loop of steps S60 to S66 of FIG. 6, the sleep (BI) state is switched to the sleep (ST) state for all the blocks 24 as the holding objects. Figure 28 In step S68 of FIG. 6, all the blocks 24A as the holding objects are set from the sleep (ST) state to the hold state. As shown in (e) of FIG. 7, the control signals ENNLB, ENSLP, and VCTRL are maintained at the states of (d) of FIG. 7, and the control signal ENRB is set from H to L. Thus, VPG2A and VPG3A are changed from H to L, the power switch PS2A is changed from ON to OFF, and the power switch PS3A is changed from OFF to ON. Thus, the power voltages VVDD-VGND of the blocks 24A as the holding objects are changed from the voltage V2 to the voltage Vl, and all the blocks 24A as the holding objects become the hold state. The power voltages VVDD-VGND of the block 24B are maintained at the voltage V0.

[0295] Figure 28 Figure 35 is a timing chart of the control signals of the type B of the hold operation. The control signals VCTRL1 to VCTRLn are the control signals VCTRL corresponding to the blocks 24i to 24n. The blocks 24i to 24k are the blocks as the holding objects, and the blocks 24k+1 to 24n are the blocks as the closing objects. Figure 35 As shown in (a) of FIG. 8, the period from the time t20 to the time t21 is the wait (BI) period, and the control signals ENNLB and ENSLP are L, and ENRB and VCTRL1 to VCTRLn are H. The period from the time t21 to the time t22 is the sleep (BI) period, and the control signal ENSLP is H.

[0296] Figure 36 At the time t23, the control signal VCTRL1 is changed from H to L. Thus, the mode of the block 24i as the object is switched from the BI mode to the ST mode. Thus, the block 24i becomes the sleep (ST) state.

[0297] As shown in (a) of FIG. 8, the period from the time t20 to the time t21 is the wait (BI) period, and the control signals ENNLB and ENSLP are L, and ENRB and VCTRL1 to VCTRLn are H. The period from the time t21 to the time t22 is the sleep (BI) period, and the control signal ENSLP is H. Figure 36 At the time t23, the control signal VCTRL1 is changed from H to L. Thus, the mode of the block 24i as the object is switched from the BI mode to the ST mode. Thus, the block 24i becomes the sleep (ST) state.

[0298] Figure 28 ​​​​S58), the control signal ENNLB becomes H. Thus, the blocks 241 to 24k as the retention targets maintain the dormant (BI) state, and the blocks 24k+1 to 24n of the UDF become the closed state. This state is the period Tl.

[0299] At time t24 Figure 28 S72), the control signal VCTRLl of the first block 241 as the retention target becomes L. Thus, the mode of the block 241 is switched from the BI mode to the ST mode, and the block 241 becomes the dormant (ST) state. The period T2 from time t24 onward is the period in which the block 241 is in the ST mode. At time t25, the control signal VCTRL2 is set to L for the second block 242 as the retention target. The block 242 becomes the dormant (ST) state, and becomes the period T2.

[0300] By performing the loop of steps S60 to S66 of Figure 28 S68 for all the blocks 241 to 24k as the retention targets. For all the blocks 241 to 24k as the retention targets, the BI mode is switched to the ST mode. At time t26 Figure 28 S68), the control signal ENRB becomes L. Thus, all the blocks 241 to 24n as the retention targets become the retention state.

[0301] At time t27, the control signal ENRB becomes H. Thus, the blocks 241 to 24k as the retention targets become the dormant (ST) state. The control signals VCTRLl to VCTRLk are sequentially set to H. The blocks 24 to 24k sequentially become the dormant (BI) state. At time t28, the mode switching from the ST mode to the BI mode ends.

[0302] [Example of Control Circuit of Type C of Retention Operation]

[0303] Figure 37 is a block diagram showing an example of the control circuit of the type C of the retention operation. The control circuit 28C is similar to the control circuit 28B of Figure 34 The OR circuit 63, the NAND circuit 64, and the AND circuit 65 are replaced with the NAND circuit 74, and the OR circuits 68, 69, and the AND circuit 70 are replaced with the OR circuit 75, compared with the control circuit 28B of

[0304] The output signals and control signals ENLB of the UDF storage units 40A to 40B are input to the NAND circuit 74. The output signals of the NAND circuit 74 and the control signals ENRB for each block 24A to 24B are input to the AND circuit 65. The output signals of the UDF storage units 40A to 40B and the control signals ENRB for each block 24A to 24B are input to the OR circuit 75. The output signal of the OR circuit 75 is input to the AND circuit 71. Other structures are similar to... Figure 34 The control circuit 28B is the same, so its description is omitted. In the control circuit 28C, it is possible to maintain each block 24A to 24B.

[0305] The levels of each signal and the operation of the power switch are related to Figure 35 (a) to Figure 35 The (e) is the same, so the explanation is omitted.

[0306] Figure 38 This is a timing diagram of the control signals for maintaining action type C. Control signals ENRB1 to ENRBn are the control signals ENRB corresponding to blocks 241 to 24n.

[0307] like Figure 38 As shown, between time t20 and time t23, the control signals ENRB1 to ENRBn are H. Other than... Figure 36 same.

[0308] At time t24 ( Figure 31 In step S72), for the first block 241, which is being held, the control signal VCTRL1 becomes L. This switches the mode of block 241 from BI mode to ST mode, and block 241 enters a sleep (ST) state. At time t25, for block 241, the control signal ENRB1 becomes L. This puts block 241 into a hold state. For the second block 242, which is being held, the control signal VCTRL2 becomes L. Block 242 enters a sleep (ST) state.

[0309] By execution Figure 31 The cycle of steps S60 to S66 is repeated, and steps S72 and S74 are executed sequentially for all blocks 241 to 24k that are being held. When the mode switching and holding for all blocks 241 to 24k that are being held are completed, at time t26, all blocks 241 to 24n that are being held are in a held state.

[0310] At time t27 and thereafter, control signals ENRB1~ENRBk and control signals VCTRL1~VCTRLk sequentially become H. Blocks 241~24k sequentially enter sleep (BI) state. At time t28, the mode switch from ST mode to BI mode ends.

[0311] [Simulation]

[0312] The BET and the latency of the mode switching of the standby (BI) state and the standby (ST) state of the electronic circuit of Example 2 were simulated. Comparative Example 2 was also simulated. In Comparative Example 2, the UDF-based simultaneous cutting of the sub-arrays 22 and the blocks 24 was not performed, all the blocks were set to the standby (BI) state, and the mode switching was performed for each block in order. Finally, all the blocks 24 were simultaneously set to the standby state.

[0313] The simulation conditions were as follows. VDDH, VDDL, VGND, VSCTRL, VLCTRL, and WL were 1.2 V, 0.2 V, 0 V, 0.3 V, 0.1 V, and 0 V, respectively. The H and L of VPG1 were 1.4 V and 0 V, respectively. The H and L of VPG2 were 1.2 V and -0.2 V, respectively. The H and L of VPG3 were 1.4 V and 0 V, respectively. The H and L of VCTRL were 1.2 V and 0 V, respectively. The bit lines BL and BLB were 1.2 V in the standby state and the sleep state, and 0 V in the standby state and the off state. As the time for charging the driver 26 at the time of the mode switching, 15 ns was set for each sub-array 22. The storage capacities of the sub-arrays 22 and the blocks 24 were 8 kbytes and 1 kbytes, respectively.

[0314] The ratio of the number of the memory cells in which the UDF was set to the number of all the memory cells in the cell array 20 was set as the UDF ratio. The case where the storage capacity of the cell array 20 was 32 kbytes, 256 kbytes, and 2 Mbytes was simulated.

[0315] Figure 39 (a) to (c) of FIG. 8 are graphs showing the BET with respect to the UDF ratio in the types A to C and Comparative Example 2, Figure 39 Figure 39 (d) to (f) of FIG. 8 are graphs showing the latency with respect to the UDF ratio. As shown in (a) to (c) of FIG. 8, in Comparative Example 2, the BET was constant regardless of the UDF ratio. In the type A, the BET was the same as that of Comparative Example 2 when the UDF ratio was 0%. When the UDF ratio became larger, the BET became shorter. In the type B, the BET was smaller than that of Comparative Example 2 when the UDF ratio was 0%. This is because, in the type B, all the blocks were simultaneously set to the sleep (BI) state before the standby, and thus the power consumption due to the leakage current of the blocks during the standby process could be suppressed. In the type C, the BET was smaller than that of the type B when the UDF ratio was 0%. This is because the switching from the sleep (BI) state to the sleep (ST) state and the standby were performed for each block as an object in order, and thus the standby time in the sleep (ST) state could be shortened, and the power consumption could be suppressed. Figure 39 Figure 39 Figure 39 As shown in (a) to (c) of FIG. 8, in Comparative Example 2, the BET was constant regardless of the UDF ratio. In the type A, the BET was the same as that of Comparative Example 2 when the UDF ratio was 0%. When the UDF ratio became larger, the BET became shorter. In the type B, the BET was smaller than that of Comparative Example 2 when the UDF ratio was 0%. This is because, in the type B, all the blocks were simultaneously set to the sleep (BI) state before the standby, and thus the power consumption due to the leakage current of the blocks during the standby process could be suppressed. In the type C, the BET was smaller than that of the type B when the UDF ratio was 0%. This is because the switching from the sleep (BI) state to the sleep (ST) state and the standby were performed for each block as an object in order, and thus the standby time in the sleep (ST) state could be shortened, and the power consumption could be suppressed. ​​​

[0316] like Figure 39 (d) to Figure 39 As shown in (f), in types A to C, compared to Comparative Example 2, latency can be reduced when the UD ratio increases. The latency is the same between types A and C.

[0317] As illustrated in the simulation above, in type A, although the BET is long, a sleep state can be omitted, making control simple. In type B, the BET falls between types A and C. Controlling type B is more complex than type A due to the sleep state requirement, but simpler than type C because it involves simultaneous holding. In type C, although the BET is short, control is complex because holding is performed sequentially.

[0318] Next, comparative example 2-1, comparative example 2-2 and type C waiting power were simulated. In comparative example 2-1, no UDF-based shutdown was performed and the device was in standby (BI) state when holding was performed. In comparative example 2-2, no UDF-based shutdown was performed and the device was in hibernation (BI) state.

[0319] Figure 40 (a) to Figure 40 Figure (c) is a comparison diagram of the VNR-SRAM and 6T-SRAM of Example 2. The standby power of the 6T-SRAM in both standby and sleep states is compared with the standby power of the VNR-SRAM of type C. Figure 40 (a) to Figure 40 As shown in (c), in the 6T-SRAM, when switching from standby to hibernation mode, the standby power can be reduced by approximately 30%. With operation type C maintained, even when the UD ratio is 0%, the standby voltage can be reduced by 90%. With the UD ratio at 100%, the standby power can be reduced by 99%.

[0320] According to Example 2, as Figure 17 , Figure 21 (a) and Figure 21 As in (b), memory cell 10 has a bistable circuit 12, which has an inverter circuit 14 (first inverter circuit) and an inverter circuit 16 (second inverter circuit) capable of switching between a BI mode (first mode) with substantially no hysteresis in the transfer characteristics and an ST mode (second mode) with hysteresis in the transfer characteristics. In the bistable circuit 12, the output node and input node of inverter circuit 14 are connected to the input node and output node of inverter circuit 16, respectively.

[0321] like Figure 25 , Figure 28 as well as Figure 31As in steps S56 and S58, the control circuit 28 turns off (discharges) one or more first memory cells 10 in which data that can not be retained is stored among the plurality of memory cells 10. As in steps S62 and S72, the control circuit 28 sets the bistable circuit 12 in the remaining one or more second memory cells 10 among the plurality of memory cells 10 to the ST mode, and as in steps S68 and S74, supplies the voltage VI (second power supply voltage) to the bistable circuit 12 in the second memory cells 10 in a state in which the ST mode is maintained. The voltage VI is lower than the voltage V3 (first power supply voltage) supplied to the bistable circuit 12 at the time of reading and / or writing data, and the bistable circuit 12 in the ST mode is able to retain data at the voltage.

[0322] Thus, since the memory cells in which data that can not be retained is stored are turned off, power consumption for switching the mode of the memory cells in which data that can not be retained is stored and maintaining the retention state can be suppressed. Furthermore, the latency can be reduced.

[0323] As Figure 22 and Figure 23 , each block 24 of the cell array 20 is divided into a plurality of blocks 24, and each block 24 contains at least 2 memory cells 10. As Figure 25 , Figure 28 and Figure 31 , the control circuit 28 extracts one or more first blocks in which data that can not be retained is stored from the plurality of blocks 24. As in step S58, the control circuit 28 turns off (discharges) the first blocks. Then, as in steps S62 and S72, the control circuit 28 sets the bistable circuit in one or more second blocks among the plurality of blocks 24 to the ST mode. As in steps S68 and S74, the control circuit 28 supplies the voltage VI to the bistable circuit 12 in the second blocks in a state in which the ST mode is maintained.

[0324] Thus, since the first blocks in which the UDF is set are turned off in units of blocks, power consumption for switching the mode of the first blocks and maintaining the retention state can be suppressed. Furthermore, the latency can be reduced. Furthermore, since the first blocks in which the UDF is set are turned off first, power consumption due to leakage current while waiting for the mode switching operation can be reduced.

[0325] As in the types B and C of the retention operation, the control circuit 28, before setting the block that is a retention object to the ST mode, as in Figure 28 and Figure 31As in step S70, a voltage V2 (third power supply voltage) is supplied to the second block, which is being held, as a power supply voltage (i.e., set to sleep mode). Voltage V2 is a power supply voltage that is lower than voltage V3 and higher than voltage V1, and the bistable circuit 12 in BI mode can hold the data. Thus, power consumption during the waiting-to-turn-off and holding period can be suppressed.

[0326] As in step S72, while supplying voltage V2 to the bistable circuit 12 in the second block, the control circuit 28 sets the bistable circuit 12 in the second block to ST mode. This suppresses power consumption during the hold period.

[0327] For example, maintaining the type C of the action. Figure 38 In this state, while the control circuit 28 is supplying voltage V2 to the bistable circuit of block 241 (the third block) in the plurality of second blocks, the bistable circuit 12 in block 241 is set to ST mode. Figure 31 In step S72 (during period T2), voltage V1 is provided to the bistable circuit 12 in block 241 in ST mode (step S74, during period T3). Afterwards, while providing voltage V1 to the bistable circuit 12 in block 242 (the fourth block), which is different from block 241 among the plurality of second blocks, the control circuit 28 sets the bistable circuit 12 in block 242 to ST mode, providing voltage V1 to the bistable circuit 12 in ST mode within block 242. This shortens the waiting period and suppresses power consumption.

[0328] For example, maintaining the type B of the action. Figure 36 Thus, when the control circuit 28 supplies voltage V2 to the bistable circuit 12 in the second block, it sets the bistable circuit 12 in the second block to ST mode. Then, when the bistable circuit 12 in the second block is in ST mode, it supplies voltage V1. Figure 28 Step S74, Figure 36 (at time t26). Therefore, compared to type C, control can be performed more simply. The control circuit 28 can also provide voltage V2 when the bistable circuits 12 in the multiple second blocks are set to ST mode. In addition, the control circuit 28 can also divide the multiple second blocks into multiple groups, each group containing one or more second blocks, and provide voltage V2 sequentially according to each divided group.

[0329] The register 40 (storage circuit) is provided outside the cell array 20, and stores a UDF (information indicating a block storing data that can not be held) received from an external circuit. The control circuit 28 extracts a block storing data that can not be held, based on the UDF (step S56). Thus, compared with a method in which a storage circuit storing the UDF is provided in each sub-array 22 or block 24, the UDF can not be transmitted to the control circuit 28 via the bus 25 or the like, and the control becomes simple.

[0330] As Figure 17 , the inverter circuits 14 and 16 have FETs ml and m3 (first FETs), FETs m2b and m4b (second FETs), FETs m2a and m4a (third FETs), and FETs m9 and mlO (fourth FETs). The FETs ml and m3 are P-channel (channel of a first conduction type) FETs whose sources are connected to a power supply line 15a (first power supply line), whose drains are connected to output nodes Q and QB, and whose gates are connected to input nodes Nl and N3. The FETs m2b and m4b are N-channel (channel of a second conduction type opposite to the first conduction type) FETs whose sources are connected to a ground line 15b (second power supply line), whose drains are connected to intermediate nodes N2 and N4, and whose gates are connected to the input nodes Nl and N3. The FETs m2a and m4a are N-channel FETs whose sources are connected to the intermediate nodes N2 and N4, whose drains are connected to the output nodes Q and QB, and whose gates are connected to the input nodes Nl and N3. The FETs m9 and mlO (fourth FETs) are N-channel FETs whose one of the source and the drain is connected to the intermediate nodes N2 and N4, whose the other of the source and the drain is connected to a control line CTRL (control node), and whose gate is connected to the output nodes Q and QB. Thus, it is possible to switch the BI mode and the ST mode by the voltage of the control line CTRL.

[0331] Also as in (a) of Figure 21 , the first FETs are FETs m2 and m4, the second FETs are FETs ml a and m3a, the third FETs are FETs ml b and m3b, and the fourth FETs are FETs m9a and mlOa. At this time, the channel of the first conduction type is an N-channel, and the channel of the second conduction type is a P-channel.

[0332] Also as in (b) of Figure 21 , as the first FETs, FETs ml a, ml b, and m3a, m3b connected in series between the power supply line 15a and the output nodes Q and QB are provided.

[0333] Embodiment 3

[0334] In (a) of Figure 17 , Figure 21 of Embodiment 2, and Figure 21In the memory cell 10 of (b), the FETs m9 and m10 that are the feedback transistors FBTr on the pull-down side are N-channel FETs. The FETs m9a and m10a that are the feedback transistors FBTr on the pull-up side are P-channel FETs.

[0335] The type provided with the FETs m9 and m10 is called pull-down feedback PDFB. The type provided with the FETs m9a and m10a is called pull-up feedback PUFB. The type provided with the FETs m9, m9a, m10, and m10a is called pull-up pull-down feedback PUPDFB. The type provided with the power switch 30 between the power supply line 15a and the power supply 15c is called head PS. The type provided with the power switch 30 between the ground line 15b and the ground terminal 15d is called tail PS. Figure 17 The memory cell of (a) is head PS·PDFB. Figure 21 The memory cell of (a) is head PS·PUFB. Figure 21 The memory cell of (b) is head PS·PUPDFB.

[0336] Hereinafter, the problem of Embodiment 2 is described with the head PS·PDFB as an example. In the head PS·PDFB, the voltages of VVDD and CTRL in the standby state and the hold state are as follows. Figure 17

[0337] Standby state (BI mode): VVDD = VVDDH, the voltage of CTRL is VFNL

[0338] Hold state (ST mode): VVDD = VVDDL, the voltage of CTRL is VFNH

[0339] Each voltage is, for example, in the following relationship.

[0340] VFNL < VFNH = VVDDL < VVDDH

[0341] VFNL < VVDDL < VFNH < VVDDH, or

[0342] VFNL < VFNH < VVDDL < VVDDH

[0343] VVDDL, VVDDH, VGND, VFNL, and VFNH are, for example, 0.2 V, 1.2 V, 0.0 V, 0.0 V, and 0.2 V, respectively.

[0344] ​For example, when the node Q is at a high level, the FET m9 is turned on, and the node N2 is charged with the voltage VFNH of the control line CTRL. However, since the FET m9 is of an N-channel type and the threshold voltage Vth of the FET m9 is positive, the charging potential charged from the control line CTRL is substantially VFNH-Vth. Thus, there is a possibility that the feedback effect of the FET m9 as the FBTr is reduced, and the operation stability (e.g., noise margin) of the bistable circuit in the hold state is reduced.

[0345] [Head PS • PDFB]

[0346] Embodiment 3 that solves the above-described problem of the memory cell of Embodiment 2 will be described. Figure 41 is a circuit diagram of the memory cell of the head PS • PDFB • Type 1 of Embodiment 3, Figure 42 is a circuit diagram of the memory cell of the head PS • PDFB • Type 2 of Embodiment 3. The Type 1 is a type in which the driver 26 is not provided, and the Type 2 is a type in which the driver 26 is provided. As Figure 41 and Figure 42 As shown in FIG. 9, the FETs m9 and m10 as the FBTrs are P-channel FETs. The gates of the FETs m9 and m10 are connected to the nodes QB and Q, respectively. The power switch 30 applies a virtual power voltage VVDD to the power line 15a.

[0347] In the Type 1 of Figure 41 , the driver 26 is not provided, and a constant voltage VFN is applied to the control line CTRL. In the Type 2 of Figure 42 , the driver 26 is provided. The driver 26 is an inverter 26a that supplies the voltage VFNL to the control line CTRL when a control signal VCTRL is at a high level, and supplies the voltage VFNH to the control line CTRL when the control signal VCTRL is at a low level. The other structures are the same as those of the memory cell of Embodiment 2, and the description thereof is omitted. Figure 17

[0348] Figure 41 The voltages of VVDD and CTRL in the wait state and the hold state in the head PS • PDFB • Type 1 shown in FIG. 9 are as follows.

[0349] Wait state (BI mode): VVDD = VVDDH, the voltage of CTRL is VFN

[0350] Hold state (ST mode): VVDD = VVDDL, the voltage of CTRL is VFN

[0351] The respective voltages are, for example, in the following relationship.

[0352] VFN = VVDDL < VVDDH

[0353] ​VVDDL < VFN < VVDDH, or

[0354] VFN < VVDDL < VVDDH (in this relationship, it is difficult to charge nodes N3 and N4 from the control line CTRL, and thus this is not preferred)

[0355] VVDDL, VVDDH, VGND, and VFN are, for example, 0.2 V, 1.2 V, 0.0 V, and 0.2 V, respectively.

[0356] Figure 42 The voltages of VVDD and CTRL in the standby state and the hold state in the head PS-PDFB- Type 2 shown are the same as the voltages exemplified in Figure 17 .

[0357] In the memory cell of Embodiment 3 of Figure 41 and Figure 42 , for example, when the node Q is at a high level, the node QB becomes at a low level, and thus the FET m9 is turned on, and the node N2 is charged by the control line CTRL at a voltage of VFN( Figure 41 ) or VFNH( Figure 42 ). Since the FET m9 is a P-channel FET, the gate of the FET m9 is applied with a voltage sufficiently lower than the source and the drain, and thus the voltage of the node N2 can be pulled up to VFN( Figure 41 ) or VFNH( Figure 42 ). Thereby, the feedback effect of the FET m9 is sufficiently produced. Thereby, the operation stability of the bistable circuit in the hold state can be improved.

[0358] In Type 1 shown in Figure 41 , by making VFN sufficiently smaller than VVDDH, even if VFN is a constant voltage, it is possible to switch the ST mode and the BI mode. For example, when the node Q is at a high level, even if the FET m9 is turned on, the voltage of the node N2 is sufficiently lower than VVDDH. Thus, the bistable circuit 12 functions as the BI mode. Thereby, the driver 26 for the control line CTRL in Figure 17 is not needed, and the chip area can be reduced. Also, by making VFN sufficiently lower than VVDDH, the leakage current in the standby state and the hold state can be suppressed.

[0359] In Type 1, in a case where VVDDH is close to VFN, sometimes the transition to the BI mode is not sufficient. As shown in Figure 42 , in Type 2, at the ST mode, the voltage of CTRL is set to VFNH, and at the BI mode, the voltage of CTRL is set to VFNL. Thereby, it is possible to sufficiently transition to the BI mode.

[0360] [Simulation]

[0361] A memory cell of a 6T-SRAM (Comparative Example 3) was simulated, Figure 17 a memory cell of Embodiment 2, Figure 41 a memory cell of Embodiment 3, head PS • PDFB • Type 1, and Figure 42 a memory cell of Embodiment 3, head PS • PDFB • Type 2.

[0362] The channel width W / length L of each FET was as follows.

[0363] FET m1, m3: 100 nm / 60 nm

[0364] FET m2a, m2b, m4a, m4b: 150 nm / 60 nm

[0365] FET m5, m6: 100 nm / 120 nm

[0366] FET m9, m10: 150 nm / 60 nm

[0367] PS1: 300 nm / 60 nm

[0368] PS3: 150 nm / 60 nm

[0369] FET of inverter 26a: 100 nm / 60 nm

[0370] Each voltage was as follows.

[0371] VVDDH = 1.2 V

[0372] VVDDL = 0.2 V

[0373] VGND = 0 V

[0374] VFNH = 0.2 V

[0375] VFNL = 0 V

[0376] VFN = 0.2 V

[0377] Figure 43 (a) of FIG. 10 is a graph showing the transfer characteristics of the inverter circuit in the hold state. Comparative Example 3 indicates the characteristics of the usual state of a 6T-SRAM. As shown in (a) of FIG. 10, in Embodiment 2, the opening of the butterfly characteristic becomes larger than that of Comparative Example 3, and the noise margin becomes larger. In Embodiment 3, Type 1 and Type 2, the noise margin is larger than that of Embodiment 2. Figure 43

[0378] Figure 43 ​(b) is a diagram showing the SNM (Static Noise Margin) in the wait state. VVDD = 1.2V, which is BI mode. "Hold" does not mean ULV hold state, but rather that FETs m5 and m6 are off and data is held. "Read" means that FETs m5 and m6 are on and bit lines BL and BLB are 1.2V. "Write" means that FETs m5 and m6 are on and one of bit lines BL and BLB is 1.2V and the other is 0V.

[0379] like Figure 43 As shown in (b), in Example 3, the SNM is slightly larger compared to Comparative Example 3 and Example 2. This is because, in Example 3, FETs m9 and m10 are P-channel FETs, so the potentials of nodes N3 and N4 are slightly higher than in Example 2. Therefore, in BI mode, a slight feedback based on FETs m9 and m10 is applied. Consequently, the SNM increases slightly.

[0380] Figure 44 (a) is a diagram showing the SNM in the hold state. Figure 44 As shown in (a), in Comparative Example 3, the SNM is approximately 50 mV, while in Example 2, the SNM can be increased to approximately 80 mV. In Example 3, the SNM is approximately 100 mV, which is about 20 mV larger than that in Example 2 and about 50 mV larger than that in Comparative Example 3. In Type 1 and Type 2 of Example 3, the SNM is approximately the same. In Example 3, the SNM is approximately twice that of Comparative Example 2. Thus, in Example 3, compared to Example 2, the SNM in the holding state can be increased, and the operational stability is improved. While ensuring that the SNM is at the same level as that in Example 2 (e.g., 80 mV), the VVDDL can be lower than that in Example 2. Therefore, power consumption can be suppressed.

[0381] The SNM of Type 1 in Example 3 is approximately 6 mV greater than that of Type 2. This is because, in Type 1, no driver 26 is provided, thus effectively biasing the control line CTRL. Although not illustrated, in PUPDFB described later, the noise margin is increased compared to PUFB and PDFB.

[0382] Figure 44 (b) is a graph showing the leakage power in the BI mode. Figure 44(b) shows that, in the standby state (BI mode) of Example 2, the leakage power can be reduced by 25% compared to Comparative Example 3. In Example 3, the leakage power can be reduced by 70% in Type 2 and by 81% in Type 1 compared to Comparative Example 3. Thus, in Example 3, the leakage power in the standby state can be suppressed compared to Example 2.

[0383] Figure 44 (c) of (d) is a graph showing the leakage power of the ST mode. Figure 44 Figure 44 Comparative Example 3 of (c) is the leakage power of the standby state of the 6T-SRAM. As Figure 44 (b) shows that, in the standby state (BI mode) of Example 2, the leakage power can be reduced by 25% compared to Comparative Example 3. In Example 3, the leakage power can be reduced by 70% in Type 2 and by 81% in Type 1 compared to Comparative Example 3. Thus, in Example 3, the leakage power in the standby state can be suppressed compared to Example 2. Figure 44 (d) shows that, in Type 1 and Type 2 of Example 3, the leakage power can be reduced by 40% and 20%, respectively, compared to Example 2.

[0384] Hereinafter, examples other than the head PS-PDFB will be described.

[0385] [Tail PS-PDFB]

[0386] Figure 45 is a circuit diagram of the memory cell of the tail PS-PDFB-Type 2 of Example 3. As Figure 45 indicated, VDD is supplied to the power supply line 15a, and the power supply switch 30 is provided between the ground line 15b and the ground terminal. The ground line 15b is a virtual ground voltage VVGND.

[0387] The voltages of VVGND and CTRL in the standby state and the hold state are as follows.

[0388] Standby state (BI mode): VVGND = VVGNDL, the voltage of CTRL is VFNL

[0389] Hold state (ST mode): VVGND = VVGNDH, the voltage of CTRL is VFNH

[0390] Each voltage is, for example, in the following relationship.

[0391] VVGNDL < VVGNDH

[0392] VFNL ~ VVGNDL, and

[0393] VFNH ~ VVGNDH

[0394] ​In addition, ~ indicates a neighborhood.

[0395] VVGNDL, VVGNDH, VDD, VFNL, and VFNH are, for example, 0.0 V, 1.0 V, 1.2 V, 0.0 V, and 1.2 V, respectively.

[0396] [PDFB]

[0397] In the PDFB, in the case of employing the head PS as Figure 41 is large (for example, 0.5 V or more, and for example, VFN-VGND < (VVDDH-VGND) / 2), it can be set to Type 1. When VVDDH-VGND is small (for example, 0.5 V or less), in Type 1, the transition to the BI mode is sometimes insufficient. Thus, by being set to Type 2, it is possible to sufficiently transition to the BI mode. In the tail PS • PDFB, as Figure 45 is Type 2.

[0398] [PDFB]

[0399] Figure 46 is a circuit diagram of a memory cell of the tail PS • PDFB • Type 1 of Embodiment 3. FETs m9a and m10a are N-channel FETs. The gates of FETs m9a and m10a are connected to nodes QB and Q, respectively. VDD is supplied to a power supply line 15a, and a power supply switch 30 is provided between a ground line 15b and a ground terminal 15d. The ground line 15b is a virtual ground voltage VVGND. A constant voltage VFP is applied to a control line CTRL. The other structures are the same as in (a) of Figure 21 of Embodiment 2, and the explanation is omitted.

[0400] The voltages of VVGND and CTRL in the wait state and the hold state are as follows.

[0401] Wait state (BI mode): VVGND = VVGNDL, the voltage of CTRL is VFP

[0402] Hold state (ST mode): VVGND = VVGNDH, the voltage of CTRL is VFP

[0403] The respective voltages are, for example, the following relationships.

[0404] VVGNDL < VFP = VVGNDH

[0405] VVGNDL < VFP < VVGNDH, or

[0406] VVGNDL < VVGNDH < VFP (under this relationship, it is difficult to discharge nodes N2a and N4a from the control line CTRL, and thus it is not preferable)

[0407] VVGNDL, VVGNDH, VDD, and VFP are, for example, 0.0 V, 1.0 V, 1.2 V, 1.0 V, respectively.

[0408] [Head PS • PUFB]

[0409] Figure 47 is a circuit diagram of a memory cell of the head PS • PUFB • Type 2 of Embodiment 3. With respect to Figure 46 , a driver 26 is provided. The driver 26 is an inverter 26a that outputs a voltage VFPH to the control line CTRL when a control signal VCTRL output from a control circuit 28 is at a low level, and outputs a voltage VFPL to the control line CTRL when VCTRL is at a high level.

[0410] The voltages of VVDD and CTRL in the standby state and the hold state are as follows.

[0411] Standby state (BI mode): VVDD = VVDDH, the voltage of CTRL is VFPH

[0412] Hold state (ST mode): VVDD = VVDDL, the voltage of CTRL is VFPL

[0413] Each voltage is, for example, in the following relationship.

[0414] VVDDL < VVDDH

[0415] VFPL ~ VGND, and

[0416] VFPH ~ VVDDH

[0417] Further, ~ indicates a neighborhood.

[0418] VVDDL, VVDDH, VGND, VFNL, and VFNH are, for example, 0.2 V, 1.2 V, 0.0 V, 0.0 V, 1.2 V, respectively.

[0419] [PUFB]

[0420] In the PUFB, in a case where a tail PS is adopted as in Figure 46 , when VDD - VVGNDL is large (for example, 0.5 V or more, and for example, VDD - VFP < (VDD - VVGNDL) / 2), it can be set to Type 1. When VDD - VVGNDL is small (for example, 0.5 V or less), in Type 1, the transition to the BI mode is sometimes insufficient. Therefore, by being set to Type 2, it is possible to sufficiently transition to the BI mode. In the head PS • PUFB, as in Figure 47 , it is Type 2.

[0421] [Head PS • PU PDFB]

[0422] Figure 48 is a circuit diagram of the memory cell of the head PS • PU PDFB of Embodiment 3. FETs m9 and m10 are P-channel FETs, and FETs m9a and m10a are N-channel FETs. The gates of FETs m9 and m9a are connected to node QB, and the gates of FETs m10 and m10a are connected to node Q. A power supply switch 30 is provided between a power supply line 15a and a power supply 15c, and a ground voltage VGND is supplied to a ground line 15b. A constant voltage VFN is supplied to the control lines CTRLN of FETs m9 and m10. Voltages are applied to the control lines CTRLP of FETs m9a and m10a from a driver 26. The driver 26 is an inverter 26a that outputs a voltage VFPH to the control line CTRLP when a control signal VCTRL output from a control circuit 28 is at a low level, and outputs a voltage VFPL to the control line CTRLP when VCTRL is at a high level. The other structures are the same as those of the memory cell of the head PS • PDFB • Type 1 shown in Figure 21 (b) of Embodiment 2, and the description is omitted.

[0423] Figure 48 the operation conditions of the memory cell of the head PS • PDFB • Type 1 shown in Figure 41 and the operation conditions of the memory cell of the head PS • PU FB • Type 2 shown in Figure 47 .

[0424] [Tail PS • PU PDFB]

[0425] Figure 49 is a circuit diagram of the memory cell of the tail PS • PU PDFB of Embodiment 3. A power supply voltage VDD is supplied to a power supply line 15a, and a power supply switch 30 is provided between a ground line 15b and a ground terminal 15d. A constant voltage VFP is supplied to the control lines CTRLP of FETs m9a and m10a. Voltages are applied to the control lines CTRLN of FETs m9 and m10 from a driver 26. The driver 26 is an inverter 26a that outputs a voltage VFNH to the control line CTRLN when a control signal VCTRL output from a control circuit 28 is at a low level, and outputs a voltage VFNL to the control line CTRLN when VCTRL is at a high level. The other structures are the same as those of the memory cell of the tail PS • PDFB • Type 2 shown in Figure 48 (b) of Embodiment 2, and the description is omitted.

[0426] Figure 49 the operation conditions of the memory cell of the tail PS • PDFB • Type 2 shown in Figure 45 and the operation conditions of the memory cell of the tail PS • PU FB • Type 2 shown in Figure 46Action condition of the memory cell of the tail PS PUFB Type 1 shown.

[0427] In the head PS, the VVDD in the standby state can be set to VVDDHS which is slightly lower than VVDDH in the normal operation state. In the tail PS, the VVGND in the standby state can be set to VVGNDLS which is slightly higher than VVGNDL in the normal operation state. In order to perform low voltage operation, VVDDM of VVDDL < VVDDM < VVDDH can also be used in the head PS, and VVGNDM of VVGNDL < VVGNDM < VVGNDL can also be used in the tail PS.

[0428] According to Embodiment 3, in the case of the PDFB, in each of the inverter circuit 14 (first inverter circuit) and the inverter circuit 16 (second inverter circuit), in the P-channel FETs ml and m3 (first FETs having a channel of a first conductivity type), the source is connected to the power supply line 15a (first power supply line), the drain is connected to the nodes Q and QB (output nodes), and the gate is connected to the nodes Nl and N3 (input nodes). In the N-channel FETs m2b and m4b (second FETs having a channel of a second conductivity type), the source is connected to the ground line 15b (second power supply line), the drain is connected to the nodes N2 and N4 (intermediate nodes), and the gate is connected to the nodes Nl and N3, where a power supply voltage VVDD-VGND is supplied between the ground line 15b and the power supply line 15a. In the N-channel FETs m2a and m4a (third FETs having a channel of the second conductivity type), the source is connected to the nodes N2 and N4, the drain is connected to the nodes Q and QB, and the gate is connected to the nodes Nl and N3.

[0429] In the P-channel FETs m9 and mlO (fourth FETs having a channel of the first conductivity type), one of the source and the drain is connected to the nodes N2 and N4, the other of the source and the drain is connected to the control line CTRL (control node), and the gate is connected to the nodes Nl and N3. The output node of the inverter circuit 14 and the input node N3 of the inverter circuit 16 are connected to the node Q (first storage node), and the input node Nl of the inverter circuit 14 and the output node of the inverter circuit 16 are connected to the node QB (second storage node). Thereby, by appropriately setting the power supply voltage VVDD-VGND and the voltage of the control line CTRL, it is possible to improve the operation stability in the ST mode.

[0430] It can also be that the gate of the FET mlO of the inverter circuit 16 is connected to the output node of the inverter circuit 14, and the gate of the FET m9 of the inverter circuit 14 is connected to the output node of the inverter circuit 16.

[0431] In the case of PUFB, the N-channel FETs m2 and m4 correspond to the first FET, the P-channel FETs ml a and m3a correspond to the second FET, the P-channel FETs ml b and m3b correspond to the third FET, and the N-channel FETs m9a and m10a correspond to the fourth FET. The ground line 15b and the power supply line 15a correspond to the first power supply line and the second power supply line, respectively.

[0432] In the case of PDFB, the power supply switch 30 (power supply circuit) switches the supply voltage VVDD-VGND to be provided between a voltage VVDDH-VGND (first voltage) at which the bistable circuit 12 can read and write data and a voltage VVDDL-VGND (second voltage) lower than the voltage VVDDH-VGND, which is a voltage at which the bistable circuit 12 cannot read and write data but can hold data. Thus, at the time of holding data, power consumption can be suppressed.

[0433] The power supply circuit can also use a transistor like the power supply switch to generate the first voltage and the second voltage from one power supply and supply them to the bistable circuit. Further, it can also be that power supply switches are connected to two power supplies, respectively, and the control circuit supplies the first voltage and the second voltage to the bistable circuit by controlling the power supply switches.

[0434] In the case of PUFB, the voltages VDD-VVGNDL and VDD-VVGNDH correspond to the first voltage and the second voltage, respectively.

[0435] As in Type 1, when the power supply switch 30 supplies either of the first voltage and the second voltage to the bistable circuit 12, a constant bias voltage (VFN in the case of PDFB and VFP in the case of PUFB) is also supplied to the control line CTRL. Thus, the driver 26 is not needed, and the chip size can be reduced.

[0436] In the head PS.PDFB of Figure 41 The constant bias voltage (VFN) in the head PS.PDFB is only a bias voltage between the voltage VVDDH of the power supply line 15a (first power supply line) at the time of supplying VVDDH-VGND (first voltage) as the supply voltage and the voltage VGND of the ground line 15b (second power supply line). In the head PS.PUFB of Figure 46In the tail PS·PUFB, the constant bias voltage (VFP) is simply the bias voltage between the voltage VVGNDL of the ground line 15b (first power line) and the voltage VDD of the power line 15a (second power line) when VDD-VVGNDL (first voltage) is provided as the power supply voltage. Therefore, even if a constant voltage is applied to the control line CTRL as in Type 1, the ST mode and BI mode can be switched by switching the power supply voltage.

[0437] exist Figure 41 In the PS·PDFB header, the constant bias voltage (VFN) is closer to the voltage VGND of ground line 15b than the voltage VVDDH of power line 15a (first power line) and the voltage VGND of ground line 15b (second power line) when VVDDH-VGND (first voltage) is provided as the power supply voltage. Figure 46 In the tail section PS·PUFB, the constant bias voltage (VFP) is close to the voltage VDD of power line 15a (the voltage VDD of the power line 15a when VDD-VVGNDL (the first voltage) is provided as the power supply voltage. This voltage (VDD-VVGNDL) / 2 is close to the voltage VDD of power line 15a. Therefore, even if a constant voltage is applied to the control line CTRL as in Type 1, ST mode and BI mode can be switched by switching the power supply voltage.

[0438] In the head PS·PDFB, the preferred VFN ratio (VVDDH-VGND) / 3 is close to VGND, and in the tail PS·PUFB, the preferred VFN ratio 2 (VDD-VVGNDL) / 3 is close to VDD.

[0439] In Type 2, in the case of PDFB, when power switch 30 provides VVDDH-VGND, control circuit 28 provides a low level to control line CTRL; when power switch 30 provides VVDDL-VGND, control circuit 28 provides a high level (higher than the low level) to control line CTRL. In the case of PUFB, when power switch 30 provides VDD-VVGNDL, control circuit 28 provides a high level to control line CTRL; when power switch 30 provides VDD-VVGNDH, control circuit 28 provides a low level (lower than the high level) to control line CTRL. Therefore, power consumption can be suppressed while holding data. Furthermore, the high level only needs to be a voltage higher than the low level.

[0440] When the memory cell of Embodiment 3 is used as the memory cell of Embodiment 2, a constant bias voltage is applied to the control line CTRL of inverter circuits 14 and 16. Inverter circuits 14 and 16 are in BI mode when provided with voltage V3 as the power supply voltage, and in ST mode when provided with voltage V1. Therefore, the control signal VCTRL is not required.

[0441] Example 4

[0442] [Explanation of head Photoshop, tail Photoshop, and double Photoshop]

[0443] First, let's summarize the various names. Figure 50 (a) to Figure 50 (f) is a diagram showing the configuration of the power switch connected to the unit. (See diagram for example.) Figure 50 As shown in (a), the voltage of power supply 15c is VDD, and the voltage of ground terminal 15d is VGND. In the header PS, a power switch 30 is connected between power supply line 15a and power supply 15c of memory cell 10. Power switch 30 switches the virtual power supply voltage VVDD of power supply line 15a between VVDDH and VVDDL. Even though the virtual power supply voltage VVDD switches between VVDDH and VVDDL, the voltage VVGND of ground line 15b is constant and is the ground voltage VGND. The power supply voltage in the standby state (BI mode) is VVDDH-VGND, and the power supply voltage in the low voltage (ULV) hold state (ST mode) is VVDDL-VGND.

[0444] like Figure 50 As shown in (b), in the tail PS, a power switch 30 is connected between the ground line 15b and the ground terminal 15d of the memory cell 10. The power switch 30 switches the virtual ground voltage VVGND of the ground line 15b between VVGNDH and VVGNDL. Even when the virtual ground voltage VVGND switches between VVGNDH and VVGNDL, the voltage VVDD of the power line 15a remains constant, which is the power supply voltage VDD. The power supply voltage in the standby state (BI mode) is VDD-VVGNDL, and the power supply voltage in the low voltage hold state (ST mode) is VDD-VVGNDH.

[0445] like Figure 50As shown in (c) of FIG. 10, in the double PS, the power switch 30 is connected between the power supply line 15a and the power supply 15c and between the ground line 15b and the ground terminal 15d. The power switch 30 switches the virtual power supply voltage VVDD of the power supply line 15a between VVDDH and VVDDL and switches the virtual ground voltage VVGND of the ground line 15b between VVGNDH and VVGNDL. The power supply voltage in the standby state (BI mode) is VVDDH-VVGNDL, and the power supply voltage in the low voltage retention state (ST mode) is VVDDL-VVGNDH.

[0446] As shown in (a) of FIG. 11, in the head PS, the power switch 30 can have the PFET 30a connected between the power supply VDD1 and the power supply line 15a and the NFET 30b connected between the ground line 15b and the ground terminal 15d. When the FET 30a is turned on and the FET 30b is turned off, the virtual power supply voltage VVDD becomes VDD1, and when the FET 30a is turned off and the FET 30b is turned on, VVDD becomes VDD2. When the FET 30a and the FET 30b are turned off, the power supply is turned off. Figure 50 As shown in (d) of FIG. 11, in the head PS, the power switch 30 can have the PFET 30a connected between the power supply VDD1 and the power supply line 15a and the PFET 30b connected between the power supply VDD2 and the power supply line 15a. When the FET 30a is turned on and the FET 30b is turned off, the virtual power supply voltage VVDD becomes VDD1, and when the FET 30a is turned off and the FET 30b is turned on, VVDD becomes VDD2. When the FET 30a and the FET 30b are turned off, the power supply is turned off.

[0447] As shown in (a) of FIG. 12, in the tail PS, the power switch 30 can have the NFET 30c connected between the ground line 15b and the ground terminal 15d and the PFET 30d connected between the power supply line 15a and the power supply VDD1. When the FET 30c is turned on and the FET 30d is turned off, the virtual ground voltage VVGND becomes VGND1, and when the FET 30c is turned off and the FET 30d is turned on, VVGND becomes VGND2. When the FET 30c and the FET 30d are turned off, the power supply is turned off. Figure 50 As shown in (d) of FIG. 12, in the tail PS, the power switch 30 can have the NFET 30c connected between the ground line 15b and the ground terminal 15d and the PFET 30d connected between the power supply line 15a and the power supply VDD2. When the FET 30c is turned on and the FET 30d is turned off, the virtual ground voltage VVGND becomes VGND1, and when the FET 30c is turned off and the FET 30d is turned on, VVGND becomes VGND2. When the FET 30c and the FET 30d are turned off, the power supply is turned off.

[0448] Figure 50 As shown in (f) of FIG. 12, in the double PS, the power switch 30 has the PFET 30a connected between VDD1 and the power supply line 15a, the PFET 30b connected between VDD2 and the power supply line 15a, the NFET 30c connected between VGND1 and the ground line 15b, and the NFET 30d connected between VGND2 and the ground line 15b. By turning on and off the FETs 30a to 30d as appropriate, the power supply voltage provided to the virtual power supply line 15a and the virtual ground line can be switched as appropriate.

[0449] [Explanation of PDFB, PUFB, and PUPDFB]

[0450] The PDFB (pull-down type feedback) is as shown in (a) of FIG. 13. The power supply voltage VDD is supplied to the power supply line 15a, and the ground voltage VSS is supplied to the ground line 15b. The power supply line 15a and the ground line 15b are connected to the power supply 15c and the ground terminal 15d, respectively. The power supply line 15a and the ground line 15b are connected to the power supply 15c and the ground terminal 15d, respectively. Figure 41 ​In this way, FET m9 feeds back to the N-channel FETs m2a and m2b of inverter circuit 14, and FET m10 feeds back to the N-channel FETs m4a and m4b of inverter circuit 16.

[0451] PUFB (Pull-Up Feedback) is like... Figure 46 In this way, FET m9a is fed back between P-channel FETs m1a and m1b in inverter circuit 14, and FET m10a is fed back between P-channel FETs m3a and m3b in inverter circuit 16.

[0452] PUPDFB (Pu-to-Pu feedback) is like... Figure 48 and Figure 49 That is, there are two types of FETs: PDFB FET m9 and m10, and PUFB FET m9a and m10a.

[0453] [Explanation of Type 1 and Type 2]

[0454] Figure 51 (a) to Figure 52 (c) is a diagram showing the configuration of the driver connected to the unit. For example... Figure 51 As shown in (a), in type 2 PUFB, a driver 26 is provided. The driver 26 switches the voltage VFP between voltage VFPH and voltage VFPL according to the control signal VCTRL output by the control circuit 28. When voltage VFP is VFPH (high level), inverter circuits 14 and 16 are in BI mode, and when voltage VFP is VFPL (low level), they are in ST mode.

[0455] like Figure 51 As shown in (b), in type 1 PUFB, driver 26 is not provided. VFP is constant bias, but inverter circuits 14 and 16 switch between BI mode and ST mode when the power supply voltage changes.

[0456] like Figure 51 As shown in (c), in PDFB Type 2, a driver 26 is provided. The driver 26 switches the voltage VFN between voltage VFNH and voltage VFNL according to the control signal VCTRL output by the control circuit 28. When voltage VFN is VFNL (low level), inverter circuits 14 and 16 are in BI mode, and when voltage VFN is VFNH (high level), they are in ST mode.

[0457] like Figure 51 As shown in (d), in PDFB type 1, driver 26 is not configured. Although VFN is a constant bias, inverter circuits 14 and 16 switch between BI mode and ST mode during power supply voltage switching.

[0458] As Figure 52 shown in (a) of FIG. 9, in the case where both VFP and VFN of the PUPDFB are of Type 2, a driver 26 is provided to the control line of both the voltages VFP and VFN. When the voltage VFP is VFPH and the voltage VFN is VFNL, the inverter circuits 14 and 16 become the BI mode, and when the voltage VFP is VFPL and the voltage VFN is VFNH, the ST mode.

[0459] As Figure 52 shown in (b) of FIG. 9, in the case where VFP of the PUPDFB is of Type 2 and VFN is of Type 1, a driver 26 is provided to the control line of the voltage VFP, and VFN is a constant bias. When the voltage VFP is VFPH, the inverter circuits 14 and 16 become the BI mode, and when the voltage VFP is VFPL, the ST mode.

[0460] As Figure 52 shown in (c) of FIG. 9, in the case where VFP of the PUPDFB is of Type 1 and VFN is of Type 2, the voltage VFP is a constant bias, and a driver 26 is provided to the control line of VFN. When the voltage VFN is VFNL, the inverter circuits 14 and 16 become the BI mode, and when the voltage VFN is VFNH, the ST mode.

[0461] Figure 53 (a) of FIG. 10 and (b) of FIG. 10 are graphs showing each voltage of the head PS.PDFB.Type 1 and the tail PS.PUFB.Type 1, respectively. In (a) of FIG. 10, VVDDH and VVDDL with respect to VGND are shown in the vertical direction, and in (b) of FIG. 10, VVGNDL and VVGNDH with respect to VDD are shown in the vertical direction. Figure 53 Figure 53 Figure 53

[0462] As Figure 53 shown in (a) of FIG. 11, in the head PS, in the standby state, VVDDH is supplied to the power supply line 15a, and VGND is supplied to the ground line 15b. At this time, when VFN is set to a constant bias of VVDDL level, since VFN is sufficiently lower than VVDDH, the inverter circuits 14 and 16 become the BI mode. In the low voltage hold state, VVDDL is supplied to the power supply line 15a, and VGND is supplied to the ground line 15b. At this time, when VFN is set to VVDDL level, since VFN is higher than VGND, the inverter circuits 14 and 16 become the ST mode.

[0463] ​​​The constant voltage VFN only needs to be smaller than VVDDH and larger than VGND. If the constant voltage VFN is too close to VVDDH, inverter circuits 14 and 16 will find it difficult to operate in BI mode when the virtual power supply voltage VVDD is set to VVDDH. Therefore, the constant voltage VFN is preferably below the voltage at the midpoint between VVDDH and VGND (i.e., (VVDDH-VGND) / 2 or less), and more preferably below the voltage obtained by adding half the difference between VVDDL and VGND to VVDDL (i.e., VVDDL+(VVDDL-VGND) / 2 or less). If the constant voltage VFN is too close to VGND, inverter circuits 14 and 16 will find it difficult to operate in ST mode when the virtual power supply voltage VVDD is set to VVDDL. Therefore, the constant voltage VFN is preferably above the voltage at the midpoint between VVDDL and VGND (i.e., (VVDDL-VGND) / 2 or more).

[0464] In the header PS·PUFB, it enters BI mode when VFP is high and ST mode when VFP is low. Therefore, if it is set to header PS·PUFB·Type 1, it is not possible to switch between BI mode and ST mode.

[0465] like Figure 53 As shown in (b), in the tail PS, in the standby state, VVGNDL is supplied to ground line 15b and VDD is supplied to power line 15a. At this time, when VFP is set to a constant bias of VVGNDH level, since VFP is sufficiently higher than VVGNDL, inverter circuits 14 and 16 are in BI mode. In the low voltage holding state, VVGNDH is supplied to ground line 15b and VDD is supplied to power line 15a. At this time, when VFP is set to VVGNDH level, since VFP is lower than VDD, inverter circuits 14 and 16 are in ST mode.

[0466] The constant voltage VFP only needs to be greater than VVGNDL and less than VDD. If the constant voltage VFP is too close to VVGNDL, inverter circuits 14 and 16 will find it difficult to operate in BI mode when the virtual ground voltage VVGND is set to VVGNDL. Therefore, the constant voltage VFP is preferably above the voltage at the midpoint between VDD and VVGNDL (i.e., (VDD-VVGNDL) / 2 or higher), and more preferably above the voltage obtained by subtracting half the difference between VDD and VVGNDH from VVGNDH (i.e., VVGNDH-(VDD-VVGNDH) / 2 or higher). If the constant voltage VFP is too close to VVDD, inverter circuits 14 and 16 will find it difficult to operate in ST mode when the virtual ground voltage VVGND is set to VVGNDH. Therefore, the constant voltage VFP is preferably below the voltage at the midpoint between VDD and VVGNDH (i.e., (VDD-VVGNDH) / 2 or lower).

[0467] In the tail PS·PDFB, when VFN is low, it becomes BI mode, and when VFN is high, it becomes ST mode. Therefore, when set to tail PS·PDFB·Type 1, it is impossible to switch between BI and ST modes.

[0468] Table 1 summarizes whether a constant bias voltage can be maintained.

[0469] [Table 1]

[0470]

[0471] As shown in Table 1, in PDFB, a constant bias can be achieved in the header PS. A constant bias cannot be achieved in the tail PS and dual PS, requiring driver 26.

[0472] In PUFB, constant bias is possible in the tail PS. Constant bias is not possible in the head PS and dual PS, requiring driver 26. In PUPDFB, constant bias is possible only on the PD (i.e., VFN) side in the head PS. Constant bias is possible only on the PU (i.e., VFP) side in the tail PS. Constant bias is not possible in dual PS.

[0473] In Embodiment 3, the gates of feedback FETs m9 and / or m9a are connected to the input node of inverter circuit 14 or the output node of inverter circuit 16, and the gates of feedback FETs m10 and / or m10a are connected to the input node of inverter circuit 16 or the output node of inverter circuit 14. This is referred to as Embodiment 3. In the case of Embodiment 3, the header PS·PDFB·Type 1 of Table 1 is... Figure 41 As shown in the diagram, the tail section PS·PUFB·Type 1 is... Figure 46 The diagram shows the head PS·PUPDFB·PD side type 1.Figure 48 The head PS • PUPDFB • PU side type 1 type is illustrated in FIG. 8. Figure 49 The tail PS • PUPDFB • PU side type 1 type is illustrated in FIG. 9.

[0474] The gate of the feedback FET m9 and / or m9a can be connected to the output node of the inverter circuit 14, and the gate of the feedback FET m10 and / or m10a can be connected to the output node of the inverter circuit 16, as in Embodiment 2. This case is called Embodiment 2 type. Table 1 also holds in the case of Embodiment 2 type.

[0475] Figure 54 is a circuit diagram of the memory cell of the head PS • PDFB • type 1 type of Embodiment 4. As shown in FIG. 10, the FET m9 (and m10) is an N-channel FET, the gate of which is connected to the output node of the inverter circuit 14 (and 16). The other structures are the same as those of Embodiment 3, and the explanation is omitted. Figure 54 Figure 41

[0476] Figure 55 is a circuit diagram of the memory cell of the tail PS • PUFB • type 1 type of Embodiment 4. As shown in FIG. 11, the FET m9a (and m10a) is a P-channel FET, the gate of which is connected to the output node of the inverter circuit 14 (and 16). The other structures are the same as those of Embodiment 3, and the explanation is omitted. Figure 55 Figure 46

[0477] Figure 56 is a circuit diagram of the memory cell of the head PS • PUPDFB • PD side type 1 type of Embodiment 4. As shown in FIG. 12, the FET m9 (and m10) is an N-channel FET, and the FET m9a (and m10a) is a P-channel FET, the gates of which are connected to the output node of the inverter circuit 14 (and 16). The other structures are the same as those of Embodiment 3, and the explanation is omitted. Figure 56 Figure 48

[0478] Figure 57 is a circuit diagram of the memory cell of the tail PS • PUPDFB • PU side type 1 type of Embodiment 4. As shown in FIG. 13, the FET m9 (and m10) is an N-channel FET, and the FET m9a (and m10a) is a P-channel FET, the gates of which are connected to the output node of the inverter circuit 14 (and 16). The other structures are the same as those of Embodiment 3, and the explanation is omitted. Figure 57 Figure 49

[0479] [Modified Example 1 of Embodiment 4]

[0480] Modified Example 1 of Embodiment 4 is an example of a master-slave type flip-flop circuit. Figure 58 ​​​​​​​​This is a circuit diagram of the electronic circuit of Modification 1 of Example 4. For example... Figure 58 As shown, latch circuits (D-latch circuits) 76 and 77 are included. Latch circuits 76 and 77 are master-side and slave-side latch circuits, respectively. Latch circuit 76 includes a bistable circuit 80 and an inverter 78a, which in turn includes inverters 80a and 80b. Inverter 78a operates when the clock signal C is high, and inverter 80b operates when the clock signal C is low. Latch circuit 77 includes a bistable circuit 12 and a transmission gate 79a. Transmission gate 79b is located within the loop of bistable circuit 12. Transmission gate 79a operates when the clock signal C is low, and transmission gate 79b operates when the clock signal C is high. The level of node QB in the loop of bistable circuit 12 is output as the Q signal via inverter 78b.

[0481] The clock generation circuit 81 operates when the enable signal VEN is high and does not operate when the enable signal VEN is low. When the input low level is used as the clock signal VCLK, the clock generation circuit 81 outputs a high level as the clock signal C and a low level as the clock signal CB. Conversely, when the input high level is used as the clock signal VCLK, the clock generation circuit 81 outputs a low level as the clock signal C and a high level as the clock signal CB.

[0482] The power switch 30 provides a virtual power supply voltage VVDD to power line 15a and a ground voltage VGND to ground line 15b, which is a PS type. The feedback FETs of inverter circuits 14 and 16 are P-channel FETs m9 and m10, which are PDFB type. The voltage VFN is a constant voltage, which is type 1. The gates of FETs m9 (and m10) are connected to the output nodes of inverter circuits 16 (and 14), which is type 3. Thus, Figure 58 Variation 1 is the header PS·PDFB·Type 1·Example 3.

[0483] Table 1 also applies to master-slave type flip-flop circuits. That is, master-slave type flip-flop circuits can adopt type 1 with tail PS·PUFB·, type 1 with head PS·PUPDFB·PD side, and type 1 with tail PS·PUPDFB·PU side. Furthermore, the bistable circuit 12 can be either type 3 or type 2. The bistable circuit 12 can be used in a master-side latch circuit.

[0484] [simulation]

[0485] The SNM and wait power of a master-slave flip-flop circuit were simulated. The simulated circuits are circuits A to C below.

[0486] Circuit A: A typical delay trigger circuit

[0487] Circuit B: Head PS • PDFB • Type 2 • Embodiment 2

[0488] Circuit C: Head PS • PDFB • Type 1 • Embodiment 3 Figure 58

[0489]

[0490] Circuit A:

[0491] The channel width W / length L of each transistor constituting the circuit was decided with reference to a standard cell.

[0492] Circuit B:

[0493] The channel width W / length L of each FET in the latch circuit 77 was as follows.

[0494] FET ml and ml a: 180 nm / 60 nm

[0495] FET m2a, m2b, m4a, and m4b: 385 nm / 60 nm

[0496] FET m9 and m10: 150 nm / 60 nm

[0497] In the circuit B, the same as in Embodiment 2 Figure 17 The inverter 26a was also provided with the channel width W / length L as follows.

[0498] FET of the inverter 26a: 150 nm / 60 nm

[0499] Circuit C:

[0500] The channel width W / length L of each FET in the latch circuit 77 was as follows.

[0501] FET ml and ml a: 130 nm / 60 nm

[0502] FET m2a, m2b, m4a, and m4b: 385 nm / 60 nm

[0503] FET m9 and m10: 150 nm / 60 nm

[0504] Each voltage was as follows.

[0505] VVDDH= 1.2 V

[0506] VVDDL= 0.2 V

[0507] VGND= 0 V

[0508] VFNH= 0.2 V

[0509] ​​Figure 59 (a) and Figure 59 (b) are graphs showing the butterfly curves of the flip-flop circuits. In Figure 59 (a), (Vin, Vout) takes (L, H) as the storage node, and in Figure 59 (b), (H, L) is taken as the storage node. In the circuit A, VVDD=0.2 V. In the circuit C, ST mode is set, and VVDDL=0.2 V. Both show TT.

[0510] TT of SNM is SNM when the threshold voltage of the FET is Typical. Hereinafter, FF, SS, FS, and SF indicate SNM when the threshold voltage deviates from the typical value by 3σ to the fast (F) side or the slow (S) side.

[0511] As shown in Figure 59 (a) and Figure 59 (b), in the circuit A, the butterfly curve is roughly symmetrical, the opening is small, and the noise margin is small. In the circuit C, by setting VVDD=0.2 V, the bistable circuit 12 becomes the ST mode, and the hysteresis of the transfer characteristics becomes large. Thus, the opening on the storage node side becomes large, and the noise margin becomes large.

[0512] Figure 60 (a) is a graph showing SNM, Figure 60 (b) is a graph showing standby power. In Figure 60 (a), for (L, H) and (H, L), SNM of TT, FF, SS, FS, and SF is shown. In the circuit A, VVDD=0.2 V, and in the circuits B and C, ST mode is set, and VVDDL=0.2 V.

[0513] In the circuit A, SNM is about 60 mV. In the circuit B, SNM is slightly higher than that of the circuit A, and is about 70 mV to 80 mV. In the circuit C, SNM is 90 mV to 100 mV, and sufficient SNM can be obtained. In the circuit C, if SNM is set to 80 mV, VVDDL can be made lower than 0.2 V, and power consumption can be further reduced.

[0514] In Figure 60In (b) of FIG. 8, "SB1.2" is a standby state with VDD = 1.2 V, and "ULV0.2" is a low-voltage hold state with VDD = 0.2 V. In SB1.2, the circuit B has a standby power that is about 14% greater than that of the circuit A. In the circuit C, the standby power can be made the same as that of the circuit A. In the ULV0.2 of the circuits B and C, the standby power can be reduced by 98% compared with the circuit A. Thus, in the flip-flop circuit C of the modified example 1 of the embodiment 4, the standby power at VDD = 1.2 V is the same as that of the circuit A, and the standby power in the low-voltage hold state can be reduced by 98%.

[0515] Table 2 is a table showing the power reduction effect, chip area, delay, BET, process cost, and control step number for the circuit A, ballooning FF, NVFF, and the circuit C. The ballooning FF is a ballooning type FF circuit, and the NVFF is an FF circuit using a nonvolatile memory element like that of the embodiment 1.

[0516] [Table 2]

[0517]

[0518] The power reduction effect indicates the reduction rate in the low-voltage hold state compared with the circuit A. In the NVFF and the circuit C, the power can be reduced by 99% and 98%, respectively, compared with the circuit A. The area of the circuit A is taken as 1. The area of the ballooning FF is 1.7 times the area of the circuit A. The area of the NVFF is 1.5 times the area of the circuit A. The area of the circuit C is 1.2 times the area of the circuit A. The delay for CLK-QH and CLK-QL is compared with the circuit A taken as 1. The delay of the ballooning FF and the NVFF is 1.1 to 1.2 compared with the circuit A. For CLK-QL, the delay of the circuit C is 1.6 compared with the circuit A.

[0519] The BET of the ballooning FF is 100 ns, and, in contrast, the BET of the NVFF is lengthened to 8 μs. In contrast, the BET of the circuit C is 160 ns, which is the same as that of the ballooning FF. For the process cost of the NV-FF, the process cost of the nonvolatile element is high, and thus the process cost of the NV-FF is high. In contrast, the circuit C can be fabricated by a CMOS process, and thus the process cost of the circuit C is low to the same degree as that of the circuit A and the ballooning FF. The control step number is the number of pulses required for control that does not include power switching. The control step number of the ballooning FF and the NVFF is 3, and, in contrast, the control step number of the circuit C is the same as that of the circuit A, which is 0.

[0520] Thus, the circuit C has the same degree of power reduction effect and chip area as the NVFF, the same degree of process cost and control step number as the circuit A, and the same degree of process cost and control step number as the BET and the balloon FF.

[0521] Next, a logic system such as an SOC (System on a chip) was assumed, and standby power was simulated. Figure 61 (a) is a conceptual diagram of the simulated logic system. 50% of the area of the system 82 is an LLC (Last-level Cache) 84. In the remaining 50% of the system 82, a plurality of cores 83 are provided. 20% of the area of each core 83 is an FF (Flip Flop) 83a, and 10% is an FLC (First-level Cache) 83b. The simulated system is the following systems A and C.

[0522] System A: Cache and flip-flop using 6T-SRAM

[0523] System C: Cache and flip-flop of the head PS.PDFB.Type 1 type of Embodiment 3 Figure 58 Flip-flop circuit shown in

[0524] Figure 61 (b) is a graph showing the normalized standby power of the systems A and C. A1 of the system A is a state in which both the core 83 and the LLC 84 are in a standby state of VVDD = 1.2 V. A2 is a state in which the FF 83a of the core 83 is in a standby state of VVDD = 1.2 V, the FLC 83b is in a sleep state of VVDD = 0.8 V, all the circuits in the core 83 other than the FF 83a and the FLC 83b are powered off, and the LLC 84 is in a standby state of VVDD = 1.2 V. A3 is a state in which the FF 83a of the core 83 is in a standby state of VVDD = 1.2 V, the FLC 83b is in a sleep state of VVDD = 0.8 V, all the circuits in the core 83 other than the FF 83a and the FLC 83b are powered off, and the LLC 84 is in a sleep state of VVDD = 0.8 V. The normalized standby power of A2 is about 0.6 of A1, and the normalized standby power of A3 is about 0.5 of A1.

[0525] C1 of the system C is a standby state in which both the core 83 and the LLC 84 are VVDD = 1.2 V. C2 is a state in which the FF 83a of the core 83 is a low-voltage hold state of VVDD = 0.2 V, the FLC 83b is a low-voltage hold state of VVDD = 0.2 V, all the circuits in the core 83 other than the FF 83a and the FLC 83b are powered off, and the LLC 84 is a standby state of VVDD = 1.2 V. C3 is a state in which the FF 83a of the core 83 is a low-voltage hold state of VVDD = 0.2 V, the FLC 83b is a low-voltage hold state of VVDD = 0.2 V, all the circuits in the core 83 other than the FF 83a and the FLC 83b are powered off, and the LLC 84 is a low-voltage hold state of VVDD = 0.2 V. The normalized standby power of C2 is 0.2 or less of Al, and the normalized standby power of C3 is about 0.05 of Cl.

[0526] As described above, in the system C, by setting the FF 83a, the FLC 83b, and the LLC 84 to low-voltage hold states, it is possible to make the standby power very small.

[0527] According to Embodiment 4 and Modification 1 thereof, in the Embodiment 2 type, the gates of the FETs m9 and m9a (fourth FETs) of the inverter circuit 14 (first inverter circuit) are connected to the output node of the inverter circuit 14 or the input node of the inverter circuit 16, and the gates of the FETs m10 and m10a of the inverter circuit 16 (second inverter circuit) are connected to the input node of the inverter circuit 14 or the output node of the inverter circuit 16. At this time, the conduction types of the channels of the FETs m9 and m10 are the same as the conduction types of the channels of the FETs m2, m2a, m2b, m4, m4a, and m4b, and the conduction types of the channels of the FETs m9a and m10a are the same as the conduction types of the channels of the FETs ml, ml a, mlb, m3, m3a, and m3b.

[0528] In Embodiment 3, the gates of the feedback FETs m9 and m9a of the inverter circuit 14 are connected to the output node of the inverter circuit 16 or the input node of the inverter circuit 14, and the gates of the FETs m10 and m10a of the inverter circuit 16 are connected to the input node of the inverter circuit 16 or the output node of the inverter circuit 14. At this time, the conduction types of the channels of the FETs m9 and m10 are the same as the conduction types of the channels of the FETs ml, ml a, mlb, m3, m3a, and m3b, and the conduction types of the channels of the FETs m9a and m10a are the same as the conduction types of the channels of the FETs m2, m2a, m2b, m4, m4a, and m4b.

[0529] In both Embodiment 2 and Embodiment 3, the power switch 30 (power circuit) switches the power supply voltage VVDD-VVGND between a first voltage and a second voltage lower than the first voltage. At the first voltage, the bistable circuit 12 can read and write data, and at the second voltage, it can retain the data. When the power switch 30 provides either the first or second voltage to the bistable circuit 12, a constant bias voltage is also provided to the control nodes of VFN and VFP. Therefore, the driver 26 is not required, enabling miniaturization of the electronic circuit. Furthermore, power consumption can be suppressed.

[0530] like Figure 53 As in (a) and Table 1, in the PDFB and PUPDFB header PS, when switching the power supply voltage VVDD-VGND between the first voltage and the second voltage, a constant ground voltage VGND (third voltage) is provided to the ground line 15b (second power line), and when switching between VVDDH (fourth voltage) and VVDDL (fifth voltage) to the power line 15a (first power line). Figure 53 As shown in (b) and Table 1, in PUFB and PUPDFB·PPS, when switching the power supply voltage VDD-VVGND between the first and second voltages, a constant power supply voltage VDD (third voltage) is provided to power supply line 15a (second power supply line), and when switching between VVGNDL (fourth voltage) and VVGNDH (fifth voltage), it is provided to ground line 15b (first power supply line). Therefore, even when a constant bias voltage VFN and VFP are provided to the control lines, it is possible to switch between BI mode and ST mode.

[0531] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments and various modifications and alterations can be made within the scope of the spirit of the present invention as set forth in the claims.

[0532] Label Explanation

[0533] 10: Memory cell; 12: Bistable circuit; 14, 16: Inverter circuit; 20: Cell array; 22, 22a-22d: Subarray; 24, 24a, 24b, 24A-24C, 241-24n: Block; 28: Control circuit; 30: Power switch; 40, 41: Register.

Claims

1. An electronic circuit having: The unit array has multiple memory units, each memory unit having a bistable circuit, the bistable circuit having a first inverter circuit and a second inverter circuit, the first inverter circuit and the second inverter circuit being able to switch between a first mode with substantially no hysteresis in the transfer characteristics and a second mode with hysteresis in the transfer characteristics, the output node of the first inverter circuit being connected to the input node of the second inverter circuit, and the input node of the first inverter circuit being connected to the output node of the second inverter circuit; as well as A control circuit, after powering down one or more first memory cells storing non-retainable data, sets the bistable circuits in the remaining one or more second memory cells to a second mode. While maintaining the second mode, the control circuit provides a second power supply voltage to the bistable circuits in the one or more second memory cells. This second power supply voltage is lower than the first power supply voltage provided to the bistable circuits during data reading and / or writing. Under this second power supply voltage, the bistable circuits in the second mode are able to retain data. Both the first inverter circuit and the second inverter circuit have: A first FET of a first conductivity type with a channel has its source connected to a first power line, its drain connected to an output node, and its gate connected to an input node. A second FET with a channel of the second conductivity type, opposite to the first conductivity type, has its source connected to the second power line, its drain connected to the intermediate node, and its gate connected to the input node. A power voltage is provided between the second power line and the first power line; The third FET of the second conductivity type has its source connected to the intermediate node, its drain connected to the output node, and its gate connected to the input node; as well as The fourth FET has one of its source and drain connected to the intermediate node, and the other of its source and drain connected to the control node. The output node of the first inverter circuit and the input node of the second inverter circuit are connected to the first storage node. The input node of the first inverter circuit and the output node of the second inverter circuit are connected to the second storage node. The gate of the fourth FET in the first inverter circuit is connected to the node of one of the first storage node and the second storage node. The gate of the fourth FET in the second inverter circuit is connected to the node of the other of the first and second storage nodes. The fourth FET in the first inverter circuit is a channel FET of the second conductivity type when its gate is connected to the first memory node, and a channel FET of the first conductivity type when its gate is connected to the second memory node. The fourth FET of the second inverter circuit is a FET of the second conductivity type when its gate is connected to the second storage node, and a FET of the first conductivity type when its gate is connected to the first storage node.

2. The electronic circuit according to claim 1, wherein, The cell array is divided into multiple blocks, each block containing at least two memory cells. After the control circuit extracts one or more first blocks from the plurality of blocks that store data that may not be retained, and de-energizes the one or more first blocks, it sets the bistable circuits in the remaining one or more second blocks of the plurality of blocks to the second mode, and provides the second power supply voltage to the bistable circuits in the one or more second blocks while maintaining the second mode.

3. The electronic circuit according to claim 2, wherein, Before setting the bistable circuit within the one or more second blocks to the second mode, the control circuit provides a third power supply voltage to the one or more second blocks. This third power supply voltage is lower than the first power supply voltage and higher than the second power supply voltage. Under this third power supply voltage, the bistable circuit in the first mode is able to retain data.

4. The electronic circuit according to claim 3, wherein, The control circuit sets the bistable circuit in the one or more second blocks to the second mode while providing the third power supply voltage to the bistable circuit in the one or more second blocks.

5. The electronic circuit according to claim 3, wherein, The one or more second blocks are multiple second blocks. The control circuit sets the bistable circuit in one or more third blocks to the second mode while providing the third power supply voltage to the bistable circuit in one or more third blocks among the plurality of second blocks, and provides the second power supply voltage while the bistable circuit in one or more third blocks is in the second mode. Then, while providing the third power supply voltage to the bistable circuit in one or more fourth blocks that are different from the one or more third blocks among the plurality of second blocks, the control circuit sets the bistable circuit in one or more fourth blocks to the second mode, and provides the second power supply voltage while the bistable circuit in one or more fourth blocks is in the second mode.

6. The electronic circuit according to claim 3, wherein, The one or more second blocks are multiple second blocks. The control circuit sets the bistable circuits in the plurality of second blocks to the second mode while providing the third power supply voltage to the bistable circuits in the plurality of second blocks, and then provides the second power supply voltage while the bistable circuits in the plurality of second blocks are in the second mode.

7. The electronic circuit according to any one of claims 2 to 6, wherein, The electronic circuit has a storage circuit disposed outside the cell array, which stores information received from an external circuit indicating blocks of data that the storage may not be retained, and the control circuit extracts the one or more first blocks of the data that the storage may not be retained based on the information.

8. The electronic circuit according to any one of claims 1 to 6, wherein, A constant bias voltage is applied to the control nodes of the first inverter circuit and the second inverter circuit. The first inverter circuit and the second inverter circuit are in the first mode when the first power supply voltage is provided, and in the second mode when the second power supply voltage is provided.

9. A bistable circuit, having: The first inverter circuit and the second inverter circuit each have a first FET with a first conductivity type channel, a second FET with a second conductivity type channel opposite to the first conductivity type, a third FET with a second conductivity type channel, and a fourth FET with a first conductivity type channel. In the first FET, the source is connected to a first power line, the drain is connected to an output node, and the gate is connected to an input node. In the second FET, the source is connected to a second power line, the drain is connected to an intermediate node, and the gate is connected to the input node. In the third FET, the source is connected to the intermediate node, the drain is connected to the output node, and the gate is connected to the input node. In the fourth FET, one of the source and drain is connected to the intermediate node, and the other of the source and drain is connected to a control node. A power voltage is provided between the second power line and the first power line; The first storage node is connected to the output node of the first inverter circuit and the input node of the second inverter circuit. as well as The second storage node is connected to the input node of the first inverter circuit and the output node of the second inverter circuit. The gate of the fourth FET in the first inverter circuit is connected to the second storage node. The gate of the fourth FET in the second inverter circuit is connected to the first storage node.

10. An electronic circuit having: The bistable circuit as described in claim 9; and A power supply circuit that switches the power supply voltage between a first voltage and a second voltage lower than the first voltage to provide the power supply voltage. At the first voltage, the bistable circuit is capable of writing and reading data, and at the second voltage, the bistable circuit is capable of holding the data.

11. The electronic circuit according to claim 10, wherein, When the power supply circuit provides either the first voltage or the second voltage to the bistable circuit, it also provides a constant bias voltage to the control node.

12. The electronic circuit according to claim 11, wherein, The constant bias voltage is the bias voltage between the voltage of the first power line and the voltage of the second power line when the first voltage is provided.

13. The electronic circuit according to claim 11, wherein, The voltage at the midpoint between the voltage of the first power line and the voltage of the second power line when the constant bias ratio provides the first voltage is close to the voltage of the second power line.

14. The electronic circuit according to claim 10, wherein, When the fourth FET is a P-channel FET, a low level is provided to the control node when the power supply circuit provides the first voltage, and a high level higher than the low level is provided to the control node when the power supply circuit provides the second voltage. When the fourth FET is an N-channel FET, a high level is provided to the control node when the power supply circuit provides the first voltage, and a low level lower than the high level is provided to the control node when the power supply circuit provides the second voltage.

15. An electronic circuit having a bistable circuit and a power supply circuit, The bistable circuit has the following characteristics: A first inverter circuit and a second inverter circuit, each having a first FET with a first conductivity type channel, a second FET with a second conductivity type channel opposite to the first conductivity type, a third FET with a second conductivity type channel, and a fourth FET. In the first FET, the source is connected to a first power supply line, the drain is connected to an output node, and the gate is connected to an input node. In the second FET, the source is connected to a second power supply line, the drain is connected to an intermediate node, and the gate is connected to the input node. In the third FET, the source is connected to the intermediate node, the drain is connected to the output node, and the gate is connected to the input node. In the fourth FET, one of the source and drain is connected to the intermediate node, and the other of the source and drain is connected to a control node. A power voltage is provided between the second power line and the first power line; The first storage node is connected to the output node of the first inverter circuit and the input node of the second inverter circuit. as well as The second storage node is connected to the input node of the first inverter circuit and the output node of the second inverter circuit. In the bistable circuit, the gate of the fourth FET of the first inverter circuit is connected to the first storage node and the node of one of the first storage nodes, and the gate of the fourth FET of the second inverter circuit is connected to the first storage node and the node of the other of the first storage nodes. The power supply circuit switches the power supply voltage between a first voltage and a second voltage lower than the first voltage. At the first voltage, the bistable circuit can write and read data; at the second voltage, the bistable circuit can retain the data. In the electronic circuit, when the power supply circuit provides either the first voltage or the second voltage to the bistable circuit, a constant bias voltage is also provided to the control node. When switching the power supply voltage between the first voltage and the second voltage, the power supply circuit provides a constant third voltage to the second power line, and switches the voltage supplied to the first power line between a fourth voltage and a fifth voltage. The constant bias voltage is the bias voltage between the third voltage and the fourth voltage.

16. The electronic circuit according to claim 15, wherein, The fourth FET of the first inverter circuit is a channel FET of the second conductivity type when its gate is connected to the output node of the first inverter circuit or the input node of the second inverter circuit, and a channel FET of the first conductivity type when its gate is connected to the input node of the first inverter circuit or the output node of the second inverter circuit. The fourth FET of the second inverter circuit is a FET of the second conductivity type when its gate is connected to the output node of the second inverter circuit or the input node of the first inverter circuit, and is a FET of the first conductivity type when its gate is connected to the input node of the second inverter circuit or the output node of the first inverter circuit.

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