Inverter circuit, bistable circuit, storage circuit, and processing circuit

Abstract

This inverter circuit comprises: a first FET of a channel of a first conductivity type in which the source is connected to an intermediate node, the drain is connected to a first power supply line, and the gate is connected to an output node; a second FET of a channel of a second conductivity type different from the first conductivity type in which the source is connected to the intermediate node, the drain is connected to the output node, and the gate is connected to an input node; and a third FET of a channel of the first conductivity type in which the source is connected to a second power supply line and the drain is connected to the output node.

Description

Inverter circuit, bistable circuit, memory circuit and processing circuit

[0001] The present invention relates to an inverter circuit, a bistable circuit, a memory circuit, and a processing circuit.

[0002] Pseudo-nonvolatile static random access memory (SRAM) (VNR-SRAM) or ultra-low voltage (ULV) retention static random access memory (SRAM) (ULVR-SRAM) is known, using an inverter circuit composed of complementary metal oxide semiconductor (CMOS) without using nonvolatile memory elements (see, for example, Patent Documents 1 to 3). VNR-SRAM uses a dual-mode inverter that can switch between a Schmitt trigger (ST) mode, which enables ULV retention, and a boosted inverter (BI) mode or normal inverter (NI) mode, which can achieve circuit performance equivalent to that of SRAM at normal voltages. This ULV retention SRAM can be used for so-called power gating (PG). SRAM cells using asymmetric Schmitt trigger-based bistable circuits are also known (see, for example, Non-Patent Document 1).

[0003] Also, in a memory having memory cells arranged in a matrix, a plurality of bit lines are provided in one column, and one of the plurality of bit lines is connected to some of the memory cells in one column but not to the other memory cells (for example, Patent Document 3).

[0004] International Publication No. WO 2016 / 158691 International Publication No. WO 2020 / 241000 International Publication No. WO 2021 / 161808

[0005] IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL. 70, NO. 10, pp. 3862-3866, OCTOBER 2023

[0006] Patent Documents 1 to 3 aim to perform ULVR operation to reduce standby power consumption. However, in order to minimize energy consumption, it is important to perform energy minimum point (EMP) operation using a voltage (e.g., 0.4 V) that minimizes the total energy consumed during operation and standby. Increasing the noise margin during EMP operation requires a large number of transistors per memory cell. For example, Patent Documents 1 to 3 use a minimum of eight transistors per memory cell. It is therefore desirable to be able to perform EMP operation while reducing the number of transistors and achieving miniaturization.

[0007] There is also a demand for reducing the number of transistors in a Schmitt trigger type inverter circuit to make it smaller.

[0008] Furthermore, there is a demand for miniaturization in memories in which multiple bit lines are provided in one column.

[0009] An object of the present disclosure is to provide an inverter circuit, a bistable circuit, a memory circuit, and a processing circuit that can be miniaturized.

[0010] An embodiment of the present disclosure is an inverter circuit including: a first FET having a channel of a first conductivity type, the channel having a source connected to an intermediate node, a drain connected to a first power supply line, and a gate connected to an output node; a second FET having a channel of a second conductivity type different from the first conductivity type, the channel having a source connected to the intermediate node, a drain connected to the output node, and a gate connected to an input node; and a third FET having a channel of the first conductivity type, the channel having a source connected to a second power supply line, and a drain connected to the output node.

[0011] An embodiment of the present disclosure is a memory circuit comprising: a first inverter circuit having a first input node and a first output node and exhibiting hysteresis in its transfer characteristics; a second inverter circuit having a second input node and a second output node and exhibiting no hysteresis in its transfer characteristics or exhibiting hysteresis in its transfer characteristics that is smaller than the hysteresis of the transfer characteristics exhibited by the first inverter circuit; a first storage node connecting the first input node and the second output node; and a second storage node connecting the first output node and the second input node; a write circuit that writes data to both the first storage node and the second storage node when writing data to the bistable circuit; and a read circuit that reads data from only the first storage node out of the first storage node and the second storage node when reading data from the bistable circuit.

[0012] An embodiment of the present disclosure relates to a first memory region including: NA×MA first memory cells arranged in a matrix with NA first rows and MA first columns, each memory cell having a storage node; and LA×LA first bit lines, each of which is a positive integer, provided in the MA first columns and connected to the first memory cells arranged in the column direction, wherein the NA first rows are divided into nA first blocks, each of which is a positive integer, each having the LA first rows. In each of the nA first blocks, each of the LA first bit lines is connected to the storage node of a first memory cell provided in one of the LA first rows and is not connected to a first memory cell provided in the remaining LA first rows. the MB×LB second memory cells; and the MB×LB second bit lines, each of which is a positive integer and is provided in each of the MB second columns, connecting the second memory cells arranged in the column direction, wherein the NB second rows are divided into nB second blocks, each of which is a positive integer and has the LB second rows, and in each of the nB second blocks, each of the LB second bit lines is connected to the memory node of a second memory cell provided in one of the LB second rows and is not connected to second memory cells provided in the remaining second rows of the LB second rows; and a readout circuit that reads data in parallel from the LA first memory cells in one of the nA first blocks and the LB second memory cells in one of the nB second blocks.

[0013] An embodiment of the present disclosure is an inverter circuit including: a first FET having a channel of a first conductivity type, the channel having a source connected to a first power supply line, a drain connected to an intermediate node, and a gate connected to an input node; a second FET having a channel of the first conductivity type, the channel having a source connected to the intermediate node, a drain connected to an output node, and a gate connected to the input node; a third FET having one of its source and drain connected to the intermediate node and the other of its source and drain connected to a control node; and a fourth FET having a channel of a second conductivity type different from the first conductivity type, the channel having a source connected to a second power supply line, a drain connected to the output node, and a gate connected to the second power supply line.

[0014] An embodiment of the present disclosure is a processing circuit comprising: a plurality of memory areas, each having memory cells arranged in a matrix; a readout circuit that reads data in parallel from the plurality of memory areas; and an arithmetic circuit that performs parallel arithmetic using the data read out in parallel from the plurality of memory areas, wherein one or more consecutive row physical addresses are assigned to the plurality of memory areas in sequence such that each of the plurality of memory areas is assigned one or more consecutive row physical addresses of the row physical addresses sequentially read out by the readout circuit; and the readout circuit reads out data in parallel from the one or more consecutive row physical addresses in the plurality of memory areas.

[0015] An embodiment of the present disclosure includes an input node and an output node, a first FET having a channel of a first conductivity type, a source connected to a first power supply line, a drain connected to a first intermediate node, and a gate connected to the input node, a second FET having a channel of the first conductivity type, a source connected to the first intermediate node, a drain connected to the output node, and a gate connected to the input node, a third FET having one of its source and drain connected to the first intermediate node and the other of its source and drain connected to a control node, a fourth FET having a channel of a second conductivity type different from the first conductivity type, a source connected to a second power supply line, a drain connected to a second intermediate node, and a gate connected to the input node, and a fourth FET having a channel of a second conductivity type different from the first conductivity type, a source connected to the second intermediate node, a drain connected to the output node, and a gate connected to the input node. a first storage node to which an input node of the first inverter circuit and an output node of the second inverter circuit are connected, and a second storage node to which the output node of the first inverter circuit and an input node of the second inverter circuit are connected, wherein a gate of the third FET of the first inverter circuit is connected to one of the first storage node and the second storage node, and a gate of the third FET of the second inverter circuit is connected to the other of the first storage node and the second storage node, and the first inverter circuit and the second inverter circuit are not provided with a transistor that feeds back the first storage node or the second storage node to the second intermediate node.

[0016] An embodiment of the present disclosure is a memory circuit including: a bistable circuit including a first inverter circuit having a first input node and a first output node; a second inverter circuit having a second input node and a second output node; a first storage node to which the first input node and the second output node are connected; and a second storage node to which the first output node and the second input node are connected; and a read port circuit including: a first FET having a source connected to a first power supply line, a drain connected to an intermediate node, and a gate connected to the first storage node and having a channel of a first conductivity type; a second FET having a source connected to a second power supply line, a drain connected to the intermediate node, and a gate connected to the first storage node and having a channel of a second conductivity type different from the first conductivity type; and a transfer gate having one end connected to the intermediate node, the other end connected to a bit line, and a gate connected to a word line.

[0017] According to the present disclosure, miniaturization is possible. Specifically, the number of transistors can be reduced while maintaining the rectangular transfer characteristics with hysteresis. Alternatively, a small-area array can be realized by paralleling the transistors without using multiports.

[0018] FIG. 1 is a circuit diagram of a Type I bistable circuit according to the first embodiment. FIG. 2 is a circuit diagram of a Type II bistable circuit according to the first embodiment. FIG. 3 is a diagram showing an example of the transfer characteristics of an inverter circuit according to the first embodiment. FIG. 4 is a diagram showing a butterfly curve of a bistable circuit according to a comparative example. FIGS. 5A and 5B are diagrams showing butterfly curves of a bistable circuit according to the first embodiment. FIG. 6 is a block diagram of a memory array according to the first embodiment. FIGS. 7A and 7B are circuit diagrams of a Type A inverter circuit according to the first embodiment. FIGS. 8A and 8B are circuit diagrams of a Type A inverter circuit according to the first embodiment. FIGS. 9A and 9B are circuit diagrams of a Type B inverter circuit according to the first embodiment. FIGS. 10A and 10B are circuit diagrams of a Type B inverter circuit according to the first embodiment. FIGS. 11A and 11B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIGS. 12A and 12B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIGS. 13A and 13B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIGS. 14A and 14B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIGS. 15A and 15B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIGS. 16A and 16B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIGS. 17A and 17B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIGS. 18A and 18B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. FIG. 19 is a circuit diagram of a memory cell according to Comparative Example 1. FIG. 20 is a circuit diagram of a memory cell according to Comparative Example 2. FIG. 21 is a circuit diagram of a memory cell according to Example 1. FIG. 22 is a circuit diagram of a memory cell according to Modification 1 of Example 1. FIG. 23 is a circuit diagram of a memory cell according to Modification 2 of Example 1. FIG. 24 is a circuit diagram of a memory cell according to Example 2. FIG. 25 is a circuit diagram of a memory cell according to Modification 1 of Example 2. FIG. 26 is a circuit diagram of a memory cell according to Example 3.FIG. 27 is a diagram showing QSNM during a read operation in Simulation 1. FIG. 28 is a diagram showing CWLM during a write operation in Simulation 1. FIGS. 29A and 29B are circuit diagrams of a Type C inverter circuit in the second embodiment. FIGS. 30A and 30B are circuit diagrams of a Type C inverter circuit in the second embodiment. FIG. 31 is a diagram showing transfer characteristics of the inverter circuit in Simulation 2. FIG. 32 is a circuit diagram of a memory cell according to Example 5. FIG. 33 is a circuit diagram of a memory cell according to Modification 1 of Example 5. FIG. 34 is a circuit diagram of a memory cell according to Modification 2 of Example 5. FIG. 35 is a circuit diagram of a memory cell according to Modification 3 of Example 5. FIG. 36 is a circuit diagram of a memory cell according to Modification 4 of Example 5. FIG. 37 is a circuit diagram of a memory cell according to Modification 5 of Example 5. FIG. 38 is a diagram showing QSNM during a read operation in Simulation 3. FIG. 39 is a diagram showing CWLM during a write operation in Simulation 3. FIG. 40 is a block diagram of a memory circuit according to the third embodiment. FIG. 41(A) is a block diagram showing two blocks and a sense amplifier according to the third embodiment, and FIG. 41(B) is a block diagram showing a memory cell. FIG. 42 is a block diagram of a memory circuit according to a third comparative example. FIG. 43(A) is a block diagram of a portion of a memory circuit according to the third comparative example, and FIG. 43(B) is a block diagram showing a memory cell. FIG. 44 is a diagram showing a normalized cell area relative to the number of parallel connections in simulation 4. FIG. 45(A) is a block diagram of a memory circuit according to a first modified example of the third embodiment, and FIG. 45(B) is a block diagram showing a memory cell. FIG. 46 is a diagram showing a normalized cell area relative to the number of parallel connections in simulation 4. FIG. 47 is a block diagram of a memory circuit according to a fifth comparative example. FIG. 48 is a block diagram of a memory circuit according to a second modified example of the third embodiment. FIG. 49 is a block diagram of a memory circuit according to a third modified example of the third embodiment. FIG. 50 is a block diagram of a memory circuit according to a fourth modified example of the third embodiment. FIG. 51 is a diagram showing a memory circuit without division. Fig. 52 is a diagram showing a memory circuit divided into two, Fig. 53 is a diagram showing a memory circuit divided into four, and Fig. 54 is a diagram showing a memory circuit divided into eight.FIG. 55 is a diagram showing the normalized cell area versus the number of parallel connections in Simulation 5. FIGS. 56(A) and 56(B) are circuit diagrams of a Type D inverter circuit in the fourth embodiment. FIG. 57 is a diagram showing the transfer characteristics of the inverter circuit in Simulation 6. FIG. 58 is a circuit diagram of a memory cell in Example 7. FIG. 59(A) is a butterfly curve for a read operation in Simulation 7, and FIG. 59(B) is a butterfly curve for ULVR mode. FIG. 60(A) is a diagram showing QSNM during a read operation in Simulation 7, and FIG. 60(B) is a diagram showing QSNM in ULVR mode. FIGS. 61(A) and 61(B) are circuit diagrams of an inverter circuit according to another example of Type C. FIGS. 62(A) and 62(B) are block diagrams of a processing circuit according to Comparative Example 1. FIGS. 63(A) and 63(B) are block diagrams of a processing circuit according to the fifth embodiment. 64(A) and 64(B) are block diagrams of a processing circuit according to Modification 1 of the fifth embodiment. FIGS. 65(A) and 65(B) are block diagrams of a processing circuit according to Modification 2 of the fifth embodiment. FIGS. 66(A) and 66(B) are block diagrams of a processing circuit according to Modification 3 of the fifth embodiment. FIG. 67 is a block diagram of a processing circuit according to Modification 4 of the fifth embodiment. FIG. 68 is a block diagram of a processing circuit according to Modification 5 of the fifth embodiment. FIG. 69 is a block diagram of a processing circuit according to Modification 6 of the fifth embodiment. FIG. 70 is a block diagram of a processing circuit according to Modification 7 of the fifth embodiment. FIG. 71 is a block diagram of a processing circuit according to Modification 8 of the fifth embodiment. FIG. 72 is a circuit diagram of a memory cell according to Comparative Example 9. FIG. 73 is a circuit diagram of a memory cell according to Example 8. FIG. 74 is a circuit diagram of a memory cell according to Example 9. FIG. 75 is a circuit diagram of a memory cell according to Example 10. FIG. 76 is a diagram showing QSNM during a read operation in Simulation 8. Fig. 77 is a diagram showing normalized leakage power in simulation 8. Fig. 78 is a circuit diagram of a memory cell according to a modification 1 of example 8. Fig. 79 is a circuit diagram of a memory cell according to a modification of example 9. Fig. 80 is a circuit diagram of a memory cell according to a modification of example 10.FIG. 81 is a diagram showing QSNM during a read operation in Simulation 9. FIG. 82 is a diagram showing normalized leakage power in Simulation 9. FIGS. 83A to 83C are circuit diagrams of read port circuits according to Comparative Example 11, Comparative Example 12, and Example 11, respectively. FIG. 84 is a diagram showing voltage versus time in Simulation 10. FIG. 85 is a diagram showing voltage versus time in Simulation 11.

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are denoted by the same reference numerals, and duplicate explanations may be omitted as appropriate.

[0020] First Embodiment The first embodiment is an example of a bistable circuit and a memory circuit capable of EMP operation and capable of reducing the number of transistors. Fig. 1 is a circuit diagram of a Type I bistable circuit according to the first embodiment. Fig. 2 is a circuit diagram of a Type II bistable circuit according to the first embodiment. In Figs. 1 and 2, transistors and the like outside the loop formed by inverter circuits 12A and 12B are not shown.

[0021] As shown in Figures 1 and 2, the bistable circuit 14 of the first embodiment includes inverter circuits 12A (INV1) and 12B (INV2). The inverter circuit 12A (first inverter circuit) has an input node IN1 (first input node) and an output node OUT1 (first output node). The inverter circuit 12B (second inverter circuit) has an input node IN2 (second input node) and an output node OUT2 (second output node). The input node IN1 and the output node OUT2 (second storage node) are connected to a storage node Q (first storage node). The output node OUT1 and the input node IN2 are connected to a storage node Q'. The storage nodes Q and Q' are also referred to as loop nodes LN.

[0022] In Fig. 1, the inverter circuit 12A (INV1) is Type A, and the output node OUT2 is fed back to the inverter circuit 12A. In Fig. 2, the inverter circuit 12A (INV1) is Type B, and the output node OUT1 is fed back to the inverter circuit 12A. In both Fig. 1 and Fig. 2, none of the input node IN1, output node OUT1, input node IN2, or output node OUT2 is fed back to the inverter circuit 12B.

[0023] 3 is a diagram showing an example of the transfer characteristics of the inverter circuit in the first embodiment. The horizontal axis indicates the voltage VIN input to the input node IN, and the vertical axis indicates the voltage VOUT output to the output node OUT. The virtual power supply voltage VVDD is set to 0.4 V, and the virtual ground voltage VVGND is set to 0.0 V. The transfer characteristics of INV1 and INV2 are respectively 5T, as described later. Ａ and 3T ０ The transfer characteristics are simulated. VVDD=0.4V is the voltage assuming EMP operation.

[0024] As shown in FIG. 3, INV1 generates hysteresis in the transfer characteristics. INV2 does not substantially generate hysteresis in the transfer characteristics. The magnitude of hysteresis in the transfer characteristics generated in IVN1 is defined as follows. For the same VOUT, the absolute value of the largest voltage difference between VIN in the transfer characteristics where VIN transitions from low level to high level and VIN in the transfer characteristics where VIN transitions from high level to low level is defined as ΔV1. ΔV1 / (VVDD-VVGND) is defined as the magnitude of hysteresis H1. For INV2, ΔV2 / (VVDD-VVGND) is also defined as H2. If no hysteresis occurs in INV2, H2=0.

[0025] Here, "hysteresis occurs in the transfer characteristics of INV1" means that hysteresis is intentionally generated in INV1, and H1 is, for example, preferably 0.1 or more, more preferably 0.5 or more, and even more preferably 0.75 or more. "No hysteresis occurs in the transfer characteristics of INV2" means that hysteresis is not intentionally generated in INV2, and H2 is preferably less than 0.1, more preferably 0.05 or less, and even more preferably 0.01 or less. Therefore, "hysteresis occurs in the transfer characteristics of INV1 and no hysteresis occurs in the transfer characteristics of INV2" includes the case where the hysteresis generated in INV2 is smaller than the hysteresis generated in INV1.

[0026] Of the bistable circuits 14 having inverter circuits INV1 and INV2, the bistable circuit 14 and memory cell in which the inverter circuit INV1 is Type A are called Type I, and the bistable circuit 14 and memory cell in which the inverter circuit INV1 is Type B are called Type II.

[0027] FIG. 4 shows butterfly curves of bistable circuits for comparison. In FIG. 4, INV1-INV1 is a butterfly curve of a comparative configuration in which both inverter circuits 12A and 12B of the bistable circuit 14 are inverter circuits INV1. MP1 is the memory point of INV1-INV1. INV2-INV2 is a butterfly curve of a comparative configuration in which both inverter circuits 12A and 12B of the bistable circuit 14 are inverter circuits INV2. MP2 is the memory point of INV2-INV2. The length of one side of a square inscribed in the butterfly curve is represented as the noise margin NM. As shown in FIG. 4, the lobe of the butterfly curve of INV1-INV1 spreads toward the memory point MP1, so the noise margin NM1 is larger than the noise margin NM2 of INV2-INV2.

[0028] 5A and 5B are diagrams showing butterfly curves of the bistable circuit in FIGS. 1 and 2 according to the first embodiment. FIG. 5A corresponds to the case where the write / read method, described later, is (C, C). FIG. 5B corresponds to the case where the write / read method, described later, is (C, S). MP is a memory point. As shown in FIG. 5A, the butterfly curve in the first embodiment is a curve that combines the transfer characteristics of INV1 and INV2. The noise margin NM is larger than the noise margins NM1 and NM2 in FIG. 4. As shown in FIG. 5B, in the case of (C, S), as in the case of (C, C), the noise margin NM is larger than the noise margins NM1 and NM2 in FIG. 4.

[0029] In this way, in the asymmetric bistable circuit 14 of the first embodiment in which INV1 having hysteresis and INV2 not having hysteresis are combined, the noise margin NM at VVDD=0.4V assuming EMP operation can be increased.

[0030] (Description of Memory Circuit) FIG. 6 is a block diagram of a memory array in the first embodiment. Note that FIG. 6 illustrates an example in which the write and read methods described below are (C, S). As shown in FIG. 6, the memory circuit 100 includes a memory array 20, a peripheral circuit 26, a control circuit 27, and a power supply circuit 28. In FIG. 6, the selection circuit 21 and the precharge circuit 22 are illustrated as selection circuit / precharge circuits 21 and 22. The memory array 20 includes a plurality of memory cells 10 arranged in a matrix. The number of memory cells 10 can be designed as appropriate. The memory array 20 may be divided into a plurality of subarrays. Within the memory array 20, word lines WL and write word lines WWL extend in the row direction, and bit lines BL and control lines CTL (or bit lines BL') extend in the column direction. Each memory cell 10 is connected to the word lines WL, write word lines WWL, bit lines BL, and control lines CTL (or bit lines BL').

[0031] The peripheral circuit 26 includes a selection circuit 21, a precharge circuit 22, a read circuit 23, a write circuit 24, and a WL decoder 25. When a control line CTL is connected to a memory cell 10, the selection circuit 21 selects either a bit line BL' or a power supply line 28A and connects it to the control line CTL. When a bit line BL' is connected to a memory cell 10, the selection circuit 21 is not provided. The precharge circuit 22 precharges the bit line BL when reading data from the memory cell 10. Note that when the bit line BL is pre-discharged, it is called a pre-discharge circuit 22. The read circuit 23 reads data from memory cells 10 in a row selected by a word line WL via the bit line BL and outputs the read data to a bus 29. The write circuit 24 writes data input from the bus 29 to memory cells 10 in a row selected by a word line WL and a write word line WWL via the bit lines BL and BL'. The WL decoder 25 selects the word line WL and write word line WWL of the row from which data is to be read or written.

[0032] The control circuit 27 controls the peripheral circuit 26 and the power supply circuit 28. The power supply circuit 28 is, for example, a power switch, and generates a virtual power supply voltage VVDD from a power supply voltage VDD and supplies the virtual power supply voltage VVDD to a power supply line 28A. The power supply voltage VDD may be supplied to the power supply line 28A. The power supply circuit 28 is provided on the ground side, and may generate a virtual ground voltage VVGND from a ground voltage VGND and supply it to the ground line. In the following description, the voltage supplied to the power supply line 28A will be referred to as the virtual power supply voltage VVDD, even if it is the power supply voltage VDD. The voltage supplied to the ground line 28B will be referred to as the virtual ground voltage VVGND, even if it is the ground voltage VGND.

[0033] (Example of a circuit used for INV1) An example of INV1 will be described below. Note that in the inverter circuits INV1 and INV2 below, a loop node LN is shown as a node that serves as the storage nodes Q and Q' in FIGS.

[0034] (Example of Type A Circuit) FIGS. 7A to 8B are circuit diagrams of Type A inverter circuits in the first embodiment. "5T" and "4T" indicate that the number of transistors in the inverter circuit is 5 and 4, respectively. Inverter circuits in which a feedback transistor FBT is connected to a driver transistor DRV are not marked with an "'", while inverter circuits in which a feedback transistor FBT is connected to a load transistor LD are marked with an "'". The subscript "A" indicates a Type A inverter circuit.

[0035] As shown in FIG. 7A, an inverter circuit 5T Ａ includes driver transistors DRV1 and DRV2, a load transistor LD, a feedback transistor FBT, and a pass transistor PSS. DRV1, DRV2, and PSS are N-channel field effect transistors (FETs). LD and FBT are P-channel FETs.

[0036] The source of DRV1 is connected to the ground line 28B, the drain of DRV1 is connected to the intermediate node IM, and the gate of DRV1 is connected to the input node IN. The source of DRV2 is connected to the intermediate node IM, the drain of DRV2 is connected to the output node OUT, and the gate of DRV2 is connected to the input node IN. The source of LD is connected to the power supply line 28A, the drain of LD is connected to the output node OUT, and the gate of LD is connected to the input node IN. A virtual power supply voltage VVDD and a virtual ground voltage VVGND are supplied to the power supply line 28A and the ground line 28B.

[0037] One of the source and drain of the FBT is connected to an intermediate node IM, the other of the source and drain of the FBT is connected to a feedback line FB, and the gate of the FBT is connected to an input FBIN. One of the source and drain of the PSS is connected to a loop node LN, the other of the source and drain of the PSS is connected to a bit line BL, and the gate of the PSS is connected to a word line WL. A feedback voltage VFB is supplied to the feedback line FB.

[0038] As shown in FIG. 7B, an inverter circuit 5T' Ａ includes a driver transistor DRV, load transistors LD1 and LD2, a feedback transistor FBT, and a pass transistor PSS. DRV, FBT, and PSS are N-channel FETs. LD1 and LD2 are P-channel FETs.

[0039] The source of LD1 is connected to the power supply line 28A, the drain of LD1 is connected to the intermediate node IM, and the gate of LD1 is connected to the input node IN. The source of LD2 is connected to the intermediate node IM, the drain of LD2 is connected to the output node OUT, and the gate of LD2 is connected to the input node IN. The source of DRV is connected to the ground line 28B, the drain of DRV is connected to the output node OUT, and the gate of DRV is connected to the input node IN. The FBT and PSS are connected to an inverter circuit 5T. Ａ Therefore, the explanation will be omitted.

[0040] Inverter circuit 5T Ａ and 5T' Ａ In the example shown in FIG. 1, the number of transistors is five. The conductivity type of the feedback transistor FBT is different from the conductivity types of the transistors sandwiching the intermediate node IM, and the input FBIN is connected to the output node of the other of the inverter circuits 12A and 12B that form the bistable circuit 14.

[0041] As shown in FIG. 8A, an inverter circuit 4T Ａ includes driver transistors DRV1 and DRV2, a load pass transistor LPT, and a feedback transistor FBT, but does not include a pass transistor. The load pass transistor LPT is a P-channel FET. The source of LPT is connected to a control line CTL, the drain of LPT is connected to an output node OUT, and the gate of LPT is connected to a word line WL. The control line CTL also serves as a power supply line 28A and a bit line BL. For example, the selection circuit 21 in FIG. 6 connects the control line CTL to the power supply line 28A when the memory cell 10 holds data, and connects the control line CTL to the bit line BL when data is written to the memory cell 10. The remaining components are an inverter circuit 5TＡ Therefore, the explanation will be omitted.

[0042] As shown in FIG. 8B, an inverter circuit 4T' Ａ includes load transistors LD1 and LD2, a driver pass transistor DPT, and a feedback transistor FBT, but does not include a pass transistor. DPT is an N-channel FET. The source of DPT is connected to a control line CTL, the drain of DPT is connected to an output node OUT, and the gate of DPT is connected to a word line WL. The control line CTL also serves as a ground line 28B and a bit line BL. For example, the selection circuit 21 in FIG. 6 connects the control line CTL to the ground line 28B when the memory cell 10 retains data, and connects the control line CTL to the bit line BL when data is written to the memory cell 10. The remaining components are an inverter circuit 5T' Ａ Therefore, the explanation will be omitted.

[0043] Inverter circuit 4T Ａ In the inverter circuit 4T', the pass transistor PSS and the load transistor LD are combined into one load pass transistor LPT, so the number of transistors is four. Ａ In this case, the pass transistor PSS and the driver transistor DRV are combined into one driver pass transistor DPT, so the number of transistors is four.

[0044] 9A to 10B are circuit diagrams of Type B inverter circuits according to the first embodiment. The subscript "B" indicates that the inverter circuit is Type B.

[0045] As shown in FIG. 9A, an inverter circuit 5T Ｂ In the example, the feedback transistor FBT is an N-channel transistor. The gate of the FBT is connected to the output node OUT. The other components are an inverter circuit 5T Ａ Therefore, the explanation will be omitted.

[0046] As shown in FIG. 9B, an inverter circuit 5T' ＢIn the inverter circuit 5T', the feedback transistor FBT is a P-channel transistor, and the gate of the FBT is connected to the output node OUT. Ａ Therefore, the explanation will be omitted.

[0047] As shown in FIG. 10A, an inverter circuit 4T Ｂ In the example, the feedback transistor FBT is an N-channel transistor, and the gate of the FBT is connected to the output node OUT. The other components are an inverter circuit 4T Ａ Therefore, the explanation will be omitted.

[0048] As shown in FIG. 10B, an inverter circuit 4T' Ｂ In the example, the feedback transistor FBT is a P-channel transistor, and the gate of the FBT is connected to the output node OUT. The other components are an inverter circuit 4T' Ａ Therefore, the explanation will be omitted.

[0049] Inverter circuit 5T Ｂ , 5T' Ｂ , 4T Ｂ and 4T' Ｂ As shown above, in the Type B inverter circuit, the conductivity type of the feedback transistor FBT is the same as the conductivity type of the transistors sandwiching the intermediate node IM, and the gate of the feedback transistor FBT is connected to the output node OUT of the inverter circuit 12A or 12B that forms the bistable circuit 14.

[0050] In Type A and Type B, examples have been described in which the output nodes of the two inverter circuits 12A or 12B that form the bistable circuit 14 are fed back to the intermediate node IM, but it is sufficient if the output node of the inverter circuit 12A or 12B is fed back to the path between the power supply line 28A and the ground line 28B.

[0051] In Type A and Type B, by appropriately selecting the feedback voltage VFB, the virtual power supply voltage VVDD, and the virtual ground voltage VVGND, it is possible to switch between a Schmitt trigger (ST) mode, in which the transfer characteristic has hysteresis, and a normal inverter (NI) mode, in which the transfer characteristic has substantially no hysteresis. However, the following description of EMP operation is based on the assumption that the device is operated in the ST mode, and mode switching is not required.

[0052] (Circuit example used for INV2) An example of INV2 will be described below. Figures 11A to 18B are circuit diagrams of the inverter circuit of INV2 in the first embodiment. "4T", "3T", and "2T" indicate that the number of transistors in the inverter circuit is 4, 3, and 2, respectively.

[0053] As shown in FIG. 11A, an inverter circuit 3T ０ The inverter circuit 3T includes a driver transistor DRV, a load transistor LD, and a pass transistor PSS. DRV and PSS are N-channel FETs. LD is a P-channel FET. The source of DRV is connected to the ground line 28B, the drain of DRV is connected to the output node OUT, and the gate of DRV is connected to the input node IN. The source of LD is connected to the power supply line 28A, the drain of LD is connected to the output node OUT, and the gate of LD is connected to the input node IN. One of the source and drain of PSS is connected to the loop node LN, the other of the source and drain of PSS is connected to the bit line BL, and the gate of PSS is connected to the word line WL. ０ is an inverter circuit used in a so-called 6T-SRAM cell.

[0054] As shown in FIG. 11B, an inverter circuit 3T' ０ In the example, the pass transistor PSS is a P-channel FET. The other components are an inverter circuit 3T ０ Therefore, the explanation will be omitted.

[0055] Inverter circuit 3T ０ and 3T' ０The subscript "0" in indicates that the inverter circuit does not have a feedback transistor FBT and has substantially no hysteresis. ０ The inverter circuit 3T' has no "'" added, and the pass transistor PSS is a P-channel FET. ０ is marked with a comma.

[0056] As shown in FIG. 12A, an inverter circuit 2T １ includes a driver transistor DRV and a load pass transistor LPT. DRV is an N-channel FET. The source of DRV is connected to the ground line 28B, the drain of DRV is connected to the output node OUT, and the gate of DRV is connected to the input node IN. LPT is a P-channel FET. The source of LPT is connected to a control line CTL, the drain of LPT is connected to the output node OUT, and the gate of LPT is connected to a word line WL. The control line CTL serves as both a power supply line 28A and a bit line BL. For example, the selection circuit 21 in FIG. 6 connects the control line CTL to the power supply line 28A when the memory cell 10 holds data, and connects the control line CTL to the bit line BL when data is written to the memory cell 10. The remaining components are an inverter circuit 3T ０ Therefore, the explanation will be omitted.

[0057] As shown in FIG. 12B, an inverter circuit 2T' １ includes a load transistor LD and a driver pass transistor DPT. LD is a P-channel FET. The source of LD is connected to a power supply line 28A, the drain of LD is connected to an output node OUT, and the gate of LD is connected to an input node IN. DPT is an N-channel FET. The source of DPT is connected to a control line CTL, the drain of DPT is connected to the output node OUT, and the gate of DPT is connected to a word line WL. The control line CTL also serves as a ground line 28B and a bit line BL. For example, the selection circuit 21 of FIG. 6 connects the control line CTL to the ground line 28B when the memory cell 10 retains data, and connects the control line CTL to the bit line BL when data is written to the memory cell 10. The remaining components are an inverter circuit 3T'１ Therefore, the explanation will be omitted.

[0058] Inverter circuit 2T １ and 2T' １ The subscript "1" indicates that the inverter circuit does not include a pass transistor PSS, and the pass transistor PSS also serves as the load transistor LD or the driver transistor DRV. １ "'" is not added to the inverter circuit 2T' provided with DPT. １ is marked with a comma.

[0059] As shown in FIG. 13A, an inverter circuit 3T ０,ｒｐ The semiconductor memory device 10 includes a driver transistor DRV, a load transistor LD, and a read port circuit 15. The read port circuit 15 includes a read port transistor RP1. RP1 is a P-channel FET. One of the source and drain of RP1 is connected to a read word line RWL, the other of the source and drain of RP1 is connected to a read bit line RBL, and the gate of RP1 is connected to a loop node LN. When reading data, the read word line RWL is set to high level, so that data can be read onto the read bit line RBL. Other components include an inverter circuit 3T ０ Therefore, the explanation will be omitted.

[0060] As shown in FIG. 13B, the inverter circuit 3T ０,ｒｎ In this example, RP1 is an N-channel FET. When reading data, the read word line RWL is set to low level, and data can be read to the read bit line RBL. The other components are an inverter circuit 3T ０，ｒｐ Therefore, the explanation will be omitted.

[0061] Inverter circuit 3T ０，ｒｐ and 3T ０，ｒｐ The subscripts "rp" and "rn" indicate that the read port transistor RP1 is a p-channel FET and an n-channel FET, respectively.

[0062] As shown in FIG. 14A, an inverter circuit 4T０,ｉｒｐ In the example, the read port circuit 15 includes read port transistors RP1 and RP2. RP1 and RP2 are P-channel FETs. The source of RP1 is connected to the power supply line 28A, the drain of RP1 is connected to one of the source and drain of RP2, and the gate of RP1 is connected to the loop node LN. One of the source and drain of RP2 is connected to the drain of RP1, the other of the source and drain of RP2 is connected to the read bit line RBL, and the gate of RP2 is connected to the read word line RWL. The remaining components are an inverter circuit 3T ０，ｒｐ Therefore, the explanation will be omitted.

[0063] As shown in FIG. 14B, an inverter circuit 4T ０,ｉｒｎ In the read port circuit 15, RP1 and RP2 are N-channel FETs. The source of RP1 is connected to the ground line 28B. The other components are an inverter circuit 4T. ０，ｉｒｐ Therefore, the explanation will be omitted.

[0064] Inverter circuit 3T ０，ｒｐ and 3T ０，ｒｎ In this case, there is a possibility that unselected memory cells connected to the same RBL may affect the data read. ０，ｉｒｐ and 4T ０，ｉｒｎ In this case, it is possible to prevent unselected memory cells connected to the same RBL from affecting data read. ０，ｉｒｐ and 4T ０，ｉｒｎ The subscript "i" in indicates that the read port circuit 15 has two transistors.

[0065] As shown in FIG. 15A, an inverter circuit 3T １,ｒｐcomprises a driver transistor DRV, a load pass transistor LPT, and a read port circuit 15. The LPT is a P-channel FET. The source of the LPT is connected to a control line CTL, the drain of the LPT is connected to an output node OUT, and the gate of the LPT is connected to a write word line WWL. The read port transistor RP1 of the read port circuit 15 is a P-channel FET. The control line CTL serves as both a power supply line 28A and a bit line BL. For example, the selection circuit 21 of FIG. 6 connects the control line CTL to the power supply line 28A when the memory cell 10 holds data or when reading data, and connects the control line CTL to the bit line BL when writing data to the memory cell 10. Other components include an inverter circuit 3T ０,ｒｐ Therefore, the explanation will be omitted.

[0066] As shown in FIG. 15B, an inverter circuit 3T' １,ｒｐ The selector circuit 21 in FIG. 6 includes a load transistor LD, a driver pass transistor DPT, and a read port circuit 15. The DPT is an N-channel FET. The source of the DPT is connected to a control line CTL, the drain of the DPT is connected to an output node OUT, and the gate of the DPT is connected to a write word line WWL. The read port transistor RP1 of the read port circuit 15 is a P-channel FET. The control line CTL serves as both a ground line 28B and a bit line BL. For example, the selector circuit 21 in FIG. 6 connects the control line CTL to the ground line 28B when the memory cell 10 holds data or when reading data, and connects the control line CTL to the bit line BL when writing data to the memory cell 10. Other components include an inverter circuit 3T ０,ｒｐ Therefore, the explanation will be omitted.

[0067] As shown in FIG. 16A, an inverter circuit 3T １,ｒｎ In the read port circuit 15, the read port transistor RP1 is an N-channel FET. The other components are an inverter circuit 3T １,ｒｐ Therefore, the explanation will be omitted.

[0068] As shown in FIG. 16B, an inverter circuit 3T' １,ｒｎIn the example, the read port transistor RP1 of the read port circuit 15 is an N-channel FET. The other components are the inverter circuit 3T' １,ｒｐ Therefore, the explanation will be omitted.

[0069] As shown in FIG. 17A, an inverter circuit 4T １,ｉｒｐ The selector circuit 21 shown in FIG. 6 includes a driver transistor DRV, a load pass transistor LPT, and a read port circuit 15. The read port circuit 15 includes read port transistors RP1 and RP2, which are P-channel FETs. The control line CTL serves as both a power supply line 28A and a bit line BL. For example, the selector circuit 21 shown in FIG. 6 connects the control line CTL to the power supply line 28A when the memory cell 10 holds data or when data is read, and connects the control line CTL to the bit line BL when data is written to the memory cell 10. The remaining components are an inverter circuit 4T ０,ｉｒｐ Therefore, the explanation will be omitted.

[0070] As shown in FIG. 17B, an inverter circuit 4T' 1，ｉｒｐ includes a load transistor LD, a driver pass transistor DPT, and a read port circuit 15. RP1 and RP2 are P-channel FETs. The control line CTL serves as both a ground line 28B and a bit line BL. For example, the selection circuit 21 in FIG. 6 connects the control line CTL to the ground line 28B when the memory cell 10 holds data or when data is read, and connects the control line CTL to the bit line BL when data is written to the memory cell 10. The other components are an inverter circuit 4T' ０,ｉｒｐ Therefore, the explanation will be omitted.

[0071] As shown in FIG. 18A, an inverter circuit 4T １,ｉｒｎ In the read port circuit, the read port transistors RP1 and RP2 are N-channel FETs. The other components are an inverter circuit 4T １,ｉｒｐ Therefore, the explanation will be omitted.

[0072] As shown in FIG. 18B, an inverter circuit 4T' １,ｉｒｎIn the read port circuit, the read port transistors RP1 and RP2 are N-channel FETs. The other components are an inverter circuit 4T' １,ｉｒｐ Therefore, the explanation will be omitted.

[0073] (Method of Writing to and Reading from a Memory Cell) There are three possible methods of writing data to a memory cell:

[0074] Method C: Write data to both storage nodes Q and Q' in FIGS.

[0075] Method S: Data is written to storage node Q in FIGS.

[0076] Method S': Data is written to storage node Q' in FIGS.

[0077] If hysteresis exists in the bistable circuit, high performance writing is difficult to achieve with single-sided writing, regardless of whether method S or method S' is used. For this reason, method C is preferred.

[0078] There are three possible methods for reading data from a memory cell:

[0079] Method C: Read data from both storage nodes Q and Q' in FIGS.

[0080] Method S: Read data from storage node Q in FIGS.

[0081] Method S': Read data from storage node Q' in FIGS.

[0082] By using method S, which reads from storage node Q, which is the output node of INV2, the hysteresis of INV1 can be effectively utilized to improve the noise margin. When reading from storage node Q', which is the output node of INV1, as in methods S' and C, the voltage change at storage node Q' has a large effect on the noise margin. Therefore, method S is preferred.

[0083] The write method and read method are represented as (C, C) and (C, S). (C, C) indicates that the write method is method C and the read method is method C. (C, S) indicates that the write method is method C and the read method is method S.

[0084] (Example of Memory Cell) Examples of memory cells in the comparative example and the first embodiment will be described below.

[0085] Comparative Example 1 Comparative Example 1 is an example of a 10T-ULVR cell having 10 transistors. FIG. 19 is a circuit diagram of a memory cell according to Comparative Example 1. As shown in FIG. 19, both inverter circuits 12A and 12B have inverter circuits 5T Ａ and has hysteresis in the transfer characteristics. The inverter circuits 12A and 12B are symmetrical Type 0. The gates of the PSSs of the inverter circuits 12A and 12B are connected to the word line WL, and the storage nodes Q and Q' are connected to the bit lines BL and BL', respectively, in both write and read operations. Therefore, the write and read methods are (C, C). The number of transistors is 10.

[0086] 20 is a circuit diagram of a memory cell according to Comparative Example 2. As shown in FIG. 20, an inverter circuit 12A is an inverter circuit 5T Ｂ The inverter circuit 12B has a hysteresis in the transfer characteristic. ０ and the transfer characteristics have substantially no hysteresis. The conductivity type of the FBT of the inverter circuit 12A is the same as that of DRV1 and DRV2. The gate of the FBT is connected to the output node of the inverter circuit 12A. As a result, the memory cell 10 is Type II. The gates of the PSSs of the inverter circuits 12A and 12B are connected to the word line WL, and the write and read methods are (C, C). The number of transistors is eight.

[0087] 21 is a circuit diagram of a memory cell according to Example 1. As shown in FIG. 21, an inverter circuit 12A is an inverter circuit 4T ＡThe inverter circuit 12B has a hysteresis in the transfer characteristic. ０ The transfer characteristics have substantially no hysteresis. The conductivity type of the FBT in the inverter circuit 12A is different from the conductivity types of DRV1 and DRV2. The gate of the FBT is connected to the output node of the inverter circuit 12B. This makes the memory cell 10 a Type I memory cell. The gate of the LPT in the inverter circuit 12A is connected to the write word line WWL. The gate of the PSS in the inverter circuit 12B is connected to the word line WL. In a write operation, the memory nodes Q and Q' are connected to the bit line BL and the control line CTL (bit line BL'), respectively, by the word line WL and the write word line WWL. In a read operation, the memory node Q is connected to the bit line BL by the word line WL, and the memory node Q' is not connected to the control line CTL. The write and read methods are (C, S). There are seven transistors.

[0088] Table 1 shows examples of voltages applied to each line in each operation in Example 1. Note that 0.0 V corresponds to the low level of storage nodes Q and Q', and 0.4 V corresponds to the high level of storage nodes Q and Q', and 0.0 V and 0.4 V are just examples. The same applies to the following tables.

[0089]

[0090] As shown in Table 1, during standby, the bit line BL is at 0.0 V. The selection circuit 21 connects the control line CTL to the power supply line 28A and applies 0.4 V as the virtual power supply voltage VVDD to the control line CTL. The WL decoder 25 applies 0.4 V to the word line WL and the write word line WWL. The LPT of the inverter circuit 12A functions as a load transistor. The PSS of the inverter circuit 12B is turned off. As a result, data is held in the storage nodes Q and Q'.

[0091] During a read operation, the pre-discharge circuit 22 pre-discharges the bit line BL. Because the PSS of the inverter circuit 12B is a P-channel FET, the pre-discharge circuit 22 pre-discharges the bit line BL to 0.0 V. This pre-discharge is different from that of a normal memory cell that uses N-channel FETs as pass transistors. The selection circuit 21 connects the control line CTL to the power supply line 28A and applies 0.4 V to the control line CTL as a virtual power supply voltage VVDD. The WL decoder 25 applies 0.0 V to the word line WL and 0.4 V to the write word line WWL. This causes the LPT of the inverter circuit 12A to function as a load transistor. The PSS of the inverter circuit 12B is turned on. The read circuit 23 reads the data at the storage node Q via the bit line BL.

[0092] During a write operation, the selection circuit 21 connects the control line CTL to the bit line BL' and then to the write circuit 24. The WL decoder 25 applies -0.1 V to the word line WL and the write word line WWL. The LPT of the inverter circuit 12A functions as a pass transistor and is turned on. The PSS of the inverter circuit 12B is turned on. The write circuit 24 applies the voltage of the data to be written to the bit line BL and the control line CTL. This causes data to be written to the storage nodes Q and Q'. The WL decoder 25 applies -0.1 V, which is lower than the low level L, to the word line WL and the write word line WWL. This overdrive improves the noise margin during the write operation. The WL decoder 25 may also apply a low level (0.0 V) to the word line WL and the write word line WWL.

[0093] (Modification 1 of Example 1) FIG. 22 is a circuit diagram of a memory cell according to Modification 1 of Example 1. As shown in FIG. 22, the inverter circuit 12B is an inverter circuit 3T ０ The other configurations are the same as those of the first embodiment.

[0094] Table 2 shows examples of voltages applied to each line in each operation in the first modification of the first embodiment.

[0095]

[0096] As shown in Table 2, during standby, the bit line BL is at 0.4 V. The selection circuit 21 connects the control line CTL to the power supply line 28A and applies 0.4 V to the control line CTL as the virtual power supply voltage VVDD. The WL decoder 25 applies 0.0 V to the word line WL and 0.4 V to the write word line WWL. The PSS of the inverter circuit 12B is turned off. As a result, data is held in the storage nodes Q and Q'.

[0097] During a read operation, the precharge circuit 22 precharges the bit line BL to 0.4 V. The selection circuit 21 connects the control line CTL to the power supply line 28A and applies 0.4 V to the control line CTL as a virtual power supply voltage VVDD. The WL decoder 25 applies 0.4 V to the word line WL and 0.4 V to the write word line WWL. This turns on the pass transistor PSS of the inverter circuit 12B. The read circuit 23 reads data from the storage node Q via the bit line BL.

[0098] During a write operation, the selection circuit 21 connects the control line CTL to the bit line BL' and then to the write circuit 24. The WL decoder 25 applies 0.5 V and -0.1 V to the word line WL and the write word line WWL, respectively. The LPT of the inverter circuit 12A functions as a pass transistor and is turned on. The PSS of the inverter circuit 12B is turned on. The write circuit 24 writes data to the storage nodes Q and Q'. Because the pass transistor PSS is an N-channel FET, the overdrive voltage of the word line WL is 0.5 V, which is higher than the high level H. If overdrive is not used, the WL decoder 25 may apply a high level (0.4 V) to the word line WL and a low level (0.0 V) to the write word line WWL.

[0099] 23 is a circuit diagram of a memory cell according to a second modification of the first embodiment. As shown in FIG. 23, the inverter circuit 12A includes an inverter circuit 4T' ＡIn this modification, load transistors LD1 and LD2 are provided in place of the driver transistors DRV1 and DRV2, and a driver pass transistor DPT is provided in place of the load pass transistor LPT. The other configurations are the same as those of the first modification of the first embodiment.

[0100] Table 3 shows examples of voltages applied to each line in each operation in the second modification of the first embodiment.

[0101]

[0102] As shown in Table 3, during standby, the bit line BL is at 0.4 V. The selection circuit 21 connects the control line CTL to the ground line 28B and applies 0.0 V to the control line CTL as a virtual ground voltage VVGND. The WL decoder 25 applies 0.0 V to the word line WL and the write word line WWL. The DPT of the inverter circuit 12A functions as a driver transistor. The PSS of the inverter circuit 12B is turned off. As a result, data is held in the storage nodes Q and Q'.

[0103] During a read operation, the precharge circuit 22 precharges the bit line BL to 0.4 V. The selection circuit 21 connects the control line CTL to the ground line 28B and applies 0.0 V to the control line CTL as a virtual ground voltage VVGND. The WL decoder 25 applies 0.4 V to the word line WL and 0.0 V to the write word line WWL. This turns on the PSS of the inverter circuit 12B. The DPT of the inverter circuit 12A functions as a driver transistor. The read circuit 23 reads data from the storage node Q via the bit line BL.

[0104] During a write operation, the selection circuit 21 connects the control line CTL to the write circuit 24 as the bit line BL'. The WL decoder 25 applies 0.5 V to the word line WL and the write word line WWL. The DPT of the inverter circuit 12A functions as a pass transistor and is turned on. The PSS of the inverter circuit 12B is turned on. The write circuit 24 applies the voltage of the data to be written to the bit line BL and the control line CTL. This causes the data to be written to the storage nodes Q and Q'. The WL decoder 25 may apply a high level (0.4 V) to the word line WL and the write word line WWL.

[0105] In the second modification of the first embodiment, since the DPT and PSS are N-channel FETs, a positive voltage (0.5 V in the example of Table 3) can be used as an overdrive for the write operation, which makes it easy to generate a voltage for the overdrive.

[0106] 24 is a circuit diagram of a memory cell according to Example 2. As shown in FIG. 24, an inverter circuit 12A includes an inverter circuit 5T Ａ The inverter circuit 12B has a hysteresis in the transfer characteristic. ０ and the transfer characteristics have substantially no hysteresis. The conductivity type of the FBT of the inverter circuit 12A is different from the conductivity types of DRV1 and DRV2. The gate of the FBT is connected to the output node of the inverter circuit 12B. As a result, the memory cell 10 is Type I. The gate of the PSS of the inverter circuit 12A is connected to the write word line WWL. The gate of the PSS of the inverter circuit 12B is electrically connected to the word line WL. The write method and read method are (C, S). The number of transistors is eight.

[0107] Table 4 shows examples of voltages applied to each line in each operation in the second embodiment.

[0108]

[0109] As shown in Table 4, during standby, the bit lines BL and BL' are at 0.4 V. The WL decoder 25 applies 0.0 V to the word line WL and the write word line WWL. The PSSs of the inverter circuits 12A and 12B are turned off. As a result, data is held in the storage nodes Q and Q'.

[0110] During a read operation, the precharge circuit 22 precharges the bit lines BL and BL' to 0.4 V. The WL decoder 25 applies 0.4 V to the word line WL and 0.0 V to the write word line WWL. This turns off the PSS of the inverter circuit 12A and turns on the PSS of the inverter circuit 12B. The read circuit 23 reads the data at the storage node Q via the bit line BL.

[0111] During a write operation, the WL decoder 25 applies 0.4 V to the word line WL and the write word line WWL. The PSSs of the inverter circuits 12A and 12B are turned on. The write circuit 24 applies the voltage of the data to be written to the bit line BL and the control line CTL. As a result, the data is written to the storage nodes Q and Q'.

[0112] 25 is a circuit diagram of a memory cell according to a first modification of the second embodiment. As shown in FIG. 25, the inverter circuit 12A is an inverter circuit 5T' Ａ The inverter circuit 12B is the inverter circuit 3T ０ The memory cell 10 is Type I. The write and read methods are (C, S). The number of transistors is eight. Examples of voltages applied to each line in each operation in the first modification of the second embodiment are the same as those in Table 4 of the second embodiment.

[0113] 26 is a circuit diagram of a memory cell according to Example 3. As shown in FIG. 26, an inverter circuit 12A is an inverter circuit 5T Ｂ The inverter circuit 12B is the inverter circuit 3T ０The gate of the PSS of the inverter circuit 12A is connected to the write word line WWL, and the gate of the PSS of the inverter circuit 12B is connected to the word line WL. The memory cell 10 is Type II. The write method and read method are (C, S). The number of transistors is eight. In Example 3, the inverter circuits 12A and 12B are the same inverter circuits 5T as the inverter circuits 12A and 12B of Comparative Example 2. Ｂ and 3T ０ However, in the third embodiment, the word line WL and the write word line WWL are separated, which makes the configuration different. In this configuration, the write method and read method can be (C, S). Examples of voltages applied to each line in each operation are the same as those in Table 4 of the second embodiment.

[0114] (Simulation 1) The noise margin was simulated for Comparative Examples 1 and 2 and Examples 1 to 3. The voltage conditions in the simulation were the same as those in Tables 1 to 4. The gate length of each FET was 60 nm.

[0115] Table 5 shows the gate width W of each FET in Examples 1 to 3.

[0116]

[0117] We simulated the QSNM (Quasi-Static Noise Margin) during read and write operations and the CWLM (Combined Word Line Margin) during write operations. "TT" represents the QSNM when the threshold voltages of the PFET and NFET are typical. "FF" represents the QSNM when the threshold voltages of the PFET and NFET both deviate from the typical value by 3σ toward the Fast (F) side (lower) due to process variations. "SS" represents the QSNM when the threshold voltages of the PFET and NFET both deviate from the typical value by 3σ toward the Slow (S) side (higher) due to process variations. "FS" and "SF" represent the QSNM when one of the threshold voltages of the PFET and NFET deviates from the typical value by 3σ toward the F side and the other deviates from the typical value by 3σ toward the S side. If the SNMs of TT, FF, SS, FS, and SF are ensured, the QSNM can be ensured even if the threshold voltages of the PFET and NFET vary within a range of ±3σ.

[0118] FIG. 27 is a diagram showing the QSNM during a read operation in Simulation 1. As shown in FIG. 27, in Comparative Example 1, which has 10 transistors, the lowest QSNM is FS, which is approximately 140 mV. In contrast, in Comparative Example 2, the number of transistors can be reduced to 8, but the QSNM is 50 mV or less in the worst case of FS. This means that the noise margin during EMP operation with VVDD at 0.4 V is too small. In Examples 1 to 3, the QSNM is 140 mV or more. As such, with seven or eight transistors, a QSNM equivalent to or higher than that of Comparative Example 1 can be achieved.

[0119] 28 is a diagram showing CWLM during a write operation in Simulation 1. As shown in FIG. 28, in Comparative Example 1, the lowest CWLM is SF, at approximately 85 mV. In contrast, in Comparative Example 2 and Examples 1 to 3, CWLM is 80 mV or higher. As such, Examples 1 to 3 have fewer transistors than Comparative Example 1, and can increase CWLM to the same extent as Comparative Example 1 during EMP operation.

[0120] In the simulation of Example 1, an overdrive is introduced. Introducing an overdrive can improve CWLM. In Example 1, a negative voltage is generated to make the overdrive negative during a write operation. In a configuration such as Modification 2 of Example 1, the overdrive can be made positive, so there is no need to generate a negative voltage. Although no overdrive is introduced in the simulations of Examples 2 and 3, introducing an overdrive can further increase CWLM.

[0121] If overdrive is introduced during a write operation, it is no longer strictly an EMP operation. However, an overdrive of about 0.1 V applied to the word line WL can achieve almost the same effect as an EMP operation. Therefore, high energy efficiency can be expected. Furthermore, when used for inference in an AI (artificial intelligence) accelerator, where read opportunities are more frequent than write opportunities, the impact on energy efficiency is small.

[0122] According to the first embodiment, by using a (C, S) write method and a (C, S) read method, the number of transistors can be reduced while maintaining the noise margin. This makes it possible to miniaturize the memory circuit. Comparative Example 2 and Example 3 use the same inverter circuit to configure a bistable circuit, but Example 3, unlike Comparative Example 2, uses a cell configuration in which the word line is separated into a word line WL and a write word line WWL, and uses a (C, S) configuration. As a result, the number of transistors can be reduced while increasing QSNM.

[0123] 1 and 2, the bistable circuit 14 includes an inverter circuit INV1 whose transfer characteristic exhibits hysteresis, and an inverter circuit INV2 whose transfer characteristic exhibits no hysteresis or exhibits hysteresis smaller than that exhibited by the inverter circuit INV1. When writing data to the bistable circuit 14, the write circuit 24 writes the data to both storage nodes Q and Q'. When reading data from the bistable circuit 14, the read circuit 23 reads the data from only the storage node Q, which is connected to the input node IN1 of the inverter circuit INV1 and the output node OUT2 of the inverter circuit INV2, out of the storage nodes Q and Q'.

[0124] Furthermore, the WL decoder 25 (selection circuit) connects the storage node Q to the bit line BL (first bit line) and connects the storage node Q' to the bit line BL' (second bit line) during a write operation. The WL decoder 25 connects the storage node Q to the bit line BL during a read operation, but does not connect the storage node Q' to the bit line BL'. This allows (C, S) to be realized.

[0125] As shown in FIGS. 1, 2, and 7A to 10B, either the signal at the output node OUT1 of the inverter circuit INV1 or the signal at the output node OUT2 of the inverter circuit INV2 is fed back to a path between one of the first power supply line 28A and the ground line 28B of the inverter circuit INV1 and the other, the second power supply line. As shown in FIGS. 1, 2, and 11A to 18B, neither the signal at the output node OUT1 nor the signal at the output node OUT2 is fed back to the inverter circuit INV2. This allows hysteresis to be generated in the transfer characteristics of the inverter circuit INV1. On the other hand, it is possible to intentionally prevent hysteresis from being generated in the transfer characteristics of the inverter circuit INV2.

[0126] As shown in FIGS. 7A to 10B, the inverter circuit INV1 is an inverter circuit 5T Ａ , 5T' Ａ , 4T Ａ , 4T' Ａ , 5T Ｂ , 5T'Ｂ , 4T Ｂ , and 4T' Ｂ Any of the above may be used. This allows hysteresis to be generated in the transfer characteristics of the inverter circuit INV1. The inverter circuit INV1 includes a first FET, a second FET, and a third FET. The first FET corresponds to DRV1 in FIGS. 7(A), 8(A), 9(A), and 10(A) and LD1 in FIGS. 7(B), 8(B), 9(B), and 10(B). The second FET corresponds to DRV2 in FIGS. 7(A), 8(A), 9(A), and 10(A) and LD2 in FIGS. 7(B), 8(B), 9(B), and 10(B). The third FET corresponds to FBT in FIGS. 7(A) to 10(B).

[0127] The first FET has a source connected to a first power line, one of the power line 28A and the ground line 28B, a drain connected to the intermediate node IM, and a gate connected to the input node IN. It has a channel of a first conductivity type. The second FET has a source connected to the intermediate node IM, a drain connected to the output node OUT, and a gate connected to the input node IN. The first FET and the second FET have channels of the same first conductivity type. The third FET has one of its source and drain connected to the intermediate node IM, the other of its source and drain connected to a feedback line FB (control node), and its gate connected to either the output node OUT or the output node OUT2 of the inverter circuit INV2. The conductivity type of the channel of the third FET may be the same first conductivity type as the first and second FETs, or may be a second conductivity type different from the first conductivity type.

[0128] The feedback voltage VFB is a voltage that causes the inverter circuit INV1 to operate in the ST mode. The feedback voltage VFB may be the same or different in the standby, read operation, and write operation.

[0129] 1 , by configuring the bistable circuit 14 as Type I, the noise margin can be increased and the number of transistors can be reduced. In the Type I bistable circuit 14, the signal at the output node OUT2 is fed back to the path between the power supply line 28A and the ground line 28B in the inverter circuit INV1, causing hysteresis in the transfer characteristics of the inverter circuit INV1. On the other hand, since neither the signal at the output nodes OUT1 nor OUT2 is fed back to the inverter circuit INV2, no hysteresis is generated in the transfer characteristics of the inverter circuit INV2, or the hysteresis generated in the inverter circuit INV2 is smaller than the hysteresis generated in the inverter circuit INV1.

[0130] As shown in FIGS. 7A to 8B, the inverter circuit INV1 of Type I is an inverter circuit 5T Ａ , 5T' Ａ , 4T Ａ and 4T' Ａ In these inverter circuits INV1, the conductivity type (second conductivity type) of the feedback transistor FBT (third FET) is different from the conductivity type (first conductivity type) of the driver transistors DRV1 and DRV2 or the load transistors LD1 and LD2 to which the intermediate node IM is connected. The gate of the feedback transistor FBT is connected to OUT2.

[0131] As shown in FIG. 7(A) and FIG. 7(B), the inverter circuit 5T Ａ and 5T' Ａ In the example, the sources of the load transistor LD and the driver transistor DRV (fourth FET) are connected to the other second power supply line of the power supply line 28A and the ground line 28B, the drains are connected to the output node OUT, and the gates are connected to the input node IN. The conductivity type (second conductivity type) of the load transistor LD is different from the conductivity type (first conductivity type) of the driver transistors DRV1 and DRV2, and the conductivity type (second conductivity type) of the driver transistor DRV is different from the conductivity type (first conductivity type) of the load transistors LD1 and LD2.

[0132] As shown in FIG. 8(A) and FIG. 8(B), an inverter circuit 4TＡ and 4T' Ａ In the bistable circuit 14, the drains of the load pass transistor LPT and the driver pass transistor DPT (fourth FET) are connected to the output node OUT, and the gates are connected to the input node IN. The selection circuit 21 connects the source of the fourth FET to the bit line BL during a write or read operation, and connects the source of the fourth FET to the power supply line 28A or the ground line 28B when the bistable circuit 14 holds data.

[0133] In addition to the EMP operation mode, the memory cell 10 can also operate in a low-voltage retention mode and a normal operation mode. In the low-voltage retention mode, power consumption can be reduced by setting the inverter circuit INV1 in ST mode and setting VVDD-VVGND to less than 0.4 V. In the normal operation mode, performance equivalent to that of a 6T-SRAM can be achieved at that voltage by setting the inverter circuit INV1 in ST mode or NI mode and setting VVDD-VVGND to 0.4 V or higher.

[0134] Second Embodiment The second embodiment is an example of an inverter circuit that generates hysteresis in the transfer characteristics by using fewer transistors than Type A and Type B. The inverter circuit of the second embodiment is called Type C to distinguish it from Type A and Type B described in the first embodiment.

[0135] (Example of Type C Circuit) FIGS. 29A to 30B are circuit diagrams of Type C inverter circuits in the second embodiment. "3T" and "4T" indicate that the number of transistors in the inverter circuit is three and four, respectively. An inverter circuit in which a feedback transistor FBT is connected to a driver transistor DRV is not marked with an "'", but an inverter circuit in which a feedback transistor FBT is connected to a load transistor LD is marked with an "'". The subscript "C" indicates that the inverter circuit is Type C.

[0136] As shown in FIG. 29A, an inverter circuit 3T Ｃcomprises a driver transistor DRV, a load pass transistor LPT, and a feedback transistor FBT. DRV is an N-channel FET. LPT and FBT are P-channel FETs.

[0137] The source of the FBT is connected to the intermediate node IM, the drain of the FBT is connected to the ground line 28B, and the gate of the FBT is connected to the output node OUT. The source of the DRV is connected to the intermediate node IM, the drain of the DRV is connected to the output node OUT, and the gate of the DRV is connected to the input node IN. The source of the LPT is connected to the control line CTL, the drain of the LPT is connected to the output node OUT, and the gate of the LPT is connected to the word line WL. A virtual ground voltage VVGND is supplied to the ground line 28B. The control line CTL serves as both the power supply line 28A and the bit line BL. For example, the selection circuit 21 of FIG. 6 connects the control line CTL to the power supply line 28A when the memory cell 10 retains data, and connects the control line CTL to the bit line BL when data is written to the memory cell 10.

[0138] As shown in FIG. 29B, an inverter circuit 3T' Ｃ comprises a load transistor LD, a driver pass transistor DPT, and a feedback transistor FBT. DPT and FBT are N-channel FETs. LD is a P-channel FET.

[0139] The source of the FBT is connected to the intermediate node IM, the drain of the FBT is connected to the power supply line 28A, and the gate of the FBT is connected to the output node OUT. The source of the LD is connected to the intermediate node IM, the drain of the LD is connected to the output node OUT, and the gate of the LD is connected to the input node IN. The source of the DPT is connected to the control line CTL, the drain of the DPT is connected to the output node OUT, and the gate of the DPT is connected to the word line WL. A virtual power supply voltage VVDD is supplied to the power supply line 28A. The control line CTL also serves as the ground line 28B and the bit line BL. For example, the selection circuit 21 of FIG. 6 connects the control line CTL to the ground line 28B when the memory cell 10 retains data, and connects the control line CTL to the bit line BL when data is written to the memory cell 10.

[0140] As shown in FIG. 30A, an inverter circuit 4T Ｃ、ｗｐ comprises a driver transistor DRV, a load transistor LD, a feedback transistor FBT, and a pass transistor PSS, but does not comprise a load pass transistor. LD and PSS are P-channel FETs. The source and gate of LD are connected to a power supply line 28A, and the drain of LD is connected to an output node OUT. One of the source and drain of PSS is connected to the output node OUT, the other of the source and drain of PSS is connected to a bit line BL, and the gate of PSS is connected to a word line WL. LD is used in an off state. Other components include an inverter circuit 3T Ｃ Therefore, the explanation will be omitted.

[0141] As shown in FIG. 30B, an inverter circuit 4T' Ｃ、ｗｎ The inverter circuit 3T' includes a driver transistor DRV, a load transistor LD, a feedback transistor FBT, and a pass transistor PSS, but does not include a driver pass transistor. DRV and PSS are N-channel FETs. The source and gate of DRV are connected to the ground line 28B, and the drain of DRV is connected to the output node OUT. One of the source and drain of PSS is connected to the output node OUT, the other of the source and drain of PSS is connected to the bit line BL, and the gate of PSS is connected to the word line WL. DRV is used in the off state. The other components are an inverter circuit 3T' Ｃ Therefore, the explanation will be omitted.

[0142] (Simulation 2) (Example 4) Inverter circuit 3T Ｃ As a comparative example, the inverter circuit 5T Ａ , 5T Ｂ and 4T Ａ The transfer characteristics were also simulated.

[0143] 31 is a diagram showing the transfer characteristics of the inverter circuit in Simulation 2. The transfer characteristics when VIN transitions from 0.0 V (low level) to 0.4 V (high level) are shown by L→H, and the transfer characteristics when VIN transitions from 0.4 V to 0.0 V are shown by H→L.

[0144] Inverter circuit 3T Ｃ In the example shown in FIG. 1, the transition from L to H is described below. The control line CTL and word line WL are at 0.4 V. When VIN is 0.0 V, the FBT and DRV are off, making it difficult for the output node OUT to discharge to the ground line 28B. The output node OUT is charged from the power supply line 28A due to the leakage current of the LPT, and VOUT is at 0.4 V. As VIN gradually increases, the DRV turns on, but the FBT remains off, making it difficult for the output node OUT to discharge. As VOUT gradually decreases and the driving force of the FBT increases above a certain level, discharge occurs from the output node OUT to the ground line 28B, and VOUT suddenly changes to a low level near 0 V.

[0145] Inverter circuit 3T Ｃ The case where the voltage changes from H to L will be described. The control line CTL and word line WL are 0.4 V. When VIN is 0.4 V, the DRV is on, and the FBT is slightly on, with its driving force being greater than the leakage current of the LPT. As a result, the output node OUT is discharged to the ground line 28B, and VOUT is at a low level near 0 V. Even as VIN gradually decreases, the LPT remains off. As a result, the output node OUT is difficult to charge. When VIN approaches 0.0 V and the DRV begins to turn off deeply, the driving force of the DRV and FBT becomes approximately the same as the driving force of the LPT, and the output node OUT begins to charge. Thereafter, the rise in VOUT turns off the FBT. As a result, VOUT rises sharply to 0.4 V.

[0146] Inverter circuit 3T Ｃ The hysteresis of the inverter circuit 4T Ａ The inverter circuit 5T has a hysteresis smaller than that of Ａ and 5T ＢIn this way, Type C can achieve rectangular characteristics with hysteresis equal to or greater than that of Types A and B, but with a smaller number of transistors.

[0147] (Example of Memory Cell) An example of the second embodiment using a Type C inverter circuit will be described below.

[0148] 32 is a circuit diagram of a memory cell according to Example 5. As shown in FIG. 32, an inverter circuit 12A includes an inverter circuit 4T Ｃ，ｗｐ The inverter circuit 12B has a hysteresis in the transfer characteristic. ０，ｉｒｎ and has substantially no hysteresis in its transfer characteristics. Since the FBT of the inverter circuit 12A is fed back from the output node of the inverter circuit 12A, the memory cell 10 is Type II. The gate of PSS of the inverter circuit 12A is connected to the write word line WWL, and the other of the source and drain of PSS is connected to the write bit line WBL. The gate of RP2 of the inverter circuit 12B is connected to the read word line RWL, and the other of the source and drain of RP2 is connected to the read bit line RBL. The write and read methods are (S, S). The number of transistors is eight.

[0149] Table 6 shows examples of voltages applied to each line in each operation in the fifth embodiment.

[0150]

[0151] As shown in Table 6, during standby, the write bit line WBL, write word line WWL, and read bit line RBL are at 0.4 V. The read word line RWL is at 0.0 V. PSS of the inverter circuit 12A and RP2 of the inverter circuit 12B are turned off. As a result, data is held in the storage nodes Q and Q'.

[0152] During a read operation, the precharge circuit 22 precharges the read bit line RBL to 0.4V. The WL decoder 25 applies 0.4V to the write word line WWL and the read word line RWL. This turns off the PSS of the inverter circuit 12A. In the inverter circuit 12B, when the storage node Q is 0.0V, RP1 is off, and even if 0.4V is applied to the gate of the read port transistor RP2, the read bit line RBL is 0.4V. When the storage node Q is 0.4V, RP1 is on. When 0.4V is applied to the gate of RP2, RP2 turns on, and the read bit line RBL is discharged from 0.4V. This allows the read circuit 23 to read data from the storage node Q via the read bit line RBL. The provision of the read port circuit 15 prevents the read operation from being disturbed by the level of the storage node Q in unselected memory cells 10 that share the read bit line RBL.

[0153] During a write operation, the WL decoder 25 applies −0.1 V to the write word line WWL and 0.0 V to the read word line RWL. PSS of the inverter circuit 12A is turned on. RP2 of the inverter circuit 12B is turned off. The write circuit 24 applies the voltage of the data to be written to the write bit line WBL. This causes the data to be written to the storage node Q'. The WL decoder 25 applies −0.1 V, which is lower than the low level, to the write word line WWL. This improves the operating margin during the write operation. The WL decoder 25 may apply 0.0 V to the word line WL and the write word line WWL.

[0154] (Modification 1 of Example 5) Fig. 33 is a circuit diagram of a memory cell according to Modification 1 of Example 5. As shown in Fig. 33, an inverter circuit 12A includes an inverter circuit 4T' Ｃ，ｗｎ The inverter circuit 12B has a hysteresis in the transfer characteristic. ０，ｉｒｎ The transfer characteristic has substantially no hysteresis. The write and read methods are (S, S). The number of transistors is eight.

[0155] Table 7 shows examples of voltages applied to each line in each operation in the first modification of the fifth embodiment.

[0156]

[0157] As shown in Table 7, during standby, the write bit line WBL, write word line WWL, and read word line RWL are at 0.0 V. The read bit line RBL is at 0.4 V. PSS of the inverter circuit 12A and RP2 of the inverter circuit 12B are turned off. As a result, data is held in the storage nodes Q and Q'.

[0158] During a read operation, the precharge circuit 22 precharges the read bit line RBL to 0.4 V. The WL decoder 25 applies 0.0 V to the write word line WWL and 0.4 V to the read word line RWL. This turns off PSS of the inverter circuit 12A and turns on RP2 of the inverter circuit 12B. The method of reading data from the storage node Q via the read bit line RBL of the read circuit 23 is the same as in the fifth embodiment.

[0159] During a write operation, the WL decoder 25 applies 0.5 V to the write word line WWL and 0.0 V to the read word line RWL. PSS of the inverter circuit 12A is turned on, and RP2 of the inverter circuit 12B is turned off. The write circuit 24 applies the voltage of the data to be written to the write bit line WBL. This causes the data to be written to the storage node Q'. The WL decoder 25 applies 0.5 V, which is lower than the high level, to the write word line WWL. This improves the noise margin during the write operation. The WL decoder 25 may also apply 0.4 V to the word line WL and the write word line WWL.

[0160] (Modification 2 of Example 5) FIG. 34 is a circuit diagram of a memory cell according to Modification 2 of Example 5. As shown in FIG. 34, the inverter circuit 12A includes an inverter circuit 4T Ｃ，ｗｐ The inverter circuit 12B has a hysteresis in the transfer characteristic. ０and the transfer characteristics have substantially no hysteresis. The gate of the PSS of the inverter circuit 12A is connected to the write word line WWL, and the other of the source and drain of the PSS is connected to the write bit line WBL. The gate of the PSS of the inverter circuit 12B is connected to the word line WL, and the other of the source and drain is connected to the bit line BL. The write and read methods are (C, S). There are seven transistors.

[0161] During standby, the write word line WWL is at 0.4 V, the word line WL is at 0.0 V, and the pass transistors PSS of the inverter circuits 12A and 12B are turned off, thereby holding data in the storage nodes Q and Q'.

[0162] During a read operation, the WL decoder 25 applies 0.4 V to the word line WL and the write word line WWL. This turns off the PSS of the inverter circuit 12A and turns on the PSS of the inverter circuit 12B. The read circuit 23 reads data from the storage node Q via the bit line BL.

[0163] During a write operation, the WL decoder 25 applies 0.5 V to the word line WL and −0.1 V to the write word line WWL. The pass transistors PSS of the inverter circuits 12A and 12B are turned on. The write circuit 24 applies the voltage of the data to be written to the bit line BL and the write bit line WBL. This causes the data to be written to the storage nodes Q and Q'. The WL decoder 25 may also apply 0.4 V to the word line WL and 0.0 V to the write word line WWL.

[0164] (Modification 3 of Example 5) FIG. 35 is a circuit diagram of a memory cell according to Modification 3 of Example 5. As shown in FIG. 35, the inverter circuit 12A includes an inverter circuit 3T Ｃ The inverter circuit 12B has a hysteresis in the transfer characteristic. ０，ｉｒｎand the transfer characteristic has substantially no hysteresis. The gate of LPT of the inverter circuit 12A is connected to the write word line WWL, and the other of the source and drain of LPT is connected to the control line CTL. The gate of RP2 of the inverter circuit 12B is connected to the read word line RWL, and the other of the source and drain of RP2 is connected to the read bit line RBL. The write method and read method are (S, S). There are seven transistors.

[0165] During standby, the write word line WWL is at 0.4 V and the read word line RWL is at 0.0 V. The selection circuit 21 connects the control line CTL to the power supply line 28A. The load pass transistor LPT of the inverter circuit 12A and the read port transistor RP2 of the inverter circuit 12B are turned off. As a result, data is held in the storage nodes Q and Q'.

[0166] During a read operation, the WL decoder 25 applies 0.4 V to the write word line WWL and the read word line RWL. This turns off LPT of the inverter circuit 12A and turns on RP2 of the inverter circuit 12B. The selection circuit 21 connects the control line CTL to the power supply line 28A. The read circuit 23 reads data from the storage node Q via the read bit line RBL.

[0167] During a write operation, the WL decoder 25 applies -0.1 V to the write word line WWL and 0.0 V to the read word line RWL. This turns on LPT of the inverter circuit 12A and turns off RP2 of the inverter circuit 12B. The selection circuit 21 connects the control line CTL to the bit line BL'. The write circuit 24 applies the voltage of the data to be written to the bit line BL'. This causes the data to be written to the storage node Q'. The WL decoder 25 may also apply 0.0 V to the write word line WWL.

[0168] (Fourth Modification of the Fifth Embodiment) FIG. 36 is a circuit diagram of a memory cell according to a fourth modification of the fifth embodiment. As shown in FIG. 36, the inverter circuit 12A is an inverter circuit 3T. Ｃ The inverter circuit 12B has a hysteresis in the transfer characteristic.０ and the transfer characteristics have substantially no hysteresis. The gate of the LPT of the inverter circuit 12A is connected to the write word line WWL, and the other of the source and drain of the LPT is connected to the control line CTL. The gate of the PSS of the inverter circuit 12B is connected to the word line WL, and the other of the source and drain of the PSS is connected to the bit line BL. The write and read methods are (C, S). There are six transistors.

[0169] During standby, the word line WL is at 0.0 V and the write word line WWL is at 0.4 V. The selection circuit 21 connects the control line CTL to the power supply line 28A. The LPT of the inverter circuit 12A and the PSS of the inverter circuit 12B are turned off. As a result, data is held in the storage nodes Q and Q'.

[0170] During a read operation, the WL decoder 25 applies 0.4 V to the write word line WWL and the word line WL. This turns off the LPT of the inverter circuit 12A and turns on the PSS of the inverter circuit 12B. The selection circuit 21 connects the control line CTL to the power supply line 28A. The read circuit 23 reads data from the storage node Q via the bit line BL.

[0171] During a write operation, the WL decoder 25 applies 0.5 V to the word line WL and −0.1 V to the write word line WWL. This turns on the LPT of the inverter circuit 12A and the PSS of the inverter circuit 12B. The selection circuit 21 connects the control line CTL to the bit line BL′. The write circuit 24 applies the voltage of the data to be written to the bit lines BL and BL′. This writes the data to the storage nodes Q and Q′. The WL decoder 25 may also apply 0.4 V to the word line WL and 0.0 V to the write word line WWL.

[0172] 37 is a circuit diagram of a memory cell according to a fifth modification of the fifth embodiment. As shown in FIG. 37, the inverter circuit 12A includes an inverter circuit 3T Ｃ The inverter circuit 12B has a hysteresis in the transfer characteristic. １and the transfer characteristics have substantially no hysteresis. The gate of the LPT of the inverter circuit 12A is connected to the write word line WWL, and the other of the source and drain of the LPT is connected to the control line CTL2. One of the source and drain of the LPT of the inverter circuit 12B is connected to the control line CTL1, the other of the source and drain of the LPT is connected to the storage node Q, and the gate of the LPT is connected to the word line WL. The write and read methods are (C, S). The number of transistors is five.

[0173] During standby, the word line WL and the write word line WWL are at 0.4 V. The selection circuit 21 connects the control lines CTL1 and CTL2 to the power supply line 28A. The load pass transistors LPT of the inverter circuits 12A and 12B are turned off. As a result, data is held in the storage nodes Q and Q'.

[0174] During a read operation, the WL decoder 25 applies 0.0 V to the word line WL and 0.4 V to the write word line WWL. This turns off the LPT of the inverter circuit 12A and turns on the LPT of the inverter circuit 12B. The selection circuit 21 connects the bit line BL to the control line CTL1 and the power supply line 28A to the control line CTL2. The read circuit 23 reads data from the storage node Q via the bit line BL.

[0175] During a write operation, the WL decoder 25 applies 0.5 V to the word line WL and the write word line WWL. This turns on the LPTs of the inverter circuits 12A and 12B. The selection circuit 21 connects the control lines CTL1 and CTL2 to the bit lines BL and BL', respectively. The write circuit 24 applies the voltage of the data to be written to the bit lines BL and BL'. This causes the data to be written to the storage nodes Q and Q'. The WL decoder 25 may also apply 0.4 V to the word line WL and the write word line WWL.

[0176] In the fifth modification of the fifth embodiment, the number of transistors can be set to five, which is the smallest number among the first and second embodiments.

[0177] (Simulation 3) The noise margin was simulated for Example 5 and its Modifications 2 to 4. The gate length of each FET was 60 nm.

[0178] Table 8 shows the gate width W of each FET in Example 5.

[0179]

[0180] 38 is a diagram showing QSNM during a read operation in Simulation 3. As shown in FIG. 38, in Example 5 and its Modification 3, an inverter circuit 4T in which a read port circuit 15 is provided in an inverter circuit 12B is used. ０,ｉｒｎ In the second and fourth modifications of the fifth embodiment, the inverter circuit 12B is provided with an inverter circuit 4T. ０,ｉｒｎ Instead of the inverter circuit 3T having no read port circuit 15, ０ In the second and fourth modifications of the fifth embodiment, the QSNM can be made equal to or greater than that of the first comparative example.

[0181] 39 is a diagram showing CWLM during a write operation in Simulation 3. Note that an overdrive of 0.1 V is applied to the write word line WWL during a write operation. As shown in FIG. 39, in Example 5 and its Modification 3, the CWLM can be made larger than in Comparative Examples 1 and 2. In Modifications 2 and 4 of Example 5, the CWLM is lower than in Example 5 and its Modification 3, but can be made approximately the same as in Comparative Example 1.

[0182] In the second and fourth modifications of the fifth embodiment, the number of transistors can be reduced by one compared to the fifth embodiment and its third modification. In particular, in the fourth modification of the fifth embodiment, the number of transistors can be reduced to six. In the second and fourth modifications of the fifth embodiment, the voltage of the control line CTL is 0.0 V or 0.4 V during a write operation. Therefore, unselected memory cells that share the control line CTL with the memory cell to be written are susceptible to the influence of voltage fluctuations on the control line CTL. However, no major problems arise if driven using a normal clock-synchronized precharge method.

[0183] The Type C inverter circuit of the second embodiment includes a first FET, a second FET, and a third FET. The first FET corresponds to the FBT in FIGS. 29(A) to 30(B). The second FET corresponds to the DRV in FIGS. 29(A) and 30(A) and the LD in FIGS. 29(B) and 30(B). The third FET corresponds to the LPT in FIG. 29(A), the DPT in FIG. 29(B), the LD in FIG. 30(A), and the DRV in FIG. 30(B).

[0184] The first FET has a source connected to the intermediate node IM, a drain connected to one of the first power supply lines, the power supply line 28A and the ground line 28B, and a gate connected to the output node OUT. The second FET has a source connected to the intermediate node IM, a drain connected to the output node OUT, and a gate connected to the input node IN. The third FET has a source connected to the other of the second power supply line, the power supply line 28A and the ground line 28B, and a drain connected to the output node OUT. The first FET and the third FET have the same first conductivity type, and the second FET has a second conductivity type different from the first conductivity type. This makes it possible to realize an inverter circuit INV1 having hysteresis in its transfer characteristics with a small number of transistors.

[0185] Inverter circuit 4T in FIG. 30(A) and FIG. 30(B) Ｃ，ｗｐ and 4T Ｃ，ｗｎ As shown above, the gate of the third FET is connected to the second power supply line, which is the other of the power supply line 28A and the ground line 28B. This allows the third FET to be used as a load transistor or a driver transistor.

[0186] As in the fifth embodiment and its modifications, a Type C inverter circuit can be used for at least one of the inverter circuits 12A and 12B of the bistable circuit 14. The inverter circuit 3T shown in FIGS. Ｃ and 3T' ＣWhen using the third FET, the selection circuit 21 connects the source of the third FET to the bit line BL' or the write bit line WBL during a write operation, and connects the source of the third FET to the second power supply line when the bistable circuit 14 holds data or during a read operation. This allows the third FET to be used as a pass transistor and a load transistor or a driver transistor.

[0187] As shown in Figures 32 to 37, the inverter circuit of Type C of the second embodiment can be used for the inverter circuit INV1 of Figure 2 of the first embodiment. The write and read methods may be any of (C, C), (C, S), and (S, S). This reduces the number of transistors and makes it possible to miniaturize the memory circuit. Note that with the current Type C configuration, it is not possible to switch between ST mode and NI mode as with Types A and B.

[0188] Third Embodiment The third embodiment is an example of a memory circuit that reads data in parallel to a logic circuit that performs parallel processing, such as a neural network accelerator. In the following description, MA, MB, NA, NB, nA, nB, LA, and LB are positive integers.

[0189] FIG. 40 is a block diagram of a memory circuit according to a third embodiment. The numbers in parentheses following MA, MB, NA, NB, nA, nB, LA, and LB indicate an example in which the memory circuit 102 has 256×256 memory cells. As shown in FIG. 40 , the memory circuit 102 according to the third embodiment includes memory regions 30A and 30B, decoders 34A and 34B, sense amplifiers 36A and 36B, and a logic circuit 38. The sense amplifiers 36A and 36B are arranged on either side of the logic circuit 38. The memory regions 30A and 30B are arranged on either side of the sense amplifiers 36A and 36B.

[0190] The memory area 30A (first memory area) includes NA×MA memory cells 10A (first memory cells) arranged in a matrix of NA first rows and MA first columns. The NA first rows are divided into nA blocks 32A (first blocks), each having LA first rows. NA word lines WLA (first word lines) are provided, each in the NA first rows, and connected to the memory cells 10A arranged in the row direction. A decoder 34A selects the word line WLA. MA×LA sense amplifiers 36A are provided.

[0191] The memory region 30B (second memory region) includes NB×MB memory cells 10B (second memory cells) arranged in a matrix of NB second rows and MB second columns. The NB second rows are divided into nB blocks 32B (second blocks), each having LB second rows. NB word lines WLB (second word lines) are provided, each in the NB second rows, and connected to the memory cells 10B arranged in the row direction. A decoder 34B selects the word line WLB. MB×LB sense amplifiers 36B are provided.

[0192] The logic circuit 38 processes in parallel the data read by the sense amplifiers 36 A and 36 B. The logic circuit 38 is, for example, an accelerator for a neural network.

[0193] The sense amplifiers 36A and 36B are simultaneously selected by word lines WLA and WLB. Data is read in parallel from MA×LA memory cells 10A in the block 32A in each of the MA first columns and MB×LB memory cells 10B in the block 32B in each of the MB second columns. This allows MA×LA+MB×LB data to be read in parallel.

[0194] FIG. 41(A) is a block diagram showing two blocks and sense amplifiers in the third embodiment, and FIG. 41(B) is a block diagram showing memory cells. As shown in FIG. 41(A), block 32A1 has LA memory cells C11 to C1L. Block 32A2 has LA memory cells C21 to C2L. The columns of block 32A1 have LA bit lines BL11 to BL1L. The columns of block 32A2 have LA bit lines BL21 to BL2L. The LA rows of blocks 32A1 and 32A2 have LA word lines WL1 to WLL. The sense amplifier 36A has sense amplifiers SA11 to SA1L and SA21 to SA2L.

[0195] 41B, a read port P is connected to a storage node Q of a memory cell C via a read unit 16. The read unit 16 is, for example, a read port circuit 15, a PSS, an LPT, or a DPT.

[0196] As shown in FIG. 41A, in block 32A1, bit line BL11 is connected to the read port P of memory cell C11, but is not connected to the other memory cells C12-C1L. Similarly, bit lines BL12 and BL1L are connected to the read ports P of memory cells C12 and C1L, respectively, but are not connected to the other memory cells. In block 32A2, the connection relationship between bit lines BL21-BL2L and memory cells C21-C2L is similar. Word line WL1 is connected to memory cells C11 and C21. Bit lines BL11-BL1L and BL21-BL2L are connected to sense amplifiers SA11-SA1L and SA21-SA2L, respectively.

[0197] As shown in Figures 40, 41A, and 41B, MA x LA bit lines BLA (first bit lines) are provided in the memory region 30A, with LA bit lines BLA provided in each of the MA first columns and connected to the memory cells 10A arranged in the column direction. In each of the nA blocks 32A, each of the LA bit lines BLA (e.g., bit line BL11) is connected to the storage node Q of a memory cell 10A (e.g., C11) provided in one of the LA first rows, and is not connected to the memory cells (e.g., C12 and C1L) provided in the remaining LA first rows. The read port P is connected to one of the complementary pair of storage nodes Q and Q' in the memory cell 10A (storage node Q in Figure 41A). The same applies to the bit lines BLB (second bit lines), memory cells 10B, and blocks 32B in the memory region 30B. The connection of a bit line to a storage node Q also includes the connection of the bit line to the storage node Q via a read section 16 .

[0198] The memory cells 10A and 10B each include a bistable circuit having two inverter circuits. The two inverter circuits are, for example, the inverter circuits described in the first and second embodiments, and may have hysteresis or may not have substantially hysteresis. For example, the memory cells 10A and 10B each include an inverter circuit 3T ０ It may be a 6T-SRAM having two of these.

[0199] The following describes the case where data is read out with eight row addresses in parallel.

[0200] When MA=MB=256, NA=NB=128, nA=nB=32, and LA=LB=4, the row addresses of the top block 32A in memory area 30A are 1-4. The row addresses of the second-lowest block are 9-12. The row addresses of the bottom block are 249-252. The row addresses of the bottom block 32B in memory area 30B are 5-8. The row addresses of the second-lowest block are 13-16. The row addresses of the top block are 253-256.

[0201] When reading data in parallel from memory cells 10A and 10B at row addresses 1-8, decoders 34A and 34B select word line WLA at row addresses 1-4 and word line WLB at row addresses 5-8. Sense amplifiers 36A and 36B read data in parallel from four memory cells 10A in the top block 32A in memory area 30A and four memory cells 10B in the bottom block 32B in memory area 30B. Sense amplifiers 36A and 36B output the read data to logic circuit 38.

[0202] Next, when reading data in parallel from memory cells 10A and 10B at row addresses 9-16, decoders 34A and 34B select word line WLA at row addresses 9-12 and word line WLB at row addresses 13-16. Sense amplifiers 36A and 36B read data in parallel from four memory cells 10A in block 32A second from the top in memory region 30A and four memory cells 10B in block 32B second from the bottom in memory region 30B. Sense amplifiers 36A and 36B output the read data to logic circuit 38. In this way, sense amplifiers 36A and 36B sequentially read data in parallel from memory cells 10A and 10B at row addresses 249-256.

[0203] In this way, data to be processed simultaneously is divided and stored in memory area 30A and memory area 30B, and data is read in parallel from memory area 30A and memory area 30B, thereby, for example, speeding up the processing of a neural network accelerator and significantly reducing the size of the entire memory area. Note that the row address arrangement is an example, and the row addresses can be set as appropriate. The same applies to the following explanation.

[0204] (Simulation 4) A simulation was performed on the normalized cell area relative to the number of parallel connections in the comparative example and the third embodiment.

[0205] (Comparative Examples 3 and 4) FIG. 42 is a block diagram of memory circuits according to comparative examples 3 and 4. As shown in FIG. 42, in memory circuits 110 and 112 according to comparative examples 3 and 4, LA and LB are doubled and nA and nB are halved compared to the third embodiment. LA and LB bit lines are provided in one column. For example, when reading data in 8 parallel rows, in memory area 30A, the top row addresses are 1-8, the second-lowest row addresses are 9-16, and the bottom row addresses are 121-128. In memory area 30B, the bottom row addresses are 129-136, the second-lowest row addresses are 137-144, and the top row address is 249-256.

[0206] When reading data in parallel from memory cells 10A at row addresses 1-8, decoder 34A selects word line WLA at row addresses 1-8. Sense amplifier 36A reads data in parallel from eight memory cells 10A in the top block 32A in memory region 30A. Sense amplifier 36A outputs the read data to logic circuit 38. At this time, decoder 34B does not select word line WLB and does not select memory region 30B, so sense amplifier 36B does not output to logic circuit 38. Therefore, logic circuit 38 performs accelerator processing using only the data in memory region 30A.

[0207] 43A is a block diagram of a portion of a memory circuit according to Comparative Example 3, and FIG. 43B is a block diagram showing memory cells. As shown in FIG. 43A, each row of word lines WL1 to WLL has LA word lines. Each row is provided with LA bit lines BL11 to BL1L (and BL21 to BL2L). Memory cells C11 to C1L (and C21 to C2L) are multi-port, and memory cell C11 is connected to LA word lines WL1 and LA bit lines BL11 to BL1L.

[0208] 43B, the storage node Q of the memory cell C is connected to LA read ports P1 to PL via LA read units 16. Bit lines BL1 to BLL are connected to the read ports P1 to PL, respectively. The LA word lines WL are connected to the LA read units 16, respectively.

[0209] As shown in Figure 43 (A), when reading data from block 32A1, decoder 34A selects a corresponding word line from LA word lines WL1, and sense amplifier 36A reads data from memory cells C11 to C1L in parallel via the corresponding bit lines from LA bit lines BL11 to BL1L.

[0210] The block diagram of the memory circuit of Comparative Example 4 is the same as that of Fig. 42. Memory cells C11 to C1L and C21 to C2L are single-port, the same as that of Fig. 41. When reading data in eight parallel rows, LA=LB=8.

[0211] (Example 6) In Example 6, the memory cells of Example 1 in FIG. 21 are used as memory cells 10A and 10B in the memory circuit of FIG. 40, and Type I 4T Ａ +3T' ０ In Comparative Examples 3 and 4, Type I 4T cells are used in the memory circuit of FIG. Ａ +3T' ０ It uses cells.

[0212] FIG. 44 is a diagram showing the normalized cell area versus the number of parallel connections in Example 6 and Comparative Examples 3 and 4.

[0213] As shown in FIG. 44 , in Comparative Example 3, the normalized cell area becomes very large as the number of parallel connections increases. This is because the number of word lines increases as the number of parallel connections increases, and the number of transistors in memory cells 10A and 10B increases to achieve multi-port configuration. In Comparative Example 4, the normalized cell area is approximately 1 when the number of parallel connections is 4 or less. This is because Comparative Example 4 is single-port, and therefore the number of word lines and the number of transistors in memory cells 10A and 10B do not increase compared to Comparative Example 3. However, when the number of parallel connections exceeds 4, the normalized cell area becomes larger than 1.

[0214] In Example 6, when the number of parallel connections is 8 or less, the normalized cell area is approximately 1. When the number of parallel connections exceeds 8, the normalized cell area becomes larger than 1. In Example 6, the number of bit lines in one row can be reduced to half compared to Comparative Example 4. Therefore, even with the same parallel connection, the normalized cell area can be reduced compared to Comparative Example 4.

[0215] (Variation 1 of Third Embodiment) FIG. 45(A) is a block diagram of a memory circuit according to Variation 1 of the third embodiment, and FIG. 45(B) is a block diagram showing a memory cell. As shown in FIG. 45(B), read ports P and P' are connected to a pair of complementary storage nodes Q and Q' of a memory cell C, respectively, via a read unit 16. As shown in FIG. 45(A), in a memory circuit 103 of the third embodiment, bit lines BL1 to BLL are connected to the read port P of memory cells C1 to CL, respectively, and bit lines BL1' to BLL' are connected to the read port P' of memory cells C1 to CL, respectively. Sense amplifiers SA1 to SAL read data from the pair of complementary read ports P and P' via bit lines BL1 to BLL and BL1' to BLL'. The rest of the configuration is the same as that of the third embodiment.

[0216] (Comparative Examples 5 and 6) Comparative Examples 5 and 6 are examples in which, in Comparative Examples 3 and 4, respectively, data is read from a pair of complementary read ports P and P' via bit lines BL1 to BLL and BL1' to BLL', as in Variation Example 1 of the third embodiment.

[0217] (Modification of Example 6) In a modification of Example 6, the memory circuit of FIG. 40 is provided with the memory cells 10A and 10B, and the Type 0 5T of Comparative Example 1 of FIG. 19 is used. Ａ +5T Ａ In Comparative Examples 5 and 6, Type 0 5T cells are used in the memory circuit of FIG. Ａ +5T Ａ It uses cells.

[0218] 46 is a diagram showing the normalized cell area relative to the number of parallel connections. As shown in FIG. 46, the normalized cell area of ​​Comparative Example 5 is larger than that of Comparative Example 6. In both Comparative Example 6 and Modification 1 of Example 6, the number of parallel connections at which the normalized cell area begins to increase is 4 and 8, respectively, which is the same as in FIG. 44. However, in Comparative Example 6 and Modification 1 of Example 6, when the number of parallel connections exceeds 4 and 8, the normalized cell area becomes suddenly larger than that in FIG. 44. This is because Modification 1 of Example 6 has a larger number of bit lines than Example 6.

[0219] Comparative Example 7 FIG. 47 is a block diagram of a memory circuit according to Comparative Example 7. As shown in FIG. 47, in a memory circuit 112 according to Comparative Example 7, memory areas 30A and 30B are arranged in the row direction. Decoders 34A and 34B are arranged to sandwich the memory areas 30A and 30B. The word line WLA of the memory area 30A and the word line WLB of the memory area 30B are arranged separately. In Comparative Example 7, when the decoder 34A selects the word line WLA of the memory area 30A, the decoder 34B does not select the word line WLB. For example, when reading data at row addresses 1-8, the decoder 34A selects the word line WLA corresponding to row addresses 1-8 in the memory area 30A. The decoder 34B does not select any word line WLA. The sense amplifier 36A reads data in parallel from memory cells 10A corresponding to row addresses 1-8. In this way, when LA=LB=8, there are eight bit lines per column and the number of parallel connections is eight, but the chip area is not smaller than that of Comparative Example 4 and is larger than that of Example 6. Alternatively, when LA=LB=4 as in Example 6, there are four bit lines per column and the number of parallel connections is four, so the number of parallel connections cannot be increased.

[0220] (Variation 2 of Third Embodiment) FIG. 48 is a block diagram of a memory circuit according to Variation 2 of the third embodiment. As shown in FIG. 48, in a memory circuit 104 according to Variation 2 of the third embodiment, memory regions 30A and 30B are arranged in the row direction. The word lines WL of the memory regions 30A and 30B are connected to each other. A decoder 34 selects the word lines WL of the memory regions 30A and 30B. For example, when reading data at row addresses 1-8, the decoder 34 selects the word lines WL corresponding to row addresses 1-4 of the memory region 30A and row addresses 5-8 of the memory region 30B. The sense amplifier 36A reads data in parallel from the memory cells 10A corresponding to row addresses 1-4, and the sense amplifier 36B reads data in parallel from the memory cells 10B corresponding to row addresses 5-8. LA = LB = 4, and there are four bit lines per column. This allows for a smaller chip area than Comparative Examples 4 and 5. However, since many bit lines are connected to one word line WL, the length of the word line WL becomes longer, which results in a deterioration in performance. The other configurations are the same as those of the third embodiment shown in FIG.

[0221] (Variation 3 of Third Embodiment) FIG. 49 is a block diagram of a memory circuit according to Variation 3 of the third embodiment. As shown in FIG. 49, in a memory circuit 105 according to Variation 3 of the third embodiment, a decoder 34 is provided between memory areas 30A and 30B. The decoder 34 can simultaneously select the word lines WLA of memory area 30A and the word lines WLB of memory area 30B. For example, when reading data at row addresses 1-8, the decoder 34A selects the word lines WLA corresponding to row addresses 1-4 of memory area 30A and the word lines WLB corresponding to row addresses 5-8 of memory area 30B. As in Variation 2 of the third embodiment, LA = LB = 4. There are four bit lines per column, which allows for a smaller chip area than in Comparative Examples 4 and 5. In Variation 3 of the third embodiment, the lengths of the word lines WLA and WLB can be shorter than in Variation 2 of the third embodiment. This reduces performance degradation. The memory circuit 102 in FIG. 40 and the memory circuit 105 in FIG. 49 are roughly equivalent in performance and chip area.

[0222] (Description of the Third Embodiment) In Modifications 2 and 3 of the third embodiment, the portion of the logic circuit 38 that processes row addresses 1-4 and the portion of the logic circuit 38 that processes row addresses 5-8 are spatially separated. In the storage circuit 102 of the third embodiment shown in FIG. 40, memory areas 30A and 30B are arranged to sandwich the sense amplifiers 36A, 36B and the logic circuit 38. This allows the portion of the logic circuit 38 that processes row addresses 1-4 and the portion of the logic circuit 38 that processes row addresses 5-8 to be located close to each other. For this reason, the circuit configuration of the third embodiment shown in FIG. 40 may be preferable depending on the configuration of the logic circuit 38.

[0223] (Fourth Modification of Third Embodiment) A fourth modification of the third embodiment is an example in which the memory is divided into four memory regions (sub-arrays). FIG. 50 is a block diagram of a memory circuit according to the fourth modification of the third embodiment. As shown in FIG. 50, the memory circuit 106 according to the fourth modification of the third embodiment includes memory regions 30A to 30D, decoders 34A and 34B, sense amplifiers 36A to 36D, and a logic circuit 38.

[0224] The memory areas 30C and 30D are provided in the row direction of the memory areas 30A and 30B. The memory areas 30C and 30D are provided on either side of the sense amplifiers 36C and 36D.

[0225] The memory region 30C includes NC×MC memory cells 10C arranged in a matrix of NC rows and MC columns. The NC rows are divided into nC blocks 32C, each having LC rows. NC word lines WLC are provided, one for each of the NC rows, and connected to the memory cells 10C arranged in the row direction. MC×LC sense amplifiers 36C are provided.

[0226] The memory region 30D includes ND x MD memory cells 10D arranged in a matrix of ND rows and MD columns. The ND rows are divided into nD blocks 32D, each having LD rows. ND word lines WLD are provided, one for each of the ND rows, and connected to the memory cells 10D arranged in the row direction. MD x LD sense amplifiers 36D are provided.

[0227] The logic circuit 38 processes the data read by the sense amplifiers 36A to 36D in parallel.

[0228] When MA=MB=MC=MD=256, NA=NB=NC=ND=64, nA=nB=nC=nD=16, and LA=LB=LC=LD=4, the row addresses of the top block 32A in memory area 30A are 1-4. The row addresses of the bottom block 32B in memory area 30B are 9-12. The row addresses of the top block 32C in memory area 30C are 5-8. The row addresses of the bottom block 32D in memory area 30D are 13-16. In this way, the row addresses are consecutive in the order of memory areas 30A, 30C, 30B, and 30D.

[0229] When reading data in parallel from memory cells 10A-10D corresponding to row addresses 1-16, decoders 34A and 34B select word lines WLA and WLB corresponding to row addresses 1-16. Sense amplifier 36A reads data in parallel from memory cells 10A corresponding to row addresses 1-4. Sense amplifier 36B reads data in parallel from memory cells 10B corresponding to row addresses 9-12. Sense amplifier 36C reads data in parallel from memory cells 10C corresponding to row addresses 5-8. Sense amplifier 36D reads data in parallel from memory cells 10D corresponding to row addresses 13-16. This allows 16 pieces of data corresponding to row addresses 1-16 to be read in parallel.

[0230] 51 to 54 are diagrams showing modified parallel readout. FIG. 51 is a diagram showing a memory circuit without division of parallel readout. As shown in FIG. 51, in the memory circuit 114, the cell array 35 is divided into two memory regions 30A and 30B. Sense amplifiers 36A, 36B and a logic circuit 38 are provided between the memory regions 30A and 30B. Decoders 34A and 34B are provided in the center of the memory regions 30A and 30B, respectively, in the row direction. The memory regions 30A and 30B each have 128 rows. The number of columns on the right and left sides of the decoders 34A and 34B is 128. The row addresses of the top block 32A in the memory region 30A are 1-4, and the row addresses increase downward in FIG. 51. The row addresses of the bottom block 32B in the memory region 30B are 129-132, and the row addresses increase upward. When data at row addresses 1-4 of memory area 30A is read in parallel, data is not read from memory area 30B. Therefore, although memory areas 30A and 30B are spatially divided, the memory cells that are read in parallel are not divided between memory areas 30A and 30B. Therefore, parallel read is not divided, and the number of parallel reads is four.

[0231] FIG. 52 is a diagram showing a memory circuit with two-division parallel readout. In the memory circuit 107, the cell array 35 is divided into two memory areas 30A and 30B. The row addresses of the top block 32A in memory area 30A are 1-4, and the row addresses of the bottom block 32B in memory area 30B are 5-8. In this way, the row addresses alternate between memory areas 30A and 30B. In memory area 30A, the row addresses increase downward in FIG. 52. In memory area 30B, the row addresses increase upward. Since data at row addresses 1-4 in memory area 30A and data at row addresses 5-8 in memory area 30B are read out in parallel, the number of parallel readouts is 8.

[0232] FIG. 53 is a diagram showing a memory circuit with four-division parallel readout. In the memory circuit 108 of FIG. 53, the cell array 35 is divided into four memory regions 30A to 30D. Sense amplifiers 36A and 36B and a logic circuit 38 are provided between memory regions 30A and 30B, and sense amplifiers 36C and 36D and a logic circuit 38 are provided between memory regions 30C and 30D. Decoders 34A to 34D are provided in the center of the row direction of each of the memory regions 30A to 30D. Each of the memory regions 30A to 30D has 64 rows. The row addresses of the top block 32A in memory region 30A are 1-4, and the row addresses of the bottom block 32B in memory region 30B are 5-8. The row addresses of the top block 32C in memory region 30C are 9-12, and the row addresses of the bottom block 32D in memory region 30D are 13-16. In this way, the row address blocks are consecutive in the order of memory areas 30A to 30D. In memory areas 30A and 30C, the row addresses increase downward. In memory areas 30B and 30D, the row addresses increase upward. Data at row addresses 1-16 in memory areas 30A to 30D are read in parallel, so the parallel number is 16.

[0233] FIG. 54 is a diagram showing a memory circuit with eight-division parallel readout. In the memory circuit 109 of FIG. 54, the cell array 35 is divided into eight memory regions 30A to 30H. Sense amplifiers 36A and 36B and a logic circuit 38 are provided between memory regions 30A and 30B, and sense amplifiers 36C and 36D and a logic circuit 38 are provided between memory regions 30C and 30D. Sense amplifiers 36E and 36F and a logic circuit 38 are provided between memory regions 30E and 30F, and sense amplifiers 36G and 36H and a logic circuit 38 are provided between memory regions 30G and 30H. Decoders 34A to 34H are provided in the center of the row direction of each of the memory regions 30A to 30H. Each of the memory regions 30A to 30H has 32 rows.

[0234] The row addresses of the top block 32A in memory area 30A are 1-4, and the row addresses of the bottom block 32B in memory area 30B are 5-8. The row addresses of the top block 32C in memory area 30C are 9-12, and the row addresses of the bottom block 32D in memory area 30D are 13-16. The row addresses of the top block 32E in memory area 30E are 17-20, and the row addresses of the bottom block 32F in memory area 30F are 21-24. The row addresses of the top block 32G in memory area 30G are 25-28, and the row addresses of the bottom block 32H in memory area 30H are 29-32. The row address blocks are consecutive in the order of memory areas 30A to 30H. In memory areas 30A, 30C, 30E, and 30G, row addresses increase downward in FIG. 54. In the memory areas 30B, 30D, 30F, and 30H, the row addresses increase upward. Since data from row addresses 1 to 32 is read in parallel, the number of parallel reads is 32.

[0235] (Simulation 5) The number of divisions into which the memory area from which data is read in parallel is divided was changed, and the normalized cell area relative to the number of parallels was simulated.

[0236] 55 is a diagram showing the normalized cell area versus the number of parallel connections in Simulation 5. No division corresponds to Comparative Example 4, two-division corresponds to Example 6, and four-division corresponds to Modification 4 of the third embodiment. The memory cells are Type I 4T of Example 1 in FIG. Ａ +3T' ０ Cells were used.

[0237] 55, the maximum number of parallel processes at which the normalized cell area does not increase compared to when the number of parallel processes is 1 is 8 parallel processes for 2 divisions, 16 parallel processes for 4 divisions, and 32 parallel processes for 8 divisions. In this way, when the number of divisions of the memory area to be processed in parallel increases, the cell area does not increase even if the number of parallel processes is increased.

[0238] This section explains how the number of parallel connections can be increased without increasing the width of the cell array by increasing the number of divisions of the memory area. The following explanation is based on an example in which NA to ND = 256 and LA to LD = 4 in the third embodiment and its modified examples. NA to ND and LA to LD can be set as appropriate.

[0239] 51 to 54, increasing the number of divisions increases the column width of cell array 35, but the number of parallel connections can be increased without increasing the row width. When examining the case where the number of parallel connections is set to 32 without division, the wiring area increases, and the occupancy rate of memory cells in cell array 35 is 38%, while the occupancy rate of areas other than memory cells (dead space) is 62%. In contrast, when divided into eight, as in FIG. 54, the occupancy rate of memory cells becomes 100%, and the occupancy rate of areas other than memory cells can be reduced to 0%.

[0240] As explained above, the number of bit lines per column can be reduced for the same number of parallel connections, thereby reducing the cell area. Note that the read circuit may be a circuit other than a sense amplifier.

[0241] Reading data in parallel from a plurality of memory cells means reading data from a plurality of memory cells connected to a plurality of selected word lines after the plurality of word lines are selected and before the selected plurality of word lines are deselected. For example, when data is read from a plurality of memory cells in synchronization with a clock signal, the data may be read from the plurality of memory cells at different times.

[0242] NA and NB may be different from each other, MA and MB may be different from each other, LA and LB may be different from each other, and nA and nB may be different from each other. By making NA and NB equal, MA and MB may be equal, LA and LB may be equal, and nA and nB may be equal, it becomes easier to read data in parallel from the memory areas 30A and 30B. MA and MB are twice the number of NA and NB. MA and MB are twice the number of NA and NB. ｎ n is a number selected from integers equal to or greater than 1. This allows the number of rows, sum, and number of columns to be the same.

[0243] When the sense amplifiers 36A and 36B read data in parallel from LA memory cells 10A in one block 32A and LB memory cells in one block 32B, the decoders 34A and 34B (selection circuits) may select a word line WLA (first word line) connected to the LA memory cells in one block 32A and a word line WLB (second word line) connected to the LB memory cells in one block 32B. This allows the sense amplifiers 36A and 36B to read data in parallel from the LA memory cells and the LB memory cells.

[0244] The sense amplifiers 36A and 36B may be provided between the memory areas 30A and 30B, which allows the word lines to be shortened, thereby suppressing performance degradation.

[0245] The decoder 34 may be provided between MA first columns and between MB second columns, thereby shortening the word lines and suppressing performance degradation.

[0246] 50, 53, and 54 of Modification 4 of the third embodiment, three or more memory regions 30A-30D may be provided for reading data in parallel. Sense amplifiers 36A-36D read data in parallel from LA-LD memory cells in blocks 32A-32D in each of the three or more memory regions 30A-30D. This makes it possible to suppress an increase in cell area even if the number of parallel connections is increased.

[0247] The memory circuit 107 of FIG. 53 includes memory regions 30A and 30B, a set 33A of sense amplifiers 36A and 36B, memory regions 30C and 30D, and a set 33B of sense amplifiers 36C and 36D. The memory circuit 108 of FIG. 54 includes, in addition to sets 33A and 33B, memory regions 30E and 30F, a set 33C of sense amplifiers 36E and 36F, and a set 33D of memory regions 30G and 30H, and sense amplifiers 36G and 36H. Multiple sets 33A-33B (or 33A-33D) are arranged in the column direction along which the bit lines extend. Sense amplifiers 36A-36D (or 36A-36H) read data in parallel from memory cells in blocks 32A-32D (or 32A-32H). This allows the number of parallel blocks to be increased without increasing the row width of the cell array 35, as described with reference to FIGS. 51 through 54. As shown in FIG. 55, the cell area can be reduced for the same number of parallel connections.

[0248] In the third embodiment and its modifications, the memory circuit is described as an SRAM, but the memory circuit may be a VNR-SRAM. The memory circuit may also be a DRAM (Dynamic Random Access Memory) or an MRAM (Magnetoresistive Random Access Memory). In this case, each memory cell has one memory node. Thus, a memory cell may have one or more memory nodes.

[0249] (Fourth Embodiment) In the bistable circuits of the first and second embodiments, in the EMP operation mode where the virtual power supply voltage VVDD is about 0.4 V, the number of transistors can be reduced while maintaining the noise margin. However, in the low voltage retention (ULVR) mode where the virtual power supply voltage VVDD is lowered to VVDD=0.2 V and data can be retained without read or write operations, the noise margin becomes smaller. The inverter circuit 4T in FIG. Ａ In the bistable circuit having the inverter circuits 12A and 12B, the noise margin can be improved in the ULVR mode, but the noise margin becomes smaller in the EMP operation mode.

[0250] The fourth embodiment is an example of an inverter circuit, a bistable circuit, and a memory circuit that can realize EMP operation with double-sided readout (complementary signal type) while improving the noise margin in ULVR mode. The inverter circuit in the fourth embodiment is called Type D to distinguish it from Type A and Type B of the first embodiment and Type C of the second embodiment.

[0251] (Example of Type D Circuit) Figures 56(A) and 56(B) are circuit diagrams of a Type D inverter circuit in the fourth embodiment. "5T" indicates that the number of transistors in the inverter circuit is five. An inverter circuit in which a feedback transistor FBT is connected to a driver transistor DRV is not marked with an "'", but an inverter circuit in which a feedback transistor FBT is connected to a load transistor LD is marked with an "'". The subscript "D" indicates that the inverter circuit is Type D.

[0252] As shown in FIG. 56(A), an inverter circuit 5T Ｄ The inverter circuit 5T in FIG. 7A includes driver transistors DRV1 and DRV2, a load transistor LD, a feedback transistor FBT, and a pass transistor PSS. DRV1, DRV2, and PSS are N-channel FETs. LD and FBT are P-channel FETs. Ａ 7A, the difference is that the gate of the LD is connected to the power supply line 28A. Ａ Therefore, the explanation will be omitted.

[0253] As shown in FIG. 56(B), an inverter circuit 5T' Ｄ The inverter circuit 5T' shown in FIG. 7B includes a driver transistor DRV, load transistors LD1 and LD2, a feedback transistor FBT, and a pass transistor PSS. DRV, FBT, and PSS are N-channel FETs. LD1 and LD2 are P-channel FETs. Ａ 7B, the difference is that the gate of DRV is connected to the ground line 28B. Ａ Therefore, the explanation will be omitted.

[0254] Inverter circuit 5T Ｄ and 5T' Ｄ The inverter circuit 5T switches between an ST (Schmitt trigger) mode and an NI (normal inverter) mode depending on the feedback voltage VFB. In the ST mode, hysteresis occurs in the transfer characteristics, and in the NI mode, hysteresis does not occur substantially in the transfer characteristics. In the EMP operation mode and the ULVR mode, the inverter circuit 5T Ｄ and 5T' Ｄ is the ST mode, and hysteresis occurs in the transfer characteristics.

[0255] (Simulation 6) VVDD=0.2V, inverter circuit 5T Ｄ The transfer characteristics of the inverter circuit 5T were simulated. Ａ and 4T Ａ The transfer characteristics were also simulated.

[0256] 57 is a diagram showing the transfer characteristics of the inverter circuit in Simulation 6. The transfer characteristics when VIN transitions from 0.0 V (low level) to 0.2 V (high level) are shown by L→H, and the transfer characteristics when VIN transitions from 0.2 V to 0.0 V are shown by H→L. The feedback voltage VFB is 0.2 V, which is the ST mode. FBIN is connected to the output of the other inverter that constitutes the bistable circuit.

[0257] As shown in FIG. 57, an inverter circuit 5T Ｄ The hysteresis of the inverter circuit 5T Ａ The hysteresis of the inverter circuit 4T is larger than that of the inverter circuit 4T. Ａ The hysteresis is about the same as that of the inverter circuit 5T. Ｄ The transfer characteristics of the inverter circuit 4T are the same for both L → H and H → L. Ａ It is the same polygon as

[0258] 58 is a circuit diagram of a memory cell according to Example 7. As shown in FIG. 58, inverter circuits 12A and 12B are inverter circuits 5T ＤThe gate of the FBT of the inverter circuit 12A is connected to the output node of the inverter circuit 12B, and the gate of the FBT of the inverter circuit 12B is connected to the output node of the inverter circuit 12A. The FBT is an FET with a channel of a second conductivity type (a conductivity type different from the first conductivity type of the first FET and the second FET). The power supply circuit 28 outputs a virtual power supply voltage VVDD to a power supply line 28A. The other configurations are the same as those of Comparative Example 1 in FIG. 19, and therefore description thereof will be omitted.

[0259] Table 9 shows examples of voltages applied to each line during EMP operation in the seventh embodiment.

[0260]

[0261] In Table 9, the standby, read operation, and write operation are in the EMP operation mode. The power supply circuit 28 supplies 0.4 V as the virtual power supply voltage VVDD. 0.4 V is applied as the feedback voltage VFB. At this time, the inverter circuits 12A and 12B are in the ST mode.

[0262] During standby, the bit lines BL and BL' are at 0.4 V. The WL decoder 25 applies 0 V to the word line WL. The PSS is turned off. As a result, data is held in the storage nodes Q and Q'.

[0263] During a read operation, the precharge circuit 22 precharges the bit lines BL and BL' to 0.4 V. The WL decoder 25 applies 0.4 V to the word line WL, which turns on the PSS. The read circuit 23 reads the data at the storage nodes Q and Q' via the bit lines BL and BL'.

[0264] During a write operation, the WL decoder 25 applies 0.4 V to the word line WL. The PSS is turned on. The write circuit 24 applies the voltage of the data to be written to the bit lines BL and BL'. As a result, the data is written to the storage nodes Q and Q'.

[0265] In ULVR mode, the power supply circuit 28 supplies 0.2 V as the virtual power supply voltage VVDD. 0.2 V is applied as the feedback voltage VFB. At this time, the inverter circuits 12A and 12B are in ST mode. The bit lines BL and BL' are at 0.2 V. The WL decoder 25 applies 0 V to the word line WL. The PSS is turned off. The inverter circuits 12A and 12B have hysteresis in the transfer characteristics, as shown in FIG. 57. This allows data to be held in the storage nodes Q and Q'.

[0266] (Simulation 7) The noise margin was simulated for Comparative Examples 1 and 8 and Examples 1 and 7. In Comparative Example 8, the inverter circuits 12A and 12B were set to 4T. Ａ The voltage conditions in the EMP operation mode are the same as those in Simulation 3. VFB=0.4V, and the inverter circuit 5T Ｄ , 5T Ａ and 4T Ａ is the ST mode.

[0267] Table 10 shows an example of the voltages applied to each line in the ULVR mode.

[0268]

[0269] As shown in Table 10, the voltage applied to each line is 0.2 V or 0.0 V. Inverter circuit 5T Ｄ , 5T Ａ and 3T' ０ The PSS is off, and the inverter circuit 4T Ａ The LPT is off, and VVDD is applied to the gate of the LPT. VFB is 0.2 V, and the inverter circuit 5T Ｄ , 5T Ａ and 4T Ａ is the ST mode.

[0270] The gate length of each FET is 60 nm. Ａ , 4T Ａ and 3T' ０ The gate width of the inverter circuit 5T is the same as that of Table 5. Ｄ 1 is a table showing the gate width W of each FET in

[0271]

[0272] FIG. 59(A) shows the butterfly curve of the read operation in Simulation 7, and FIG. 59(B) shows the butterfly curve of the ULVR mode. ０ +3T ０ 59A and 59B, the butterfly curve of the 6T-SRAM is small, and the noise margin is small in both the EMP operation mode and the ULVR mode.

[0273] As shown in FIG. 59A, in the read operation in the EMP operation mode, Ａ +4T Ａ In Comparative Example 8, the lobe is small. This is because, during a read operation, the LPT is turned on to connect the storage nodes Q and Q' to the bit lines BL and BL', respectively. That is, the LPT functions as a PSS and loses its function as a load transistor LD. Ａ +5T Ａ In the comparative example 1, the lobe on the memory point MP side is larger than that of the 6T-SRAM. This increases the noise margin. Ｄ +5T Ｄ In Example 7, the lobe on the side of the memory point MP is as large as that in Comparative Example 1, and the noise margin is large. Ａ and 5T Ｄ This is because the transfer characteristic has hysteresis and the LD is independent of the PSS.

[0274] As shown in FIG. 59B, in the ULVR mode, the lobe in Comparative Example 1 is larger than that in 6T-SRAM, but cannot be maximized. In Comparative Example 8 and Example 7, the lobe on the memory point MP side is larger than that in Comparative Example 1. This is because, as shown in FIG. Ａ and 5T Ｄ This is because the hysteresis of the transfer characteristic is large and the butterfly curve is angular.

[0275] 60A is a diagram showing QSNM during a read operation in Simulation 7, and FIG. 60B is a diagram showing QSNM in ULVR mode. As shown in FIG. 60A, in a read operation, Comparative Example 8 has a small QSNM. In Example 7, QSNM can be increased to the same extent as in Comparative Example 1 and Example 1.

[0276] 60B, in the ULVR mode, QSNM is small in Example 1. In Example 7, QSNM can be increased to the same extent as in Comparative Example 8, and can be increased more than in Comparative Example 1.

[0277] As described above, the inverter circuit 5T of Type D Ｄ and 5T' Ｄ Now, the fourth FET (5T Ｄ LD and 5T' Ｄ The gate of the second power supply line (5T Ｄ Power supply lines 28A and 5T' Ｄ This connects the inverter circuits 12A and 12B to the inverter circuit 5T. Ｄ and 5T' Ｄ When this is set, it is possible to improve the noise margin in the ULVR mode and realize the EMP operation of double-sided readout (complementary signal type).

[0278] Furthermore, the power supply circuit 28 selects and applies either a first voltage V1 for the EMP operation mode or a second voltage V2 for the ULVR mode as a power supply voltage VVDD-VVGND between the power supply line 28A and the ground line 28B. When the read circuit 23 reads data from at least one of the storage nodes Q and Q', the power supply circuit 28 applies the first voltage V1 as the power supply voltage. When the write circuit 24 writes data to at least one of the storage nodes Q and Q', the power supply circuit 28 applies the first voltage V1 as the power supply voltage. When the power supply circuit 28 applies the second voltage V2 as the power supply voltage, the bistable circuit 14 holds data in the storage nodes Q and Q', the read circuit 23 does not read data from at least one of the storage nodes Q and Q', and the write circuit 24 does not write data to at least one of the storage nodes Q and Q'. This improves the noise margin in both the EMP operation mode and the ULVR mode.

[0279] Whether the power supply circuit 28 applies the first voltage V1 or the second voltage V2, hysteresis occurs in the transfer characteristics of the inverter circuits 12A and 12B. This allows the ULVR to have a very large noise margin. This effect also allows it to operate with EMP.

[0280] The feedback voltage VFB may be a voltage different from the virtual power supply voltage VVDD. VFB may be a voltage that sets the inverter circuits 12A and 12B in ST mode in the EMP operation mode and the ULVR mode. By making VFB the same as VVDD, it is not necessary to generate VFB separately from VVDD. Therefore, it is not necessary to provide a voltage generation circuit.

[0281] 61(A) and 61(B) are circuit diagrams of inverter circuits according to other examples of Type C. "4T" and "5T" indicate that the number of transistors in the inverter circuit is four and five, respectively. The subscript "C" indicates that the inverter circuit is Type C.

[0282] As shown in FIG. 61(A), an inverter circuit 4T Ｃincludes a driver transistor DRV, a load transistor LD, and feedback transistors pFBT and nFBT. DRV and nFBT are N-channel FETs. LD and pFBT are P-channel FETs.

[0283] The source of the pFBT is connected to the intermediate node IM1, the drain of the pFBT is connected to the ground line 28B, and the gate of the pFBT is connected to the output node OUT. The source of the DRV is connected to the intermediate node IM1, the drain of the DRV is connected to the output node OUT, and the gate of the DRV is connected to the input node IN. The source of the LD is connected to the intermediate node IM2, the drain of the LD is connected to the output node OUT, and the gate of the LD is connected to the input node IN. The source of the nFBT is connected to the intermediate node IM2, the drain of the nFBT is connected to the power supply line 28A, and the gate of the nFBT is connected to the output node OUT.

[0284] As shown in FIG. 61(B), an inverter circuit 5T Ｃ comprises a driver transistor DRV, a load transistor LD, feedback transistors pFBT and nFBT, and a pass transistor PSS. DRV, nFBT, and PSS are N-channel FETs. LD and pFBT are P-channel FETs. One of the source and drain of PSS is connected to the output node OUT, the other of the source and drain of PSS is connected to the bit line BL, and the gate of PSS is connected to the word line WL. The other configuration is the same as in Figure 61 (A), so description will be omitted.

[0285] Inverter circuit 4T Ｃ and 5T Ｃ So, Type C inverter circuit 3T Ｃ Since the FBTs in are on both the pull-up side and the pull-down side, the hysteresis spreads to both sides. This increases the hysteresis of the transfer characteristic. Ｃ and 5T Ｃ may also be used.

[0286] In the first, second, and fourth embodiments, an example of VVDD-VVGND in the EMP operation mode has been described as 0.4 V, but VVDD-VVGND is, for example, 0.2 V or more and 0.5 V or less, and is less than 0.4 V. In the ULVR mode, an example of VVDD-VVGND in the ULVR mode has been described as 0.2 V, but VVDD-VVGND is smaller than VVDD-VVGND in the EMP operation mode, and is, for example, about 0.2 V, and is about 0.15 V or more.

[0287] Fifth Embodiment The fifth embodiment and its modifications are examples of a processing circuit having an arithmetic circuit that performs parallel processing and a memory circuit that reads data in parallel. The processing circuits of the fifth embodiment and its modifications are used, for example, as accelerators for a neural network. In the fifth embodiment and its modifications, row addresses are assigned to the cell array 35 of the memory circuit. The row addresses are row physical addresses. The readout circuit reads data in the order of the row addresses. That is, the row addresses are sequentially read out to the readout circuit. At this time, the readout circuit reads data of a predetermined number of consecutive row addresses in parallel. The arithmetic circuit processes the data in the order of the read row addresses. At this time, the arithmetic circuit processes data of a predetermined number of consecutive row addresses in parallel. The sequential data sequentially processed by the arithmetic circuit is stored in the row addresses in the order of the row addresses.

[0288] The cell array 35 is divided into multiple memory regions 30A-30H (i.e., subarrays), and row addresses are sequentially assigned to the multiple memory regions 30A-30H in units of one or more consecutive row addresses, thus changing the spatial address mapping. This reduces the number of bit lines even if the number of rows read in parallel remains the same, making it possible to downsize the processing circuitry compared to when the spatial address mapping is not changed.

[0289] The number of parallel reads of data from the cell array by the read circuit is set to Np. The number of parallel reads of data Np is typically 2. ｎ = 2, 4, 8, 16, 32, etc. (n is an integer of 1 or more). The number of parallel connections Np is 2 ｎThe number of memory areas 30A to 30H (subarrays) included in the cell array 35 is defined as Na. ｎ In this case, there are multiple possible numbers Na, Na = Np, Np / 2, Np / 4, ..., Np / 2 ｎ－１ In this case, the number of bit lines per column, mb, is given by Np / Na = 1, 2, 4, 8, .... When mb = 1, the number Na of memory areas 30A to 30H is Np. Furthermore, when the number of bit lines that can be arranged in one column, mb = 1, 2, 4, 8, ..., is greater than 1, the most effective number Na is Np / mb. For example, when Np = 16 and mb = 8, the number Na of memory areas is 2. When Np = 16 and Np = 4, the number Na of memory areas is 4. The above applies to the case of single-ended readout. Below, an example of a cell array 35 with 256 rows and 256 columns will be described.

[0290] (Comparative Example 1) Comparative Example 1 is an example in which the spatial address mapping is not changed. FIGS. 62A and 62B are block diagrams of a processing circuit according to Comparative Example 1. The decoder is not shown. In the processing circuit 120, the number of parallel operations Np is 2. Row addresses 1 to 128 are assigned to memory area 30A, and row addresses 129 to 256 are assigned to memory area 30B. That is, the first 128 row addresses of the sequential row addresses are assigned to memory area 30A, and the last 128 row addresses are assigned to memory area 30B. The number of consecutive row addresses La, which is the number of consecutive row addresses consecutively assigned to one memory area 30A or 30B, is 128, but the memory areas 30A and 30B are physically separated by the presence of sense amplifiers 36A and 36B and logic circuit 38 between them. However, in the entire memory area consisting of 30A and 30B, the number of consecutive row addresses La can be regarded as substantially 256. In the processing circuit 120, the number Na of memory areas consisting of 30A and 30B is regarded as substantially one.

[0291] The number of parallel read rows Lb, from which data is read in parallel per memory area 30A or 30B, corresponds to LA and LB in the third embodiment and its modifications. The memory area 30A has a plurality of blocks 32A, and the memory area 30B has a plurality of blocks 32B. The number of rows in one block 32A is the number of parallel read rows Lb. The number of rows in one block 32B is the number of parallel read rows Lb. In comparative example 1, the number of parallel read rows Lb is 2. The circuit configurations of the blocks 32A and 32B are the same as those shown in, for example, FIGS. 41A and 41B of the third embodiment. When the number of parallel read rows Lb is 2, the number of bit lines BL (referred to as the number of BLs Mb) in one memory area 30A or 30B is 2×256=512. When blocks 32A and 32B are in complementary readout as shown in Figures 45(A) and 45(B), the number of bit lines is 1024, which is twice as many as in the single-ended case as shown in Figures 41(A) and 41(B). In the following explanation, the single-ended case will be used as an example.

[0292] As shown in Figure 62A, when reading data, the sense amplifier 36A first reads the data of the first two row addresses 1 and 2 in parallel. In Figure 62A, the rows that are read in parallel are cross-hatched. This also applies to the following figures. The logic circuit 38 processes the read data of row addresses 1 and 2 in parallel.

[0293] Next, as shown in FIG. 62(B), sense amplifier 36A reads out data from the next two row addresses, row addresses 3 and 4, in parallel. Logic circuit 38 processes the read data from row addresses 3 and 4 in parallel. Then, data up to row addresses 128 is read out from memory area 30A. Data from row addresses 129 to 256 is read out from memory area 30B. By reading out data from two row addresses in parallel 128 times in this way, processing circuit 120 can process data from 256 row addresses.

[0294] In the processing circuit 120 of comparative example 1, data from two row addresses is read in parallel, which increases the processing speed. However, the number of bit lines BL in one memory area 30A or 30B is 2 × 256 = 512. This increases the width of the cell array 35, and the size of the processing circuit 120.

[0295] (Fifth Embodiment: Example where Np = 2, Na = 2, La = 1, Lb = 1) FIGS. 63A and 63B are block diagrams of a processing circuit according to the fifth embodiment. Similar to FIG. 40 of the third embodiment, memory areas 30A and 30B each have memory cells arranged in a matrix. In the processing circuit 121, the number Na of memory areas 30A and 30B is two, and the number of parallel connections Np is two. The spatial address mapping has been changed from FIGS. 62A and 62B. Odd row addresses, i.e., row addresses 1, 3, 5, 7, to 255, are assigned to memory area 30A. Even row addresses, i.e., row addresses 2, 4, 6, 8, to 256, are assigned to memory area 30B. In other words, data for 256 row addresses is stored alternately in memory areas 30A and 30B for every 128 bits for one row address. The number of consecutive row addresses La is 1. The number of parallel read rows Lb is 1. That is, the number of rows in each of the blocks 32A and 32B is 1. Therefore, the number of BLs Mb is 1×256=256.

[0296] 63A, data is stored in memory areas 30A and 30B. Sense amplifiers 36A and 36B (read circuits) read data from memory areas 30A and 30B, respectively. Logic circuit 38 (arithmetic circuit) performs parallel arithmetic using the data read from memory areas 30A and 30B.

[0297] When reading data, the sense amplifier 36A first reads the first piece of data at row address 1, and the sense amplifier 36B then reads the next piece of data at row address 2. The logic circuit 38 processes the read data at row addresses 1 and 2 in parallel.

[0298] Next, as shown in FIG. 63B, sense amplifier 36A reads out the data at row address 3 in parallel, and sense amplifier 36B reads out the data at row address 4 in parallel. Logic circuit 38 processes the read data at row addresses 3 and 4 in parallel. Then, sense amplifiers 36A and 36B read out data in parallel from one row address in memory area 30A and one row address in memory area 30B. By reading out data from two row addresses in parallel 128 times in this way, processing circuit 121 can process data from 256 row addresses.

[0299] In the processing circuit 121 of the fifth embodiment, the spatial address mapping is changed from that of the processing circuit 120 of the comparative embodiment 1, and row addresses are alternately assigned to the memory areas 30A and 30B. The sense amplifiers 36A and 36B read data in parallel from the memory areas 30A and 30B. As a result, even if the number of parallel connections Np is the same as in the comparative embodiment 1, the number of BLs Mb can be reduced to half that of the processing circuit 120 of the comparative embodiment 1. Therefore, even if the processing speed is approximately the same as in the comparative embodiment 1, the horizontal width of the cell array 35 can be reduced, and the processing circuit 121 can be made smaller.

[0300] (Example of Modification 1 of Fifth Embodiment: Np = 4, Na = 2, La = 1, Lb = 2) Figures 64(A) and 64(B) are block diagrams of a processing circuit according to Modification 1 of the fifth embodiment. In the processing circuit 122, the number Na of memory areas 30A and 30B is 2, and the number of parallel operations Np is 4. The spatial address mapping is the same as that of Figures 63(A) and 63(B) of the fifth embodiment. Therefore, the number of consecutive row addresses La is 1. The number of parallel readout rows Lb is 2. In other words, the number of rows in each of blocks 32A and 32B is 2. Therefore, the number of BLs Mb is 2 x 256 = 512.

[0301] 64A, when reading data, sense amplifier 36A first reads data in parallel from row addresses 1 and 3, and sense amplifier 36B reads data in parallel from row addresses 2 and 4. Logic circuit 38 processes the read data from row addresses 1 to 4 in parallel.

[0302] Next, as shown in FIG. 64B, sense amplifier 36A reads data from row addresses 5 and 7 in parallel, and sense amplifier 36B reads data from row addresses 6 and 8 in parallel. Logic circuit 38 processes the read data from row addresses 5 to 8 in parallel. Then, sense amplifiers 36A and 36B read data in parallel from two row addresses in memory area 30A and two row addresses in memory area 30B. In this way, by reading data from four row addresses in parallel 64 times, processing circuit 122 can process data from 256 row addresses.

[0303] In the processing circuit 122 of Modification 1 of the fifth embodiment, the spatial address mapping is the same as that of the processing circuit 121 of the fifth embodiment, and the number of parallel readout rows Lb is set to 2. This allows the parallel number Np to be set to 4. In this way, in the processing circuit 122 of the fifth embodiment, the number of BLs Mb is set to 512, the same as in Comparative Example 1, and the parallel number Np can be set to 4, which is twice that of Comparative Example 1. This allows the processing speed to be improved with almost no change in the horizontal width compared to the processing circuit 120 of Comparative Example 1.

[0304] (Example of Modification 2 of Fifth Embodiment: Np = 4, Na = 2, La = 2, Lb = 2) Figures 65(A) and 65(B) are block diagrams of a processing circuit according to Modification 2 of the fifth embodiment. In the processing circuit 123, the spatial address mapping differs from that of Modification 1 of the fifth embodiment shown in Figures 64(A) and 64(B). Memory area 30A is assigned two consecutive row addresses, one every two rows, namely row addresses 1-2, 5-6, and up to 254. Memory area 30B is assigned two consecutive row addresses, one every two rows, namely row addresses 3-4, 7-8, and up to 256. In other words, data for 256 row addresses is stored alternately in memory areas 30A and 30B for every two row addresses. The number of consecutive row addresses La is 2. The number of parallel read rows Lb is 2. The number of BLs Mb is 2 x 256 = 512.

[0305] 65A, when reading data, first, sense amplifier 36A reads data in parallel from row addresses 1 and 2, and sense amplifier 36B reads data in parallel from row addresses 3 and 4. Logic circuit 38 processes the read data from row addresses 1 to 4 in parallel.

[0306] Next, as shown in FIG. 65B, sense amplifier 36A reads data from row addresses 5 and 6 in parallel, and sense amplifier 36B reads data from row addresses 7 and 8 in parallel. Logic circuit 38 processes the read data from row addresses 5 to 8 in parallel. Then, sense amplifiers 36A and 36B read data in parallel from two row addresses in memory area 30A and two row addresses in memory area 30B. In this way, by reading data from four row addresses in parallel 64 times, processing circuit 123 can process data from 256 row addresses.

[0307] As in the processing circuit 123 of the second modification of the fifth embodiment, the number of consecutive row addresses La may be set to 2, and every third row address may be alternately assigned to the memory areas 30A and 30B.

[0308] (Example of Modification 3 of Fifth Embodiment: Np = 4, Na = 4, La = 1, Lb = 1) FIGS. 66A and 66B are block diagrams of a processing circuit according to Modification 3 of the fifth embodiment. In the processing circuit 124, the number Na of memory areas 30A to 30D is 4, and the parallel number Np is 4. Memory area 30A is assigned row addresses that are obtained by dividing row addresses 1, 5, ... by 4 with a remainder of 1. Memory area 30B is assigned row addresses that are obtained by dividing row addresses 2, 6, ... by 4 with a remainder of 2. Memory area 30C is assigned row addresses that are obtained by dividing row addresses 3, 7, ... by 4 with a remainder of 3. Memory area 30D is assigned row addresses that are obtained by dividing row addresses 4, 8, ... by 4 with a remainder of 0. In this way, data for 256 row addresses is stored sequentially in memory areas 30A to 30D, one row address at a time. The number of consecutive row addresses La is 1. The number of parallel read rows Lb is 1. That is, the number of rows that each of the blocks 32A to 32D has is 1. The number of BLs Mb is 256.

[0309] 66A, when reading data, sense amplifier 36A reads data at row address 1, sense amplifier 36B reads data at row address 2, sense amplifier 36C reads data at row address 3, and sense amplifier 36D reads data at row address 4 in parallel. Logic circuit 38 processes the read data at row addresses 1 to 4 in parallel.

[0310] 66(B), sense amplifier 36A reads out the data at row address 5, sense amplifier 36B reads out the data at row address 6, sense amplifier 36C reads out the data at row address 7, and sense amplifier 36D reads out the data at row address 8 in parallel. Thereafter, sense amplifiers 36A to 36D read out data in parallel from one row address each in memory areas 30A to 30D. In this way, by reading out data for four row addresses in parallel 64 times, processing circuit 124 can process data for 256 row addresses.

[0311] As in the processing circuit 124 of Modification 3 of the fifth embodiment, row addresses may be assigned sequentially to the memory areas 30A to 30D one by one. This allows the number of BLs Mb to be 256, half that of the processing circuits 122 and 123, even if the number of parallel connections Np is set to 4, the same as in Modifications 1 and 2 of the fifth embodiment. This allows the horizontal width of the cell array 35 to be reduced.

[0312] (Example of Modification 4 of Fifth Embodiment: Np = 8, Na = 2, La = 1, Lb = 4) Figure 67 is a block diagram of a processing circuit according to Modification 4 of the fifth embodiment. In the processing circuit 125, the number Na of memory areas 30A and 30B is 2, and the parallel number Np is 8. The spatial address mapping is the same as that of Figures 63(A) and 63(B) of the fifth embodiment. Therefore, the number of consecutive row addresses La is 1. The number of parallel read rows Lb is 4. In other words, the number of rows in each of blocks 32A and 32B is 4. Therefore, the number of BLs Mb is 4 x 256 = 1024.

[0313] As shown in FIG. 67, when reading data, sense amplifier 36A reads data from row addresses 1, 3, 5, and 7 in parallel, and sense amplifier 36B reads data from row addresses 2, 4, 6, and 8 in parallel. Logic circuit 38 processes the read data from row addresses 1 to 8 in parallel. Next, sense amplifier 36A reads data from row addresses 9, 11, 13, and 15 in parallel, and sense amplifier 36B reads data from row addresses 10, 12, 14, and 16 in parallel. Logic circuit 38 processes the read data from row addresses 9 to 16 in parallel. Then, sense amplifiers 36A and 36B read data in parallel from four row addresses each in memory areas 30A and 30B. In this way, by reading data for eight row addresses 32 times in parallel, processing circuit 125 can process data for 256 row addresses.

[0314] In the processing circuit 125 of the fourth modification of the fifth embodiment, the spatial address mapping is the same as that of the processing circuit 122 of the fifth embodiment, and the number of parallel readout rows Lb is set to 4. This allows the number of parallel operations Np to be 8. In this way, in the processing circuit 125 of the fourth modification of the fifth embodiment, the number of parallel operations Np can be set to four times that of the processing circuit 121 of the third embodiment. This allows the processing speed to be improved compared to the processing circuit 121 of the third embodiment.

[0315] (Example of Modification 5 of Fifth Embodiment: Np = 8, Na = 2, La = 4, Lb = 4) Figure 68 is a block diagram of a processing circuit according to Modification 5 of the fifth embodiment. In the processing circuit 126, the spatial address mapping differs from that of Modification 4 of the fifth embodiment shown in Figure 67. Memory area 30A is assigned four consecutive row addresses, with row addresses 1 to 4, 9 to 12, etc., every four rows. Memory area 30B is assigned four consecutive row addresses, with row addresses 5 to 8, 13 to 16, etc., every four rows. In other words, data for 256 row addresses is stored alternately in memory areas 30A and 30B every four row addresses. The number of consecutive row addresses, La, is 4. The number of parallel readout rows, Lb, is 4. The number of BLs, Mb, is 4 x 256 = 1024.

[0316] As shown in FIG. 68, when reading data, sense amplifier 36A reads data from row addresses 1 to 4 in parallel, and sense amplifier 36B reads data from row addresses 5 to 8 in parallel. Logic circuit 38 processes the read data from row addresses 1 to 8 in parallel. Next, sense amplifier 36A reads data from row addresses 9 to 12 in parallel, and sense amplifier 36B reads data from row addresses 13 to 16 in parallel. Logic circuit 38 processes the read data from row addresses 9 to 16 in parallel. Then, sense amplifiers 36A and 36B read data in parallel from four row addresses in memory area 30A and four row addresses in memory area 30B. In this way, by reading data for eight row addresses in parallel 32 times, processing circuit 126 can process data for 256 row addresses.

[0317] As in the processing circuit 126 of the fifth modified example of the fifth embodiment, four consecutive row addresses may be alternately assigned to the memory areas 30A and 30B every four row addresses.

[0318] (Example of Modification 6 of Fifth Embodiment: Np = 8, Na = 4, La = 1, Lb = 2) Figure 69 is a block diagram of a processing circuit according to Modification 6 of the fifth embodiment. In the processing circuit 127, the number Na of memory areas 30A to 30D is 4, and the number of parallel operations Np is 8. The spatial address mapping is the same as that shown in Figures 66(A) and 66(B) of Modification 3 of the fifth embodiment. Therefore, the number of consecutive row addresses La is 1. The number of parallel readout rows Lb is 2. In other words, the number of rows in each of blocks 32A and 32B is 2. Therefore, the number of BLs Mb is 2 x 256 = 512.

[0319] As shown in FIG. 69, when reading data, sense amplifier 36A reads data from row addresses 1 and 5 in parallel, sense amplifier 36B reads data from row addresses 2 and 6, sense amplifier 36C reads data from row addresses 3 and 7, and sense amplifier 36D reads data from row addresses 4 and 8. Logic circuit 38 processes the read data from row addresses 1 to 8 in parallel. Next, sense amplifier 36A reads data from row addresses 9 and 13 in parallel, sense amplifier 36B reads data from row addresses 10 and 14 in parallel, sense amplifier 36C reads data from row addresses 11 and 15 in parallel, and sense amplifier 36D reads data from row addresses 12 and 16 in parallel. Logic circuit 38 processes the read data from row addresses 9 to 16 in parallel. Then, sense amplifiers 36A to 36D read data in parallel from two row addresses each in memory areas 30A to 30D. In this way, by reading out data for eight row addresses 32 times in parallel, the processing circuit 125 can process data for 256 row addresses.

[0320] In the processing circuit 127 of Modification 6 of the fifth embodiment, the spatial address mapping is the same as that of the processing circuit 124 of Modification 3 of the fifth embodiment, and the number of parallel readout rows Lb is set to 2. This allows the parallel number Np to be 8. In this way, in the processing circuit 127 of Modification 6 of the fifth embodiment, the parallel number Np can be doubled compared to that of the processing circuit 124 of Modification 3 of the third embodiment. This allows the processing speed to be improved compared to that of the processing circuit 124 of Modification 3 of the third embodiment.

[0321] (Example of Modification 7 of Fifth Embodiment: Np=8, Na=4, La=2, Lb=2) FIG. 70 is a block diagram of a processing circuit according to Modification 7 of the fifth embodiment. In the processing circuit 128, the spatial address mapping differs from that shown in FIG. 69 for Modification 6 of the fifth embodiment. Memory area 30A is assigned two consecutive row addresses every six rows, i.e., row addresses 1-2, 9-10, etc. Memory area 30B is assigned two consecutive row addresses every six rows, i.e., row addresses 3-4, 11-12, etc. Memory area 30C is assigned two consecutive row addresses every six rows, i.e., row addresses 5-6, 13-14, etc. Memory area 30D is assigned two consecutive row addresses every six rows, i.e., row addresses 7-8, 15-16, etc. In other words, data for 256 row addresses is stored in memory areas 30A-30D in order, every two row addresses. The number of consecutive row addresses La is 2. The number of parallel readout rows Lb is 2. The number of BLs Mb is 2×256=512.

[0322] As shown in FIG. 70, when reading data, sense amplifier 36A reads data from row addresses 1 and 2, sense amplifier 36B reads data from row addresses 3 and 4, sense amplifier 36C reads data from row addresses 5 and 6, and sense amplifier 36D reads data from row addresses 7 and 8 in parallel. Logic circuit 38 processes the read data from row addresses 1 to 8 in parallel. Next, sense amplifier 36A reads data from row addresses 9 and 10, sense amplifier 36B reads data from row addresses 11 and 12, sense amplifier 36C reads data from row addresses 13 and 14, and sense amplifier 36D reads data from row addresses 15 and 16 in parallel. Logic circuit 38 processes the read data from row addresses 9 to 16 in parallel. Then, sense amplifiers 36A to 36D read data in parallel from two row addresses each in memory areas 30A to 30D. In this way, by reading out data for eight row addresses 32 times in parallel, the processing circuit 128 can process data for 256 row addresses.

[0323] As in the processing circuit 128 of the seventh modification of the fifth embodiment, two consecutive row addresses may be assigned to the memory areas 30A to 30D in order.

[0324] (Example of Modification 8 of Fifth Embodiment: Np = 8, Na = 8, La = 1, Lb = 1) FIG. 71 is a block diagram of a processing circuit according to Modification 8 of the fifth embodiment. In the processing circuit 129, the number Na of memory areas 30A to 30H is 8, and the parallel number Np is 8. Memory area 30A is assigned row addresses that are obtained by dividing row addresses 1, 9, ... by 8 with a remainder of 1. Memory area 30B is assigned row addresses that are obtained by dividing row addresses 2, 10, ... by 8 with a remainder of 2. Memory area 30C is assigned row addresses that are obtained by dividing row addresses 3, 11, ... by 8 with a remainder of 3. Memory area 30D is assigned row addresses that are obtained by dividing row addresses 4, 12, ... by 8 with a remainder of 4. Memory area 30E is assigned row addresses that are obtained by dividing row addresses 5, 13, ... by 8 with a remainder of 5. Memory area 30F is assigned row addresses 6, 14, ..., with a remainder of 6 when divided by 8. Memory area 30G is assigned row addresses 7, 15, ..., with a remainder of 7 when divided by 8. Memory area 30G is assigned row addresses 8, 16, ..., with a remainder of 0 when divided by 8. In this way, data for 256 row addresses is stored sequentially in memory areas 30A to 30H, one row address at a time. The number of consecutive row addresses La is 1. The number of parallel read rows Lb is 1. In other words, each of blocks 32A to 32D has one row. The number of bit lines BL Mb is 256.

[0325] As shown in FIG. 71, when reading data, sense amplifiers 36A-36H read data from row addresses 1-8 in parallel, respectively. Logic circuit 38 processes the read data from row addresses 1-8 in parallel. Next, sense amplifiers 36A-36H read row addresses 9-16 in parallel, respectively. After that, sense amplifiers 36A-36H read data in parallel from one row address in each of memory areas 30A-30H. In this way, by reading data for eight row addresses in parallel 32 times, processing circuit 129 can process data for 256 row addresses.

[0326] As in the processing circuit 129 of the eighth modification of the fifth embodiment, row addresses may be assigned to the memory areas 30A to 30H one by one in order. This allows the number of BLs Mb to be 256 even if the number of parallel connections Np is 8, the same as in the fourth to seventh modifications of the fifth embodiment. This allows the horizontal width of the cell array 35 to be reduced.

[0327] (Summary of the Fifth Embodiment and its Modifications) The size of the cell array 35 is Lm rows x Mm columns. The number of parallel connections Np is, for example, 2 when n0 is a number selected from integers equal to or greater than 1. ｎ０ The number Na of memory areas 30A to 30H is, for example, Na=Np / 2, where n1 is an integer selected from 0 to n0-1. ｎ１ Note that Lm>Na. In this case, the number of parallel readout rows Lb is Np / Na. In the case of single-ended readout, the number of BLs Mb is Mb=Lb×Mm. Furthermore, the number of consecutive row addresses La is a number selected from integers equal to or greater than 1 and equal to or less than Lb.

[0328] Table 12 shows the number Na of memory areas 30A to 30H, the number Lb of parallel read rows, the number Mb of BLs, and Mb when Mm = 256 when the parallel number Np is 8 and 32 when the spatial address mapping is not changed as in Comparative Example 1. When the spatial address mapping is not changed, the number Na of memory areas consisting of 30A and 30B is substantially 1, as in the processing circuit 120 of Figures 62(A) and 62(B).

[0329]

[0330] As shown in Table 12, when the parallel number Np is set to 8, the parallel readout row number Lb is 8. Therefore, the BL number Mb is 8 × Mm. When Mm is 256, the BL number Mb is 2048. When the parallel number Np is set to 32, the parallel readout row number Lb is 32. Therefore, the BL number Mb is 32 × Mm. When Mm is 256, the BL number Mb is 8192.

[0331] Table 13 shows the number Na of memory areas 30A to 30H, the number Lb of parallel read rows, the number Mb of BLs, and Mb when Mm = 256 when the parallel number Np is 8 and 32 when the spatial address mapping is changed as in the fifth embodiment and its modified examples.

[0332]

[0333] As shown in Table 13, when the parallel number Np is set to 8, the number of memory areas Na can be set to 8, 4, and 2, and the number of parallel read rows Lb can be set to 1, 2, and 4, respectively, thereby making the number of BLs Mb Mm, 2×Mm, and 4×Mb. When the parallel number Np is set to 32, the number of memory areas Na can be set to 32, 16, 8, 4, and 2, and the number of parallel read rows Lb can be set to 1, 2, 4, 8, and 16, respectively, thereby making the number of BLs Mb Mm, 2×Mm, 4×Mm, 8×Mm, and 16×Mm. In this way, by changing the spatial address mapping, the number of BLs Mb can be reduced even with the parallel number Np remaining the same as in Table 12, and the horizontal width can be reduced.

[0334] By setting the number of parallel readout rows Lb to 1, the number of BLs Mb can be minimized to Mm. However, the number of memory areas Na increases, which results in larger peripheral circuits. By setting the number of parallel readout rows Lb to 2 or more, the number of memory areas Na can be reduced, which results in smaller peripheral circuits. However, the number of BLs Mb increases. In this way, the number of parallel readout rows Lb and the number of memory areas Na can be appropriately selected depending on the purpose.

[0335] According to the fifth embodiment and its modifications, one or more consecutive row addresses are assigned to the memory regions 30A-30H in order so that one or more consecutive row addresses are assigned to each of the memory regions 30A-30H among the row addresses (i.e., row physical addresses) sequentially read by the sense amplifiers 36A-36H (readout circuits). The sense amplifiers 36A-36H read data in parallel from one or more (i.e., La) consecutive row addresses in the memory regions 30A-30H. This reduces the number of bit lines per memory region 30A-30H, thereby enabling the processing circuit to be miniaturized.

[0336] Sixth Embodiment The sixth embodiment is an example using an inverter circuit having two driver transistors DRV1 and DRV2 and two load transistors LD1 and LD2.

[0337] (Type I) (Comparative Example 9) Fig. 72 is a circuit diagram of a memory cell according to Comparative Example 9. As shown in Fig. 72, the inverter circuits 12A and 12B each include driver transistors DRV1 and DRV2, load transistors LD1 and LD2, feedback transistors FBT1 and FBT2, and a pass transistor PSS. Each of the inverter circuits 12A and 12B is Type A, and includes an inverter circuit 7T having seven transistors. Ａ Inverter circuit 7T Ａ is the inverter circuit 5T of FIG. Ａ In comparison, there are two load transistors LD1 and LD2 and two feedback transistors FBT1 and FBT2.

[0338] DRV1, DRV2, FBT2, and PSS have N-channels (channels of the first conductivity type). LD1, LD2, and FBT1 have P-channels (channels of the second conductivity type). The source, drain, and gate of DRV1 (first FET) are connected to the ground line 28B (first power supply line), the intermediate node IM1 (first intermediate node), and the input node IN, respectively. The source, drain, and gate of DRV2 (second FET) are connected to the intermediate node IM1, the output node OUT, and the input node IN, respectively. One of the source and drain, the other of the source and drain, and the gate of FBT1 (third FET) are connected to the intermediate node IM1, the feedback line FB1, and the output node OUT of the corresponding inverter circuit 12A or 12B, respectively.

[0339] The source, drain, and gate of LD2 (fourth FET) are connected to the intermediate node IM2 (second intermediate node), the output node OUT, and the input node IN, respectively. The source, drain, and gate of LD1 (fifth FET) are connected to the power supply line 28A (second power supply line), the intermediate node IM2, and the input node IN, respectively. The source of LD2 is connected to the power supply line 28A via LD1. One of the source and drain, the other of the source and drain, and the gate of FBT2 are connected to the intermediate node IM2, the feedback line FB2, and the output node OUT of the other inverter circuit 12A or 12B, respectively. One of the source and drain, the other of the source and drain, and the gate of PSS are connected to the bit line BL or BL', the output node OUT, and the word line WL, respectively.

[0340] By applying appropriate voltages to the feedback lines FB1 and FB2, the inverter circuits 12A and 12B have hysteresis in their transfer characteristics. The gates of FBT1 and FBT2 are connected to the output nodes OUT of the other inverter circuits 12A and 12B, and are Type A.

[0341] The memory cell 10 is a symmetrical Type 0. The gates of the PSSs of the inverter circuits 12A and 12B are connected to the word line WL, and the storage nodes Q and Q' are connected to the bit lines BL and BL', respectively, in both write and read operations. Therefore, the write and read methods are (C, C). The number of transistors is 14.

[0342] 73 is a circuit diagram of a memory cell according to Example 8. As shown in FIG. 73, an inverter circuit 12A is an inverter circuit 7T Ａ The inverter circuit 12B has a hysteresis in the transfer characteristic. ０and the transfer characteristics have substantially no hysteresis. The inverter circuit 12A is Type A, and the memory cell 10 is Type I. The gate of the PSS of the inverter circuit 12A is connected to the write word line WWL, and the gate of the PSS of the inverter circuit 12B is connected to the word line WL. The write method and read method are (C, S). The number of transistors is 10. The other configurations are the same as those of Example 2 and Comparative Example 9, so description thereof will be omitted.

[0343] 74 is a circuit diagram of a memory cell according to Example 9. As shown in FIG. 74, each of the inverter circuits 12A and 12B does not have an FBT2, is a Type A inverter circuit 6T having six transistors. Ａ The memory cell 10 is Type 0. The write method and read method are (C, C). The number of transistors is 12. The other configurations are the same as those of Comparative Example 9, and therefore description thereof will be omitted.

[0344] 75 is a circuit diagram of a memory cell according to Example 10. As shown in FIG. 75, an inverter circuit 12A includes an inverter circuit 6T Ａ The memory cell 10 is Type I. The write and read methods are (C, S). The number of transistors is nine. The other configurations are the same as those in Example 9, and therefore a description thereof will be omitted.

[0345] (Simulation 8) The noise margin and leakage power in a read operation were simulated for symmetrical memory cells, Comparative Example 1 in FIG. 19, Example 9 in FIG. 74, and Comparative Example 9 in FIG. 72, and asymmetrical memory cells, Example 2 in FIG. 24, Example 10 in FIG. 75, and Example 8 in FIG. 73. The FET was a FinFET with one fin. The low level was 0 V, the high level was 0.3 V, and the word line was not underdriven.

[0346] FIG. 76 is a diagram showing QSNM during a read operation in Simulation 8. The figure shows the QSNM of FS, which has the smallest noise margin among TT, FF, SS, FS, and SF. As shown in FIG. Ａ, 6T Ａ and 7T Ａ In both cases, the asymmetric memory cell has improved QSNM compared to the symmetric memory cell. Ａ Example 10 is 5T Ａ and 7T Ａ The QSNM is improved compared to Examples 2 and 8.

[0347] 77 is a diagram showing the normalized leakage power in Simulation 8. The normalized leakage power is normalized by setting the leakage power of Comparative Example 1 to 1. As shown in FIG. Ａ , 6T Ａ and 7T Ａ In any case, the asymmetric memory cell can reduce leakage power compared to the symmetric memory cell. Ａ Example 10 is 5T Ａ and 7T Ａ The leakage power can be reduced compared to the second and eighth embodiments.

[0348] (Type II) (Modification 1 of Example 8) Fig. 78 is a circuit diagram of a memory cell according to Modification 1 of Example 8. As shown in Fig. 78, in an inverter circuit 12A, FBT1 is an N-channel FET and FBT2 is a P-channel FET. The gates of FBT1 and FBT2 are connected to the output node OUT of the inverter circuit 12A, and the gates of the inverter circuit 7T of Type B are connected to the output node OUT of the inverter circuit 12A. Ｂ The memory cell 10 is Type II. The write and read methods are (C, S). The number of transistors is 10. The other configurations are the same as those of the eighth embodiment, and therefore, description thereof will be omitted.

[0349] (Modification 1 of Example 9) FIG. 79 is a circuit diagram of a memory cell according to a modification of Example 9. As shown in FIG. 79, each of the inverter circuits 12A and 12B is an inverter circuit 6T that does not have an FBT2. Ｂ The memory cell 10 is Type 0. The write and read methods are (C, C). The number of transistors is 12. The other configurations are the same as those of the ninth embodiment, and therefore a description thereof will be omitted.

[0350] (Modification 1 of Example 10) Fig. 80 is a circuit diagram of a memory cell according to a modification of Example 10. As shown in Fig. 80, an inverter circuit 12A includes an inverter circuit 6T Ｂ The memory cell 10 is Type II. The write and read methods are (C, S). The number of transistors is 9. The other configurations are the same as those of the tenth embodiment, and therefore, description thereof will be omitted.

[0351] (Simulation 9) As a symmetrical memory cell, Comparative Example 1, 5T of FIG. Ｂ +5T Ｂ , Modification 1 of Example 9 in FIG. 79, 7T Ｂ +7T Ｂ 26, Modification 1 of Example 10 of FIG. 80, and Modification 1 of Example 8 of FIG. 78 as asymmetric memory cells, the noise margin and leakage power in the read operation were simulated. The simulation conditions were the same as those in Simulation 8.

[0352] 81 is a diagram showing QSNM during a read operation in Simulation 9. The figure shows the QSNM of FS, which has the smallest noise margin among TT, FF, SS, FS, and SF. As shown in FIG. Ｂ , 6T Ｂ and 7T Ｂ In either case, the asymmetric memory cell has the same or slightly improved QSNM compared to the symmetric memory cell.

[0353] FIG. 82 is a diagram showing the normalized leakage power in Simulation 9. As shown in FIG. Ｂ , 6T Ｂ and 7T Ｂ In either case, the asymmetric memory cell can reduce leakage power compared to the symmetric memory cell. Ｂ The first modification of the tenth embodiment is 5T Ｂ and 7T Ｂ The leakage power can be reduced compared to the second embodiment and the first modification of the eighth embodiment.

[0354] As described above, in both the Type I and Type II memory cells, the 7T Ａ , 7T Ｂ , 6T Ａ and 6T Ｂ By using the 7T type in the memory cell as in the eighth and tenth embodiments, the leakage power can be reduced compared to the symmetrical memory cell. Ａ and 6T Ａ By using the 6T to form an asymmetric memory cell, the noise margin can be improved and the leakage power can be reduced compared to a symmetric memory cell. Ａ and 6T Ｂ By using Ａ , 5T Ｂ , 7T Ａ and 7T Ｂ The leakage power can be reduced compared to the conventional method.

[0355] As described above, according to the sixth embodiment, in the memory cells of Type I and Type II, the inverter circuit 12A Ａ , 7T Ｂ , 6T Ａ and 6T Ｂ LD1, LD2, DRV2, and DRV1 are connected in series between the power supply line 28A and the ground line 28B.

[0356] The inverter circuit 12A is the inverter circuit 7T Ａ and 7T Ｂ 76 and 77, and the 7T in FIG. Ｂ +7T Ｂ As can be seen from the comparison between the first modification of the eighth embodiment and the second modification, by using asymmetric memory cells, it is possible to improve the noise margin and reduce the leakage power compared to symmetric memory cells.

[0357] The inverter circuit 12A is an inverter circuit 6T Ａ and 6T Ｂ75 and 76 , and a comparison between Example 3 and Modification 1 of Example 8 and Modification 1 of Example 10 in FIGS. 81 and 82 , the noise margin can be improved the most and the leakage power can be reduced the most among asymmetric memory cells.

[0358] Also, as in the ninth embodiment and its modified example 1, the inverter circuit 6T Ａ and 6T Ｂ may be used for both the inverter circuits 12A and 12B of the symmetrical memory cells. This allows the comparison between Comparative Example 1 and Comparative Example 9 and Example 9 in FIG. 77, and the comparison between the 5T Ｂ +5T Ｂ and 7T Ｂ +7T Ｂ As can be seen from the comparison between this and the first modification of the ninth embodiment, among the symmetrical memory cells, the leakage power can be reduced most.

[0359] In the ninth embodiment and its variant 1 and the tenth embodiment and its variant 1, examples have been described in which the inverter circuits 12A and 12B have FBT1 but do not have FBT2, but the inverter circuits 12A and 12B may have FBT2 but not FBT1.

[0360] Seventh Embodiment The seventh embodiment is an example of a read port circuit such as the read port circuit 15 in the fifth embodiment shown in FIG. 32 and the reading unit 16 in FIG. 41(B).

[0361] Comparative Example 10 Comparative Example 10 is the read port circuit 15 in the fifth embodiment shown in FIG.

[0362] (Comparative Example 11) FIG. 83A is a circuit diagram of a read port circuit according to Comparative Example 11. As shown in FIG. 83A, the read port circuit of Comparative Example 11 includes read port transistors RP1 to RP3, which are N-channel FETs, and a read port transistor RP4, which is a P-channel FET. The source, drain, and gate of RP1 are connected to the ground line 28B, node N2, and storage node Q, respectively. The source, drain, and gate of RP3 are connected to node N2, node N1, and read word line RWL, respectively. The source, drain, and gate of RP4 are connected to the power supply line 28A, node N1, and storage node Q, respectively. One of the source and drain, the other of the source and drain, and the gate of RP2 are connected to node N1, read bit line RBL, and read word line RWL, respectively.

[0363] (Comparative Example 12) FIG. 83B is a circuit diagram of a read port circuit according to Comparative Example 12. As shown in FIG. 83B, the read port circuit of Comparative Example 12 includes read port transistors RP1, RP2, and RP3', which are N-channel FETs, and a read port transistor RP4', which is a P-channel FET. The source, drain, and gate of RP3' are connected to the ground line 28B, node N4, and read word line RWL, respectively. The source, drain, and gate of RP1 are connected to node N4, node N3, and storage node Q, respectively. The source, drain, and gate of RP4' are connected to the power supply line 28A, node N3, and read word line RWL, respectively. One of the source and drain, the other of the source and drain, and the gate of RP2 are connected to node N3, read bit line RBL, and read word line RWL, respectively.

[0364] Example 11 FIG. 83C is a circuit diagram of a read port circuit according to Example 11. As shown in FIG. 83C, the read port circuit of Example 11 includes read port transistors RP1 to RP3, which are N-channel (first conductivity type channel) FETs, and read port transistors RP4 and RP5, which are P-channel (second conductivity type channel) FETs. The source, drain, and gate of RP1 (first FET) are connected to the ground line 28B (first power supply line), node N2 (first intermediate node), and storage node Q, respectively. The source, drain, and gate of RP3 (third FET) are connected to node N2, node N1 (second intermediate node), and read word line RWL, respectively. The source, drain, and gate of RP4 (second FET) are connected to the power supply line 28A (second power supply line), node N1, and storage node Q, respectively. One end, the other end, and the gate of the transfer gate TG are connected to the node N1, the read bit line RBL, and the read word line RWL, respectively. The transfer gate TG includes RP2 and RP5. One of the source and drain of RP2 and RP5, and the other of the source and drain, are connected to the node N1 and the read bit line RBL, respectively. The gates of RP2 and RP5 are connected to the read word lines RWL and RWLB, respectively. The signal on the read word line RWLB is the complementary signal of the read word line RWL.

[0365] (Simulation 10) Inverter circuit 3T ０The effects of leakage current were simulated when the read port circuits of Comparative Examples 10 to 12 and Example 11 were used with memory cells of a 6T-SRAM using a 6T-SRAM. It was assumed that 128 memory cells were provided in one column, and that an inverter circuit was connected to the read bit line RBL as a read circuit. The read bit line RBL was precharged to a high level. The storage node Q to which the read port circuit of one selected memory cell out of the 128 memory cells was connected was assumed to be at a low level. The storage nodes Q of the 127 unselected memory cells were assumed to be at a high level. This condition represents the worst case scenario in which the most leakage current flows through the read port circuit. The high level was set to 0.45 V, and the low level was set to 0 V. The temperature was set to 85°C.

[0366] FIG. 84 is a diagram showing voltages over time in simulation 10. Voltage VRWL indicates the voltage of the read word line RWL connected to the selected memory cell. Voltage VRBL indicates the voltage of the read bit line RBL. Voltage VOUT indicates the output voltage of the read circuit. As shown in FIG. 84, between times 0 ns and 10 ns, voltage VRWL becomes 0.45 V. The voltage of the read word line RWL connected to the unselected memory cell is 0 V. The storage node Q of the selected memory cell is at a low level (0 V). Even if voltage VRWL becomes a high level (0.45 V), voltage VRBL maintains a high level (0.45 V) and voltage VOUT maintains a low level (0 V), which is normal operation.

[0367] In Comparative Example 10, when the voltage VRWL becomes 0.45 V, the voltage VRBL drops, and the voltage VOUT becomes 0.45 V. This results in a read error. Explaining this with reference to FIG. 15 , in the 127 unselected memory cells 10, the storage node Q is at a high level, PR1 is on, and the read word line RWL is at a low level, and RP2 is off. Due to the leakage current of PR2, a current flows from the read bit line RBL to the ground line 28B, and the voltage VRBL of the read bit line RBL drops.

[0368] In Comparative Example 11 and Example 11, the drop in voltage VRBL is suppressed when voltage VRWL is 0.45 V, and voltage VOUT is maintained at 0 V. As shown in Figures 82A and 82C, two FETs, RP2 and RP3, are stacked between read word line RWL and ground line 28B. Therefore, in an unselected memory cell, even if storage node Q is at a high level, PR1 is on, and read word line RWL is at a low level, leakage current from read bit line RBL to ground line 28B is reduced compared to Comparative Example 10.

[0369] In Example 11, the drop in voltage VRBL is smaller than in Comparative Example 11. In Figures 82(A) and 82(C), in the selected memory cell, storage node Q is at a low level and PR4 is turned on. In Example 11, a transfer gate TG is formed between node N1 and read bit line RBL, and the charging effect from power supply line 28A to read bit line RBL is greater than in Comparative Example 11. For this reason, the drop in voltage VRBL is smaller in Example 11.

[0370] 82B, in an unselected memory cell, even if storage node Q is at a high level and RP1 is on, read word line RWL is at a low level, RP3' is off, RP4' is on, node N3 is at a high level, and no leakage current flows between read bit line RBL at a high level and node N3 at a high level.

[0371] (Simulation 11) In Figures 40 to 41(B) of the third embodiment, it is assumed that the number of read bit lines RBL in block 32 is 16, that the 16 read bit lines RBL overlap the memory cells in a plan view, that seven of the read bit lines RBL are provided in the second wiring layer, and that nine of the read bit lines RBL are provided in the fourth wiring layer. It is assumed that 128 memory cells are provided in one column, and that eight memory cells are connected to one read bit line RBL. It is assumed that all read bit lines RBL are precharged to a high level, and then data is read in parallel from the 16 memory cells so that adjacent read bit lines RBL alternately go high and low. This allows the simulation of the effect of crosstalk between adjacent read bit lines RBL. The parasitic capacitance between adjacent read bit lines RBL is set to 10 fF. The memory cell configuration is the same as in Simulation 10.

[0372] 85 is a diagram showing voltages over time in Simulation 11. The voltages VRBL and VOUT represent the voltages of the multiple read bit lines RBL that read a low level and the output voltage thereof, respectively. Even if the read word line RWL of the memory cell selected from time 0 ns to 10 ns becomes a high level (0.45 V), the normal operation is that the voltage VRBL maintains a high level (0.45 V) and the voltage VOUT maintains a low level (0 V).

[0373] In Comparative Example 12, when the voltage VRWL is 0.45V, the voltage VRBL drops, causing the voltage VOUT to approach high level, resulting in a read error in some memory cells. This occurs because the voltage VRBL drops due to crosstalk when the adjacent read bit line RBL is at low level. In Figure 43(B), in the selected memory cell, the read word line RWL is at high level and RP4' is off. Therefore, the read bit line RBL is not charged from the power supply line 28A, and the voltage VRBL remains low.

[0374] In Comparative Example 11, even though the voltage VRBL drops when the voltage VRWL reaches 0.45 V, the voltage VRBL then gradually increases. As a result, the voltage VOUT increases but then returns to a low level. This is because, even if the voltage VRBL drops due to crosstalk, in FIG. 43A, the storage node Q is at a low level, so RP4 is on and the read bit line RBL is charged from the power supply line 28A via RP4 and RP2. However, charging the read bit line RBL via RP4 and RP2 does not sufficiently compensate for the drop in voltage VRBL due to crosstalk.

[0375] In Example 11, even when the voltage VRWL reaches 0.45 V, the voltage VRBL only drops slightly, and then returns to its original state. The voltage VOUT remains at 0 V. This is because, even if the voltage VRBL drops due to crosstalk, in FIG. 43C , the transfer gate TG is located between the node N1 and the read bit line RBL, and therefore the read bit line RBL is charged from the power supply line 28A via RP4 and the transfer gate TG. In this way, the charge of the read bit line RBL via RP4 and the transfer gate TG can compensate for the drop in voltage VRBL due to crosstalk.

[0376] According to the eleventh embodiment, the influence of crosstalk can be reduced by providing a transfer gate TG between the node N1 and the read bit line RBL. RP3 may not be provided, and the drain of RP1 may be directly connected to the node N1.

[0377] If RP3 is not provided, the leakage current will be large. Therefore, it is preferable to provide RP3 and connect the drain of RP1 to node N1 via RP3. This reduces the effect of the leakage current, as shown in FIG.

[0378] The first power supply line and the second power supply line are a power supply line 28A and a ground line 28B, respectively, and the first conductivity type and the second conductivity type may be P-type and N-type, respectively.

[0379] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as set forth in the claims.

[0380] This application claims priority to basic patent application No. 2024-130618 filed with the Japan Patent Office on August 7, 2024, and basic patent application No. 2024-231726 filed with the Japan Patent Office on December 27, 2024, the entire contents of which are incorporated herein by reference.

[0381] 10 Memory cell 12A, 12B Inverter circuit 14 Bistable circuit 15 Read port circuit 20 Memory array 21 Selection circuit 22 Precharge circuit 23 Read circuit 24 Write circuit 25 WL decoder 26 Peripheral circuit 27 Control circuit 28A Power supply line 28B Ground line 30A to 30H Memory area 32A to 32H, 32A1, 32A2 Block 33A to 33D Set 34, 34A to 34H Decoder 36A to 36H Sense amplifier 38 Logic circuit

Claims

1. An inverter circuit comprising: a first FET having a channel of a first conductivity type, the channel being connected to an intermediate node, the drain being connected to a first power supply line, and the gate being connected to an output node; a second FET having a channel of a second conductivity type different from the first conductivity type, the channel being connected to the intermediate node, the drain being connected to the output node, and the gate being connected to an input node; and a third FET having a channel of the first conductivity type, the channel being connected to a second power supply line, and the drain being connected to the output node.

2. The inverter circuit according to claim 1, wherein the gate of said third FET is connected to said second power supply line.

3. A bistable circuit according to claim 1 or 2, comprising: a first inverter circuit having a first input node and a first output node; a second inverter circuit having a second input node and a second output node; a first storage node to which the first input node and the second output node are connected; and a second storage node to which the first output node and the second input node are connected.

4. A memory circuit comprising: the bistable circuit of claim 3; a word line connected to the gate of the third FET; and a selection circuit that connects the source of the third FET to a bit line when data is written to or read from the bistable circuit, and that connects the source of the third FET to the second power supply line when the bistable circuit holds data.

5. A memory circuit comprising: a bistable circuit according to claim 3; a write circuit that writes data to both the first memory node and the second memory node when writing data to the bistable circuit; and a read circuit that reads data from only the first memory node out of the first memory node and the second memory node when reading data from the bistable circuit.

6. A memory circuit comprising: a first inverter circuit having a first input node and a first output node, and having hysteresis in its transfer characteristic; a second inverter circuit having a second input node and a second output node, and having no hysteresis in its transfer characteristic or having hysteresis in its transfer characteristic that is smaller than the hysteresis of the transfer characteristic generated in the first inverter circuit; a bistable circuit comprising: a first storage node connecting the first input node and the second output node; and a second storage node connecting the first output node and the second input node; a write circuit that writes data to both the first storage node and the second storage node when writing data to the bistable circuit; and a read circuit that reads data from only the first storage node out of the first storage node and the second storage node when reading data from the bistable circuit.

7. The memory circuit according to claim 6, wherein a signal at either the first output node or the second output node is fed back to a path between a first power supply line and a second power supply line in the first inverter circuit, and neither a signal at the first output node nor a signal at the second output node is fed back to the second inverter circuit.

8. The memory circuit according to claim 6, wherein the first inverter circuit comprises: a first FET having a first conductivity type channel, a source connected to a first power supply line, a drain connected to a first intermediate node, and a gate connected to the first input node; a second FET having the first conductivity type channel, a source connected to the first intermediate node, a drain connected to the first output node, and a gate connected to the first input node; and a third FET having one of its source and drain connected to the first intermediate node, the other of its source and drain connected to a control node, and a gate connected to either the first output node or the second output node.

9. The memory circuit according to claim 8, wherein the first inverter circuit comprises a fourth FET having a channel of a second conductivity type different from the first conductivity type, the fourth FET having a source connected to a second power supply line, a drain connected to the first output node, and a gate connected to the first input node.

10. The memory circuit described in claim 9, wherein the first inverter circuit includes a fifth FET having a channel of the second conductivity type, the source of which is connected to the second power supply line, the drain of which is connected to a second intermediate node, and the gate of which is connected to the first input node; and the source of the fourth FET is connected to the second intermediate node and is connected to the second power supply line via the fifth FET.

11. The memory circuit according to claim 10, wherein no transistor is provided for feeding back the first output node or the second output node to the second intermediate node.

12. A memory circuit according to claim 6 or 7, further comprising a selection circuit that connects the first memory node to a first bit line and the second memory node to a second bit line when data is written to the bistable circuit, and that connects the first memory node to the first bit line and does not connect the second memory node to the second bit line when data is read from the bistable circuit.

13. A first memory region comprising: NA × MA first memory cells arranged in a matrix with NA first rows and MA first columns, each having a storage node; LA × LA first bit lines, each of which is a positive integer, provided in the MA first columns and connected to the first memory cells arranged in the column direction; the NA first rows are divided into nA first blocks, each of which is a positive integer, having the LA first rows; and in each of the nA first blocks, each of the LA first bit lines is connected to the storage node of a first memory cell provided in one of the LA first rows, and is not connected to first memory cells provided in the remaining first rows of the LA first rows; and the NB × MB second memory cells arranged in a matrix with NB second rows and MB second columns, each of which is a positive integer, and each having a storage node. a second memory region, wherein LB second bit lines, where LB is a positive integer, are provided in each of the MB second columns, connecting second memory cells arranged in the column direction; the NB second rows are divided into nB second blocks, where nB is a positive integer, each block having the LB second rows, and in each of the nB second blocks, each of the LB second bit lines is connected to the storage node of a second memory cell provided in one of the LB second rows, and is not connected to second memory cells provided in the remaining second rows of the LB second rows; and a readout circuit that reads data in parallel from the LA first memory cells in one of the nA first blocks and the LB second memory cells in one of the nB second blocks.

14. The memory circuit of claim 13, wherein the NA × MA first memory cells each have a complementary pair of the storage nodes, and the NB × MB second memory cells each have a complementary pair of the storage nodes, and in each of the nA first blocks, each of the LA first bit lines is connected to at least one of the pair of storage nodes in a first memory cell provided in one of the LA first rows, and in each of the nB second blocks, each of the LB second bit lines is connected to at least one of the pair of storage nodes in a second memory cell provided in one of the LB second rows.

15. The memory circuit of claim 13 or 14, wherein the read circuit reads data in parallel from the MA × LA first memory cells in the one first block in each of the MA first columns and the MB × LB second memory cells in the one second block in each of the MB second columns.

16. The memory circuit according to claim 13 or 14, wherein the NA and NB are equal, the MA and MB are equal, the LA and LB are equal, and the nA and nB are equal.

17. The MA and MB numbers are 2 of the NA and NB numbers when n is a number selected from integers equal to or greater than 1. ｎ 17. The memory circuit of claim 16, wherein the number of inputs is two.

18. The memory circuit according to claim 13 or 14, comprising: NA first word lines provided in the NA first rows, respectively, and connected to first memory cells arranged in the row direction; NB second word lines provided in the NB second rows, respectively, and connected to second memory cells arranged in the row direction; and a selection circuit that selects the first word line connected to the LA first memory cells in the one first block and the second word line connected to the LB second memory cells in the one second block when the read circuit reads data in parallel from the LA first memory cells in the one first block and the LB second memory cells in the one second block.

19. The memory circuit according to claim 13 or 14, wherein the read circuit is provided between the first memory area and the second memory area.

20. The memory circuit of claim 18, wherein the selection circuit is provided between the MA first columns and between the MB second columns.

21. The memory circuit according to claim 18, wherein a plurality of sets of the first memory region, the second memory region, and the readout circuit are provided, and the plurality of readout circuits read data in parallel from the LA first memory cells in the first block in the plurality of first memory regions and the LB second memory cells in the second block in the plurality of second memory regions.

22. An inverter circuit comprising: a first FET having a channel of a first conductivity type, the source of which is connected to a first power supply line, the drain of which is connected to an intermediate node, and the gate of which is connected to an input node; a second FET having a channel of the first conductivity type, the source of which is connected to the intermediate node, the drain of which is connected to an output node, and the gate of which is connected to the input node; a third FET having one of its source and drain connected to the intermediate node, and the other of its source and drain connected to a control node; and a fourth FET having a channel of a second conductivity type different from the first conductivity type, the source of which is connected to a second power supply line, the drain of which is connected to the output node, and the gate of which is connected to the second power supply line.

23. A bistable circuit comprising: a first inverter circuit as defined in claim 22, wherein the input node is a first input node and the output node is a first output node; a second inverter circuit as defined in claim 22, wherein the input node is a second input node and the output node is a second output node; a first storage node to which the first input node and the second output node are connected; and a second storage node to which the first output node and the second input node are connected; wherein the gate of the third FET of the first inverter circuit is connected to either the first output node or the second output node; and wherein the gate of the third FET of the second inverter circuit is connected to the other of the first output node and the second output node.

24. The bistable circuit of claim 23, wherein the gate of the third FET of the first inverter circuit is connected to the second output node, the gate of the third FET of the second inverter circuit is connected to the first output node, and the third FET of the first inverter circuit and the third FET of the second inverter circuit are FETs with channels of the second conductivity type.

25. A bistable circuit according to claim 23 or 24, comprising: a power supply circuit that selectively applies either a first voltage or a second voltage lower than the first voltage as a power supply voltage between the first power supply line and the second power supply line; a read circuit that reads data from at least one of the first storage node and the second storage node; and a write circuit that writes data to at least one of the first storage node and the second storage node, wherein when the read circuit reads data from at least one of the first storage node and the second storage node, the power supply circuit applies the first voltage as the power supply voltage; and when the write circuit writes data to at least one of the first storage node and the second storage node, the power supply circuit applies the first voltage as the power supply voltage. a memory circuit, wherein when the power supply circuit applies the second voltage as the power supply voltage, the bistable circuit holds data in the first storage node and the second storage node, the read circuit does not read data from at least one of the first storage node and the second storage node, and the write circuit does not write data to at least one of the first storage node and the second storage node.

26. A processing circuit comprising: a plurality of memory areas, each having memory cells arranged in rows and columns; a read circuit that reads data in parallel from the plurality of memory areas; and an arithmetic circuit that performs parallel arithmetic using the data read in parallel from the plurality of memory areas, wherein one or more consecutive row physical addresses are assigned to the plurality of memory areas in order such that each of the plurality of memory areas is assigned one or more consecutive row physical addresses of the row physical addresses sequentially read by the read circuit, and the read circuit reads data in parallel from the one or more consecutive row physical addresses in the plurality of memory areas.

27. The processing circuit of claim 26, wherein the one or more consecutive row physical addresses are La consecutive row physical addresses, and when the read circuit reads data in parallel from the La consecutive row physical addresses in the plurality of memory regions, the read circuit reads data in parallel from Lb row physical addresses in the plurality of memory regions that are equal to or greater than La.

28. The processing circuit of claim 27, wherein Lb is 2 or greater.

29. The processing circuit of claim 27, wherein Lb is 1.

30. When the number of row physical addresses read in parallel from the plurality of memory cells by the read circuit is Np and n0 is a number selected from integers equal to or greater than 1, Np is 2. ｎ０ When the number of the plurality of memory areas is Na and n1 is an integer selected from 0 to n0-1, Na is Np / 2 ｎ１ 30. The processing circuit according to claim 27, wherein Lb is Np / Na, and La is a number selected from integers equal to or greater than 1 and equal to or less than Lb.

31. A first inverter circuit and a second inverter circuit, each comprising: an input node and an output node; a first FET having a first conductivity type channel, a source connected to a first power supply line, a drain connected to a first intermediate node, and a gate connected to the input node; a second FET having the first conductivity type channel, a source connected to the first intermediate node, a drain connected to the output node, and a gate connected to the input node; a third FET having one of its source and drain connected to the first intermediate node and the other of its source and drain connected to a control node; a fourth FET having a second conductivity type channel different from the first conductivity type, a source connected to a second power supply line, a drain connected to a second intermediate node, and a gate connected to the input node; and a fifth FET having the second conductivity type channel, a source connected to the second intermediate node, a drain connected to the output node, and a gate connected to the input node; a first storage node connecting the input node of the first inverter circuit and the output node of the second inverter circuit; and a second storage node connecting the output node of the first inverter circuit and the input node of the second inverter circuit, a gate of the third FET of the first inverter circuit is connected to one of the first storage node and the second storage node, a gate of the third FET of the second inverter circuit is connected to the other of the first storage node and the second storage node, and the first inverter circuit and the second inverter circuit do not include a transistor that feeds back the first storage node or the second storage node to the second intermediate node.

32. A memory circuit comprising: a bistable circuit comprising: a first inverter circuit having a first input node and a first output node; a second inverter circuit having a second input node and a second output node; a first storage node to which the first input node and the second output node are connected; and a second storage node to which the first output node and the second input node are connected; a first FET having a source connected to a first power supply line, a drain connected to a first intermediate node, and a gate connected to the first storage node, and having a channel of a first conductivity type; a second FET having a source connected to a second power supply line, a drain connected to a second intermediate node, and a gate connected to the first storage node, and having a channel of a second conductivity type different from the first conductivity type; a third FET having a source connected to the first intermediate node, a drain connected to the second intermediate node, a gate connected to a word line, and having a channel of the first conductivity type; and a transfer gate having one end connected to the second intermediate node, the other end connected to a bit line, and the gate connected to the word line.

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