Method of manufacturing a semiconductor device

Abstract

Various embodiments of the present invention relate to a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device is provided, which improves the manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having a front surface and a back surface opposite to the front surface; (b) polishing the back surface of the wafer in a manner that a center portion (first portion) and a peripheral portion (second portion) surrounding the center portion are thinner than a peripheral edge portion; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) dividing the center portion from the peripheral portion by cutting a portion of the center portion with a blade (rotary blade) while the wafer is held by the first tape.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of Chinese patent application No. 201610170129.6, filed on March 23, 2016, entitled "Method for Manufacturing a Semiconductor Device".

[0003] Cross-reference to related applications

[0004] The publication of Japanese Patent Application No. 2015-070422, filed on March 30, 2015, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0005] This invention relates to a manufacturing technique for semiconductor devices, and more specifically, to a technique that is effectively applied to a method of manufacturing semiconductor devices, the technique comprising the step of dicing a semiconductor wafer to obtain a plurality of semiconductor chips. Background Technology

[0006] Japanese Patent Application Publication No. 2011-96767 (Patent Document 1), Japanese Patent Application Publication No. 2014-138177 (Patent Document 2), and Japanese Patent Application Publication No. 2014-170822 (Patent Document 3) describe methods for grinding the back side of a wafer to retain the protruding peripheral portion in the form of a ring surrounding the device region.

[0007] Patent document 1 discloses a method involving slicing a device region from its peripheral portion and then grinding the back side of the device region. Patent document 2 discloses a method involving grinding the back side of a wafer to preserve its peripheral portion, and then separating the device region from the peripheral portion using an adhesive tape attached to the back side of the wafer via a laser and a dicing blade. Patent document 3 discloses a method involving grinding the back side of a wafer to preserve its peripheral portion, and then separating the device region from the peripheral portion using an adhesive tape attached to the back side of the wafer via a dicing blade in contact with the front surface of the wafer.

[0008] Japanese Patent Application Publication No. 2012-19126 (Patent Document 4) discloses a method involving cutting the outer periphery of a wafer in a circular pattern with a first blade and polishing the outer periphery of the wafer with a second blade.

[0009] [Existing Technical Documents]

[0010] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2011-96767

[0012] [Patent Document 2] Japanese Patent Application Publication No. 2014-138177

[0013] [Patent Document 3] Japanese Patent Application Publication No. 2014-170822

[0014] [Patent Document 4] Japanese Patent Application Publication No. 2012-19126 Summary of the Invention

[0015] In semiconductor device manufacturing methods, an integrated circuit is jointly formed in multiple corresponding chip regions disposed in the device region of a semiconductor wafer, and then the chip regions are divided to manufacture the semiconductor device. In this case, various types of manufacturing processes are performed on the semiconductor wafer without separating the chip regions from the semiconductor wafer until the step of dividing the chip regions is reached.

[0016] To process semiconductor wafers with medium to high precision in each of the various manufacturing processes, a technique is needed to suppress warping and deformation of the semiconductor wafer. For example, a method involving grinding the back side of a semiconductor wafer to retain annular protrusions on the periphery of the device region, as described in Patent Document 3 mentioned above, is effectively a technique for suppressing warping and deformation of semiconductor wafers during the manufacturing process.

[0017] However, the aforementioned methods have various problems in improving the manufacturing efficiency of semiconductor devices. For example, it is difficult to separate the chip region from the annular protrusions formed on the outer periphery of the device region. Therefore, the aforementioned protrusions need to be removed before dividing the chip region. However, according to the methods for removing the annular protrusions, separating the annular protrusions from the device region requires a large margin, which may reduce the effective area of ​​the device region. This reduction in the effective area of ​​the device region leads to a decrease in manufacturing efficiency.

[0018] Other issues and other novel features of the invention will be clarified through the description in this specification and the accompanying drawings.

[0019] In a semiconductor device manufacturing method according to one embodiment, a surface of a semiconductor wafer is ground to make a first portion thinner than a second portion surrounding the first portion. In the aforementioned semiconductor device manufacturing method, the bonding surface of a first adhesive tape is attached to a surface opposite to the first surface of the semiconductor wafer. While holding the semiconductor wafer with the first adhesive tape, the first portion is separated from the second portion by cutting a portion of the first portion using a rotating blade in contact with the first surface.

[0020] According to one embodiment described above, the manufacturing efficiency of semiconductor devices can be improved. Attached Figure Description

[0021] Figure 1 This is a top view of a semiconductor chip in one embodiment.

[0022] Figure 2 Is Figure 1 The image shows a bottom view of a semiconductor chip.

[0023] Figure 3 It shows that it is included Figure 1 and Figure 2 The image shows a cross-sectional view of an example of the main part of the element structure of a field-effect transistor in a semiconductor chip.

[0024] Figure 4 It is installed on it Figure 1 The image shows a top view of a semiconductor device (semiconductor package) containing a semiconductor chip.

[0025] Figure 5 Is Figure 4 The image shows a bottom view of a semiconductor chip.

[0026] Figure 6 It shows that it was removed from it. Figure 4 The diagram shows a plan view of the internal structure of a semiconductor device with a hermetically sealed enclosure.

[0027] Figure 7 It is along Figure 6 The cross-sectional view intercepted by line AA.

[0028] Figure 8 This is an explanatory diagram showing a summary of the manufacturing process for a semiconductor device according to one embodiment.

[0029] Figure 9 It is shown in Figure 8 The diagram shows a plan view of the plane on the main surface side of the semiconductor wafer prepared during the wafer preparation steps.

[0030] Figure 10 Is Figure 9 The image shows a cross-sectional view of a semiconductor wafer.

[0031] Figure 11 It is shown in Figure 8 The diagram shows a schematic illustration of the back-side grinding process.

[0032] Figure 12 This is a plan view of the back surface of the wafer after the back-side grinding process.

[0033] Figure 13 Is Figure 12 The image shows an enlarged cross-sectional view of the area near the periphery of the wafer.

[0034] Figure 14 It is shown in Figure 13 The image shows an enlarged cross-sectional view of the wafer's back surface in which a metal film has been formed.

[0035] Figure 15 It shows that it will be Figure 14 The diagram shows a schematic perspective view of a wafer in a state where the peripheral portion is separated from its central portion and then removed from it.

[0036] Figure 16 It shows that by holding the tape will Figure 14 The image shows a perspective view of the wafer being fixed to the retaining ring.

[0037] Figure 17 Is Figure 16 The image shows an enlarged cross-sectional view of the area near the periphery of the wafer.

[0038] Figure 18 It shows that it will be Figure 17 The diagram shows a plan view of the step of cutting a ring shape near the boundary between the central portion and the peripheral portion of the wafer.

[0039] Figure 19 It shows the use in Figure 18 The image shows an enlarged cross-sectional view of a portion of a wafer being cut by a blade.

[0040] Figure 20 It shows the effect of ultraviolet irradiation on Figure 19 The image shows a perspective view of the tape being held in place.

[0041] Figure 21 This illustrates removing the peripheral portion of the wafer from... Figure 20 The diagram shows a cross-sectional view of the tape being held in place and removed.

[0042] Figure 22 It shows that it was kept in Figure 21 The diagram shows a plan view of the state in which markings are formed in the retaining tape of the central portion of the wafer.

[0043] Figure 23 It is shown that it will be used to keep in Figure 22 The diagram shows a schematic plan view of how the retaining tape of the central portion of the wafer is cut to separate the wafer from the retaining ring.

[0044] Figure 24 It shows that it will be Figure 23 The diagram shows a schematic plan view illustrating the wafer dicing steps for dividing a chip region.

[0045] Figure 25 It shows that it will be Figure 23 The image shows a cross-sectional view of the wafer and the holding film laminated for the wafer dicing step.

[0046] Figure 26 It shows cutting with a blade. Figure 25 The cross-sectional view of the wafer process shown in the figure.

[0047] Figure 27 It is shown in relation to Figure 19 The corresponding modified example shows an enlarged cross-sectional view of the state in which a groove is formed in the peripheral portion of the central part of the wafer during the first cutting step of the circular dicing process.

[0048] Figure 28 It is shown that by going along in Figure 27 The image shows an enlarged cross-sectional view of the wafer being cut using a trench dicing process.

[0049] Figure 29 It shows the relationship with Figure 19 The corresponding enlarged cross-sectional view of the example is shown. Detailed Implementation

[0050] (Explanation of the format, basic terminology, and usage in this application)

[0051] In this application, for convenience, the following embodiments may be described by dividing them into multiple parts, etc., which are not independent of each other unless otherwise stated. Regardless of their location, one of these parts may be a portion of a single example, a detail of a portion of another example, a modified example of a portion or all of another example, etc. In principle, parts with the same function are not described repeatedly. Corresponding components of the various embodiments are not essential unless otherwise stated, except when the number of components is theoretically limited, and when it is obvious from the context that this is not the case.

[0052] Similarly, in the descriptions of various embodiments, etc., terms such as "X is composed of A" regarding materials, composition, etc., do not exclude the presence of components other than A as one of the main components, unless otherwise stated, and unless it is obvious from the context that this is not the case. For example, regarding components, the above expression means "X containing A as a main component," etc. Specifically, terms such as "silicon component" are not limited to components made of pure silicon, and obviously can include components containing SiGe (silicon germanide) alloys, other multi-component alloys containing silicon as a main component, other additives, etc. Terms such as "gold plating," "copper layer," "nickel plating," etc., include not only pure components, but also components containing gold, copper, nickel, etc. as main components, unless otherwise stated.

[0053] Furthermore, similarly, when referring to specific numerical values ​​or quantities, the numerical values ​​used for elements may exceed or be less than the specific numerical values, unless otherwise stated, and except when theoretically limited to specific numbers, or when it is obvious from the context that this is not the case.

[0054] In each of the various embodiments, the same or similar parts are indicated by the same or similar reference numerals or numbers, and their description will not be repeated in principle.

[0055] In the corresponding figures, if drawing shading lines might complicate the cross-sectional view, or if cavities are easily distinguishable, shading lines may be omitted even in cross-sectional views in some cases. In this document, the outline of a hole that is planarly closed relative to the background may be omitted where it is clearly understood from the specification or other means. Furthermore, shading lines or dot patterns are sometimes used to represent non-cavity parts or to clearly show the boundaries between areas, even if the figure is not a cross-sectional view.

[0056] Semiconductor Devices

[0057] This embodiment will take a semiconductor device as an example to illustrate semiconductor chip 1 (see...). Figure 1 The semiconductor chip 1 includes, for example, a transistor element incorporated in a power converter and used as a switching element; and a semiconductor device PKG1 having the semiconductor chip 1 mounted thereon. Figure 1 This is a top view of the semiconductor chip in this embodiment, and Figure 2 Is Figure 1 The image shows a bottom view of a semiconductor chip. Figure 3 It shows that it is included Figure 1 and Figure 2 The image shows a cross-sectional view of an example of the main part of the element structure of a field-effect transistor in a semiconductor chip.

[0058] In this embodiment, the semiconductor chip 1 has... Figure 1 The front surface (surface, upper surface) 1t and the back surface (surface, lower surface) 1b opposite the front surface 1t are shown in the figure (see Figure 2 Semiconductor chip 1 has multiple electrodes. In one example of this embodiment, semiconductor chip 1 has a gate terminal (electrode pad) 1GT and a source terminal (electrode pad) 1ST on the front surface 1t side. Semiconductor chip 1 has a drain terminal (electrode pad) 1DT on the back surface 1b side.

[0059] Furthermore, semiconductor chip 1 includes a circuit with semiconductor elements. Figure 3In the example shown, semiconductor chip 1 includes, for example, an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Semiconductor chip 1 is, for example, a so-called power semiconductor device, which is incorporated in a power conversion circuit (such as a DC-DC converter or inverter) and used as a switching element.

[0060] Reference Figure 3 The structural example shown has a semiconductor chip 1 having, for example, a semiconductor substrate WH made of n-type single-crystal silicon. - An epitaxial layer EP is formed on the main surface Wt of the semiconductor substrate WH. The semiconductor substrate WH and the epitaxial layer EP are configured as the drain region of a MOSFET. The drain region is electrically coupled to the drain terminal 1DT formed on the back surface 1b side of the semiconductor chip 1. Figure 2 In the example shown, the drain terminal 1DT is formed across the entire back surface 1b of the semiconductor chip 1.

[0061] Channel formation region CH as p - The n-type semiconductor region is formed on the epitaxial layer EP. The source region SR serves as the n-type semiconductor region. + The semiconductor region is formed on the channel formation region CH. The trench (opening, recess) TR1 is formed to extend from the upper surface of the source region SR through the channel formation region CH to the interior of the epitaxial layer EP.

[0062] A gate insulating film GI is formed on the inner wall of trench TR1. A gate electrode GE, used to fill trench TR1, is laminatedly formed on the gate insulating film GI. The gate electrode GE is electrically coupled to the inner wall of trench TR1 via lead connections. Figure 1 The semiconductor chip 1 shown in the figure has a gate terminal 1GT.

[0063] The trench (opening, recess) TR2 for body contact is formed adjacent to the trench TR1, in which the gate electrode GE is embedded, via the corresponding element region SR. Figure 3 In the example shown, trench TR2 is formed to be adjacent to both sides of trench TR1. As p + A body contact region BC is formed at the bottom of each trench TR2 in the semiconductor region. By providing the body contact region BC, the base resistance of the parasitic bipolar transistor, which includes a source region SR as the emitter region, a channel formation region CH as the base region, and an epitaxial layer EP as the collector region, can be reduced.

[0064] exist Figure 3In the example shown, a trench TR2 is formed for body contact, thereby positioning the upper surface of the body contact region BC below the lower surface of the source region SR (on the lower surface side of the channel forming region CH). Although the illustration is omitted, as a modified example, the body contact region BC can be formed with a height substantially the same as its height in the source region SR, without forming the trench TR2 for body contact.

[0065] An insulating film IL is formed over the source region SR and the gate electrode GE. A barrier conductive film BM is formed over the insulating film IL and the region including the inner wall of the trench TR2 for body contact. Wiring CL is formed over the barrier conductive film BM. Wiring CL is electrically coupled to the region formed on the barrier conductive film BM. Figure 1 The source terminal 1ST is shown on the surface of the semiconductor chip CP1.

[0066] Wiring CL is electrically coupled to both the source region SR and the body contact region BC via the blocking conductive film BM. That is, the source region SR and the body contact region BC are at the same potential. This arrangement prevents the parasitic bipolar transistor mentioned above from being turned on due to the potential difference between the source region SR and the body contact region BC.

[0067] exist Figure 3 In the MOSFET shown, the drain region and source region SR are arranged such that a channel forming region CH is sandwiched between them in the thickness direction, thereby forming a channel in the thickness direction (hereinafter referred to as a vertical channel structure). In this case, compared with a field-effect transistor having a channel formed along the main surface Wt, the area occupied by the element in the planar view can be reduced. As a result, the planar size of the semiconductor chip 1 can be reduced (see...). Figure 1 ).

[0068] In the case of the vertical channel structure mentioned above, the semiconductor chip 1 can be thinned to reduce its on-resistance. For example, in a switching circuit including a high-side switch and a low-side switch, when a MOSFET is used as the low-side switch, the on-time of the low-side switch is longer than that of the high-side switch. Therefore, in the MOSFET used in the low-side switch, the losses due to on-resistance appear to be more severe than the switching losses. To address this, applying the vertical channel structure mentioned above to the low-side MOSFET can reduce the on-resistance of the low-side field-effect transistor.

[0069] It should be noted that Figure 3 The diagram illustrates the component structure of a field-effect transistor. Figure 1 In the semiconductor chip 1 shown, for example, it has in Figure 3 The component structure shown has multiple field-effect transistors coupled together in parallel. In this way, the power MOSFET can be configured to allow the flow of large currents, such as 1A.

[0070] Next, the device installed on it will be... Figure 1 An example of the semiconductor package structure of semiconductor chip 1 shown in the figure will be described. Figure 4 It is installed on it Figure 1 The image shows a top view of a semiconductor device (semiconductor package) containing a semiconductor chip. Figure 5 Is Figure 4 The image shows a bottom view of a semiconductor device. Figure 6 It shows that it was removed from it. Figure 4 The internal structure of the semiconductor device with a hermetically sealed enclosure is shown in the figure. Figure 7 It is along Figure 6 The cross-sectional view intercepted by line AA.

[0071] like Figures 4 to 7 As shown, the semiconductor device PKG1 includes: a semiconductor chip 1 (see...) Figure 6 and Figure 7 ); carrier tape 3, on which semiconductor chip 1 is mounted (see Figures 5 to 7 ); and multiple leads 4, which act as external terminals (see Figures 5 to 7 The upper surface 3t of the semiconductor chip 1, the upper surface 4t of the carrier tape 3, and the upper surface 4t of the lead wire are sealed together by a sealing body (resin body) 5.

[0072] As mentioned above, when semiconductor chip 1 has a vertical channel structure, semiconductor chip 1 is thinned (so that...). Figure 7 The distance between the front surface 1t and the back surface 1b shown in the diagram is smaller, thus enabling a reduction in on-resistance. For example, in Figure 7 In the example shown, the thickness of semiconductor chip 1 is in the range of approximately 50 μm to 100 μm.

[0073] like Figure 6 and Figure 7 As shown, the semiconductor device PKG1 has a carrier tape (chip mounting section) 3, on which the semiconductor chip 1 is mounted. Figure 7 As shown, the carrier tape 3 has an upper surface (chip mounting surface) 3t, on which the semiconductor chip 1 is mounted via a conductive bonding material (conductive member) 6; and a lower surface (mounting surface) 3b, which is opposite to the upper surface 3t. Figure 6 As shown, the carrier tape 3 and the lead wire 4D are integrally formed. Figure 7 As shown, the drain terminal 1DT formed on the back surface 1b of the semiconductor chip 1 is electrically coupled to the carrier tape 3 via the conductive bonding material 6.

[0074] exist Figure 6In the example shown, the planar size of semiconductor chip 1 (area of ​​the front surface 1t) is smaller than the planar size of carrier tape 3 (area of ​​the upper surface 3t). (Refer to...) Figure 5 and Figure 7 The lower surface 3b of the carrier tape 3 is exposed from the sealant 5 at the lower surface 5b of the sealant 5. When the semiconductor device PKG1 is mounted on a mounting substrate (not shown), the exposed surface of the carrier tape 3 is provided with a metal film (external plating) SD to improve the wettability of the solder material used as a bonding material.

[0075] Increasing the planar size of the carrier tape 3 to expose its lower surface 3b from the seal improves the heat dissipation efficiency of heat generated in the semiconductor chip 1. Furthermore, increasing the planar size of the carrier tape 3 to expose its lower surface 3b from the seal reduces impedance when the carrier tape 3 is used as part of an external terminal.

[0076] exist Figure 6 and Figure 7 The conductive bonding material shown is a conductive component (die bonding material) used to fix the semiconductor chip 1 onto the carrier tape 3 and electrically couple the semiconductor chip 1 to the carrier tape 3. Suitable conductive bonding materials 6 can be, for example, conductive resin materials or solder materials. For example, the conductive resin material is a so-called silver (Ag) paste, which contains multiple (large amounts) conductive particles such as silver (Ag) particles in a thermosetting resin.

[0077] When the semiconductor device PKG1 is mounted on a mounting substrate (not shown) (motherboard), solder material can be used as a bonding material to electrically couple the leads 4 of the semiconductor device PKG1 to terminals (not shown) on the mounting substrate side. (Refer to...) Figure 6 and Figure 7 For the purpose of improving the wettability of the solder material used as a bonding material, a metal film SD is formed at the corresponding bonding surface of the terminal of the semiconductor device PKG1. The metal film SD is, for example, an external coating made of solder.

[0078] In the step of mounting the semiconductor device PKG1, a heat treatment called a reflow process is performed by melting solder material (not shown) to bond the lead 4 to the corresponding terminal on the mounting substrate side (not shown). When a conductive adhesive containing conductive particles mixed in resin is used as the conductive bonding material 6, the conductive bonding material will not melt even if the processing temperature of the reflow process is arbitrarily set. Thus, the conductive bonding material 6 at the junction between the semiconductor chip 1 and the carrier tape 3 preferably meets the condition of preventing inconvenience caused by remelting during the mounting of the semiconductor device PKG1.

[0079] On the other hand, when solder material is used as the conductive bonding material 6 for bonding the semiconductor chip 1 to the carrier tape 3, it is preferable to use solder material that has a higher melting point than the bonding material during mounting to suppress remelting during the mounting of the semiconductor device PKG1. Therefore, the choice of material is limited when the solder material used for the conductive bonding material 6 is used as the die bonding material. However, for the purpose of improving electrical coupling reliability, using solder material is more preferable than using conductive adhesive.

[0080] like Figure 5 and Figure 6 As shown, the carrier tape 3 is supported by a suspension lead TL. The suspension lead TL is a support member used to fix the carrier tape 3 to the frame portion of the lead frame during the manufacturing process of the semiconductor device PKG1.

[0081] like Figure 6 and Figure 7 As shown, the source terminal 1ST of the semiconductor chip 1 is electrically coupled to the lead 4S via a metal clip (conductive component, metal plate) 7. The metal clip 7 is made of, for example, copper (Cu). The metal clip 7 is electrically coupled to the source terminal 1ST of the semiconductor chip 1 via a conductive bonding material 8. The metal clip 7 is electrically coupled to the lead 4S via the conductive bonding material 8.

[0082] exist Figure 6 and Figure 7 The conductive bonding material 8 shown is a conductive member used to fix the metal strip 7 to the leads 4S and source terminals 1ST of the semiconductor chip 1, and to electrically couple the semiconductor chip 1 to the metal strip 7, and to couple the leads 4S to the metal strip 7. Suitable conductive bonding materials 8 can be, for example, conductive resin materials or solder materials. Conductive resin materials are, for example, so-called silver (Ag) paste, which contains a plurality of (a large number of) conductive particles such as silver (Ag) particles in a thermosetting resin.

[0083] like Figure 6 As shown, lead 4G is configured to be an external terminal adjacent to carrier tape 3, electrically coupled to the gate terminal 1GT of semiconductor chip 1. Lead 4G is spaced apart from carrier tape 3. Lead 4G is electrically coupled to gate terminal 1GT via a wiring (conductive member) 9, which is a metal wire.

[0084] like Figure 7 As shown, the corresponding portions of the semiconductor chip 1, the metal strip 7, and the lead 4 are sealed with a sealing body 5. Figure 6 A portion of lead 4G and wiring 9 shown in the diagram are sealed with a sealing body 5.

[0085] The sealing body 5 is a resin body used to seal multiple semiconductor chips 1, metal strips 7, and wiring 9. The sealing body 5 has an upper surface 5t (see...). Figure 4 and Figure 7 ) and the lower surface (mounting surface) 5b, which is positioned relative to the upper surface 5t (see Figure 5 and Figure 7 ).

[0086] This embodiment has been described above by way of example, including a semiconductor chip 1 comprising a MOSFET and a semiconductor device PKG1 as a semiconductor package on which the semiconductor chip 1 is mounted. There are several modified examples of semiconductor devices to which the techniques described below can be applied. For example, in addition to transistors, the elements (circuits) in the semiconductor chip 1 may also include elements such as diodes. For example, a large number of terminals may be formed on the front surface 1t of the semiconductor chip 1. A semiconductor package, for example, having a semiconductor chip mounted on a wiring substrate, may be used. In some cases, the circulation form for a semiconductor device includes: a step of forming multiple circuits in a semiconductor wafer, and another step of dividing (monodividing) the semiconductor wafer into multiple individual chip regions; these steps are performed in different enterprises or by different operators. In this case, the semiconductor wafer before monolithization may also be considered a semiconductor device.

[0087] Methods for Manufacturing Semiconductor Devices

[0088] Next, the method for manufacturing the semiconductor device in this embodiment will be described. According to... Figure 8 The process shown in the diagram is used to manufacture in Figure 4 and Figure 7 The semiconductor device PKG1 is shown in the figure. Figure 8 This is an explanatory diagram showing a summary of the manufacturing steps of the semiconductor device used in this embodiment.

[0089] Semiconductor chip preparation steps

[0090] First, will be on Figure 8 The semiconductor chip preparation steps shown are described below. Figure 8 As shown, the semiconductor chip preparation steps include: wafer preparation step, backside grinding step, backside terminal formation step, peripheral portion dicing step, marking formation step, tape cutting step, wafer dicing step, and chip acquisition step.

[0091] <Chip Preparation Steps>

[0092] In the wafer preparation steps, such as Figure 9 and Figure 10 As shown, prepare the wafer (semiconductor wafer) 10. Figure 9 It is shown in Figure 8 The diagram shows a plan view of the main surface side of the semiconductor wafer prepared during the wafer preparation steps. Figure 10 Is Figure 9 The image shows a cross-sectional view of a semiconductor wafer.

[0093] The wafer 10 is formed in a substantially circular planar shape and has a front surface (surface, upper surface) 1t and a back surface (surface, lower surface) 10b positioned opposite the front surface 1t (see...). Figure 10 For example, in this embodiment, in Figure 9 and Figure 10 The wafer 10 shown has a diameter of 200 mm and a thickness of 770 μm. It should be noted that the front surface 1t of the wafer 10 is aligned with the... Figure 7 The semiconductor chip 1 shown corresponds to the main surface 1t. The wafer 10 includes a plurality of chip regions 10c formed on its main surface 1t, and dicing regions 10d formed between adjacent chip regions 10c. Each of the chip regions 10c is associated with the semiconductor chip 1 using... Figures 1 to 3 Corresponding to the semiconductor chip 1 described. The source terminal 1ST and the gate terminal 1GT are formed at the positive surface 1t. Marks 10n are formed at the peripheral portion of the wafer 10 to serve as markers for identifying the orientation of the plane of the wafer 10.

[0094] exist Figure 8 The wafer preparation steps shown include: forming a wafer by using... Figure 3 The description includes the steps involved in assembling a semiconductor element, such as a MOSFET, into a circuit (integrated circuit) (circuit formation steps), and the steps involved in performing electrical tests to verify the electrical characteristics of the circuit (electrical testing steps). It should be noted that in... Figure 8 After the back-side grinding step, it forms on Figure 3 The drain terminal 1DT is shown in the figure. Electrical testing can also be performed before the drain terminal 1DT is formed. When it is preferred to perform the electrical testing step after the drain terminal 1DT is formed, the electrical testing step can be performed after back-side grinding of the surface.

[0095] <Backside Grinding Steps>

[0096] Then, as Figure 11 and Figure 12 As shown, the back-side polishing step involves polishing the wafer 10 (see...) Figure 11 The back surface 10b is ground to expose the back surface 1b located on the side of the front surface 1t (see...). Figure 12 and Figure 13 Instead of the back surface 10b. Figure 11 It is shown in Figure 8 The diagram shows a schematic illustration of the back-side grinding process. Figure 12 This is a plan view of the back surface of the wafer after the back-side grinding step. Figure 13 Is Figure 12 The image shows an enlarged cross-sectional view of the area near the periphery of the wafer.

[0097] In this step, the back surface 10b of the wafer 10 is ground until the thickness of the wafer 10 reaches the specified value. Figure 7 The thickness of the semiconductor chip 1 shown in the figure (e.g., 50 μm) extends up to the thickness of the semiconductor chip 1 shown in the figure. Figure 13 (The location of the back surface 1b shown in the figure). Another method for obtaining the thin semiconductor chip 1 can also be proposed, which involves pre-thinning the semiconductor substrate (the silicon wafer in this embodiment) that serves as the substrate. When the thickness of the semiconductor substrate is excessively thinned, the substrate in… Figure 8 The deterioration of operability in the wafer preparation steps shown can lead to wafer breakage. Thinning of the wafer can cause warping and deformation in some cases, reducing processing accuracy.

[0098] In the wafer preparation and wafer fixing steps of this embodiment, processing is performed on a wafer having a sufficient first thickness (e.g., in the range of 700 μm to 800 μm) from the viewpoint of suppressing degradation of operability or suppressing warping and deformation. Then, the back surface 10b (see...) Figure 10 The wafer is ground to reduce its thickness (e.g., to 50 μm). This method can prevent grinding on the back side at each step of the grinding process (e.g., in...). Figure 8 Simultaneously with the breakage of the wafer in the circuit formation steps shown in the diagram, the obtained semiconductor chip 1 (see...) is... Figure 7 It was thinned.

[0099] If, during the back-side grinding step, for the Figure 10 The entire back surface 10b of the wafer 10 shown is simply ground to produce a wafer 10 with an overall thickness of less than or equal to 100 μm, which degrades the operability of the wafer 10 between the back-side grinding step and the wafer dicing step. Warping in the wafer 10 leads to a degradation in the processing accuracy during the wafer dicing step.

[0100] In this embodiment, during the back-side grinding step, the surface of the surface is polished. Figure 12 The central portion (device region, first portion) 11 of the back surface 10b of the wafer 10 shown is selectively ground to thin it. Specifically, in the plan view, the wafer 10 has: a central portion 11 having the chip region 10c formed therein; and a peripheral portion (second portion) 12 continuously surrounding the central portion 11. The chip region 10c is not disposed in the peripheral portion 12. In the back-side grinding step of this embodiment, as... Figure 12 and Figure 13As shown, the back surface 10b of the wafer 10 is polished, making the central portion 11 thinner than the peripheral portion 12. For example, in Figure 13 In the example shown, the thickness of the central portion 11, i.e., the distance from the front surface 1t to the back surface 1b, is 50 μm. On the other hand, the thickness of the peripheral portion 12, i.e., the distance from the front surface 1t to the back surface 12b, is approximately 650 μm.

[0101] like Figure 12 As shown, the width 12w of the peripheral portion 12, excluding the portion with the notch 10n, is constantly set to the same value around its entire perimeter. Figure 12 and Figure 13 In the example shown, the width 12w is in the range of approximately 2mm to 2.5mm.

[0102] In this way, the peripheral portion 12 surrounding the central portion 11 is thinned and thus serves as a reinforcing member for suppressing warping and deformation of the wafer 10. Therefore, this embodiment can suppress warping and deformation of the wafer 10 in steps performed after the thickness of the wafer 10 has been reduced to less than or equal to 100 μm.

[0103] Now, refer to Figure 11 The details of the back-side grinding process in this embodiment are described below. In this process, firstly, as... Figure 11 As shown in the preliminary stage, back-side polishing tape 20 is attached to the surface of wafer 10. Back-side polishing tape 20 is a protective tape used to prevent contamination of circuits formed on the front surface 1t side by water, cleaning water, etc., caused by chip polishing during the back-side polishing process. Back-side polishing tape 20 has an adhesive layer formed on one side of a resin film as a substrate. The surface with the adhesive layer formed thereon is bonded to the front surface 1t of wafer 10.

[0104] Then, although not in Figure 11 As shown, when the back-side polishing tape 20 is attached to the wafer 10, the entire back surface 10b of the wafer 10 is polished to a thickness of approximately 50 μm to 100 μm (preliminary polishing step). In the preliminary polishing step, polishing is performed continuously until... Figure 13 The wafer 10 is produced by exposing the back surface 12b shown in the figure, resulting in a total thickness of approximately 650 μm. It should be noted that the preliminary polishing step can be largely omitted.

[0105] Then, as Figure 11 As shown in the intermediate stage, while the back surface polishing tape 20 is applied (in the coarse polishing step), the back surface 10b of the wafer 10 is polished using a polishing stone (polishing jig) 21. In this step, the central portion 11 is selectively polished until... Figure 12 and Figure 13 The thickness shown in the figure is until the predetermined thickness is reached (e.g., approximately 60 μm).

[0106] Then, as Figure 11 As shown in the later stage, while the back surface polishing tape 20 is applied, the back surface 10b of the wafer 10 is polished using a polishing stone (polishing jig) 22, which is different from the polishing stone 21, thereby exposing the back surface 10b (fine polishing step). In this step, the back surface 10b is polished on the wafer 10. Figure 12 and Figure 13 The central portion 11 shown is selectively ground until its thickness reaches a target value according to the design (e.g., 50 μm). Grinding stone 21 differs from grinding stone 22 in the size of the abrasive particles. The particle size of the abrasive included in grinding stone 22 is smaller than that included in grinding stone 21. In other words, the particle size of the abrasive included in grinding stone 21 is larger than that included in grinding stone 22.

[0107] In this way, the wafer is polished with polishing stones 21 with large particle sizes until just before reaching the target thickness according to the design, thereby reducing the polishing process time. On the other hand, the back surface 1b is exposed with polishing stones 22 with small particle sizes, thereby improving the flatness of the back surface 1b. The flatness of the back surface 1b affects... Figure 3 The electrical characteristics of the semiconductor chip 1 shown are improved to enhance the flatness of the back surface 1b, thereby stabilizing the electrical characteristics of the semiconductor chip 1.

[0108] As in this embodiment, when a fine grinding step is performed after a coarse grinding step, a stepped portion 13 is formed at the boundary between the central portion 11 and the peripheral portion 12. Figure 13 As shown. The height difference of the stepped portion 13 is, for example, in the range of about a few μm to 10 μm, that it is thinner than the central portion 11.

[0109] It should be noted that after this step, a cleaning process is performed on the wafer 10 to remove the polishing chip or polishing solution attached to the wafer 10. At this time, the back polishing tape 20 is removed from the wafer. Figure 11 The front surface 1t of the wafer 10 shown is peeled off, and then the front surface 1t of the wafer 10 is also cleaned. If the wafer 10 is thin overall, warping tends to occur in the wafer 10 when the back-side abrasive tape 20 is peeled off. However, in this embodiment, as Figure 12 As shown, a peripheral portion 12, whose thickness is greater than or equal to twice the thickness of the central portion 11 (e.g., 650 μm), is configured to surround the central portion 11 in which the chip region 10c is disposed. This prevents the wafer 10 from warping even when the back surface tape 20 is peeled off.

[0110] To prevent warping of the wafer 10, the peripheral portion 12 should be as thick as possible. If... Figure 12 As shown, the width 12w of the peripheral portion 12 increases, so the thickness of the peripheral portion 12 can be less than twice the thickness of the central portion 11. However, the increase in width 12w leads to a reduction in the area of ​​the central portion 11, or the effective area for the chip region 10c, thereby reducing the area of ​​the semiconductor chip 1 obtainable from a wafer 10 (see...). Figure 1 The number of semiconductor chips 1 obtained from a single wafer 10 is reduced. Therefore, from the viewpoint of increasing the number of semiconductor chips 1 that can be obtained from a single wafer 10, thereby improving its manufacturing efficiency, the thickness of the peripheral portion 12 is preferably greater than or equal to twice the thickness of the central portion 11. When the thickness of the central portion 11 is less than or equal to 100 μm, as in this embodiment, the thickness of the peripheral portion 12 is more preferably greater than or equal to five times the thickness of the central portion 11.

[0111] The planar shape of the central part 11 (in) Figure 12 The shape of the back surface 1b shown is circular. For the purpose of suppressing warping and deformation of the wafer 10, the planar shape of the central portion 11 is not limited to a circle, but can adopt various modified shapes, such as polygons. It should be noted that since the planar shape of the wafer 10 is generally circular, from the viewpoint of maximizing the area of ​​the back surface 1b of the central portion 11, the planar shape of the central portion 11 is preferably as shown... Figure 12 The circle shown.

[0112] <Back Terminal Formation Steps>

[0113] Then, in Figure 8 In the back terminal forming step shown in the figure, such as Figure 14 As shown, a metal film 15 is formed on the back surface 1b and back surface 12b of the wafer 10. Figure 14 It is shown in Figure 13 The image shows an enlarged cross-sectional view of the state in which a metal film is formed on the back surface of the wafer.

[0114] exist Figure 14 The metal film 15 shown is, for example, a laminated film made of titanium (Ti) and gold (Au). For example, the metal film 15 is formed by sputtering, by laminating titanium and gold films in this order. The metal film 15 is formed on... Figure 3 and Figure 7 The metal film of the drain terminal 1DT is shown in the figure. In this step, a metal film 15 is formed to cover the entire back surface 1b, thereby making it possible for... Figure 12 The drain terminal 1DT in chip region 10c shown in the figure (see Figure 7 They can be formed together.

[0115] In this embodiment, for the purpose of improving semiconductor chip 1 (see...) Figure 3 The electrical characteristics of ) or improvements in Figure 7 The purpose of illustrating the bonding properties between the semiconductor chip 1 and the conductive bonding material 6, as shown in the figure, is that the metal film 15 (see Figure 14 The drain terminal 1DT is set. It should be noted that in the modified examples corresponding to this embodiment, the metal film 15 is not provided in some cases.

[0116] When a metal film 15 is formed on one surface of the wafer 10 in this embodiment, if the thickness of the peripheral portion 12 of the wafer 10 is substantially the same as the thickness of the central portion 11, it will cause warping and deformation of the wafer 10. However, in this embodiment, as mentioned above, the peripheral portion 12 is thicker than the central portion 11, thereby preventing warping and deformation of the wafer 10 even when the metal film 15 is formed.

[0117] <Steps for segmenting the perimeter>

[0118] Then, in Figure 8 In the peripheral segmentation steps shown in the figure, such as Figure 15 As shown, the central portion 11 of the wafer 10 is cut and separated from its peripheral portion 12. Figure 15 It shows that it will be Figure 14 The diagram shows a schematic perspective view of a wafer in a state where the peripheral portion is separated from its central portion and then removed from it. Figure 16 It shows that by holding the tape will Figure 14 The image shows a perspective view of the wafer being fixed to the retaining ring. Figure 17 Is Figure 16 The image shows an enlarged cross-sectional view of the area near the periphery of the wafer. Figure 18 It shows the point of view in Figure 17 The diagram shows a plan view of the steps of cutting near the boundary between the center and the peripheral portion of the wafer and cutting it in a circular pattern. Figure 19 It shows the use in Figure 18 The image shows an enlarged cross-sectional view of a portion of a wafer being cut by a blade. Figure 20 It shows the effect of irradiating with ultraviolet light. Figure 19 The image shows a perspective view of the tape being held in place. Figure 21 It involves removing the peripheral portion of the chip from... Figure 20 The diagram shows a cross-sectional view of the tape being peeled off and removed.

[0119] It should be noted that, Figure 18 In order to easily distinguish the boundary line between the chip region 10c and the direction of travel of the blade 36, the dicing region is represented by a dashed line, and the arrow showing the direction of travel of the blade 36 is represented by a two-dot dashed line.

[0120] In the peripheral segmentation step, in order to pre-separate the central portion 11 of the wafer 10 from its peripheral portion 12, such as... Figure 16 As shown, retaining tape 31 is attached to the chip 10, and then the chip 10 is fixed to the retaining ring (support member) 30 via retaining tape 31 (retaining tape attachment step).

[0121] The retaining ring 30 is a support member, such as a ring-shaped metal member, used to deliver and secure the wafer 10 to the worktable during the peripheral dicing step. The retaining tape 31 is a resin film attached to the retaining ring 30 in a taut manner. Figure 17 As shown, one surface of the resin substrate 31f is covered by an adhesive layer 31a. In the upper surface 31t and lower surface 31b of the retaining tape 31, the upper surface 31t, on which the adhesive layer 31a is formed, serves as the bonding surface of the retaining tape 31.

[0122] In the peripheral segmentation step, as described later... Figure 18 As shown, by using the blade 36 in a ring-shaped pair Figure 17 The cutting process is performed near the boundary between the central portion 11 and the peripheral portion 12 shown in the figure. The blade 36 is a rotating blade with abrasive grains fixed to its periphery, thereby cutting the periphery of the central portion 11 into a circle. When cutting a wafer using a blade, typically, as... Figure 29 The example shown in the figure involves attaching a retaining tape 41, referred to as dicing tape, to the back surface 1b side of the wafer 10, and then performing a dicing process on the wafer using a blade 36 that contacts the front surface 1t side. Figure 29 It shows the relationship with Figure 19 Enlarged cross-sectional view of the corresponding example.

[0123] Here, when the peripheral portion 12 is thicker than the central portion 11, such as in wafer 10, in this embodiment, the back surface 1b and the back surface 12b are different in height from each other. In this case, to prevent the wafer 10 from being damaged during the dicing process with the blade 36, the central portion 11 and the peripheral portion 12 of the wafer 10 need to be supported separately. For this purpose, as... Figure 29 As shown, during the cutting process using the blade 36, the stage 33 supporting the wafer 10 needs to have a portion 33A located directly below the central portion 11 and a portion 33B located directly below the peripheral portion 12, wherein portion 33A protrudes relative to portion 33B.

[0124] However, based on the research conducted by the inventors of this application, such as Figure 29As shown, it was found that when performing a dicing process on the wafer 10 from the side of the front surface 1t of the wafer 10, the following points should be considered. When attaching the retaining tape 41 to the back surfaces 1b and 12b of the wafer 10, due to the effect of the step portion caused by the thickness difference between the central portion 11 and the peripheral portion 12, a gap 34 is likely to occur between the wafer 10 and the retaining tape 41 at the boundary between the central portion 11 and the peripheral portion 12. Similarly, due to the effect of the step portion caused by the height difference between portions 33A and 33B of the stage 33, a gap 35 is likely to occur.

[0125] Therefore, the location where the central portion 11 of the wafer 10 is cut by the blade 36 needs to be set taking into account the gaps 34 and 35. That is, as Figure 29 As shown, the width 11w of the portion separated from the central portion 11 and cut together with the peripheral portion 12 should be set to large. This results in... Figure 12 The effective area of ​​the device region in the central portion 11 shown, where the chip region 10c can be formed, is small. Therefore, the reduction in the effective area of ​​the device region may reduce the number of semiconductor chips 1 that can be obtained from a single wafer 10 (see...). Figure 1 This reduces manufacturing efficiency.

[0126] Moreover, included Figure 29 The protrusion degree of portion 33A in the stage 33 shown should be varied according to the height difference between the back surfaces 1b and 12b of the wafer 10. Since the substrate 41f of the retaining tape 41 is made of resin film, if the height difference between the back surfaces 1b and 12b is due to minor errors such as those caused by processing precision, then such errors can be tolerated by the elastic deformation of the retaining tape 41. However, when processing multiple products with different design thicknesses, the type of stage 33 used for each product must be changed in order to reliably adhere portions 33A and 33B to the retaining tape 41 respectively. In this case, the apparatus must be changed whenever the type of product changes, which leads to a reduction in manufacturing efficiency.

[0127] Therefore, the inventors of this application have discovered this embodiment by considering the foregoing points. That is, as... Figure 17 As shown, in this embodiment, during the retaining tape attachment step, the retaining tape 31 is attached to the wafer 10 such that the front surface 1t of the wafer 10 faces the upper surface 31t, which serves as the bonding surface of the retaining tape 31. In other words, in this embodiment, the retaining tape 31 is attached to the front surface 1t of the wafer 10. Thus, as... Figure 19As shown, in this embodiment, when the cutting process is performed with the blade 36, the wafer 10 can be supported by a stage 37 having a flat support surface 37t, regardless of the height difference between the back surface 1b and the back surface 12b of the wafer 10. In this embodiment, the central support portion 11 and the peripheral portion 12 can be reliably supported without causing [damage / damage]. Figure 29 The gaps 34 and 35 are shown in the figure.

[0128] Therefore, in this embodiment, the portion of the central portion 11 in the wafer 10 that needs to contact the blade 36 can be positioned close to the boundary with the peripheral portion 12. In other words, as Figure 19 As shown, with Figure 29 In comparison, the width 11w of the portion of the central part 11 that is cut off and separated from the peripheral part 12 can be made smaller. As a result, the width of the portion of the central part 11 that is cut off and separated from the peripheral part 12 can be increased. Figure 12 The effective area of ​​the device region in the central portion 11 shown in the figure, in which the chip region 10c can be disposed, is illustrated. This allows for a larger effective area of ​​the device region, thereby increasing the semiconductor chip 1 that can be obtained from a single wafer 10 (see Figure 1). Figure 1 This improved manufacturing efficiency by increasing the quantity of [items / products].

[0129] As mentioned above, the stage 37 of this embodiment has a flat support surface 37t, regardless of the height difference between the back surface 1b and the back surface 12b of the wafer 10. Therefore, manufacturing efficiency can be improved without switching the stage 37 according to the type of product.

[0130] like Figure 17 As shown, when the retaining tape 31 is attached to the front surface 1t of the wafer 10, it is necessary to ensure that the adhesive layer 31a is in close contact with the wafer. This depends on the multiple terminals formed on the front surface 1t (in Figure 9 The shape of the source terminal 1ST or gate terminal 1GT is shown in the figure. Therefore, in this step, the adhesive layer 31a of the retaining tape 31 attached to the wafer 10 needs to be more than that in… Figure 29 The adhesive layer 41a of the retaining tape 41 shown is thicker. For example, the thickness of the adhesive layer 31a is in the range of approximately 20 μm to 40 μm. On the other hand, in Figure 29 The thickness of the adhesive layer 41a shown is in the range of approximately 5 μm to 10 μm. It should be noted that when used in… Figure 29 The retaining tape shown is for holding wafer 10 during the wafer dicing step, which will be described later.

[0131] In the peripheral segmentation step, after the tape adhesion step described above, as follows: Figure 18 and Figure 19As shown, while holding the wafer 10 by the tape 31, a portion of the central portion 11 is cut in a circular motion by the blade 36, thereby cutting the central portion 11 and separating it from the peripheral portion 12 (circular cutting step).

[0132] In the circular cutting process, such as Figure 18 As shown, the blade 36, attached to the spindle 38, is rotated to perform a cutting process on the central portion 11 of the wafer 10. As mentioned above, since the blade 36 contacts the wafer 10 from the back surface 1b side in this embodiment, cutting can be performed near the boundary between the central portion 11 and the peripheral portion 12. The blade 36 is a cutting jig (rotating blade) with multiple abrasive particles made of diamond or the like, attached to the outer periphery of a thin plate having a substantially circular shape. The blade 36, with abrasive particles fixed to its outer periphery, performs a cutting process on the object to be cut by rotating the thin plate, thereby cutting the object.

[0133] exist Figure 18 In the embodiment shown, during the circular dicing step, a dicing process is performed to form a circular trajectory for the dicing line. Specifically, during the circular dicing step, the position of the blade 36 is moved to draw concentric circles relative to the outer edge of the wafer 10. During the circular dicing step, the position of the blade 36 is moved while rotating the blade 36 in a manner that draws an arc along the outer edge of the middle portion 11.

[0134] In this step, a cut is made near the boundary between the central portion 11 and the peripheral portion 12, thereby maximizing the area of ​​the central portion 11. Therefore, the shape of the cutting line is not limited to a circle and can be any shape, as long as it is formed along the outer edge of the central portion 11. For example, when the planar shape of the central portion 11 is a polygon, the shape of the cutting line can be a polygon.

[0135] It should be noted that if a portion of the peripheral portion 12 is monolithized during the circular dicing step, that portion may become a foreign object. Therefore, as in this embodiment, for the purpose of dicing the wafer to prevent the peripheral portion 12 from being monolithized, the shape of the dicing line is preferably circular. When the shape of the central portion 11 and the shape of the dicing line are circular, the effective area of ​​the chip region 10c in the central portion 11 of the wafer 10 having a circular planar shape can be maximized.

[0136] In this step, a blade 36 that contacts the wafer 10 is used to cut from the wafer 10. Figure 19 The back surface 1b of the wafer 10 shown is subjected to a dicing process, thereby dicing the wafer in the thickness direction from the back surface 1b to the front surface 1t. After this step is completed, as... Figure 15As shown, the disc-shaped central portion 11 is separated from the annular peripheral portion 12.

[0137] It should be noted that Figure 19 An example is shown where the blade 36 does not overlap the step portion 13 of the wafer 10 in the thickness direction. When the height difference of the step portion 13 is small, a portion of the blade 36 may overlap the step portion 13. In this case, for the purpose of improving the durability of the blade 36, the cutting width of the blade 36 is preferably thick.

[0138] In the peripheral segmentation step, after the circle cutting step described above, as follows: Figure 20 As shown, ultraviolet light is irradiated in preparation for removing the peripheral portion 12, which has been separated from the central portion 11, from the retaining tape 31 (ultraviolet irradiation step). Figure 19 The adhesive layer 31a shown contains a UV-curable resin. For example... Figure 20 As shown, the retaining tape 31 is irradiated from the lower surface 31b side with ultraviolet light (UVR), thereby promoting the removal of the retaining tape 31 from the wafer 10.

[0139] It should be noted that during ultraviolet (UVR) irradiation, the retaining tape 31 is not immediately peeled off the wafer 10; instead, the retaining force of the retaining tape 31 on the wafer 10 weakens. Therefore, in this step, the entire retaining tape 31 may be irradiated with ultraviolet (UVR).

[0140] In the peripheral segmentation step, after the ultraviolet irradiation step described above, as... Figure 15 As shown, while the central portion 11 of the wafer 10 is held by the retaining tape 31, the annular peripheral portion 12 is peeled off from the retaining tape 31 and removed (peripheral portion removal step).

[0141] In the peripheral removal step, such as Figure 21 As shown, after the peripheral portion 12 of the wafer 10 is held by the chuck of the delivery jig 39, the peripheral portion 12 is raised, wherein the central portion 11 is attached to the retaining tape 31.

[0142] After the peripheral portion separation step is completed, for example, a central portion 11 with a thickness of approximately 50 μm remains on the retaining tape 31. Here, warping and deformation can occur when the central portion 11 is peeled off from the retaining tape 31. However, the retaining tape 31 is thicker than the central portion 11 of the wafer 10. Specifically, in Figure 17In the example, the thickness of the substrate 31f of the retaining tape 31 is in the range of approximately 150 μm to 200 μm. Thus, when the retaining tape 31, which is thicker than the center portion 11 of the wafer 10, is attached to the wafer 10, the retaining tape 31 acts as a reinforcing member. Therefore, while attaching the retaining tape 31 to the wafer 10, warping or deformation of the wafer 10 can be prevented.

[0143] <Marker Formation Steps>

[0144] Then, in Figure 8 In the mark formation steps shown in the figure, such as Figure 22 As shown, through holes are formed in the retaining tape 31 to form a mark 31c, which indicates an identification mark for specifying the orientation of the wafer 10. Figure 22 It shows that it was kept in Figure 21 The diagram shows a plan view of the state in which markings are formed in the retaining tape of the central portion of the wafer.

[0145] like Figure 22 As shown, after the peripheral segmentation step, it is set to... Figure 18 The notch 10n in the peripheral portion 12 of the wafer 10 shown is removed from the peripheral portion 12. The wafer 10 can be aligned by using the retaining ring 30 as a reference until the center portion 11 of the wafer 10 is separated from the retaining ring 30. Once the wafer 10 is separated from the retaining ring 30, an identification mark for alignment is required, that is, a mark for identifying the orientation of the wafer 10.

[0146] Therefore, in this embodiment, a marking step is performed before the tape cutting step, which will be described later, to form a mark 31c in the holding tape 31. Figure 22 In the example shown, mark 31c is a circular through-hole. It should be noted that the shape of mark 31c can be modified in various ways, as long as it specifies the orientation of wafer 10. As a method for forming mark 31c, for example, a pressing process using a molding die can be performed to form mark 31c. Alternatively, the mark can be formed using irradiation from a laser.

[0147] The location in which the mark 31c is formed is not specifically limited thereto. However, when considering ease of identification of the location of the mark 31c, the mark 31c is preferably formed in Figure 18 The location of the notch 10n shown in the figure.

[0148] <Tape Cutting Steps>

[0149] Then, in Figure 8 In the tape cutting steps shown, as Figure 23As shown, the retaining tape 31 surrounding the central portion 11 of the wafer 10 is cut to separate the central portion 11 from the retaining ring 30. Figure 23 It shows that it will be used to keep Figure 22 The diagram shows a schematic plan view of how the retaining tape is cut in the center of the wafer to separate the wafer from the retaining ring.

[0150] like Figure 23 As shown, in this step, for example, the wafer 10 is separated from the retaining ring 30 by cutting around the center portion 11 of the wafer 10 using a tape cutter TC. Since the retaining ring 30 only needs to be separated from the wafer 10 in this step, various modifications can be made to the cutting position of the retaining tape 31. Figure 23 In the example shown, the tape cutter TC moves in a circular motion to track the tape in the image. Figure 18 The location of the outer periphery of the peripheral portion 12 of the wafer 10 is shown in the diagram. Thus, a retaining tape 31 with the same planar dimensions as the wafer 10 before the peripheral portion 12 is removed is obtained. In this case, Figure 8 In the wafer dicing step shown, the preferred feature of this arrangement is that the wafer dicing step can be performed by treating the peripheral portion of the retaining tape 31 as the peripheral portion of the wafer.

[0151] <Wafer Splitting Steps>

[0152] Then, as in Figure 24 As indicated by the arrows, in the wafer dicing step, the wafer 10 is cut along the extending direction of the dicing region 10d using a blade 42, thereby dividing the wafer 10 into chip regions 10c. Figure 24 It shows that it will be Figure 23 The diagram shows a schematic plan view illustrating the wafer dicing steps for dividing a chip region. Figure 25 It involves attaching a retaining film used in the wafer dicing process to... Figure 23 The image shows a cross-sectional view of the wafer. Figure 26 It shows cutting with a blade. Figure 25 The cross-sectional view of the wafer process shown in the figure.

[0153] It should be noted that, Figure 24 In order to easily distinguish between the dicing area 10d and the direction of travel of the blade 42, the dicing area is represented by a dashed line, and the arrow indicating the direction of travel of the blade 42 is represented by a two-dot dashed line.

[0154] In the wafer dicing process, such as Figure 25As shown, when preparing for the dicing of the wafer 10, a retaining tape (dicing tape, wafer dicing retaining tape) 41 is attached to the wafer 10, thereby fixing the wafer 10 to the retaining ring (support member) 40 via the retaining tape 41 (wafer dicing retaining tape attachment step).

[0155] The retaining ring 40 is a support member used to deliver and secure the wafer 10 to a worktable (not shown) during the wafer dicing process. The retaining ring 40 is a ring-shaped metal member. The retaining tape 41 is a resin film attached to the retaining ring 40 in a taut manner. Figure 25 As shown, one surface of the resin substrate 41f is covered by an adhesive layer 41a. In the upper surface 41t and lower surface 41b of the retaining tape 31, the upper surface 41t, on which the adhesive layer 41a is formed, serves as the bonding surface of the retaining tape 31.

[0156] like Figure 25 As shown, the wafer 10 undergoing this step is the central portion 11, from which the peripheral portion 12 has been removed (see figure). Figure 15 And has a uniform thickness. Therefore, in this step, the upper surface 41t, which serves as the bonding surface of the retaining tape 41, is attached to the back surface 1b of the wafer 10. When the retaining tape 41 is attached to the back surface 1b of the wafer 10 in this manner, as... Figure 9 As shown, the retaining tape can be aligned with high precision by identifying the metal pattern formed on the side of the positive surface 1t, including the source terminal 1ST and the gate terminal 1GT.

[0157] The back surface 1b of wafer 10 has a higher flatness than the front surface 1t. Therefore, as... Figure 25 As shown, the adhesive layer 41a of the retaining tape 41 is thinner than the adhesive layer 31a of the retaining tape 41. This thinning of the adhesive layer 41a of the retaining tape 41 allows for easier use of the blade 42 (see...). Figure 24 During the cutting process, the components of the adhesive layer 41a are attached to the blade 42, thereby suppressing the reduction of the cutting processability of the blade 42.

[0158] In this embodiment, as Figure 25 As shown, retaining tape 41 is attached to the back surface 1b, while retaining tape 31 is attached to the front surface 1t of the wafer 10. Then, retaining tape 31 is peeled off from the front surface 1t of the wafer 10. That is, at least one of retaining tape 31 and retaining tape 41 is attached to the wafer 10 until the wafer 1 is diced. Each of retaining tape 41 and retaining tape 31 is thicker than the wafer 10 obtained after backside grinding, and the attachment of at least one of retaining tape 31 and retaining tape 41 to the wafer 10 can suppress warping and deformation of the wafer 10.

[0159] In the wafer dicing step, after the aforementioned holding tape application step for wafer dicing, while holding the wafer 10 with the holding tape 31, the wafer 10 is cut using a blade (rotating blade) 42, such as... Figure 24 and Figure 26 As shown, this divides the wafer into chip regions 10c (see...) Figure 24 (Division steps).

[0160] like Figure 26 As shown, in this step, the blade 42 is moved along the dicing area 10d (see...). Figure 24 The blade 42 travels from the front surface 1t of the wafer 10, thereby cutting the wafer 10 to divide it into chip regions 10c. The blade 42 is a cutting fixture (rotating blade) with multiple abrasive particles made of diamond or the like, fixed to the outer periphery of a thin plate with a substantially circular shape. The blade 42 operates to cut the wafer by performing a cutting process on the object to be cut with the abrasive particles, which are fixed to the outer periphery by the rotation of the thin plate.

[0161] As the blade 42 rotates and moves along a straight line during this step, as described above... Figure 18 Compared to the case where the blade 36 is moved to draw an arc in the circular cutting step shown in the diagram, the load on the blade 42 is reduced. Therefore, it is possible to... Figure 26 The width (cutting width) of the blade 42 shown is greater than that in Figure 19 The blade 36 shown is narrower in width (cutting width). In this case, because it can make the cutting width narrower... Figure 9 The width of the dicing region 10d shown is narrowed, thus increasing the effective area of ​​the chip region 10c. As a result, the number of semiconductor chips that can be obtained from a single wafer 10 can be increased, thereby improving manufacturing efficiency.

[0162] It should be noted that when the wafer 10 is thin enough and the load on the blade 36 is sufficiently small during the circular dicing step, Figure 26 The width (cutting width) of the blade 42 shown can be compared with that in Figure 19 The width of the blade 36 (cutting width) shown is substantially the same. In this case, the area of ​​the central portion 11 can be widened.

[0163] <Steps to Obtain the Chip>

[0164] Then, in the chip acquisition step, from in Figure 26 The retaining tape 41 shown in the figure is used to individually remove the corresponding segmented chip region 10c (see figure). Figure 24 ), to obtain in Figures 1 to 3The multiple semiconductor chips 1 shown in the figure. The step of individually removing the corresponding chip region 10c from the retaining tape 41 can be performed by applying a general technique for removing monolithically formed semiconductor chips from dicing tape. For example, it is permissible to pre-include a UV-curable resin component in the adhesive layer 41a of the retaining tape 41 before curing (see Figure 25 In the wafer dicing step, the retaining tape 41 is irradiated with ultraviolet light, and the adhesive paste is cured, which reduces the bonding strength of the retaining tape 41. If the bonding strength of the retaining tape 41 is reduced, the corresponding chip region 10c can be easily removed by using a retaining jig (pick-up jig), for example, a retaining jig called a chuck (not shown). Figures 1 to 3 The semiconductor chip 1 shown is processed in this step, where the semiconductor chip 1 has a very small thickness. However, in the wafer dicing step mentioned above, the monolithized semiconductor chip 1 has a thickness greater than that of the integrated wafer 10 (see, for example...). Figure 24 The smaller planar region of the front surface 1t and the planar region of the back surface 1b make it difficult to cause deformation and damage to the semiconductor chip during processing.

[0165] In the steps described above, you will obtain Figures 1 to 3 The semiconductor chip 1 shown is... Figure 8 The semiconductor chip preparation steps shown in the image are about to be completed.

[0166] Assembly steps for semiconductor devices

[0167] Then, refer to Figure 8 For Figures 4 to 7 The assembly steps of the semiconductor device PKG1 shown are briefly described below. It should be noted that in this section, reference will be made to... Figures 4 to 7 The assembly steps are described.

[0168] First of all, Figure 8 In the substrate preparation step shown, a lead frame is prepared, which includes a carrier tape 3, the carrier tape 3 being made of, for example... Figure 6 The suspended lead TL support is shown; and multiple leads 4 are configured to surround the carrier tape 3.

[0169] Then, in the chip mounting step, the semiconductor chip 1 prepared in the semiconductor chip preparation step mentioned above is mounted as follows: Figure 6 On the carrier tape 3 of the lead frame shown. In this step, as Figure 7As shown, a semiconductor chip 1 is mounted on a carrier tape 3 via a conductive bonding material 6, wherein the back surface 1b of the semiconductor chip 1 faces the upper surface 3t of the carrier tape 3. After mounting the semiconductor chip 1, the conductive bonding material 6 is cured, thereby fixing the semiconductor chip 1 to the carrier tape 3. The drain terminal 1DT, on which the electrode is disposed on the back surface 1b side of the semiconductor chip 1, is electrically coupled to the carrier tape 3 via the conductive bonding material 6.

[0170] Then, in the lead coupling step, the terminals of the semiconductor chip 1 are electrically coupled to the leads 4 that are configured to surround the carrier tape 3. Figure 6 In the example shown, the gate electrode 1GT is electrically coupled to lead 4G via wiring 9 (wiring connection step). The source terminal 1ST is electrically coupled to lead 4S via metal strip 7 (strip connection step). It should be noted that, as Figure 7 As shown, the drain terminal 1DT is disposed on the back surface 1b side of the semiconductor chip 1. During the semiconductor chip mounting step, the drain terminal 1DT is electrically coupled to the lead 4S.

[0171] Next, in Figure 8 In the sealing steps shown, such as Figure 7 As shown, a semiconductor chip 1, a metal strip 7, and a lead 4 are partially sealed with resin to form a seal 5. Figure 5 As shown, in this step, a portion of the lead 4 is exposed from the seal 5 to form the semiconductor device PKG1.

[0172] Figures 4 to 7 The finished semiconductor device PKG1 is shown. In many semiconductor device manufacturing methods, multiple semiconductor devices PKG1 are manufactured together using a lead frame with multiple product areas. In this case, in Figure 8 In the monolithization steps shown, in Figure 6 The suspension leads TL and 4 shown are separated from the lead frame to monolithize them.

[0173] Then, in the inspection and selection steps, inspections, such as visual inspections, are performed to select products as good or defective, thereby obtaining [the desired outcome]. Figures 4 to 7 The semiconductor device PKG1 is shown in the figure.

[0174] <Modification Example>

[0175] Although the present invention has been described in detail based on various embodiments, it is not limited to the embodiments mentioned above. It will be apparent that various modifications and changes can be made without departing from the scope of the invention. For example, multiple modification examples described above or explained below can be applied in combination.

[0176] For example, the various embodiments mentioned above have described a semiconductor chip 1 including a MOSFET as an example of a semiconductor device, and a semiconductor device PKG1 having the semiconductor chip 1 mounted thereon as an example. However, there are various modified examples of semiconductor devices to which the techniques mentioned above can be applied. In some cases, for example, the circulation form of a semiconductor device includes a step of forming multiple circuits in a semiconductor wafer, and another step of dividing (monodividing) the semiconductor wafer into individual chip regions; these steps are performed at different companies. In this case, the semiconductor wafer obtained as an intermediate product before the wafer dicing step mentioned above can also be regarded as a semiconductor device.

[0177] In this case, when fixed to Figure 22 After the wafer 10, with the retaining ring 30 shown, undergoes necessary inspections (such as visual inspection), it can be packaged and transported. Alternatively, the retaining tape 31 surrounding the wafer 10 can be used... Figure 23 The tape cutter TC shown in the figure cuts the tape into rings, and the wafer with the tape 31 attached can be transported.

[0178] For example, in the embodiments mentioned above, warping and deformation of the wafer can easily occur without any measures, as illustrated by products in which the thickness of the central portion 11 is ground to less than or equal to 100 μm. Based on the inventors' research, warping and deformation can occur even with wafers having a thickness greater than 100 μm. For example, as... Figure 14 As shown, when a metal film 15 is formed to uniformly cover the back surface 1b side of the wafer 10, warping or deformation can occur in the wafer even if the wafer has a thickness greater than or equal to 100 μm. When the wafer 10 has a diameter, for example, greater than 200 mm, warping and deformation can occur in the wafer in some cases even if the wafer thickness is greater than 100 μm.

[0179] Therefore, the inventors of this application, through [the following], Figure 14 The wafer with a central portion 11 having a thickness greater than 100 μm, as shown in the figure, was investigated using the techniques described in the embodiments mentioned above. As a result, it was found that for wafers with a thick central portion 11, the load on the cutting blade during the circular dicing step should be reduced. Figure 27 It is shown in relation to Figure 19 The corresponding modified example shows an enlarged cross-sectional view of the state in which a groove is formed in the peripheral portion of the central part of the wafer during the first cutting step of the circular cutting process. Figure 28 It shows along Figure 27The image shows an enlarged cross-sectional view of the wafer being cut using the trenches.

[0180] Although Figure 27 and Figure 28 Omitted in Figure 19 The stage 37 is shown in the image; however, even in this modified example, a cutting process is performed on the stage 37. Figure 27 and Figure 28 The chip 10A shown is one in which each has the same characteristics as in... Figure 19 The structure of the wafer 10 shown is the same as that of a semiconductor wafer, except that the central portion 11 is thicker (e.g., 200 μm).

[0181] As described in the embodiments mentioned above, the circular cutting step involves: moving the blade 36 to, as... Figure 18 The diagram shows the cutting process where the blade 36 rotates while drawing an arc. That is, the blade 36 performs the cutting process while moving non-linearly. When the cutting process is performed in this way while the blade 36 moves non-linearly, the load on the blade increases compared to the case of performing the cutting process along a straight line, as in the wafer dicing step mentioned above. The load on the blade increases proportionally to the thickness of the wafer, which is the object to be cut.

[0182] Greater loads on the cutting blade can lead to uneven wear (one polished surface of the blade wears more easily than the other) or damage to the blade. Furthermore, greater loads on the blade make the cutting process unstable, leaving chips of the wafer, the object to be cut, in the peripheral portion of the cutting area. As is known from the research conducted by the inventors of this application, when the wafer has a thickness greater than 150 μm, the aforementioned problems of blade damage and chipping are severely exacerbated.

[0183] Techniques for reducing the load on the blade during the circular dicing step have been studied, and the following method has been discovered. That is, the technique is a method involving dicing wafer 10a from the back surface 1b to the front surface 1t by performing dicing processes multiple times during the circular dicing step.

[0184] In the modified example, firstly, as Figure 27 As shown, a trench CTR1 is formed by cutting the back surface 1b side of the central portion 11 using a blade 36 (trench formation step). In this modified example, after the trench formation step mentioned above, a cutting process is performed along the trench CTR1 using the blade 36 to cut the central portion 11 in the thickness direction (cutting step). When the object to be cut, such as wafer 10A, is thick, the cutting process is performed multiple times to reduce the load on the blade 36.

[0185] As the inventors of this application further considered, as in this modified example, when the cutting process is performed multiple times, the cutting depth in the previous cutting process (the groove forming step mentioned above) (in) Figure 27 The depth T1 shown is preferably greater than the depth of the cutting groove in the next cutting process (in the cutting step mentioned above). Figure 28 The depth shown in the figure (T2) is deeper. When cutting wafer 10A, the aforementioned chips are prone to occur. Therefore, the portion to be cut in the cutting step is pre-thinned, which can suppress the occurrence of chips.

[0186] It should be noted that, Figure 27 The depth of trench CTR1 in the trench formation step shown is preferably suppressed to less than 150 μm. Therefore, when the thickness of wafer 10A is greater than 300 μm, the dicing process is preferably performed three times. In this case, the depth of the dicing trench in the first dicing process is preferably deeper than the depth cut from wafer 10A in the third dicing process.

[0187] When performing the cutting process multiple times, as in this modified example, a method involving the use of blades 36 with different widths can also be used. It should be noted that, in order to widen the effective area of ​​the central portion 11, the width of the blades 36 is preferably as narrow as possible. Therefore, as... Figure 27 and Figure 28 As shown, in the trench forming step and the cutting step, the cutting process is preferably performed by using blades 36 with the same width.

[0188] It should be noted that although in this modified example, wafer 10A is cut by performing multiple dicing processes, the blade 36 can be temporarily separated from wafer 10A between the first and second dicing processes. In this case, the blade 36 is aligned to insert into the groove CTR1 formed in the first dicing process before the second dicing process.

[0189] It should be noted that in another modified example of this example, the blade 36 may not be separated from the wafer 10A between the first and second cutting processes. In other words, the blade 36 and the wafer 10A may be kept in contact with each other between the first and second cutting processes. For example, if the blade 36 is along the path formed by... Figure 18 The circular trajectory, represented by one long and two short alternating dashed lines, continuously orbits the blade 36 and the wafer 10A, maintaining them in contact with each other, as mentioned above. In this case, alignment is not required between the first and second cutting processes, thus improving manufacturing efficiency.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a circuit on a first surface of a semiconductor wafer, the semiconductor wafer having the first surface and a second surface opposite to the first surface; (b) polishing the second surface of the semiconductor wafer having a first portion and a second portion surrounding the first portion, so that the first portion is thinner in thickness than the second portion, the first portion having a plurality of chip regions and a plurality of dicing regions provided between the plurality of chip regions; (c) attaching a bonding surface of a first tape to the first surface of the semiconductor wafer; and (d) separating the first portion from the second portion by cutting a part of the first portion with a first rotary blade in contact with the second surface of the first portion while the semiconductor wafer is held by the first tape; (e) removing the second portion after the step (d); (f) attaching a bonding surface of a second tape to the second surface side of the first portion of the semiconductor wafer with the first tape attached to the semiconductor wafer; and (g) peeling the first tape from the semiconductor wafer after the step (f); (h) cutting the first portion along respective extension directions of the dicing regions with a second rotary blade in contact with the first surface side of the first portion while the semiconductor wafer is held by the second tape after the step (g), thereby separating the wafer into the respective chip regions; the first tape including a first base material and a first adhesive layer provided at one surface of the first base material and attached to the first surface of the semiconductor wafer, wherein the second tape includes a second base material and a second adhesive layer provided at one surface of the second base material and attached to the second surface of the first portion of the semiconductor wafer, and wherein the first adhesive layer is thicker than the second adhesive layer; the step (b) is, (b1) a polishing step of the second surface of the semiconductor wafer using a first polishing stone, (b2) after the step (bl), polishing the second surface of the semiconductor wafer using a second polishing stone having a smaller polishing grain particle size than a polishing grain particle size of the first polishing stone; a step portion is formed between the first portion and the second portion of the semiconductor wafer after the step (b) is completed, in the step (d), a part of the first rotary blade overlaps the step portion.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the first tape is thicker than the first portion after the step (b).

3. The method of manufacturing a semiconductor device according to claim 1, wherein the step (d) includes the steps of: (d1) performing a dicing process at the second surface side of the first portion by moving the rotary blade while rotating the rotary blade to trace an arc along an outer edge of the first portion of the semiconductor wafer, thereby forming a groove; and (d2) after the step (d1), performing a further dicing process along the groove, thereby dicing the first portion in a thickness direction thereof.

4. The method of manufacturing a semiconductor device according to claim 3, wherein a depth of the groove formed in the step (d1) is deeper than a dicing groove depth in the dicing process performed in the step (d2).

5. The method of manufacturing a semiconductor device according to claim 3, wherein a dicing process width in the step (d1) is the same as a dicing process width in the step (d2).

6. The method of manufacturing a semiconductor device according to claim 3, wherein the rotary blade and the semiconductor wafer remain in contact with each other between the step (d1) and the step (d2).

7. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), dicing is performed along an outer edge of the first portion of the semiconductor wafer.

8. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), the first portion is diced to trace an arc along an outer edge of the first portion of the semiconductor wafer.

9. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (b), a thickness of the first portion is less than or equal to 100 μm.

10. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: after the step (b) and before the step (c), forming a metal film to cover the second surface of the first portion.

11. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: after the step (d), forming a mark for identifying an orientation of the semiconductor wafer in a portion of the first tape.

12. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a circuit on a first surface of a semiconductor wafer, the semiconductor wafer having the first surface and a second surface opposite to the first surface; (b) polishing the second surface of the semiconductor wafer having a first portion and a second portion surrounding the first portion, so that a thickness of the first portion is thinner than a thickness of the second portion, the first portion having a plurality of chip regions and a plurality of dicing regions provided between the plurality of chip regions; (c) a process of adhering an adhesive surface of a first tape adhered to a fixing ring and having a first thickness thicker than the first portion after the (b) process to the first surface of the semiconductor wafer; and (d) a process of dicing the first portion along an outer edge of the first portion of the semiconductor wafer. (d) separating the first portion from the second portion by cutting a portion of the first portion with a first rotary blade in contact with the second surface of the first portion while the semiconductor wafer is held by the first tape, removing the second portion; (e) after the step (d), forming a mark for identifying the direction of the semiconductor wafer in a portion of the first tape; (f) attaching the second surface side of the first portion of the semiconductor wafer to a bonding surface of a second tape with the first tape attached; (g) after the step (f), peeling the first tape from the semiconductor wafer; (h) after the step (g), cutting the first portion along respective extension directions of the cut regions with a second rotary blade in contact with the first surface side of the first portion while the semiconductor wafer is held by the second tape, thereby separating respective die regions; the first tape includes a first base material and a first adhesive layer provided at one surface of the first base material and attached to the first surface of the semiconductor wafer, wherein the second tape includes a second base material and a second adhesive layer provided at one surface of the second base material and attached to the second surface of the first portion of the semiconductor wafer, and wherein the first adhesive layer is thicker than the second adhesive layer; the step (b) is, (b1) performing a polishing step on the second surface of the semiconductor wafer using a first polishing stone, (b2) after the step (b1), polishing the second surface of the semiconductor wafer using a second polishing stone having a smaller polishing grain particle size than a polishing grain particle size of the first polishing stone; after the step (b) is completed, a step portion is formed between the first portion and the second portion of the semiconductor wafer, in the step (d), a portion of the first rotary blade overlaps the step portion.

13. The method of manufacturing a semiconductor device according to claim 12, wherein after the step (e), the semiconductor wafer held by the first tape is separated from the fixing ring by cutting around the first tape.

14. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a circuit on a first surface of a semiconductor wafer, the semiconductor wafer having the first surface and a second surface opposite to the first surface; (b) polishing the second surface of the semiconductor wafer, thereby making a first portion thinner than a second portion surrounding the first portion; (c) attaching a bonding surface of a first tape to the first surface of the semiconductor wafer; (d) separating the first portion from the second portion by cutting a portion of the first portion with a first rotary blade in contact with the second surface of the first portion while the semiconductor wafer is held by the first tape, removing the second portion; (e) after (d), removing the second portion; (f) attaching a bonding surface of a second tape to the second surface side of the first portion of the semiconductor wafer with the first tape attached to the semiconductor wafer; and (g) after (f), peeling the first tape from the semiconductor wafer; wherein (d) includes: (d1) while rotating the first rotary blade, performing a cutting process at the second surface side of the first portion by moving the first rotary blade to trace an arc along an outer edge of the first portion, thereby forming a groove; and (d2) after (d1), performing a further cutting process by moving the first rotary blade along the groove, thereby further cutting the first portion in a thickness direction thereof, thereby separating the first portion from the second portion; wherein the first tape includes: a first base material, and a first adhesive layer provided at one surface of the first base material and attached to the first surface of the semiconductor wafer, wherein the second tape includes: a second base material, and a second adhesive layer provided at one surface of the second base material and attached to the second surface of the first portion of the semiconductor wafer, and wherein the first adhesive layer is thicker than the second adhesive layer; wherein in (c), the first tape is also attached to a first fixed ring, wherein in (f), the second tape is also attached to a second fixed ring different from the first fixed ring, and wherein the method further includes: after (e) and before (f), cutting the first tape between the first fixed ring and an outer periphery of the first portion of the semiconductor wafer.

15. The method of manufacturing a semiconductor device according to claim 14, wherein after cutting the first tape, a remaining portion of the first tape attached to the first surface has the same area in plan view as the semiconductor wafer prior to removal of the second portion in (e).

16. The method of manufacturing a semiconductor device according to claim 14, wherein the first base material has a thickness greater than the first portion of the semiconductor wafer.

17. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a circuit on a first surface of a semiconductor wafer, the semiconductor wafer having the first surface and a second surface opposite the first surface; (b) grinding the second surface of the semiconductor wafer, thereby making a first portion thinner than a second portion surrounding the first portion; (c) attaching a bonding surface of a first tape to the first surface of the semiconductor wafer; and (d) while the semiconductor wafer is held by the first tape, separating the first portion from the second portion by cutting a portion of the first portion with a first rotary blade in contact with the second surface of the first portion; (e) after (d), removing the second portion; (f) attaching an engaging surface of a second adhesive tape to the second surface side of the first portion of the semiconductor wafer, with the first adhesive tape attached to the semiconductor wafer; and (g) after (f), peeling the first adhesive tape from the semiconductor wafer; wherein (d) includes: (d1) while rotating the first rotary blade, performing a cutting process at the second surface side of the first portion by moving the first rotary blade to draw an arc along an outer edge of the first portion, thereby forming a groove; and (d2) after (d1), performing a further cutting process by moving the first rotary blade along the groove, thereby further cutting the first portion in a thickness direction thereof, thereby separating the first portion from the second portion; wherein the first adhesive tape includes: a first base material, and a first adhesive layer provided at one surface of the first base material and attached to the first surface of the semiconductor wafer, wherein the second adhesive tape includes: a second base material, and a second adhesive layer provided at one surface of the second base material and attached to the second surface of the first portion of the semiconductor wafer, and wherein the first adhesive layer is thicker than the second adhesive layer, and wherein the method further includes: after (d), forming a mark for identifying a direction of the semiconductor wafer in a portion of the first adhesive tape.

18. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a circuit on a first surface of a semiconductor wafer, the semiconductor wafer having the first surface and a second surface opposite to the first surface; (b) grinding the second surface of the semiconductor wafer, thereby making a first portion thinner than a second portion surrounding the first portion; (c) attaching an engaging surface of a first adhesive tape to the first surface of the semiconductor wafer; and (d) while the semiconductor wafer is held by the first adhesive tape, separating the first portion from the second portion by cutting a portion of the first portion with a first rotary blade in contact with the second surface of the first portion; wherein (d) includes: (d1) while rotating the first rotary blade, performing a cutting process at the second surface side of the first portion by moving the first rotary blade to draw an arc along an outer edge of the first portion, thereby forming a groove; and (d2) after (d1), performing a further cutting process by moving the first rotary blade along the groove, thereby further cutting the first portion in a thickness direction thereof, thereby separating the first portion from the second portion.

19. The method of manufacturing a semiconductor device according to claim 18, wherein a depth of the groove formed in (d1) is greater than a depth in the further cutting process performed in (d2).

20. The method of manufacturing a semiconductor device according to claim 18, ​ wherein the width of the cutting process in (d1) is the same as the width of the further cutting process in (d2).

21. The method of manufacturing a semiconductor device according to claim 18, wherein the rotating blade and the semiconductor wafer are maintained in contact with each other between (d1) and (d2).

22. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a circuit on a first surface of a semiconductor wafer, the semiconductor wafer having the first surface and a second surface opposite the first surface; (b) grinding the second surface of the semiconductor wafer so that a first portion is thinner than a second portion surrounding the first portion; (c) attaching an engaging surface of a first adhesive tape to the first surface of the semiconductor wafer, the first adhesive tape being attached to a holding ring and having a first thickness greater than a thickness of the first portion after (b); and (d) separating the first portion from the second portion by cutting a portion of the first portion with a rotating blade in contact with the second surface of the first portion while the semiconductor wafer is held by the first adhesive tape, thereby removing the second portion; (e) after (d), forming a mark in a portion of the first adhesive tape for identifying an orientation of the semiconductor wafer; (f) attaching an engaging surface of a second adhesive tape to the first portion of the semiconductor wafer on a side of the semiconductor wafer opposite the first surface while the first adhesive tape is maintained attached to the semiconductor wafer; and (g) after the step (f), peeling the first adhesive tape from the semiconductor wafer; wherein the first adhesive tape comprises: a first base material, and a first adhesive layer between the first base material and the semiconductor wafer, wherein the second adhesive tape comprises: a second base material, and a second adhesive layer between the second base material and the semiconductor wafer, and wherein the first adhesive layer is thicker than the second adhesive layer, and wherein the method further comprises: after (e), separating the semiconductor wafer held by the first adhesive tape from the holding ring by cutting around the first adhesive tape, and wherein the second adhesive tape is attached to a second holding ring different from the holding ring of the first adhesive tape.

Images