Chip sealing ring

Abstract

The present invention provides a chip sealing ring, comprising: first to Nth metal layers, sequentially formed on a substrate, the N metal layers being separated by dielectric layers, each metal layer comprising first to Nth metal strips, the first to Nth metal strips in the same metal layer sequentially surrounding the chip from the inside out to form N non-closed ring structures, each metal strip having a first opening, each metal strip in each metal layer being connected to a metal strip in an adjacent layer, and metal strips in the same metal layer being unable to connect to the same metal strip; and multiple electrical test keys for testing the electrical properties of the metal layers, with each metal strip having two electrical test keys. The electrical parameters of the metal layer connected to the electrical test keys are obtained by testing the signals from the electrical test keys.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip sealing ring. Background Art

[0002] During the wafer packaging process, chips need to be cut. To protect the chip, a chip seal ring is typically placed between the chip and the cut path. This ring prevents any cracks from invading the chip interior. Part of the chip seal ring's structure is an interlayer dielectric (IMD).

[0003] The semiconductor industry is constantly striving to fit more chips per wafer. Existing methods typically involve reducing the dicing street width or omitting the die seal ring structure, reducing the area outside the die, thereby increasing the number of chips on a wafer. However, sufficient electrical test keys must be placed on the dicing street, and in some processes, all of the test keys are located on the dicing street. These test keys can be used to test various electrical properties, such as leakage current between metal layers. Therefore, blindly reducing the dicing street width may prevent the placement of test keys or impair their functionality. Omitting the die seal ring, on the other hand, may increase the risk of chip failure during subsequent dicing. Numerous cases of chip cracking have occurred in both advanced 28nm and standard 0.18μm processes. Failure analysis generally indicates that mechanical forces generated during dicing break through the die seal ring, causing cracks in the die seal ring. These cracks then extend into the interior of the die, causing disconnection and damage to internal circuits. Therefore, the die seal ring is essential. Summary of the Invention

[0004] The purpose of the present invention is to provide a chip sealing ring that can protect the chip from being affected by the mechanical force generated by cutting when cutting a wafer to form independent chips. At the same time, it can also test the electrical properties, reduce the electrical test keys on the cutting path, and thus reduce the width of the cutting path to form more chips on the wafer.

[0005] In order to achieve the above object, the present invention provides a chip sealing ring, comprising:

[0006] The substrate surrounds the chip to form a closed ring structure;

[0007] A first metal layer to an Nth metal layer are sequentially formed on the substrate, the N metal layers are separated by a dielectric layer, each of the metal layers includes a first metal strip to an Nth metal strip, the first metal strip to the Nth metal strip in the same metal layer sequentially surround the chip from the inside to the outside to form N non-closed ring structures, each of the metal strips has a first opening, each metal strip in each metal layer is connected to a metal strip in an adjacent layer, and metal strips in the same metal layer cannot be connected to the same metal strip; and

[0008] A plurality of electrical test keys are used to test the electrical properties of the metal layer. Each metal strip has two electrical test keys, and the two electrical test keys are respectively located on two ends of the metal strip at the first opening.

[0009] Optionally, in the chip sealing ring, among the N metal strips of each metal layer, except for the metal strips whose number is the same as the number of layers of the metal layer, the remaining N-1 metal strips also have a second opening, and the first opening and the second opening are in two opposite directions of the metal strips.

[0010] Optionally, in the chip sealing ring, the distance between the metal strips on the same metal layer is 1 μm.

[0011] Optionally, in the chip sealing ring, the electrical test key includes a pad.

[0012] Optionally, in the chip sealing ring, the distance between the pad and the adjacent metal strip is 1 μm.

[0013] Optionally, in the chip sealing ring, the pad is square, and the side length of the pad is 5 μm.

[0014] Optionally, in the chip sealing ring, each metal strip of each metal layer is connected to a metal strip of an adjacent layer through a connector.

[0015] Optionally, in the chip sealing ring, the substrate and the first metal layer are separated by a dielectric layer, and the first metal layer is connected to the surface of the substrate through a connector.

[0016] Optionally, in the chip sealing ring, N is four, and the four metal layers are respectively a first metal layer, a second metal layer, a third metal layer and a fourth metal layer; the first metal layer is located on the substrate and is separated from the substrate by a dielectric layer, and the first metal layer is also connected to the surface of the substrate through a connector; the second metal layer is located on the first metal layer and is separated from the first metal layer by a dielectric layer; the third metal layer is located on the second metal layer and is separated from the second metal layer by a dielectric layer; the fourth metal layer is located on the third metal layer and is separated from the third metal layer by a dielectric layer.

[0017] Optionally, in the chip sealing ring, each metal layer includes four metal strips, namely a first metal strip, a second metal strip, a third metal strip and a fourth metal strip; the first metal strip surrounds the chip to form a non-closed ring structure; the second metal strip surrounds the first metal strip to form a non-closed ring structure; the third metal strip surrounds the second metal strip to form a non-closed ring structure; and the fourth metal strip surrounds the third metal strip to form a non-closed ring structure.

[0018] In the chip sealing ring provided by the present invention, the electrical parameters of the metal strip connected to the electrical test key are obtained through the signal of the electrical test key, and the metal layer includes the metal strip, so the electrical parameters of the metal layer can be tested through the signal of the electrical test key. Therefore, the chip sealing ring of the present invention can not only protect the chip from being affected by the mechanical force generated by cutting when cutting the wafer to form independent chips, but also can test the electrical properties, reduce the electrical test keys on the cutting path, and thus reduce the width of the cutting path to form more chips on the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a chip sealing ring according to an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of the fourth metal layer according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of the third metal layer according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of the second metal layer according to an embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of the first metal layer according to an embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of four metal layers connected in an embodiment of the present invention;

[0025] In the figure: 1-chip sealing ring, 100-first metal layer, 110-first metal strip, 120-second metal strip, 130-third metal strip, 140-fourth metal strip, 200-second metal layer, 210-first metal strip, 220-second metal strip, 230-third metal strip, 240-fourth metal strip, 300-third metal layer, 310-first metal strip, 320-second metal strip, 330-third metal strip, 340-fourth metal strip, 400-fourth metal layer, 410-first metal strip, 420-second metal strip, 430-third metal strip, 440-fourth metal strip, 510-electrical test key, 600-connector. DETAILED DESCRIPTION

[0026] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0027] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0028] The inventors discovered how to minimize the scribe line width while preserving the chip seal ring. Previously, electrical test keys were all located on the scribe line. There was no precedent for combining a seal ring with an electrical test key.

[0029] Therefore, the present invention provides a chip sealing ring, comprising:

[0030] The substrate surrounds the chip to form a closed ring structure;

[0031] A first metal layer to an Nth metal layer are sequentially formed on the substrate, the N metal layers are separated by a dielectric layer, each of the metal layers includes a first metal strip to an Nth metal strip, the first metal strip to the Nth metal strip in the same metal layer sequentially surround the chip from the inside to the outside to form N non-closed ring structures, each of the metal strips has a first opening, each metal strip in each metal layer is connected to a metal strip in an adjacent layer, and metal strips in the same metal layer cannot be connected to the same metal strip; and

[0032] A plurality of electrical test keys are used to test the electrical properties of the metal layer. Each metal strip has two electrical test keys, and the two electrical test keys are respectively located on two ends of the metal strip at the first opening.

[0033] The substrate and the first metal layer are separated by a dielectric layer, and the first metal layer is connected to the surface of the substrate through a connector.

[0034] Please refer to Figure 1 , is the overall structure diagram of the chip sealing ring, which is similar to the structure of an overall frame, with the chip area in the middle. Figure 1 The area between the inner frame and the outer frame of the frame diagram is where the sealing ring structure is located, and outside the outer frame is the cutting path area. When cutting on the cutting path, the chips on the wafer can be separated. The chip sealing ring can block the mechanical force generated during cutting to prevent the chip from being damaged by the mechanical force. In the embodiment of the present invention, a plurality of electrical test keys are set on the chip sealing ring, and the electrical test keys can be used to test the electrical parameters of the metal strip to replace the function of the partial test-key that must be placed on the cutting path. It can not only protect the chip, but also test electrical problems and reduce the area of ​​the cutting path, so that more chips can be obtained on the unit area of ​​the wafer. Therefore, in fact, the cross-section of the substrate is also Figure 1 Box Figure 1 Then, various metal layers and test structures between the metal layers are formed on the substrate.

[0035] Preferably, the distance between the metal strips is 1 μm. The metal strips are made into relatively regular shapes. Optionally, in the chip sealing ring, the distance between the metal strips on the same metal layer is 1 μm.

[0036] In an embodiment of the present invention, the electrical test key includes a pad. The distance between the pad and the adjacent metal strip is 1 μm. The pad is square. The side length of the pad is 5 μm. Each metal strip in each metal layer is connected to a metal strip in the adjacent layer via a connector. The electrical parameters of the metal layer, such as the resistance of the metal strip, are tested by measuring the values ​​between the pads.

[0037] Furthermore, among the N metal strips of each metal layer, except for the metal strips with the same number of metal strips as the number of metal layers of the current layer, the remaining N-1 metal strips also have a second opening, and the first opening and the second opening are in two opposite directions of the metal strips. That is, all metal strips have a first opening, and in the Xth metal layer, except for the Xth metal strip, the remaining N-1 metal strips also have a second opening, and the value of X is 1 to N. For example, the first opening is on the first side, and the second opening is on the second side, and the first side and the second side are two sides of a rectangular non-closed shape, and the first side and the second side are parallel and tangential to each other. For example, Figure 2 , in the fourth metal layer, except for the edge of the fourth metal strip, the other three metal strips all have second openings; Figure 3 , except for the edge of the third metal strip, the other three metal strips of the third metal layer all have second openings; Figure 4 , except for the edge of the second metal strip, the other three metal strips of the second metal layer all have second openings; Figure 5 Except for the edge of the first metal strip, the other three metal strips of the first metal layer all have second openings.

[0038] Taking N as an example, the four metal layers are the first metal layer, the second metal layer, the third metal layer and the fourth metal layer; the first metal layer is located on the substrate and is separated from the substrate by a dielectric layer, and the first metal layer is also connected to the surface of the substrate through a connector; the second metal layer is located on the first metal layer and is separated from the first metal layer by a dielectric layer; the third metal layer is located on the second metal layer and is separated from the second metal layer by a dielectric layer; the fourth metal layer is located on the third metal layer and is separated from the third metal layer by a dielectric layer.

[0039] Furthermore, each metal layer includes four metal strips, namely a first metal strip, a second metal strip, a third metal strip and a fourth metal strip; the first metal strip surrounds the chip to form a non-closed ring structure; the second metal strip surrounds the first metal strip to form a non-closed ring structure; the third metal strip surrounds the second metal strip to form a non-closed ring structure; the fourth metal strip surrounds the third metal strip to form a non-closed ring structure. The line width and the distance between the lines of the embodiment of the present invention can be set by design rules before production. Please refer to Figures 2 to 6 , Figure 2 This is a top view of the fourth metal layer, also known as the TOP metal layer. In the fourth metal layer, except for fourth metal strip 440, which only has a first opening, first metal strip 410, second metal strip 420, and third metal strip 430 all have first and second openings, and the first and second openings are in opposite directions. In this case, testing the two electrical test keys 510 on fourth metal strip 440 can test the electrical properties of the fourth metal strip, such as its resistance. Testing the electrical test keys 510 for adjacent metal strips can test the electrical parameters between adjacent metal strips, such as BVD or leakage current. Since the metal layer includes the metal strips, the electrical parameters of the metal layer are indirectly tested. Figure 3This is a top view of the third metal layer. In the third metal layer, except for the third metal strip 330 which has only the first opening, the first metal strip 310, the second metal strip 320 and the fourth metal strip 340 all have the first opening and the second opening, and the first opening and the second opening are in opposite directions. At this time, the two electrical test keys 510 on the third metal strip 330 can be used to test the electrical properties of the third metal strip, for example, the resistance of the third metal strip. Figure 4 This is a top view of the second metal layer. In the second metal layer, except for the second metal strip 220 which has only the first opening, the first metal strip 210, the third metal strip 230 and the fourth metal strip 240 all have the first opening and the second opening, and the first opening and the second opening are in opposite directions. At this time, the two electrical test keys 510 on the second metal strip 220 can be used to test the electrical properties of the second metal strip, for example, the resistance of the second metal strip. Figure 5 It is a top view of the first metal layer. In the first metal layer, except for the first metal strip 110 which has only the first opening, the second metal strip 120, the third metal strip 130 and the fourth metal strip 140 all have the first opening and the second opening, and the first opening and the second opening are in opposite directions. At this time, testing the two electrical test keys 510 on the first metal strip 110 can test the electrical properties of the first metal strip, for example, the resistance of the first metal strip. The first openings of the first metal strip, the second metal strip and the third metal strip and the opening of the fourth metal strip are also not in the same direction. Preferably, they can be in the same direction. The first openings of the first metal strip, the second metal strip and the third metal strip and the fourth metal strip can be in the squares on the four sides of the rectangle respectively. If there is a fifth metal strip, the first opening of the fifth metal strip can be in the same direction as the first opening of the first metal strip. The above are all preferred ways to form more regular and space-saving metal strips. In other embodiments of the present invention, the first opening can be irregular and not limited in direction. In order to facilitate testing, the electrical test keys 510 can be placed on the end metal strips of the first opening, and the two ends can each form a pad. Please continue to refer to Figure 6 , Figure 6 yes Figure 2In the longitudinal cross-sectional view taken along line AB in FIG, the first metal strip 110 of the first metal layer, the first metal strip 210 of the second metal layer, the first metal strip 310 of the third metal layer, and the first metal strip 410 of the fourth metal layer are all connected via a connector 600; the second metal strip 120 of the first metal layer, the second metal strip 220 of the second metal layer, the second metal strip 320 of the third metal layer, and the second metal strip 420 of the fourth metal layer are all connected via a connector 600; the third metal strip 130 of the first metal layer, the third metal strip 230 of the second metal layer, the third metal strip 330 of the third metal layer, and the third metal strip 430 of the fourth metal layer are all connected via a connector 600, and the fourth metal strip 140 of the first metal layer, the fourth metal strip 240 of the second metal layer, the fourth metal strip 340 of the third metal layer, and the fourth metal strip 440 of the fourth metal layer are all connected via a connector 600.

[0040] The present invention allows for resistance testing of metal strips during WAT testing or online testing. Therefore, after each metal layer is fabricated, the resistance of the metal strip can be measured online using the electrical test key. After fabrication of the entire metal layer, the electrical properties of the metal layer can also be tested using the test key for the TOP metal layer (Nth metal layer).

[0041] In summary, in the chip sealing ring provided in the embodiment of the present invention, the electrical parameters of the metal strip connected to the electrical test key are obtained through the signal of the electrical test key, and the metal layer includes the metal strip, so the electrical parameters of the metal layer can be tested through the signal of the electrical test key. Therefore, the chip sealing ring of the present invention can not only protect the chip from being affected by the mechanical force generated by cutting when cutting the wafer to form independent chips, but also can test the electrical properties, reduce the electrical test keys on the cutting path, and thus reduce the width of the cutting path to form more chips on the wafer.

[0042] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A chip sealing ring, characterized in that: include: The substrate surrounds the chip to form a closed ring structure; A first metal layer to an Nth metal layer are sequentially formed on the substrate from bottom to top, the N metal layers are separated by a dielectric layer, each metal layer includes a first metal strip to an Nth metal strip with metal strips numbered 1 to N, the first metal strip to the Nth metal strip in the same metal layer sequentially surround the chip from the inside to the outside to form N non-closed ring structures, each metal strip has a first opening, each metal strip in each metal layer is connected to a metal strip in an adjacent layer, and metal strips in the same metal layer cannot be connected to the same metal strip; as well as A plurality of electrical test keys for testing the electrical properties of the metal layer, wherein each metal strip has two electrical test keys, and the two electrical test keys are respectively located at two ends of the metal strip at the first opening; Among the N metal strips of each metal layer, except for the metal strip with the same metal strip number as the metal layer of the current layer, the remaining N-1 metal strips also have a second opening, and the first opening and the second opening are in two opposite directions of the metal strips.

2. The chip sealing ring according to claim 1, wherein: The distance between the metal strips on the same metal layer is 1 μm.

3. The chip sealing ring according to claim 1, wherein: The electrical test key includes a pad.

4. The chip sealing ring according to claim 3, wherein: The pad is square, and the side length of the pad is 5 μm.

5. The chip sealing ring according to claim 1, wherein: Each metal strip of each metal layer is connected to a metal strip of an adjacent layer through a connecting piece.

6. The chip sealing ring according to claim 1, wherein: The substrate and the first metal layer are separated by a dielectric layer, and the first metal layer is connected to the surface of the substrate through a connector.

7. The chip sealing ring according to claim 1, wherein: N is four, and the four metal layers are a first metal layer, a second metal layer, a third metal layer and a fourth metal layer; the first metal layer is located on the substrate and is separated from the substrate by a dielectric layer, and the first metal layer is also connected to the surface of the substrate through a connector; the second metal layer is located on the first metal layer and is separated from the first metal layer by a dielectric layer; the third metal layer is located on the second metal layer and is separated from the second metal layer by a dielectric layer; the fourth metal layer is located on the third metal layer and is separated from the third metal layer by a dielectric layer.

8. The chip sealing ring according to claim 1, wherein: Each metal layer includes four metal strips, namely a first metal strip, a second metal strip, a third metal strip and a fourth metal strip; the first metal strip surrounds the chip to form a non-closed ring structure; the second metal strip surrounds the first metal strip to form a non-closed ring structure; the third metal strip surrounds the second metal strip to form a non-closed ring structure.

9. The chip sealing ring according to claim 8, wherein: The fourth metal strip surrounds the third metal strip to form a non-closed ring structure. The first metal strips of each metal layer are connected, the second metal strips of each metal layer are connected, the third metal strips of each metal layer are connected, and the fourth metal strips of each metal layer are connected.

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