An adapter board and chip packaging structure

Abstract

This invention discloses an adapter board and a chip packaging structure. The adapter board includes: at least one signal transmission hole; at least one insulating dielectric isolation ring surrounding the signal transmission hole; at least one reverse-biased PN junction isolation ring surrounding the at least one insulating dielectric isolation ring, the reverse-biased PN junction isolation ring including a first conductivity type semiconductor ring and a second conductivity type semiconductor ring from the inside out, wherein the second conductivity type semiconductor ring is connected to a bias potential. The technical solution of this invention can reduce the coupling and crosstalk of signal channels in different signal transmission holes in the adapter board.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to an adapter board and a chip packaging structure. Background Art

[0002] With the increasing integration and storage capacity of semiconductor integrated circuits, three-dimensional packaging structures that stack individual chips have replaced traditional chip packaging structures. In these stacked chip three-dimensional packaging structures, conductive material is filled into the through-silicon vias on the adapter board to serve as signal transmission holes, enabling signal transmission between chips and between chips and the substrate.

[0003] However, as chip integration and complexity increase, the density of signal transmission holes on existing adapter boards continues to increase, which leads to an increase in coupling and crosstalk between signal channels in different signal transmission holes. Summary of the Invention

[0004] The main objective of this invention is to propose an adapter board and chip packaging structure, which aims to reduce the coupling and crosstalk of signal channels in different signal transmission holes in the adapter board.

[0005] To achieve the above objectives, embodiments of the present invention provide an adapter board, comprising:

[0006] At least one signal transmission hole;

[0007] At least one insulating dielectric isolation ring, wherein the insulating dielectric isolation ring surrounds one of the signal transmission holes;

[0008] At least one reverse-biased PN junction isolation ring, wherein one of the reverse-biased PN junction isolation rings surrounds at least one of the insulating dielectric isolation rings, the reverse-biased PN junction isolation ring comprising a first conductivity type semiconductor ring and a second conductivity type semiconductor ring from the inside out, wherein the second conductivity type semiconductor ring is connected to a bias potential.

[0009] To achieve the above objectives, embodiments of the present invention also propose a chip packaging structure, comprising:

[0010] A substrate having at least one pad disposed thereon;

[0011] The adapter board is located on the surface of the substrate. The adapter board is as described in any of the above technical solutions, and a signal transmission hole is coupled to a pad.

[0012] The chip is located on the side of the adapter board away from the substrate, and the chip is provided with connection pads, which are coupled to the signal transmission hole.

[0013] In the technical solution of this invention embodiment, under the coupling effect of the first conductive type semiconductor ring and the signal channel in the signal transmission hole, the potential of the first conductive type semiconductor ring is the signal coupling potential, and the second conductive type semiconductor ring is connected to the bias potential. A space charge region exists at the interface between the first and second conductive type semiconductor rings. Since the first and second conductive type semiconductor rings form a reverse-biased PN junction isolation ring, a depletion layer exists within the space charge region. This depletion layer can isolate and shield the signal transmission hole, thereby reducing the coupling and crosstalk between signal channels in different signal transmission holes in the adapter board. Furthermore, the stronger the signal strength within the signal channel of the signal transmission hole, the greater the signal coupling potential of the first conductive type semiconductor ring. The thicker the depletion layer within the space charge region, the stronger the isolation and shielding effect of the reverse-biased PN junction isolation ring on the signal transmission hole. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of an adapter plate in the prior art;

[0015] Figure 2 This is a schematic diagram of the structure of an adapter plate provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of another adapter plate provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of another adapter plate provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of a chip packaging structure provided in an embodiment of the present invention. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no inherent meaning. Therefore, "module," "part," or "unit" may be used interchangeably.

[0021] As described in the background section above, the increasing density of signal transmission holes on existing adapter boards leads to a corresponding increase in coupling and crosstalk between signal channels in different signal transmission holes. Figure 1 This is a schematic diagram of the structure of an adapter plate in the prior art. Figure 1 b is Figure 1 Cross-sectional view along the A1-A2 direction in section a. See also Figure 1 The adapter board includes at least one signal transmission hole 101 and an insulating dielectric isolation ring 102 surrounding the signal transmission hole 101. As the density of the signal transmission holes 101 increases, the coupling and crosstalk between the signal channels in different signal transmission holes 101 also increase.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide an adapter board designed to reduce coupling and crosstalk between signal channels in different signal transmission holes within the adapter board.

[0023] Figure 2 This is a schematic diagram of the structure of an adapter plate provided in an embodiment of the present invention. Figure 2 b is Figure 2 Cross-sectional view along direction B1-B2 in section a. See also Figure 2 The adapter board includes: at least one signal transmission hole 101; at least one insulating dielectric isolation ring 102 surrounding a signal transmission hole 101; at least one reverse bias PN junction isolation ring 103 surrounding at least one insulating dielectric isolation ring 102, the reverse bias PN junction isolation ring 103 including a first conductivity type semiconductor ring 103A and a second conductivity type semiconductor ring 103B from the inside out, the second conductivity type semiconductor ring 103B being connected to a bias potential.

[0024] In the prior art, signal channels in different signal transmission holes 101 may be coupled and crosstalked through the insulating dielectric isolation ring 102.

[0025] For example, Figure 2 The diagrams show the case where a reverse-biased PN junction isolation ring 103 surrounds one insulating dielectric isolation ring 102, and the case where a reverse-biased PN junction isolation ring 103 surrounds two insulating dielectric isolation rings 102.

[0026] In this embodiment, under the coupling effect of the first conductivity type semiconductor ring 103A and the signal channel in the signal transmission hole 101, the potential of the first conductivity type semiconductor ring 103A is the signal coupling potential, and the second conductivity type semiconductor ring 103B is connected to the bias potential. A space charge region exists at the interface between the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B. Since the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B constitute a reverse bias PN junction isolation ring 103, a depletion layer exists within the space charge region. This depletion layer can isolate and shield the signal transmission hole 101, thereby reducing the coupling and crosstalk between signal channels in different signal transmission holes 101 in the adapter board. Furthermore, the stronger the signal strength in the signal channel of the signal transmission hole 101, the larger the signal coupling potential of the first conductivity type semiconductor ring 103A. The thicker the depletion layer in the space charge region, the stronger the isolation and shielding effect of the reverse bias PN junction isolation ring 103 on the signal transmission hole 101.

[0027] Optionally, see Figure 2 The signal channels of the signal transmission holes 101 distributed in the space surrounded by the reverse bias PN junction isolation ring 103 are coupled to each other.

[0028] Specifically, Figure 2The example illustrates a reverse-biased PN junction isolation ring 103 surrounding two insulating dielectric isolation rings 102. Specifically, when there are two signal transmission holes 101 distributed within the space surrounded by the reverse-biased PN junction isolation ring 103, the signal channels of these two signal transmission holes 101 are mutually coupled. The signal in the signal channel of one signal transmission hole 101 is coupled to the signal in the signal channel of the other signal transmission hole 101. The depletion layer within the reverse-biased PN junction isolation ring 103 can isolate and shield the signal transmission holes 101 between the inside and outside of the space surrounded by the reverse-biased PN junction isolation ring 103, thereby reducing the coupling and crosstalk between the signal channels of different signal transmission holes 101 between the inside and outside of the space surrounded by the reverse-biased PN junction isolation ring 103 in the adapter board. Furthermore, the stronger the signal in the signal channel of the signal transmission hole 101, the greater the signal coupling potential of the first conductivity type semiconductor ring 103A. The thicker the depletion layer within the space charge region, the stronger the isolation and shielding effect of the reverse-biased PN junction isolation ring 103 on the signal transmission aperture 101. Furthermore, the signal transmission apertures 101, with their signal channels mutually coupled, are distributed within a space surrounded by the reverse-biased PN junction isolation ring 103, reducing the area occupied by the reverse-biased PN junction isolation ring 103 in the adapter board, improving the integration density of the adapter board, and lowering its manufacturing cost. It should be noted that conductive interconnects can be used to electrically connect different signal transmission apertures 101 to the same conductive interconnect, thereby achieving mutual coupling of the signal channels of different signal transmission apertures 101. This embodiment of the invention does not limit the number of signal transmission apertures 101 distributed within the space surrounded by the reverse-biased PN junction isolation ring 103.

[0029] In the above technical solution, the depletion layer in the reverse bias PN junction isolation ring 103 can isolate and shield the signal transmission hole 101, thereby reducing the coupling and crosstalk of signal channels in different signal transmission holes 101 in the adapter board.

[0030] Optionally, see Figure 2 The signal transmission holes 101 are evenly distributed in the space surrounded by the reverse bias PN junction isolation ring 103.

[0031] Specifically, the signal transmission holes 101 are evenly distributed in the space surrounded by the reverse bias PN junction isolation ring 103, so that the signal transmission holes 101 are evenly distributed in the space surrounded by the depletion layer in the reverse bias PN junction isolation 103, so as to uniformly reduce the coupling and crosstalk of the signal channels in different signal transmission holes 101 in the adapter board.

[0032] Optionally, see Figure 2A reverse bias PN junction isolation ring 103 surrounds an insulating dielectric isolation ring 102, and the signal transmission hole 101 and the reverse bias PN junction isolation ring 103 are coaxially arranged.

[0033] Specifically, a reverse bias PN junction isolation ring 103 surrounds an insulating dielectric isolation ring 102. The signal transmission hole 101 and the reverse bias PN junction isolation ring 103 are coaxially arranged to ensure that the signal transmission hole 101 is evenly distributed in the space surrounded by the depletion layer within the reverse bias PN junction isolation ring 103, so as to uniformly reduce the coupling and crosstalk of signal channels in different signal transmission holes 101 in the adapter board.

[0034] Optionally, the first conductivity type includes N-type, the second conductivity type includes P-type, and the second conductivity type semiconductor ring 103B is grounded.

[0035] Specifically, the first conductivity type semiconductor ring 103A is an N-type semiconductor ring, and the second conductivity type semiconductor ring 103B is a P-type semiconductor ring. The potential of the first conductivity type semiconductor ring 103A is the signal coupling potential, and the second conductivity type semiconductor ring is grounded to ensure that the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B are in a reverse bias state. A space charge region exists at the interface between the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B. A depletion layer exists within the space charge region. This depletion layer can isolate and shield the signal transmission hole 101, reducing coupling and crosstalk between signal channels in different signal transmission holes 101 in the adapter board. Furthermore, the stronger the electrical signal in the signal channel of the signal transmission hole 101, the larger the signal coupling potential. The thicker the depletion layer in the space charge region, the stronger the isolation and shielding effect of the reverse bias PN junction isolation ring 103 on the signal transmission hole 101.

[0036] Optionally, the first conductivity type includes P-type, the second conductivity type includes N-type, the second conductivity type semiconductor ring 103B is connected to the first potential, and the first potential is greater than the signal coupling potential of the first conductivity type semiconductor ring 103A.

[0037] The first conductivity type semiconductor ring 103A is a P-type semiconductor ring, and the second conductivity type semiconductor ring 103B is an N-type semiconductor ring. The potential of the first conductivity type semiconductor ring 103A is the signal coupling potential, and the second conductivity type semiconductor ring 103B is connected to the first potential to ensure that the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B are in a reverse bias state. The first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B constitute a reverse bias PN junction isolation ring 103. A depletion layer exists within the space charge region. The depletion layer within the space charge region can isolate and shield the signal transmission hole 101 to reduce the coupling and crosstalk of signal channels in different signal transmission holes 101 in the adapter board. The stronger the electrical signal in the signal channel of the signal transmission hole 101, the larger the value of the first potential. The thicker the depletion layer in the space charge region, the stronger the isolation and shielding effect of the reverse bias PN junction isolation ring 103 on the signal transmission hole 101.

[0038] In the above technical solution, the adapter board includes an insulating dielectric isolation ring 102 and a reverse bias PN junction isolation ring 103 to reduce the coupling and crosstalk of signal channels in different signal transmission holes 101 in the adapter board. The specific structure of the adapter board is described in detail below. Figure 3 This is a schematic diagram of another adapter plate provided in an embodiment of the present invention. Figure 3 b is Figure 3 A cross-sectional view along the B1-B2 direction in section a. Optionally, see... Figure 3 The adapter plate also includes a first conductive type semiconductor substrate 10, which has at least one through hole 10A and at least one second conductive type semiconductor ring 103B. An insulating dielectric material 10B and a conductive pillar 10C are arranged sequentially from the outside to the inside of the through hole 10A. The insulating dielectric material 10B forms an insulating dielectric isolation ring 102, and the conductive pillar 10C forms a signal transmission hole 101. A second conductive type semiconductor ring 103B surrounds at least one through hole 10A and is spaced at a predetermined distance from the through hole 10A. The first conductive type semiconductor substrate 10 between the through hole 10A and the second conductive type semiconductor ring 103B forms the first conductive type semiconductor ring 103A.

[0039] For example, the first conductivity type semiconductor substrate 10 can be a first conductivity type silicon substrate. The entire adapter board is fabricated on the first conductivity type silicon substrate. Through-hole 10A is formed by etching. Insulating dielectric material 10B and conductive pillar 10C are sequentially disposed on the inner wall of through-hole 10A. The insulating dielectric material 10B forms an insulating dielectric isolation ring 102, and the conductive pillar 10C forms a signal transmission hole 101. Afterwards, the surfaces of the first conductivity type silicon substrate 10, the insulating dielectric material 10B, and the conductive pillar 10C can be mechanically and chemically polished until the surfaces of the first conductivity type silicon substrate 10 and the through-hole 10A are smooth and flat. Among them, the insulating dielectric isolation ring 102 formed by the insulating dielectric material 10B plays an isolation and shielding role for the signal transmission hole 101 formed by the conductive pillar 10C. Under the coupling effect of the signal channel in the first conductivity type semiconductor ring 103A and the signal transmission hole 101, the potential of the first conductivity type semiconductor ring 103A is the signal coupling potential, and the second conductivity type semiconductor ring 103B is connected to the bias potential. A space charge region exists at the interface between the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B. Since the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B form a reverse bias PN junction isolation ring 103, a depletion layer exists within the space charge region. This depletion layer can isolate and shield the signal transmission hole 101, thereby reducing the coupling and crosstalk between signal channels in different signal transmission holes 101 in the adapter board. Furthermore, the stronger the signal intensity within the signal channel of the signal transmission hole 101, the greater the signal coupling potential of the first conductivity type semiconductor ring 103A. The thicker the depletion layer within the space charge region, the stronger the isolation and shielding effect of the reverse bias PN junction isolation ring 103 on the signal transmission hole 101.

[0040] Optionally, the material of the second conductivity type semiconductor ring 103B includes one or more of the second conductivity type metal oxide, the second conductivity type elemental semiconductor material, and the second conductivity type compound semiconductor material.

[0041] For example, let's take N-type as the first conductivity type and P-type as the second conductivity type. Aluminum-doped zinc oxide and tin-doped silver oxide can be used as P-type metal oxides. P-type impurity-doped silicon can be used as P-type elemental semiconductor materials. P-type impurity-doped gallium nitride can be used as P-type compound semiconductor materials.

[0042] It should be noted that the fabrication process of the second conductivity type semiconductor ring 103B can be achieved by ion doping on the first conductivity type semiconductor substrate 10. Alternatively, it can be achieved by etching through holes in the first conductivity type semiconductor substrate 10 and filling the through holes with one or more of the following: a second conductivity type metal oxide, a second conductivity type elemental semiconductor material, and a second conductivity type compound semiconductor material.

[0043] For example, the material of the conductive post 10C can be copper and / or aluminum, which have good conductivity and are inexpensive.

[0044] In a three-dimensional packaging structure that stacks individual chips, the signal transmission hole 101 on the adapter board is used to realize signal transmission between chips and between a chip and a substrate. Static charge can be transferred to the chip through the signal transmission hole 101. Since different chips have different anti-static capabilities, chips with weak anti-static capabilities will have their performance significantly affected by static charge. To solve the above technical problems, embodiments of the present invention provide the following technical solution:

[0045] Figure 4 This is a schematic diagram of another adapter plate provided in an embodiment of the present invention. Figure 4 b is Figure 4 A cross-sectional view along the C1-C2 direction in a. Figure 4 c is Figure 4 Another cross-sectional view along the C1-C2 direction in section a. See also Figure 4 The adapter board also includes at least one anti-static device 104 located on the surface of the first conductive type semiconductor ring 103A. The anti-static device 104 includes a first connection end 104A and a second connection end 104B. The first connection end 104A is connected to the signal transmission hole 101 through a conductive interconnect line 105, and the second connection end 104B is connected to the second conductive type semiconductor ring 103B through a conductive interconnect line 105.

[0046] It should be noted that, see Figure 4 The conductive interconnect 105 is coupled to the antistatic device 104 and the first conductive type semiconductor ring 103A through the conductive via 20A passing through the passivation layer 20.

[0047] Specifically, when there is static charge in the signal channel of the signal transmission hole 101, it will be coupled to the second conductive type semiconductor ring 103B through the anti-static device 104. Since the second conductive type semiconductor ring 103B is connected to the bias potential, when the static charge in the signal channel of the signal transmission hole 101 is large enough to break down the anti-static device 104, the anti-static device 104 and the second conductive type semiconductor ring 103B connected to the bias potential form a vertical static charge discharge channel. The static charge is coupled to the bias potential through the anti-static device 104, which can prevent the static charge from being transferred to the chip or substrate through the signal transmission hole 101 and affecting the performance of the chip and chip packaging structure.

[0048] Optionally, see Figure 4 b. The anti-static device 104 includes a reverse bias diode; the first electrode of the reverse bias diode is connected to the signal transmission hole 101 via a conductive interconnect 105 as a first connection terminal 104A, and the second electrode of the reverse bias diode is connected to the second conductivity type semiconductor ring 103B via a conductive interconnect 105 as a second connection terminal 104B.

[0049] For details, see Figure 4 b. Taking an N-type semiconductor ring with a grounded second conductivity type as an example, the reverse bias diode includes an N-type doped region 104C. An N+ region is formed in the N-type doped region using ion implantation as the first electrode and the first connection terminal 104A, and a P+ region is formed as the second electrode and the second connection terminal 104B. This ensures that the anti-static device 104 is a reverse bias diode. When the static charge in the signal channel of the signal transmission hole 101 is relatively small, the reverse bias diode is in a reverse bias state. When the static charge in the signal channel of the signal transmission hole 101 is too large, it will break down the reverse bias diode. The reverse bias diode and the second conductivity type semiconductor ring 103B connected to the bias potential form a vertical static charge discharge channel. The static charge is coupled to the second conductivity type semiconductor ring 103B through the reverse bias diode. Since the second conductivity type semiconductor ring 103B is grounded, the static charge can be prevented from being transferred to the chip or substrate through the signal transmission hole 101, thus avoiding affecting the performance of the chip and chip packaging structure. It should be noted that the N-type doped region 104C has a higher carrier concentration than the first conductivity type semiconductor ring 103A.

[0050] Optionally, see Figure 4 c. The anti-static device 104 includes a metal-oxide-semiconductor field-effect transistor (MOSFET); the gate of the MOSFET is connected to the signal transmission hole 101 via a conductive interconnect 105 as a first connection terminal 104A, and the source or drain of the MOSFET is connected to the second conductivity type semiconductor ring 103B via a conductive interconnect 105 as a second connection terminal 104B.

[0051] For details, see Figure 4 c. Taking an N-type semiconductor ring with a grounded second conductivity type as an example, the metal-oxide-semiconductor (MOSFET) includes an N-type doped region 104C. Two P+ regions and an N+ region are formed in the N-type doped region using ion implantation. The N+ region serves as the gate of the MOSFET, i.e., the first connection terminal 104A. The P+ region serves as the source or drain of the MOSFET, i.e., the second connection terminal 104B. When the static charge in the signal channel of the signal transmission aperture 101 is low, the MOSFET is in the off state. When the static charge in the signal channel of the signal transmission aperture 101 is high, the MOSFET is in the on state. The MOSFET and the second conductivity type semiconductor ring 103B, which is biased, form a vertical static charge discharge channel. The static charge is coupled to the second conductivity type semiconductor ring 103B through the MOSFET. Since the second conductivity type semiconductor ring 103B is grounded, static charge is prevented from being transferred to the chip or substrate through the signal transmission aperture 101, thus avoiding impact on chip performance.

[0052] Optionally, the insulating dielectric isolation ring 102 may be made of silicon oxide and / or aluminum oxide.

[0053] Specifically, silicon oxide and / or aluminum oxide are high dielectric insulating materials that can isolate and shield the signal transmission hole 101.

[0054] This invention also provides a chip packaging structure. Figure 5 This is a schematic diagram of a chip packaging structure provided in an embodiment of the present invention. See also... Figure 5 The chip packaging structure includes: a substrate 30, on which at least one pad 30A is disposed; an adapter plate 100 located on the surface of the substrate 30, the adapter plate 100 being any of the adapter plates described in the above technical solutions, a signal transmission hole 101 being coupled to a pad 30A; and a chip 40 located on the side of the adapter plate 100 away from the substrate 30, the chip 40 being provided with a connection pad 40A, the connection pad 40A being coupled to the signal transmission hole 101.

[0055] It should be noted that the pads 30A on the substrate 30 are coupled to the signal transmission holes 101 through conductive vias 20A passing through the passivation layer 20. The connection pads 40A of the chip 40 are also coupled to the signal transmission holes 101 through conductive vias 20A passing through the passivation layer 20. Conductive interconnects can be provided on the substrate 30, allowing different signal transmission holes 101 to be electrically connected to the same conductive interconnect, thereby achieving mutual coupling of the signal channels of different signal transmission holes 101.

[0056] In this embodiment, the signal transmission hole 101 on the adapter plate 100 is used to realize signal transmission between chips 40 and between chips 40 and substrate 30. Under the coupling effect of the first conductivity type semiconductor ring 103A and the signal channel in the signal transmission hole 101, the potential of the first conductivity type semiconductor ring 103A is the signal coupling potential, and the second conductivity type semiconductor ring 103B is connected to the bias potential. There is a space charge region at the interface of the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B. Since the first conductivity type semiconductor ring 103A and the second conductivity type semiconductor ring 103B form a reverse bias PN junction isolation ring 103, there is a depletion layer in the space charge region. The depletion layer in the space charge region can play a role in isolating and shielding the signal transmission hole 101, so as to reduce the coupling and crosstalk of the signal channels in different signal transmission holes 101 in the adapter plate. Moreover, the stronger the signal in the signal channel in the signal transmission hole 101, the larger the value of the signal coupling potential of the first conductivity type semiconductor ring 103A. The thicker the depletion layer in the space charge region, the stronger the isolation and shielding effect of the reverse bias PN junction isolation ring 103 on the signal transmission hole 101.

[0057] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0058] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0059] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but this does not limit the scope of the invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of the present invention should be within the scope of the present invention.

Claims

1. An adapter board, characterized in that, include: At least one signal transmission hole; At least one insulating dielectric isolation ring, wherein the insulating dielectric isolation ring surrounds one of the signal transmission holes; At least one reverse-biased PN junction isolation ring, wherein the reverse-biased PN junction isolation ring surrounds at least one insulating dielectric isolation ring, the reverse-biased PN junction isolation ring comprising a first conductivity type semiconductor ring and a second conductivity type semiconductor ring from the inside out, wherein the second conductivity type semiconductor ring is connected to a bias potential; At least one anti-static device is located on the surface of the first conductive type semiconductor ring. The anti-static device includes a first connection terminal and a second connection terminal. The first connection terminal is connected to a signal transmission hole through a conductive interconnect line, and the second connection terminal is connected to the second conductive type semiconductor ring through a conductive interconnect line.

2. The adapter board according to claim 1, characterized in that, The signal channels of the signal transmission holes distributed within the space surrounded by the reverse bias PN junction isolation ring are coupled to each other.

3. The adapter board according to claim 1, characterized in that, The signal transmission holes are evenly distributed within the space surrounded by the reverse bias PN junction isolation ring.

4. The adapter board according to claim 1, characterized in that, A reverse-biased PN junction isolation ring surrounds an insulating dielectric isolation ring, and the signal transmission port and the reverse-biased PN junction isolation ring are coaxially arranged.

5. The adapter board according to claim 1, characterized in that, The first conductivity type includes N-type, the second conductivity type includes P-type, and the second conductivity type semiconductor ring is grounded.

6. The adapter board according to claim 1, characterized in that, It also includes a first conductivity type semiconductor substrate, wherein the first conductivity type semiconductor substrate is provided with at least one through hole and at least one second conductivity type semiconductor ring; An insulating dielectric material and a conductive post are sequentially arranged from the outside to the inside of the through hole. The insulating dielectric material constitutes the insulating dielectric isolation ring, and the conductive post constitutes the signal transmission hole. A second type of conductive semiconductor ring surrounds at least one of the vias and is spaced at a predetermined distance from the vias. A first type of conductive semiconductor substrate between the vias and the second type of conductive semiconductor ring constitutes the first type of conductive semiconductor ring.

7. The adapter board according to claim 1, characterized in that, The anti-static device includes a reverse bias diode; the first electrode of the reverse bias diode serves as the first connection terminal and is connected to the signal transmission hole via a conductive interconnect line, and the second electrode of the reverse bias diode serves as the second connection terminal and is connected to the second conductivity type semiconductor ring via a conductive interconnect line.

8. The adapter board according to claim 1, characterized in that, The anti-static device includes a metal oxide semiconductor field-effect transistor; The gate of the metal-oxide-semiconductor field-effect transistor (MOSFET) serves as the first connection terminal and is connected to the signal transmission hole via a conductive interconnect line. The source or drain of the MOSFET serves as the second connection terminal and is connected to the second conductivity type semiconductor ring via a conductive interconnect line.

9. The adapter board according to claim 1, characterized in that, The insulating dielectric isolation ring is made of silicon oxide and / or aluminum oxide.

10. A chip packaging structure, characterized in that, include: A substrate having at least one pad disposed thereon; The adapter board is located on the surface of the substrate, and the adapter board is the adapter board as described in any one of claims 1-9, wherein a signal transmission hole is coupled to a pad; The chip is located on the side of the adapter board away from the substrate, and the chip is provided with connection pads, which are coupled to the signal transmission hole.

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