Single-ended trans-differential transimpedance amplifier

Abstract

This invention discloses a single-ended to differential transimpedance amplifier, comprising a main transimpedance amplifier, a redundant transimpedance amplifier, and capacitors C1 and C2. The main transimpedance amplifier includes field-effect transistors M1 and M3, a feedback resistor Rf1, a load resistor RL1, and an AC coupling capacitor Cc. The drain of M1 is grounded, the gate of M3 is connected to a bias voltage VB, and the drain of M3 is connected to the source of M1. One end of Rf1 is connected to the base of M1, and the other end is connected to the source of M3. One end of RL1 is connected to the source of M3, and the other end is connected to an external voltage. The redundant transimpedance amplifier includes M2 and M4, a feedback resistor Rf2, and a load resistor RL2. One end of Cc is connected to the drain of M3, and the other end is connected to the gate of M2. C1 and C2 form a capacitively coupled AC coupling pair; one end of C1 is connected to the source of M2, and the other end is connected to the base of M4; one end of C2 is connected to the source of M4, and the other end is connected to the base of M3. Compared with existing technologies, this invention achieves better output symmetry and robustness. When the small-signal transconductances of M3 and M4 are the same, the output can be symmetrical. The small-signal transconductances of M3 and M4 are easier to satisfy during circuit operation, resulting in better robustness.

Description

Technical Field

[0001] This invention relates to a single-ended to differential transimpedance amplifier in the field of front-end design of optoelectronic receivers, and more particularly to a single-ended to differential transimpedance amplifier. Background Technology

[0002] Traditional transimpedance amplifiers use single-ended input, therefore they often employ pseudo-differential structures to suppress common-mode noise, such as... Figure 1 As shown. The specific principle is that the input signal passes through the main transimpedance amplifier, with single-ended input and single-ended output. Simultaneously, a redundant transimpedance amplifier is added, which only outputs a DC level and does not output a signal. This increases chip area and power consumption. Recently, researchers have conducted some research on this problem, for example proposing a mirrored differential transimpedance amplifier, which realizes the function of single-ended input and differential output of the transimpedance amplifier. However, the conditions for achieving differential output with this structure are difficult to meet in practical applications. For example... Figure 2 The circuit diagram of the single-ended to differential transimpedance amplifier shown is taken from SGKim et al., "A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol.54, no.5, pp.1468-1474, May 2019. The condition for achieving differential output is gm2 = gm3, where gm2 is the transconductance of field-effect transistor M2 and gm3 is the transconductance of field-effect transistor M3. However, it is difficult to achieve matching between transistors M2 and M3 during operation, therefore the condition of equal transconductance between M2 and M3 is difficult to satisfy. Summary of the Invention

[0003] To address the problem that it is difficult to meet the output conditions of a single-ended to differential structure, this invention provides a single-ended to differential transimpedance amplifier.

[0004] To achieve the above objectives, the present invention employs the following technical solution: a single-ended to differential transimpedance amplifier, comprising a main transimpedance amplifier, a redundant transimpedance amplifier, and capacitors C1 and C2;

[0005] The main transimpedance amplifier includes a field-effect transistor M1, the gate of which serves as the input current I of the single-ended to differential transimpedance amplifier. in +, the drain of field-effect transistor M1 is electrically grounded; field-effect transistor M3, the gate of field-effect transistor M3 is connected to the bias voltage VB, the drain of field-effect transistor M3 is electrically connected to the source of field-effect transistor M1, and the source of field-effect transistor M3 serves as the output voltage Vout+ of the single-ended to differential transimpedance amplifier; feedback resistor Rf1, one end of feedback resistor Rf1 is electrically connected to the base of field-effect transistor M1, and the other end of feedback resistor Rf1 is electrically connected to the source of field-effect transistor M3; load resistor RL1, one end of load resistor RL1 is electrically connected to the source of field-effect transistor M3, and the other end of load resistor RL1 is connected to the external voltage VDD; and AC coupling capacitor Cc, one end of AC coupling capacitor Cc is connected to the drain of field-effect transistor M3;

[0006] The redundant transimpedance amplifier includes: a field-effect transistor M2, the gate of which is electrically connected to the other end of an AC coupling capacitor Cc, and the drain of which is electrically grounded; a field-effect transistor M4, the gate of which is connected to a bias voltage VB, and the drain of which is electrically connected to the source of which is connected to the source of which is connected to the source of which is connected to the single-ended to differential transimpedance amplifier; a feedback resistor Rf2, one end of which is electrically connected to the base of which is connected to the source of which is connected to the source of which is connected to the source of which is connected to the source of which is connected to the source of which is connected to the single-ended to differential transimpedance amplifier; and a load resistor RL2, one end of which is electrically connected to the source of which is ... the source of which is connected to the source of the source of which is connected to the source of the source of which is connected to the source of the source of which is connected to the source of the source of which is connected to the source of the source of

[0007] Capacitors C1 and C2 form a capacitively coupled AC coupling pair. One end of capacitor C1 is electrically connected to the source of field-effect transistor M3, and the other end of capacitor C1 is electrically connected to the base of field-effect transistor M4. One end of capacitor C2 is electrically connected to the source of field-effect transistor M4, and the other end of capacitor C2 is electrically connected to the base of field-effect transistor M3.

[0008] Regarding output symmetry, the capacitively coupled AC coupling pair added in this invention can be equivalent to two pairs of CS-CG (common source-common gate) single-ended to differential pairs. A second signal transmission path is introduced based on the existing path of the AC coupling capacitor Cc, making the differential output more symmetrical. Compared with existing technologies, the differential output conditions of this invention are easier to meet, thus exhibiting better robustness in practical applications. Simultaneously, the proposed circuit structure can better improve output symmetry and reduce gain and phase errors.

[0009] As a further improvement to the above scheme, the single-ended to differential transimpedance amplifier further includes: a voltage divider resistor R1, one end of which is electrically connected to the base of the field-effect transistor M3, and the other end of which is connected to the bias voltage VB; and a voltage divider resistor R2, one end of which is electrically connected to the base of the field-effect transistor M4, and the other end of which is connected to the bias voltage VB.

[0010] As a further improvement to the above scheme, the single-ended to differential transimpedance amplifier further includes: a light-emitting diode VD, the anode of the light-emitting diode VD being electrically connected to the base of the field-effect transistor M1, and the cathode of the light-emitting diode VD being connected to the input current I. in +.

[0011] As a further improvement to the above scheme, the bias voltage VB is an external voltage from outside the single-ended to differential transimpedance amplifier, or an internal voltage from inside the single-ended to differential transimpedance amplifier.

[0012] The present invention also provides a single-ended to differential transimpedance amplifier module, which employs any of the above-mentioned single-ended to differential transimpedance amplifiers, and the single-ended to differential transimpedance amplifier module includes at least the following terminals:

[0013] The non-inverting input terminal is used to input the input current I. in +;

[0014] The non-inverting output terminal is used to output the output voltage Vout+;

[0015] The inverting output terminal is used to output the output voltage Vout-.

[0016] The power supply terminal is used to input the external voltage VDD.

[0017] Grounding terminal, used for electrical grounding.

[0018] As a further improvement to the above solution, when the bias voltage VB is an external voltage from outside the single-ended to differential transimpedance amplifier, the single-ended to differential transimpedance amplifier module further includes the following terminals:

[0019] The bias voltage input terminal is used to connect the bias voltage VB.

[0020] The present invention also provides a 25Gbps differential transimpedance amplifier, which includes an input stage amplifier, a continuous linear time equalizer amplifier, and an output buffer stage amplifier connected in sequence; the input stage amplifier adopts any of the above-mentioned single-ended to differential transimpedance amplifiers.

[0021] As a further improvement to the above scheme, the output voltage Vout+ and output voltage Vout- of the single-ended to differential transimpedance amplifier are respectively connected to the non-inverting input terminal and the inverting input terminal of the continuous linear time equalizer amplifier, and the non-inverting output terminal and the inverting output terminal of the continuous linear time equalizer amplifier are respectively connected to the non-inverting input terminal and the inverting input terminal of the output buffer stage amplifier.

[0022] Specifically, the non-inverting and inverting output terminals of the output buffer stage amplifier serve as the two output terminals of the 25Gbps differential transimpedance amplifier; the input current I of the single-ended to differential transimpedance amplifier... in + serves as the input to the 25Gbps differential transimpedance amplifier.

[0023] Furthermore, the 25Gbps differential transimpedance amplifier also includes:

[0024] Resistor R3, one end of which is electrically connected to the non-inverting output terminal of the output buffer stage amplifier, and the other end of which is connected to the external voltage VDD.

[0025] Resistor R4, one end of which is electrically connected to the inverting output terminal of the output buffer stage amplifier, and the other end of which is connected to the external voltage VDD.

[0026] The present invention also provides a four-channel 100Gbps transimpedance amplifier, which employs four 25Gbps differential transimpedance amplifiers connected in parallel, wherein the 25Gbps differential transimpedance amplifiers are any of the aforementioned 25Gbps differential transimpedance amplifiers.

[0027] Compared with existing technologies, this invention achieves better output symmetry and robustness. Small-signal analysis of the proposed circuit derives the small-signal gain of the differential output in the mid-frequency band. When the small-signal transconductances of field-effect transistors M3 and M4 are the same, the output symmetry is achieved. The small-signal transconductances of field-effect transistors M3 and M4 are more easily satisfied during circuit operation, thus resulting in better robustness.

[0028] Compared with existing technologies, the differential output conditions of this invention are easier to meet, exhibiting better robustness and achieving better output symmetry. Small-signal analysis of the proposed circuit allows for the derivation of the small-signal gain for differential output in the mid-frequency band. Differential output can be achieved when the small-signal transconductances of field-effect transistors M3 and M4 are the same. Compared with the existing technology in the background section (Reference 1), the small-signal transconductances of field-effect transistors M3 and M4 are easier to meet during circuit operation, thus resulting in better robustness. Regarding output symmetry, the capacitively coupled AC coupling pair added in this invention can be equivalent to two pairs of CS-CG (common-source-common-gate) single-ended to differential pairs: a second signal transmission path is introduced based on the existing path of the AC coupling capacitor Cc, making the differential output more symmetrical. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a pseudo-differential structure circuit for a traditional transimpedance amplifier using a single-ended input.

[0031] Figure 2 The circuit diagram is shown for the single-ended to differential transimpedance amplifier in Reference 1.

[0032] Figure 3 The circuit diagram of a single-ended to differential transimpedance amplifier provided in an embodiment of the present invention.

[0033] Figure 4 for Figure 3 A schematic diagram of the circuit path for a single-ended to differential transimpedance amplifier.

[0034] Figure 5 for Figure 3 A comparison image of the gain error between a single-ended to differential transimpedance amplifier and a traditional single-ended to differential transimpedance amplifier.

[0035] Figure 6 for Figure 3 A comparison image of the phase error between a single-ended to differential transimpedance amplifier and a traditional single-ended to differential transimpedance amplifier.

[0036] Figure 7 For application Figure 3 A schematic diagram of a single-ended to differential transimpedance amplifier module.

[0037] Figure 8 For application Figure 7A circuit diagram of a 25Gbps differential transimpedance amplifier in a single-ended to differential transimpedance amplifier module.

[0038] Figure 9 For application Figure 8 A circuit diagram of a four-channel 100Gbps transimpedance amplifier with a 25Gbps differential transimpedance amplifier. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] Please see Figure 3 and Figure 4 The single-ended to differential transimpedance amplifier in this embodiment mainly includes a main transimpedance amplifier 1 and a redundant transimpedance amplifier 2.

[0041] The main transimpedance amplifier 1 includes a field-effect transistor M1, a field-effect transistor M3, a feedback resistor Rf1, a load resistor RL1, an AC coupling capacitor Cc, and may also include a voltage divider resistor R1 and a light-emitting diode VD.

[0042] The gate of the field-effect transistor M1 serves as the input current i of the single-ended to differential transimpedance amplifier. in +, the drain of field-effect transistor M1 is electrically grounded; the gate of field-effect transistor M3 is connected to the bias voltage VB, and the drain of field-effect transistor M3 is electrically connected to the source of field-effect transistor M1. The source of field-effect transistor M3 serves as the output voltage Vout+ of the single-ended to differential transimpedance amplifier; one end of feedback resistor Rf1 is electrically connected to the base of field-effect transistor M1, and the other end of feedback resistor Rf1 is electrically connected to the source of field-effect transistor M3; one end of load resistor RL1 is electrically connected to the source of field-effect transistor M3, and the other end of load resistor RL1 is connected to the external voltage VDD; one end of AC coupling capacitor Cc is connected to the drain of field-effect transistor M3. Voltage divider resistor R1 is connected, with one end electrically connected to the base of field-effect transistor M3 and the other end connected to the bias voltage VB. The anode of light-emitting diode VD is electrically connected to the base of field-effect transistor M1, and the cathode of light-emitting diode VD is connected to the input current i. in +.

[0043] The bias voltage VB can be an external voltage from outside the single-ended to differential transimpedance amplifier, or it can be an internal voltage from inside the single-ended to differential transimpedance amplifier.

[0044] The redundant transimpedance amplifier includes field-effect transistor M2, field-effect transistor M4, feedback resistor Rf2, load resistor RL2, and may also include voltage divider resistor R2.

[0045] The gate of field-effect transistor M2 is electrically connected to the other end of AC coupling capacitor Cc, and the drain of field-effect transistor M2 is electrically grounded. The gate of field-effect transistor M4 is connected to a bias voltage VB, and the drain of field-effect transistor M4 is electrically connected to the source of field-effect transistor M2. The source of field-effect transistor M4 serves as the output voltage Vout- of the single-ended to differential transimpedance amplifier. One end of feedback resistor Rf2 is electrically connected to the base of field-effect transistor M2, and the other end of feedback resistor Rf2 is electrically connected to the source of field-effect transistor M4. One end of load resistor RL2 is electrically connected to the source of field-effect transistor M4, and the other end of load resistor RL2 is connected to an external voltage VDD. A voltage divider resistor R2 is connected, with one end electrically connected to the base of field-effect transistor M4 and the other end connected to the bias voltage VB.

[0046] In this embodiment, the single-ended to differential transimpedance amplifier is configured with an external voltage VDD and ground GND separately. In other embodiments, the external voltage VDD and ground GND can also be configured with the single-ended to differential transimpedance amplifier, without the need for separate configuration of external voltage VDD and ground GND.

[0047] This embodiment of the single-ended to differential transimpedance amplifier uses a main amplifier section based on a parallel feedback transimpedance amplifier structure. It receives the input current signal and amplifies it into a voltage signal for output. To achieve the single-ended to differential function, the redundant amplifier section receives a portion of the main amplifier's output signal and amplifies it into a voltage signal for output. In the main transimpedance amplifier, field-effect transistors M1 and M3, load resistor RL1, and feedback resistor Rf1 constitute the aforementioned basic parallel feedback transimpedance amplifier. Similarly, in the redundant transimpedance amplifier, field-effect transistors M2 and M4, load resistor RL2, and feedback resistor Rf2 constitute the aforementioned basic parallel feedback transimpedance amplifier. An AC coupling capacitor Cc couples the output voltage signal of the main transimpedance amplifier at point B to the redundant transimpedance amplifier. Furthermore, the added capacitively coupled AC coupling pairs M3 and M4, based on the AC coupling capacitor Cc, simultaneously and symmetrically amplify the voltage signals V+ and V- at points A and B, respectively, and output V+ and V- differentially, further improving the symmetry of the differential output and reducing the output gain and phase errors.

[0048] Compared with existing technologies, this invention achieves better output symmetry and robustness. Small-signal analysis of the proposed circuit derives the small-signal gain of the differential output in the mid-frequency band. As can be seen from the formula, when the small-signal transconductances of field-effect transistors M3 and M4 are the same, the output can achieve symmetry. Furthermore, compared with the existing technology in Reference 1, the small-signal transconductances of field-effect transistors M3 and M4 are easier to satisfy during circuit operation, thus resulting in better robustness.

[0049]

[0050]

[0051] Among them, V outn For the output voltage Vout+, V outp For the output voltage Vout-, i in Input current I in +, gm1, gm2, gm3, and gm4 are the transconductances of field-effect transistors M1, M2, M3, and M4, respectively.

[0052] Please combine Figure 5 , Figure 6 It can be seen that the gain error curve when using a single-ended to differential transimpedance amplifier (with cross-couple) differs greatly from the gain error curve when using a traditional single-ended to differential transimpedance amplifier (without cross-couple); the phase error curve when using a single-ended to differential transimpedance amplifier (with cross-couple) also differs significantly from the phase error curve when using a traditional single-ended to differential transimpedance amplifier (without cross-couple).

[0053] In summary, Figure 3 and Figure 4 The circuit mainly consists of two parts: a main transimpedance amplifier section and a redundant transimpedance amplifier section. The main amplifier section is a parallel feedback transimpedance amplifier structure based on the main amplifier, receiving the input current signal and amplifying it into a voltage signal for output. To achieve the single-ended to differential function, the redundant amplifier section of this circuit receives a portion of the main amplifier's output signal and amplifies it into a voltage signal for output. In the main transimpedance amplifier, field-effect transistors M1 and M3, load resistor RL1, and feedback resistor R... f1 This constitutes the basic parallel feedback transimpedance amplifier mentioned earlier. Similarly, in a redundant transimpedance amplifier, field-effect transistors M2 and M4, load resistor RL2, and feedback resistor R... f2This forms the basic parallel feedback transimpedance amplifier mentioned earlier. The AC coupling capacitor Cc couples the output voltage signal of the main transimpedance amplifier at point B to the redundant transimpedance amplifier. In addition, the AC coupling pairs M3 and M4 added to this circuit, based on the AC coupling capacitor Cc, simultaneously and symmetrically amplify the voltage signals at points A and B and output them differentially.

[0054] This invention can further improve the output symmetry of single-ended to differential conversion and reduce the gain and phase errors of the differential output by adding an AC coupling pair with capacitive coupling. Compared with existing technologies, the differential output conditions of this invention are easier to meet, it has better robustness, and it can achieve better output symmetry. Small-signal analysis of the proposed circuit can derive the small-signal gain of the differential output in the mid-frequency band. From Equations 1 and 2, it can be seen that when the small-signal transconductance g of the field-effect transistors M3 and M4... m3 and g m4 When they are identical, differential output can be achieved. Compared with the existing technology in Reference 1, the small-signal transconductance of field-effect transistors M3 and M4 is easier to satisfy during circuit operation, thus exhibiting better robustness. Regarding output symmetry, the capacitively coupled AC coupling pair added in this invention can be equivalent to two pairs of CS-CG (common-source-common-gate) single-ended to differential pairs, such as... Figure 4 As shown, a second signal transmission path (dashed line path with arrow) is introduced based on the existing path (solid line path with arrow) of the AC coupling capacitor Cc, making the differential output more symmetrical.

[0055] Please combine Figure 7 , Figure 7 The single-ended to differential transimpedance amplifier module uses Figure 3 Single-ended to differential transimpedance amplifier.

[0056] A single-ended to differential transimpedance amplifier module includes at least the following terminals:

[0057] The non-inverting input terminal is used to input the input current I. in +;

[0058] The non-inverting output terminal is used to output the output voltage Vout+;

[0059] The inverting output terminal is used to output the output voltage Vout-.

[0060] The power supply terminal is used to input the external voltage VDD.

[0061] Grounding terminal, used for electrical grounding.

[0062] When the bias voltage VB is an external voltage from outside the single-ended to differential transimpedance amplifier, the single-ended to differential transimpedance amplifier module also includes a bias voltage input terminal for connecting the bias voltage VB.

[0063] The single-ended to differential transimpedance amplifier module can be a chip; when it is a chip, these terminals are the chip's pins.

[0064] Please combine Figure 8 , Figure 8 The 25Gbps differential transimpedance amplifier includes an input stage amplifier, a continuous linear time equalizer amplifier (CTLE stage), and an output buffer stage amplifier connected in sequence, and may also include resistors R3 and R4. The input stage amplifier is a single-ended to differential transimpedance amplifier. Figure 8 As shown, the high single-ended to differential transimpedance amplifier proposed in this invention, compared with the structure in Reference 1, adds a capacitively coupled AC coupling pair. The differential output condition of this structure is the small-signal transconductance g of the field-effect transistors M3 and M4. m3 and g m4 Similarly, this condition is easier to meet in practical applications, thus resulting in better robustness. Furthermore, the proposed circuit structure can better improve output symmetry, further enhancing the output symmetry of the single-ended to differential conversion, and reducing the gain and phase errors of the differential output.

[0065] The output voltages Vout+ and Vout- of the single-ended to differential transimpedance amplifier are connected to the non-inverting and inverting input terminals of the continuous linear time equalizer amplifier, respectively. The non-inverting and inverting output terminals of the continuous linear time equalizer amplifier are connected to the non-inverting and inverting input terminals of the output buffer stage amplifier, respectively.

[0066] The non-inverting and inverting output terminals of the output buffer stage amplifier serve as the two output terminals of the 25Gbps differential transimpedance amplifier, respectively; the input current I of the single-ended to differential transimpedance amplifier... in + serves as the input to the 25Gbps differential transimpedance amplifier. One end of resistor R3 is electrically connected to the non-inverting output of the output buffer stage amplifier, and the other end of resistor R3 is connected to the external voltage VDD; one end of resistor R4 is electrically connected to the inverting output of the output buffer stage amplifier, and the other end of resistor R4 is connected to the external voltage VDD.

[0067] The input stage amplifier uses a high single-ended to differential transimpedance amplifier, which gives the 25Gbps differential transimpedance amplifier the characteristics of high transimpedance, low bandwidth and low noise. Compared with traditional transimpedance amplifiers, the proposed single-ended to differential transimpedance amplifier can achieve twice the transimpedance gain.

[0068] Please combine Figure 9 , Figure 9The four-channel 100Gbps transimpedance amplifier uses four 25Gbps differential transimpedance amplifiers connected in parallel. Compared with the traditional four-channel 100Gbps transimpedance amplifier, the use of single-ended to differential transimpedance amplifiers can greatly improve the common-mode rejection capability and reduce the common-mode noise and crosstalk in multi-channel systems.

[0069] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A single-ended to differential transimpedance amplifier, comprising a main transimpedance amplifier and a redundant transimpedance amplifier; The main transimpedance amplifier includes: Field-effect transistor M1, the gate of field-effect transistor M1 serves as the input current I of the single-ended to differential transimpedance amplifier. in +, the drain of the field-effect transistor M1 is electrically grounded; Field-effect transistor M3 has a gate connected to a bias voltage VB, and its drain is electrically connected to the source of field-effect transistor M1. The source of field-effect transistor M3 serves as the output voltage Vout+ of the single-ended to differential transimpedance amplifier. Feedback resistor Rf1, one end of which is electrically connected to the base of field-effect transistor M1, and the other end of which is electrically connected to the source of field-effect transistor M3. Load resistor RL1 is connected at one end to the source of field-effect transistor M3, and the other end of load resistor RL1 is connected to an external voltage VDD; and An AC coupling capacitor Cc is connected at one end to the drain of a field-effect transistor M3. The redundant transimpedance amplifier includes: Field-effect transistor M2, the gate of field-effect transistor M2 is electrically connected to the other end of AC coupling capacitor Cc, and the drain of field-effect transistor M2 is electrically grounded; Field-effect transistor M4, the gate of field-effect transistor M4 is connected to bias voltage VB, the drain of field-effect transistor M4 is electrically connected to the source of field-effect transistor M2, and the source of field-effect transistor M4 serves as the output voltage Vout- of the single-ended to differential transimpedance amplifier. Feedback resistor Rf2, one end of which is electrically connected to the base of field-effect transistor M2, and the other end of which is electrically connected to the source of field-effect transistor M4; and The load resistor RL2 is electrically connected at one end to the source of the field-effect transistor M4, and the other end of the load resistor RL2 is connected to the external voltage VDD. The single-ended to differential transimpedance amplifier is characterized by: Capacitors C1 and C2 form a capacitively coupled AC coupling pair. One end of capacitor C1 is electrically connected to the source of field-effect transistor M3, and the other end of capacitor C1 is electrically connected to the base of field-effect transistor M4. One end of capacitor C2 is electrically connected to the source of field-effect transistor M4, and the other end of capacitor C2 is electrically connected to the base of field-effect transistor M3.

2. The single-ended to differential transimpedance amplifier as described in claim 1, characterized in that, The single-ended to differential transimpedance amplifier also includes: Voltage divider resistor R1, one end of which is electrically connected to the base of field-effect transistor M3, and the other end of which is connected to bias voltage VB. Voltage divider resistor R2 is connected at one end to the base of field-effect transistor M4, and at the other end to bias voltage VB.

3. The single-ended to differential transimpedance amplifier as described in claim 1, characterized in that, The single-ended to differential transimpedance amplifier also includes: LED VD, the anode of LED VD is electrically connected to the base of MOSFET M1, and the cathode of LED VD is connected to the input current I. in +.

4. The single-ended to differential transimpedance amplifier as described in claim 1, characterized in that, The bias voltage VB is an external voltage from outside the single-ended to differential transimpedance amplifier, or an internal voltage from inside the single-ended to differential transimpedance amplifier.

5. A single-ended to differential transimpedance amplifier module, characterized in that, It employs a single-ended to differential transimpedance amplifier as described in any one of claims 1 to 4, wherein the single-ended to differential transimpedance amplifier module includes at least the following terminals: The non-inverting input terminal is used to input the input current I. in +; The non-inverting output terminal is used to output the output voltage Vout+; The inverting output terminal is used to output the output voltage Vout-. The power supply terminal is used to input the external voltage VDD. Grounding terminal, used for electrical grounding.

6. The single-ended to differential transimpedance amplifier module as described in claim 5, characterized in that, When the bias voltage VB is an external voltage from outside the single-ended to differential transimpedance amplifier, the single-ended to differential transimpedance amplifier module further includes the following terminals: The bias voltage input terminal is used to connect the bias voltage VB.

7. A 25Gbps differential transimpedance amplifier, comprising an input stage amplifier, a continuous linear time equalizer amplifier, and an output buffer stage amplifier connected in sequence; characterized in that, The input stage amplifier is a single-ended to differential transimpedance amplifier as described in any one of claims 1 to 4.

8. The 25Gbps differential transimpedance amplifier as described in claim 7, characterized in that, The output voltages Vout+ and Vout- of the single-ended to differential transimpedance amplifier are connected to the non-inverting and inverting input terminals of the continuous linear time equalizer amplifier, respectively. The non-inverting and inverting output terminals of the continuous linear time equalizer amplifier are connected to the non-inverting and inverting input terminals of the output buffer stage amplifier, respectively. Specifically, the non-inverting and inverting output terminals of the output buffer stage amplifier serve as the two output terminals of the 25Gbps differential transimpedance amplifier; the input current I of the single-ended to differential transimpedance amplifier... in + serves as the input to the 25Gbps differential transimpedance amplifier.

9. The 25Gbps differential transimpedance amplifier as described in claim 8, characterized in that, The 25Gbps differential transimpedance amplifier also includes: Resistor R3, one end of which is electrically connected to the non-inverting output terminal of the output buffer stage amplifier, and the other end of which is connected to the external voltage VDD. Resistor R4, one end of which is electrically connected to the inverting output terminal of the output buffer stage amplifier, and the other end of which is connected to the external voltage VDD.

10. A four-channel 100Gbps transimpedance amplifier, comprising four 25Gbps differential transimpedance amplifiers connected in parallel, characterized in that... The 25Gbps differential transimpedance amplifier is the 25Gbps differential transimpedance amplifier as described in any one of claims 7 to 9.

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