A control circuit for use in a low-power SAR ADC

Abstract

The application discloses a control circuit for low-power SAR ADC, comprising a same-phase terminal capacitor array, an opposite-phase terminal capacitor array, a same-phase terminal mixed switch control circuit, an opposite-phase terminal mixed switch control circuit, a Vcm sampling switch circuit and a voltage comparator; the same-phase terminal capacitor array is selected to access a same-phase input signal V ip , a common-mode level Vcm, a same-phase reference level VRP or an opposite-phase reference level VRN through the same-phase terminal mixed switch control circuit, the opposite-phase terminal capacitor array is selected to access an opposite-phase input signal V in , the common-mode level Vcm, the same-phase reference level VRP or the opposite-phase reference level VRN through the opposite-phase terminal mixed switch control circuit; the same-phase terminal capacitor array and the opposite-phase terminal capacitor array are connected with the Vcm sampling switch circuit, and are connected with a same-phase input terminal and an opposite-phase input terminal of the voltage comparator respectively. The application has fast speed in first comparison, low energy consumption and no capacitor array transverse overlength.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of bioelectronics, and particularly relates to a control circuit for a low-power SAR ADC. BACKGROUND

[0002] Successive approximation analog-to-digital converter (SAR ADC) is a kind of medium-high precision and medium-speed analog-to-digital converter, which has the advantages of low power consumption and fast speed. Low-frequency low-power SAR ADC is used in low-power analog front-end, biomedical signal processing and medical electronic equipment.

[0003] In many cases, the digital-to-analog converter (DAC) is the most power-consuming component in the SAR ADC, so reducing the power consumption of the DAC is the key to reducing the total power consumption of the SAR ADC system. At present, many methods have been proposed to reduce the power consumption of the DAC, such as introducing two-step switching, monotonic switching, split capacitor switching and Vcm-based switching in the DAC, etc. Compared with the traditional split capacitor technology, the Vcm-based switching technology can reduce the switching energy by 88% based on the differential configuration [1], and the split capacitor technology combined with the energy-saving switching sequence technology can save 56% of the conversion energy [2].

[0004] [1] Y. Zhu, C.-H. Chan, U. F. Chio, S.-W. Sin, U. Seng-Pan, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS / s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.

[0005] [2] Y. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500-KS / s low power SAR ADC for bio-medical applications,” in Proc. IEEE ASSCC Dig. Tech. Papers, Nov. 2007, pp. 228-231.

[0006] But the common mode switch technology and split capacitor switch technology has the following problems:

[0007] 1, the common mode switch algorithm alone, because of the introduction of common mode level Vcm, will make the transistor V GS VDD-Vcm, the on-resistance of the switch becomes large, so that the time to establish a comparison of growth;

[0008] 2, split capacitor structure can not need to access the common mode level Vcm, but the split capacitor structure will make the capacitor horizontal distribution too long, resulting in the probability of step effect increases, ultimately reduces the matching accuracy of the capacitor;

[0009] 3, the selection of different reference level of the free end of the capacitor will lead to different results of energy consumption, now usually will choose the ground level GND, the full range of a conversion range, the switch energy consumption is large. SUMMARY

[0010] The purpose of the application: in order to overcome the shortcomings of the prior art, the application provides a control circuit for low power SAR ADC.

[0011] Technical scheme: a control circuit for low power SAR ADC, comprising a capacitor array, a mixed switch control circuit, a Vcm sampling switch circuit and a voltage comparator, wherein the capacitor array comprises a same phase end capacitor array and an opposite phase end capacitor array; the mixed switch control circuit comprises a same phase end mixed switch control circuit and an opposite phase end mixed switch control circuit; the same phase end capacitor array is connected to the same phase input signal V ip , common mode level Vcm, same phase reference level VRP or opposite phase reference level VRN through the same phase end mixed switch control circuit, and the opposite phase end capacitor array is connected to the opposite phase input signal V in , common mode level Vcm, same phase reference level VRP or opposite phase reference level VRN through the opposite phase end mixed switch control circuit; the same phase end capacitor array is connected with the Vcm sampling switch circuit, and is connected with the same phase input end of the voltage comparator at the same time; the opposite phase end capacitor array is connected with the Vcm sampling switch circuit, and is connected with the opposite phase input end of the voltage comparator at the same time.

[0012] Preferably, the same phase end capacitor array comprises a segmented capacitor Ca, a high potential segment capacitor array and a low potential segment capacitor array, and the segmented capacitor Ca is connected in series with the high potential segment capacitor array and the low potential segment capacitor array; wherein the high potential segment capacitor array comprises a unit capacitor group C pc , a capacitor group C PM1 , a capacitor group C PM2 , ……, a capacitor group C PM ( M -1) Capacitor group C PMM and capacitor group C PMMs There are a total of M+2 capacitor banks; among them, the highest-weighted reassembly includes capacitor bank C. PMM and capacitor group C PMMs The low-potential capacitor array includes capacitor bank C. PL1 Capacitor group C PL2 ... capacitor bank C PLL There are a total of L capacitor groups; the capacitor arrays at the non-inverting end are arranged in binary weight order; the capacitor array at the inverting end and the mixed switch control circuit at the inverting end are symmetrical to the capacitor array at the non-inverting end and the mixed switch control circuit at the non-inverting end, respectively.

[0013] Preferably, the unit capacitor bank C pc Includes 1 unit capacitor, capacitor bank C PM1 Includes 1 unit capacitor, capacitor bank C PM2 Including two unit capacitors connected in parallel, capacitor bank C PM3 A capacitor bank C consists of four unit capacitors connected in parallel, ... PM ( M-1) Including 2 M-2 The highest-weighted capacitor group consists of 2 parallel unit capacitors. M-1 A number of unit capacitors connected in parallel, wherein the capacitor bank C PMM Including 2 M-2 A unit capacitor connected in parallel, capacitor bank C PMMs Including 2 M-2 Two unit capacitors connected in parallel are required, totaling 2 M One capacitor; capacitor bank C PL1 There is a single unit capacitor, and the capacitor bank C... PL2 A capacitor bank C consists of two unit capacitors connected in parallel, ... PLL From 2 L-1 It consists of 2 unit capacitors connected in parallel, requiring a total of 2 L -1 unit capacitor; the inverting capacitor array and the inverting mixed switch control circuit are symmetrical to the non-inverting capacitor array and the non-inverting mixed switch control circuit, respectively.

[0014] Preferably, the unit capacitor group C in the in-phase capacitor array (101) pc Capacitor group C PM1 Capacitor group C PM2 ... capacitor bank C PM ( M -1 ) Capacitor group C PMM and capacitor group C PMMs The top plates of each capacitor are connected, and the capacitor bank C PL1 Capacitor group C PL2 ... capacitor bank C PLThe top plates of all capacitors are connected, and the segmented capacitor Ca connects the two top plate connection points in series to form a common point. This common point is connected to the non-inverting input of the voltage comparator, and simultaneously connected to the common-mode level Vcm through the Vcm sampling switch circuit; the unit capacitor group C in the non-inverting capacitor array... pc The base plate selects the connection of the in-phase input signal V through the in-phase hybrid switch control circuit. ip Or common-mode level Vcm, capacitor bank C PM1 Capacitor group C PM2 ... capacitor bank C PM ( M-1 The base plate is controlled by a mixed-mode switch circuit at the in-phase input to select and connect to the common-mode level Vcm, the in-phase reference level VRP, the inverting reference level VRN, or to the in-phase input signal V. ip The capacitor group C of the highest weighted group PMM and capacitor group C PMMs The base plate selects the input in-phase reference level VRP, in-phase reference level VRN, or in-phase input signal V through a mixed-signal control circuit at the in-phase input terminal. ip Capacitor group C in the low-potential capacitor array at the non-inverting input PL1 Capacitor group C PL2 ... capacitor bank C PLL The base plate is connected to the common-mode level Vcm, the in-phase reference level VRP, or the inverting reference level VRN through the in-phase hybrid switch control circuit; the inverting capacitor array and the inverting hybrid switch control circuit are symmetrical to the in-phase capacitor array and the in-phase hybrid switch control circuit, respectively.

[0015] In addition, the control circuit includes three operating stages, specifically:

[0016] Sampling phase: Unit capacitor bank C in the in-phase capacitor array pc Capacitor group C PM1 Capacitor group C PM2 ... capacitor bank C PM ( M -1 ) Capacitor group C PMM and capacitor group C PMMs The base plate selects the input signal V through a non-inverting hybrid switch control circuit. ip capacitor bank C PL1 Capacitor group C PL2 ... capacitor bank C PLL The capacitor base plate is connected to the common-mode level Vcm through the non-inverting hybrid switch control circuit, and the common point of the non-inverting capacitor array is connected to the common-mode level Vcm at the same time.

[0017] Charge transfer stage: Unit capacitor bank C in the in-phase capacitor array pc Capacitor group CPM1 Capacitor group C PM2 ... and capacitor bank C PM ( M-1) The base plate selects the common-mode level Vcm via a mixed-mode switch control circuit at the non-inverting input, and the capacitor bank C... PMM Select the in-phase reference level VRP, capacitor bank C PMMs Select the inverting reference level VRN, capacitor bank C PL1 Capacitor group C PL2 ... capacitor bank C PLL The capacitor remains connected to the common-mode level Vcm, while the top plate of the non-inverting capacitor array is disconnected from the common-mode level Vcm via the Vcm sampling switch circuit, and the non-inverting input signal V... ip The first comparison is completed by directly inputting the non-inverting input of the voltage comparator.

[0018] Comparison Phase: Based on the comparison result of the previous bit, the highest-weighted capacitor group C in the in-phase capacitor array is selected. PMM and capacitor group C PMMs The base plate is selected to connect to either the in-phase reference level VRP or the in-phase reference level VRN. Once the selection is complete, the comparison is established, and then the second signal comparison is performed. This process is repeated until all comparisons are completed.

[0019] Preferably, the in-phase hybrid switch control circuit and the inverting hybrid switch control circuit form a dual-ended signal input, and the in-phase capacitor array and the inverting capacitor array form a dual-ended input and output; wherein, the common-mode level is: Vcm = 12(VRP + VRN). Beneficial effects: Compared with the prior art, the present invention has the following beneficial effects:

[0020] (1) Based on the common-mode switching algorithm, a hybrid switching algorithm is proposed, which eliminates the need for the highest weight capacitor group to be connected to the common-mode level Vcm, thereby improving the speed of the first comparison establishment; the hybrid switching algorithm can further reduce energy consumption while maintaining the advantages of the common-mode switching algorithm.

[0021] (2) By combining the split capacitor structure, only the highest weight capacitor group of the capacitor array adopts the split capacitor structure, which will not affect the ADC accuracy and will not cause the capacitor array to be too long laterally; in addition, this kind of hybrid switching circuit can also be used in the top plate sampling structure.

[0022] (3) Compared with the traditional capacitor switching conversion algorithm that introduces the ground level GND, this invention increases the common mode level Vcm, so the first conversion is not full scale and the switching energy consumption is less. Attached Figure Description

[0023] Figure 1 This is a block diagram of the control circuit of the present invention;

[0024] Figure 2 The 4bit control circuit composition block diagram of the embodiment of the present application;

[0025] Figure 3 The working process diagram of the embodiment of the present application; wherein (a) is the circuit state schematic diagram of the 4bit control circuit sampling stage, (b) is the circuit state schematic diagram of the 4bit control circuit charge transfer stage, (c) is the circuit state schematic diagram of the 4bit control circuit comparison stage, and (d) is the schematic diagram of the 4bit control circuit remaining bit comparison process;

[0026] Figure 4 The switch switching schematic diagram of the embodiment of the present application;

[0027] Figure 5 The switch energy simulation diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0028] The present application will be described in detail below in combination with specific embodiments and drawings.

[0029] As shown in the drawings, Figure 1 The control circuit for low-power SAR ADC of the present application includes a capacitor array 10, a mixed switch control circuit 20, a Vcm sampling switch circuit 30 and a voltage comparator 40, wherein the capacitor array 10 includes an in-phase end capacitor array 101 and an anti-phase end capacitor array 102; the mixed switch control circuit 20 includes an in-phase end mixed switch control circuit 201 and an anti-phase end mixed switch control circuit 202.

[0030] Further, the in-phase end capacitor array 101 is selected to access the in-phase input signal V ip , the common mode level Vcm, the in-phase reference level VRP or the anti-phase reference level VRN through the in-phase end mixed switch control circuit 201; the anti-phase end capacitor array 102 is selected to access the anti-phase input signal V in , the common mode level Vcm, the in-phase reference level VRP or the anti-phase reference level VRN through the anti-phase end mixed switch control circuit 202; the in-phase end capacitor array 101 is connected with the Vcm sampling switch circuit 30 and at the same time connected with the in-phase input end of the voltage comparator 40; the anti-phase end capacitor array 102 is connected with the Vcm sampling switch circuit 30 and at the same time connected with the anti-phase input end of the voltage comparator 40; the in-phase end mixed switch control circuit 201 and the anti-phase end mixed switch control circuit 202 constitute double-end signal input, and the in-phase end capacitor array 101 and the anti-phase end capacitor array 102 double-end input and output; wherein the common mode level is: Vcm=12(VRP+VRN).

[0031] Specifically, the in-phase terminal capacitor array 101 includes a segmented capacitor Ca, a high-potential segmented capacitor array, and a low-potential segmented capacitor array; the segmented capacitor Ca connects the high-potential segmented capacitor array and the low-potential segmented capacitor array in series. The high-potential segmented capacitor array is composed of unit capacitor groups C pc , capacitor group C PM1 , capacitor group C PM2 , …, capacitor group C PM ( M -1), capacitor group C PMM , and capacitor group C PMMs , a total of M+2 capacitor groups; wherein the highest bit weight capacitor group (MSB) is evenly split into two capacitor groups, i.e., capacitor group C PMM and capacitor group C PMMs ; the low-potential segmented capacitor array is composed of capacitor group C PL1 , capacitor group C PL2 , …, capacitor group C PLL , a total of L capacitor groups. The in-phase terminal capacitor array 101 is arranged in a binary weight order, i.e., 2 N , N=1, 2, 3, …; wherein: the unit capacitor group C pc has 1 unit capacitor, the capacitor group C PM1 has 1 unit capacitor, the capacitor group C PM2 is composed of 2 unit capacitors in parallel, C PM3 is composed of 4 unit capacitors in parallel, …, the capacitor group C PM ( M-1 ) is composed of 2 M-2 unit capacitors in parallel, the highest weight capacitor group (MSB) is composed of 2 M-1 unit capacitors in parallel, wherein the capacitor group C PMM is composed of 2 M-2 unit capacitors in parallel, the split capacitor group C PMMs is composed of 2 M-2 unit capacitors in parallel, a total of 2 M unit capacitors are needed; the capacitor group C PL1 has 1 unit capacitor, the capacitor group C PL2 is composed of 2 unit capacitors in parallel, …, the capacitor group C PLL is composed of 2 L-1 unit capacitors in parallel, a total of 2 L -1 unit capacitors are needed.

[0032] Further, the unit capacitor group C pc , capacitor group C PM1 , capacitor group C PM2 , …, capacitor group C PM ( M -1), capacitor group C PMMand capacitor group C PMMs The top plates of each capacitor in capacitor group C PL1 , capacitor group C PL2 , ……, capacitor group C PLL are connected, and the two top plate connecting points of the segmented capacitor Ca are connected in series to form a common point, which is connected to the non-inverting input terminal of the voltage comparator 40, and the common point is connected to the common mode voltage Vcm through the Vcm sampling switch circuit 30; the bottom plate (free point) of the unit capacitor group C pc in the non-inverting terminal capacitor array 101 is connected to the non-inverting input signal V ip or the common mode voltage Vcm through the non-inverting terminal mixed switch control circuit 201, and the capacitor group C PM1 , capacitor group C PM2 , ……, capacitor group C PM ( M-1) The bottom plate (free point) of the capacitor group C ip and capacitor group C PMM is connected to the common mode voltage Vcm, the non-inverting reference voltage VRP, the inverting reference voltage VRN or the non-inverting input signal V PMMs through the non-inverting terminal mixed switch control circuit 201; the bottom plate (free point) of the capacitor group C ip and capacitor group C PL1 , capacitor group C PL2 , ……, capacitor group C PLL is connected to the common mode voltage Vcm, the non-inverting reference voltage VRP or the inverting reference voltage VRN through the non-inverting terminal mixed switch control circuit 201; the inverting terminal circuit is symmetrical to the non-inverting terminal circuit.

[0033] Further, the working of the control circuit of the present application has three stages in common, and the conditions of each stage are as follows: sampling stage: the bottom plate (free point) of the unit capacitor group C pc , capacitor group C PM1 , capacitor group C PM2 , ……, capacitor group C PM ( M -1 ) , capacitor group C PMM and capacitor group C PMMs is connected to the non-inverting input signal V ip through the non-inverting terminal mixed switch control circuit 201, and the capacitor group C PL1 , capacitor group C PL2 , ……, capacitor group C PLLThe bottom plate (free point) of the capacitor array 101 in the same phase is connected to the common mode voltage Vcm through the same phase hybrid switch control circuit 201, and the common point of the same phase capacitor array 101 is connected to the common mode voltage Vcm; the charge transfer stage: the unit capacitor group C pc , the capacitor group C PM1 , the capacitor group C PM2 , …, and the capacitor group C PM ( M-1) The bottom plate (free point) of the capacitor array 101 in the same phase is connected to the common mode voltage Vcm through the same phase hybrid switch control circuit 201, and the common point of the same phase capacitor array 101 is connected to the common mode voltage Vcm; the charge transfer stage: the unit capacitor group C PMM The bottom plate (free point) of the capacitor group C PMMs The bottom plate (free point) of the capacitor group C PL1 , the capacitor group C PL2 , …, the capacitor group C PLL The capacitor of the same phase capacitor array 101 is connected to the common mode voltage Vcm, and the top plate (common point) of the same phase capacitor array 101 is disconnected from the common mode voltage Vcm through the Vcm sampling switch circuit 30, and the same phase input signal V ip can be directly input to the same phase of the voltage comparator 40 to complete the first comparison; the comparison stage: according to the comparison result of the last bit, the highest weight capacitor group C PMM and the capacitor group C PMMs The bottom plate (free point) of the capacitor group C ip The same phase reference voltage VRP or the inverted reference voltage VRN is selected, and the comparison is established after the selection is completed, and the second signal comparison can be performed, and so on until all comparisons are completed. The inverted phase circuit is similar to the same phase circuit.

[0034] The following will be described taking a 4-bit circuit as an example:

[0035] As shown in Figure 2 , it is a 4-bit circuit composition block diagram of the embodiment, since the number of capacitors used by the 4-bit circuit is small, the segmented capacitor structure can not be used, so there is no segmented capacitor Ca. The structure includes a capacitor array 10, a hybrid switch control circuit 20, a Vcm sampling switch circuit 30 and a voltage comparator 40. Among them, the capacitor array 10 includes a same phase capacitor array 101 and an inverted phase capacitor array 102; the hybrid switch control circuit 20 includes a same phase hybrid switch control circuit 201 and an inverted phase hybrid switch control circuit 202.

[0036] Further, the same phase capacitor array 101 selects to connect to the same phase input signal V ip , the common mode voltage Vcm or the reference voltage V ref through the same phase hybrid switch control circuit 201, and the inverted phase capacitor array 102 selects to connect to the inverted phase input signal V in, common mode level Vcm or reference level V ref ; the in-phase end capacitor array 101 is connected to the in-phase input end of the voltage comparator 40, and the anti-phase end capacitor array 102 is connected to the anti-phase input end of the voltage comparator 40. The hybrid switch control circuit 20 constitutes a double-ended signal input, and the capacitor array 10 is double-ended input and output; for the convenience of description, a reference level V ref is introduced to represent the in-phase reference level VRP and the anti-phase reference level VRN, wherein Vcm = 1 / 2V ref .

[0037] Further, the in-phase end capacitor array 101 includes a unit capacitor Cc and a binary weight capacitor group; wherein the binary weight capacitor group is composed of B p0 , B p1 , B p2 and B p2s , wherein the most significant bit (MSB) group is composed of B p2 and B p2s ; the in-phase end capacitor array 101 is arranged in the order of binary weight values, wherein: the unit capacitor Cc has 1 unit capacitor, the capacitor group B p0 has 1 unit capacitor, the capacitor group B p1 is composed of 2 unit capacitors in parallel, the capacitor group B p2 is composed of 2 unit capacitors in parallel, and the capacitor group B p2s is composed of 2 unit capacitors in parallel.

[0038] Further, the top plates of the capacitor groups B p0 , B p1 , B p2 and B p2s and the unit capacitor Cc in the in-phase end capacitor array 101 are connected to form a common point and are connected to the in-phase input end of the voltage comparator 40, and are connected to the common mode level Vcm through the Vcm sampling switch circuit 30; the bottom plates (free points) of the capacitor group B p0 and the capacitor group B p1 in the in-phase end capacitor array 101 are selectively connected to the common mode level Vcm, the reference level V ref or the in-phase input signal V ip through the in-phase end hybrid switch control circuit 201; the bottom plate (free point) of the unit capacitor Cc is selectively connected to the common mode level Vcm or the in-phase input signal V ip through the in-phase end hybrid switch control circuit 201; the bottom plates (free points) of the MSB capacitor groups B p2 and B p2s are selectively connected to the reference level V ref or the in-phase input signal V ipThe inverting terminal circuit is symmetrical with the non-inverting terminal circuit.

[0039] As shown in Figure 3 , the capacitor array 101 used in the embodiment adopts bottom sampling, and its working process includes a sampling stage, a charge transfer stage and a comparison stage, specifically:

[0040] (1) In the sampling stage, referring to (a) in Figure 3 , the non-inverting terminal capacitor array 101 and the inverting terminal capacitor array 102 respectively input the non-inverting input signal V ip and the inverting input signal V in from the bottom plate, and the non-inverting input signal V ip and the inverting input signal V in are sampled to the capacitor bottom plate through the non-inverting terminal hybrid switch control circuit 201 and the inverting terminal hybrid switch control circuit 202 respectively, and the unit capacitor Cc also participates in sampling; at the same time, the top plate (common point) of the non-inverting terminal capacitor array 101 and the inverting terminal capacitor array 102 is connected to the reference level Vcm. At this point, the sampling stage is completed;

[0041] (2) Charge transfer: referring to (b) in Figure 3 , the top plate (common point) of the capacitor group in the non-inverting terminal capacitor array 101 and the inverting terminal capacitor array 102 is disconnected from the common mode level Vcm and is suspended, and the bottom plate (except the highest weight capacitor group) is connected to the common mode level Vcm, the bottom plate of the highest weight capacitor group B p2 in the non-inverting terminal capacitor array 101 is connected to VRN, the bottom plate of the capacitor group B p2s is connected to VRP, the bottom plate of the highest weight capacitor group B n2 in the inverting terminal capacitor array 102 is connected to VRN, and the bottom plate of the capacitor group B n2s is connected to VRP to complete the charge transfer, and this stage does not consume energy;

[0042] (3) Successive comparison stage: referring to (c) in Figure 3 , after the charge transfer is completed, the input signal is transferred to the top plate of the capacitor group, and the signal can be directly input to the voltage comparator 40 for comparison to obtain the comparison result D0. If D0=1, the capacitor group B p2 in the non-inverting terminal capacitor array 101 will be connected to the inverting reference level VRN, the capacitor group B p2s remains connected to the inverting reference level VRN, the capacitor group B n2 in the inverting terminal capacitor array 102 is connected to the non-inverting reference level VRP, and the capacitor group B n2s remains connected to the non-inverting reference level VRP; D0=0 is symmetrical; after the comparison is established, the signal can be input to the voltage comparator 40 for comparison to obtain the comparison result D1; referring to (d) in Figure 3 , and so on, until the comparison is completed.

[0043] In fact, in SAR ADC, the capacitor does not consume energy as an energy storage element, and the energy consumption of the capacitor switch refers to the energy consumed by the bottom plate of the capacitor switching between different levels. Since the bottom plate sampling technology is used in the embodiment, the reference voltage is sampled on the bottom plate of the capacitor, but the reference voltage is transferred to the top plate of the capacitor by charge transfer, and no energy conversion occurs during the transfer, so the energy consumed by the charge transfer stage E ex = 0; like the top plate sampling, the circuit compares the signal input to the comparator directly for the first time, without switching action of the switch, and the energy consumed E1 = 0. For the split capacitor of the MSB bit, during the charge transfer, half of the split capacitor is connected to the same phase reference level VRP and the other half is connected to the opposite phase reference level VRN, so as to maintain the common mode level Vcm. According to the output result of the previous comparison bit, the split capacitor of the MSB bit needs to be selected to be connected to VRP or VRN, and no matter which one is connected, the split capacitor only needs to convert half of the capacitor, and the other half of the capacitor belongs to the "off" state. Compared with the case where the MSB bit needs to convert all the capacitors, the split capacitor can save about half of the energy.

[0044] In the case where the overall capacitance of the DAC capacitor array is unchanged, different switching modes of the switch will result in different DAC power consumptions, and thus the energy Es consumed by the split capacitor of the highest bit weight component can be calculated as:

[0045]

[0046] wherein Q C is the amount of charge carried by the current capacitor, and C is the capacitance of the capacitor. The energy of the non-split capacitor is E = CV r 2 ef . Therefore, the split capacitor can save about 50% of the energy during conversion.

[0047] The switching energy E ref of the remaining capacitor groups is:

[0048]

[0049] If the ground GND level is selected, the energy consumption is:

[0050]

[0051] Referring to Figure 4 , let C1 represent the capacitor whose bottom plate is switched from the common mode level Vcm to the reference level V ref , C2 represent the capacitor whose bottom plate is directly connected to the reference level V ref , and C3 represent the capacitor whose bottom plate is always connected to the common mode level Vcm. It is assumed that the switch connects the bottom plate of the capacitor C from Vcm to V refand reaches a steady state at t = t s , and the voltage values of the node Va at t = t0 and t = t s are Va[t0] and Va[t s ], respectively. It can be seen that the reference level of the capacitor is selected as the common mode voltage Vcm, which can save about 50% of the energy consumption compared with selecting the ground GND level.

[0052] As shown in Figure 5 , simulation results of the circuit structure of the application and the traditional structure, split capacitor structure and common mode switch structure applied to 10bit SAR ADC, the horizontal axis is the output code word, and the vertical axis is the consumed switch energy. The average energy consumed by the circuit structure of the application is about 127.8CV 2 ref , the average energy of the split capacitor structure is about 800CV 2 ref , and the average energy of the common mode switch structure is about 170.2CV 2 ref The switch algorithm of the application is lower than the other two structures.

Claims

1. A control circuit for use in a low-power SAR ADC, characterized by: The control circuit comprises three working stages, specifically: The in-phase terminal capacitor array (101) comprises a segmented capacitor Ca, a high-potential segmented capacitor array and a low-potential segmented capacitor array, the segmented capacitor Ca connects the high-potential segmented capacitor array and the low-potential segmented capacitor array in series; wherein the high-potential segmented capacitor array comprises unit capacitor groups C pc , capacitor group C PM1 , capacitor group C PM2 , ……, capacitor group C PM（M-1） , capacitor group C PMM and capacitor group C PMMs There are M+2 capacitor groups in total, and the unit capacitor group C pc The in-phase terminal hybrid switch control circuit (201) selects to access the in-phase input signal V ip or the common-mode level Vcm; the capacitor group C PM1 , capacitor group C PM2 , ……, capacitor group C PM（M-1） all select to access the in-phase input signal V ip or the common-mode level Vcm or the in-phase reference level VRP or the inverted reference level VRN through the in-phase terminal hybrid switch control circuit (201); wherein the highest weight group comprises the capacitor group C PMM and capacitor group C PMMs all select to access the in-phase input signal V ip or the in-phase reference level VRP or the inverted reference level VRN through the in-phase terminal hybrid switch control circuit (201); the low-potential segmented capacitor array comprises capacitor group C PL1 , capacitor group C PL2 , ……, capacitor group C PLL There are L capacitor groups in total, all of which select to access the common-mode level Vcm or the in-phase reference level VRP or the inverted reference level VRN through the in-phase terminal hybrid switch control circuit (201); all the capacitors in the in-phase terminal capacitor array (101) except the unit capacitor group C pc are arranged in the order of binary weight; the inverted terminal capacitor array (102) and the inverted terminal hybrid switch control circuit (202) are symmetrical to the in-phase terminal capacitor array (101) and the in-phase terminal hybrid switch control circuit (201) respectively; unit capacitance group C pc comprises 1 unit capacitance, the capacitance group C PM1 comprises 1 unit capacitance, the capacitance group C PM2 comprises 2 unit capacitances in parallel, the capacitance group C PM3 comprises 4 unit capacitances in parallel, the capacitance group C PM（M-1） comprises 2 M-2 unit capacitances in parallel, the highest weight capacitance group comprises 2 M-1 unit capacitances in parallel, wherein the capacitance group C PMM comprises 2 M-2 unit capacitances in parallel, the capacitance group C PMMs comprises 2 M-2 unit capacitances in parallel, a total of 2 M capacitances are required; the capacitance group C PL1 has 1 unit capacitance, the capacitance group C PL2 comprises 2 unit capacitances in parallel, the capacitance group C PLL comprises 2 L-1 unit capacitances in parallel, a total of 2 L -1 unit capacitance; the inverting terminal capacitance array (102) and the inverting terminal hybrid switch control circuit (202) are respectively symmetrical with the non-inverting terminal capacitance array (101) and the non-inverting terminal hybrid switch control circuit (201).

2. The control circuit for use in a low-power SAR ADC according to claim 1, wherein: The top plates of each capacitor in the high potential section capacitor array in the in-phase terminal capacitor array (101) are connected, the top plates of each capacitor in the low potential section capacitor array are connected, the section capacitor Ca connects the two top plate connection points in series, and the top plates of each capacitor in the high potential section capacitor array are connected to the in-phase input terminal of the voltage comparator (40), and at the same time, the top plates of each capacitor in the high potential section capacitor array are connected to the common mode voltage Vcm through the Vcm sampling switch circuit (30); the bottom plates of the unit capacitor groups C pc , C ip , ……, C PM（M-1） in the in-phase terminal capacitor array (101) are connected to the in-phase input signal V ip or the common mode voltage Vcm through the in-phase terminal mixed switch control circuit (201), the bottom plates of the capacitor groups C PM1 , C PM2 , ……, C PM（M-1） are connected to the common mode voltage Vcm or the in-phase reference voltage VRP or the inverted reference voltage VRN or the in-phase input signal V ip through the in-phase terminal mixed switch control circuit (201). The highest weight group of capacitors C PMM and the bottom plate of the capacitor group C PMMs is selected by the in-phase end hybrid switch control circuit (201) to access the in-phase reference level VRP or the anti-phase reference level VRN or the in-phase input signal V ip ; the capacitors C PL1 , the capacitors C PL2 , …, the capacitors C PLL of the in-phase end low potential capacitor array are connected to the common mode level Vcm or the in-phase reference level VRP or the anti-phase reference level VRN through the in-phase end hybrid switch control circuit (201); the anti-phase end capacitor array (102) and the anti-phase end hybrid switch control circuit (202) are symmetrical with the in-phase end capacitor array (101) and the in-phase end hybrid switch control circuit (201) respectively.

3. The control circuit for use in a low-power SAR ADC according to claim 1, characterized in that: ​ Sampling phase: the unit capacitance group C pc , the capacitance group C PM1 , the capacitance group C PM2 , …, the capacitance group C PM（M-1） , the capacitance group C PMM and the capacitance group C PMMs The bottom plate of the capacitor group C ip , the capacitor group C PL1 , the capacitor group C PL2 , …, the capacitor group C PLL is accessed to the common mode level Vcm through the in-phase end hybrid switch control circuit (201), and the common point of the in-phase end capacitance array (101) is accessed to the common mode level Vcm. Charge transfer stage: Unit capacitor bank C in the in-phase capacitor array (101) pc Capacitor group C PM1 Capacitor group C PM2 ... and capacitor bank C PM（M-1） The base plate selects the common-mode level Vcm and capacitor bank C through the non-inverting hybrid switch control circuit (201). PMM Select the in-phase reference level VRP, capacitor bank C PMMs Select the inverting reference level VRN, capacitor bank C PL1 Capacitor group C PL2 ... capacitor bank C PLL The capacitor remains connected to the common-mode level Vcm, while the top plate of the non-inverting capacitor array (101) is disconnected from the common-mode level Vcm through the Vcm sampling switch circuit (30), and the non-inverting input signal V... ip The first comparison is completed by directly inputting the non-inverting input of the voltage comparator (40); Comparative stage: according to the comparison result of the last bit, the highest bit weight capacitor group C PMM and the bottom plate of the capacitor group C PMMs selects the same phase reference level VRP or the opposite phase reference level VRN, the selection is completed, the comparison is established, and then the second signal comparison is carried out, and so on, until all comparisons are completed.

4. The control circuit for use in a low-power SAR ADC according to claim 1, characterized in that: The in-phase end hybrid switch control circuit (201) and the anti-phase end hybrid switch control circuit (202) constitute a double-end signal input, and the in-phase end capacitor array (101) and the anti-phase end capacitor array (102) constitute a double-end input and output; wherein the common-mode level is: .

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