Method and apparatus for testing a radar integrated circuit

Abstract

The present invention describes methods, apparatuses, systems, and articles of manufacture for testing a radar integrated circuit. The radar circuit (102) includes: a local oscillator (LO) (110); a transmitter (112a) coupled to the LO (110) and configured to be coupled to a transmission network (104); a receiver (118a) configured to be coupled to the transmission network (104); and a controller (108) coupled to the LO (110), the transmitter (112a), and the receiver (118a), the controller (108) being operative to cause the LO (110) to generate a frequency-modulated continuous waveform (FMCW), cause the transmitter (112a) to modulate the FMCW into a modulated FMCW, cause the transmitter (112a) to transmit the modulated FMCW via the transmission network (104) and the receiver (118a) to obtain a received FMCW from the transmission network (118a), and in response to obtaining the received FMCW from the receiver (118a), generate performance characteristics of the radar circuit (102) based on the received FMCW.

Description

[0001] This description generally relates to radar single-chip systems (SoCs), and more particularly, to methods and apparatuses for testing radar integrated circuits. Background Art

[0002] In recent years, integrated circuit (IC) manufacturers have developed techniques for fabricating compact ICs incorporating components for computers or other electronic systems. Such ICs are referred to as single-chip systems or SoCs. Often times, such SoCs include a central processing unit (CPU), memory, input / output ports, and secondary storage all on the same substrate. Depending on the application, an SoC may include digital, analog, mixed-signal, radio frequency (RF), or other signal processing functions. Brief Description of the Drawings

[0003] Figure 1 is a block diagram of an example radar SoC test system.

[0004] Figure 2 is a block diagram showing further details of an example radar controller. Figure 1 of

[0005] Figure 3 is a block diagram showing further details of an example transmission network. Figure 1 of

[0006] Figure 4 is a graphical illustration of an example fast Fourier (Fourier) transform (FFT) output versus frequency graph.

[0007] Figure 5 is a graphical illustration of an example FFT output versus frequency graph.

[0008] Figure 6 is a graphical illustration of an example low noise amplifier (LNA) power output versus power amplifier (PA) gain graph.

[0009] Figure 7 is a graphical illustration of an example analog-to-digital converter (ADC) power output versus PA gain graph.

[0010] Figure 8 is a graphical illustration of an example ADC power output versus LNA power output graph.

[0011] Figure 9 is a flowchart representing example machine-readable instructions that may be executed to implement Figure 1 and 2 a radar controller to test a radar SoC.

[0012] Figure 10 is a flowchart representing example machine-readable instructions that may be executed to implement Figure 1 and 2Flowchart of example machine-readable instructions for a radar controller to generate performance characteristics of a radar SoC.

[0013] Figure 11 represents executable to implement Figure 1 and 2 Flowchart of example machine-readable instructions for a radar controller to alternatively test a radar SoC.

[0014] Figure 12 represents executable to implement Figure 1 and 2 Flowchart of example machine-readable instructions for a radar controller to alternatively test a radar SoC.

[0015] The figures are not to scale. In general, the same reference numbers will be used throughout the drawings and the accompanying written description to refer to the same or like parts.

[0016] In this document, descriptors such as "first", "second", "third", etc. are used when identifying multiple elements or components that can be referenced separately. Unless otherwise specified or understood based on the context in which they are used, such descriptors do not impart any meaning of precedence or chronological ordering, but are merely used for marking multiple elements or components for separate reference for ease of understanding the described examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to in the claims using a different descriptor such as "second" or "third". Such descriptors are used only for ease of referencing multiple elements or components. Detailed Description

[0017] The examples described herein provide methods, apparatuses, and articles of manufacture for testing a radar integrated circuit at production. The examples described herein provide a radar circuit including: a local oscillator (LO); a transmitter coupled to the LO and configured to couple to a transmission network; a receiver configured to couple to the transmission network; and a controller coupled to the LO, the transmitter, and the receiver, the controller to cause the LO to generate a frequency modulated continuous waveform (FMCW), cause the transmitter to modulate the FMCW to a modulated FMCW, cause the transmitter to transmit the modulated FMCW via the transmission network, and cause the receiver to obtain a received FMCW from the transmission network, and in response to obtaining the received FMCW from the receiver, generate performance characteristics of the radar circuit based on the received FMCW.

[0018] In recent years, IC manufacturers have developed manufacturing technologies for compact ICs that incorporate most or all of the components of a computer or other electronic system. Such ICs are referred to as SoCs. Very often, such SoCs include a CPU, memory, input / output ports, and secondary storage devices all on the same substrate. Depending on the application, an SoC may include digital, analog, mixed-signal, radio frequency (RF), or other signal processing functions.

[0019] There are many advantages to using an SoC solution rather than a distributed architecture. For example, using an SoC solution allows for a smaller area to be consumed on a printed circuit board (PCB) compared to an equivalent distributed solution. Another advantage of using an SoC solution is that such solutions consume less power than distributed solutions because they are integrated on a single substrate. While there are many advantages to using an SoC solution, individual SoCs can be difficult to test. It is important for any SoC manufacturer to test an SoC before selling and / or using it in consumer applications to ensure the desired functionality. Specifically, in radio detection and ranging (radar) SoC applications, testing for correct functionality can be difficult and / or expensive.

[0020] Some methods test radar SoCs and / or other radar circuits by integrating an individual radar SoC with a larger test system. For example, a manufacturer may use expensive test equipment to test an individual radar SoC to generate the necessary signals to confirm the correct operation of the radar SoC. In addition to the cost, the time to run the tests to confirm operation can be long and slow down the production process. Other test systems may require the production of a PCB system to test the radar SoC. For example, this PCB system integrates an antenna, a power supply, and other modules to facilitate the testing of the radar SoC. The disadvantage of this test system is that if the radar SoC fails, then the manufactured PCB and the components integrated on the PCB must be discarded. This test system is very costly and increases the time taken to test the radar SoC (e.g., reduces the rate at which the radar SoC can be tested) because the PCB must be manufactured and the radar SoC must be soldered to the PCB before testing can begin.

[0021] Moreover, some test methods may not account for inter-channel imbalances in the radar SoC, in-chip leakage in the radar SoC, corruption by the baseband circuitry, and other performance characteristics that can prove critical to the correct functionality of the radar SoC.

[0022] To improve methods that are costly, slow, and unable to address important performance characteristics of a radar SoC, the examples described herein provide methods, apparatuses, and articles for testing individual radar SoCs at production time without the need for expensive test equipment or custom PCB designs for testing the radar SoC. Specifically, many of the examples described herein allow the radar SoC to be tested at production time without additional peripheral active electrical devices. The examples described herein allow the testing of the radar SoC to be tested at production time to verify the correct functionality of the radar SoC. The various examples described herein allow the radar SoC to be tested at production time to confirm that in-channel imbalances, baseband corruption, in-chip leakage, and other performance characteristics meet the desired specifications without peripheral active electrical test equipment.

[0023] As used herein, "at production time" refers to a point in time during the production process of an IC. For example, the production process involves many steps from refining the silicon to storing the completed IC and / or shipping the completed IC to a customer. The production process begins when the silicon ingot is refined. After the silicon ingot is refined, wafers are cut from the ingot and polished. The surface of the wafer is coated with a layer of silicon dioxide or any other suitable insulating substrate. Next, a photoresist material is sprayed onto the surface of the wafer. Next, the wafer is irradiated with light to imprint the mask (e.g., circuit design) of the first layer of the IC. Next, the areas of the photoresist that were not dissolved from the irradiation are doped or chemically etched to create positive or negative doped regions. The masking and doping processes are repeated for the remaining layers of the IC. Finally, individual ICs are cut from the wafer and bonded to their mounting packages. Next, the ICs are tested to determine correct functionality. Those that pass the test are determined to have been correctly manufactured and are ready to be stored or delivered to a customer, while those that do not pass the test are determined to have not been correctly manufactured and are removed from the production line.

[0024] Figure 1 is a block diagram of an example radar SoC test system 100. The radar SoC test system 100 includes an example radar SoC 102, an example transmission network 104, and an example remote device 106. In Figure 1 the example, the example radar SoC 102 includes a radar controller 108, an example local oscillator (LO) generator 110, a first transmitter 112a, a second transmitter 112b, a first receiver 118a, a second receiver 118b, a third receiver 118c, and a fourth receiver 118d.

[0025] In Figure 1In an example, the first transmitter 112a includes a first phase shifter 114a and a first power amplifier (PA) 116a. The second transmitter 112b includes a second phase shifter 114b and a second power amplifier (PA) 116b. The first receiver 118a includes a first low noise amplifier (LNA) 120a, a first signal mixer 122a, a first filter 124a, and a first analog-to-digital converter (ADC) 126a. The second receiver 118b includes a second low noise amplifier (LNA) 120b, a second signal mixer 122b, a second filter 124b, and a second analog-to-digital converter (ADC) 126b. The third receiver 118c includes a third low noise amplifier (LNA) 120c, a third signal mixer 122c, a third filter 124c, and a third analog-to-digital converter (ADC) 126c. The fourth receiver 118d includes a fourth low noise amplifier (LNA) 120d, a fourth signal mixer 122d, a fourth filter 124d, and a fourth analog-to-digital converter (ADC) 126d. The radar controller 108 includes machine-readable instructions 128.

[0026] In Figure 1 the illustrated example, the radar controller 108 is coupled to the LO 110, the first phase shifter 114a, the first PA 116a, the second phase shifter 114b, the second PA 116b, the first LNA 120a, the second LNA 120b, the third LNA 120c, the fourth LNA 120d, the example first filter 124a, the example second filter 124b, the example third filter 124c, the example fourth filter 124d, the first ADC 126a, the second ADC 126b, the third ADC 126c, the fourth ADC 126d, and the remote device 106. In Figure 1 the example, the LO 110 is coupled to the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, the fourth signal mixer 122d, the first phase shifter 114a, the second phase shifter 114b, and the radar controller 108.

[0027] In Figure 1 the illustrated example, the first phase shifter 114a is coupled to the LO 110, the first PA 116a, and the radar controller 108. In Figure 1 the example, the first PA 116a is coupled to the first phase shifter 114a, the transmission network 104, and the radar controller 108. In Figure 1 the example, the second phase shifter 114b is coupled to the LO 110, the second PA 116a, and the radar controller 108. In Figure 1 the example illustrated, the second PA 116b is coupled to the second phase shifter 114a, the transmission network 104, and the radar controller 108.

[0028] The transmission network 104 can be part of the test socket, and the components of the radar SoC 102 can be coupled to the transmission network 104 for verification by inserting the radar SoC 102 into the test socket. In Figure 1 the illustrated example, the transmission network 104 is coupled to the first PA 116a, the second PA 116b, the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d. In the example, the remote device 106 is coupled to the radar controller 108. In Figure 1 the example illustrated, the first LNA 120a is coupled to the transmission network 104, the first signal mixer 122a, and the radar controller 108. In Figure 1 the example, the first signal mixer 122a is coupled to the first filter 124a and the first LNA 120a. In Figure 1 the illustrated example, the first filter 124a is coupled to the first ADC 126a, the first signal mixer 122a, and the radar controller 108. In the example, the first ADC 126a is coupled to the first filter 124a and the radar controller 108.

[0029] In Figure 1 the illustrated example, the second LNA 120b is coupled to the transmission network 104, the second signal mixer 122b, and the radar controller 108. In Figure 1 the example, the second signal mixer 122b is coupled to the second filter 124b and the second LNA 120b. In Figure 1 the example, the second filter 124b is coupled to the second ADC 126b, the second signal mixer 122b, and the radar controller 108. In the example, the second ADC 126b is coupled to the second filter 124b and the radar controller 108. In Figure 1 the example, the third LNA 120c is coupled to the transmission network 104, the third signal mixer 122c, and the radar controller 108. In Figure 1 the example illustrated, the third signal mixer 122c is coupled to the third filter 124c and the third LNA 120c. In Figure 1 the example, the third filter 124c is coupled to the third ADC 126c, the third signal mixer 122c, and the radar controller 108. In the example, the third ADC 126c is coupled to the third filter 124c and the radar controller 108. In Figure 1 the example, the fourth LNA 120d is coupled to the transmission network 104, the fourth signal mixer 122d, and the radar controller 108. In Figure 1In an example, the fourth signal mixer 122d is coupled to the fourth filter 124d and the fourth LNA 120d. In Figure 1 In the example described in Figure 1 , the fourth filter 124d is coupled to the fourth ADC 126d, the fourth signal mixer 122d, and the radar controller 108. In the example, the fourth ADC 126d is coupled to the fourth filter 124d and the radar controller 108.

[0030] In Figure 1 In the illustrated example of Figure 1 , the transmission network 104 is a passive network including transmission lines, combiners, and / or splitters. The transmission network 104 includes transmission lines individually coupled to the first transmitter 112a and the second transmitter 112b. The transmission network 104 also includes transmission lines individually coupled to the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d. In the transmission network 104, the individual transmission lines coupled to the first transmitter 112a and the second transmitter 112b are combined by a combiner into a single transmission line. In the transmission network 104, the single transmission line is split by a splitter into two transmission lines. In the example, each of the two transmission lines is split by a corresponding splitter into two additional transmission lines. Thus, in the example, each of the four individual transmission lines separated from the single transmission line is coupled to the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d, respectively.

[0031] In Figure 1 In the illustrated example of Figure 1 , the remote device 106 is a device that removes the radar SoC (e.g., the radar SoC 102) from the production line in response to a status indication from the radar controller 108, transports the radar SoC to be shipped and / or stored, thereby causing the radar SoC to be shipped and / or stored, removes the radar SoC from the production line, or thereby causes the radar SoC to be removed from the production line. In Figure 1 In Figure 1 , the remote device 106 includes a robotic arm. Additionally or alternatively, the remote device 106 may include a control computer, a processor platform, a personal computing device, or any other suitable device at a test station for an application.

[0032] In Figure 1 In the illustrated example of Figure 1 , the radar controller 108 controls the operation of the radar SoC 102 and facilitates the testing of the radar SoC 102.

[0033] In Figure 1In the illustrated example, the LO 110 is a device that generates a signal based on a signal from the radar controller 108 for transmission via one or more of the first transmitter 112a or the second transmitter 112b. For example, the LO 110 may include a digital-to-analog converter (DAC), a voltage-controlled oscillator, and a bandpass filter. In this example, the DAC converts a signal (e.g., a control signal) from the radar controller 108 into an analog voltage to control the voltage-controlled oscillator. Also, in this example, the output of the voltage-controlled oscillator can be filtered by the bandpass filter to remove high-frequency spikes and unwanted harmonics, and then the output of the bandpass filter is output from the LO 110. In the illustrated example, the LO 110 is controlled by the radar controller 108. The LO 110 generates a continuous waveform in response to a signal from the radar controller 108. In other examples, the LO 110 is any device that generates a frequency to be transmitted by the first transmitter 112a and the second transmitter 112b.

[0034] In Figure 1 the illustrated example, each of the first phase shifter 114a and the second phase shifter 114b is a device that adjusts the phase of a signal received from the LO 110. For example, each of the phase shifters 114a, 114b may include a passive analog phase shifter. In other examples, each of the phase shifters 114a, 114b includes any phase shifter suitable for the application. In Figure 1 the example, each of the exemplary phase shifters 114a, 114b includes functionality that is enabled and / or disabled based on a signal (e.g., a control signal) from the radar controller 108. Also, each of the exemplary phase shifters 114a, 114b includes functionality that adjusts the phase of an input signal based on a signal (e.g., a control signal) from the radar controller 108 to adjust the frequency of the input signal. For example, each of the phase shifters 114a, 114b changes the phase of the corresponding output signal relative to the signal received from the LO 110 at a constant rate to introduce a corresponding frequency shift on the corresponding output signal. Also, the first phase shifter 114a can be switched to change the coupling between the first phase shifter 114a and the first PA 116a to the coupling between the first phase shifter 114a and one or more of the first LNA 120a, the second LNA 120b, the third LNA 120c, or the fourth LNA 120d. Also, the second phase shifter 114b can be switched to change the coupling between the second phase shifter 114b and the second PA 116b to the coupling between the second phase shifter 114b and one or more of the first LNA 120a, the second LNA 120b, the third LNA 120c, or the fourth LNA 120d.

[0035] In Figure 1In the illustrated example, the coupling between the first phase shifter 114a and one or more of the first LNA 120a, the second LNA 120b, the third LNA 120c, or the fourth LNA 120d is facilitated by an example first internal feedback path 115a and an example second internal feedback path 115b that respectively correspond to the first phase shifter 114a and the second phase shifter 114b. Also, the coupling between the second phase shifter 114b and one or more of the first LNA 120a, the second LNA 120b, the third LNA 120c, or the fourth LNA 120d is also facilitated by the first internal feedback path 115a and the second internal feedback path 115b.

[0036] In Figure 1 the illustrated example, each of the first PA 116a and the second PA 116b is an electronic amplifier that converts a low-power radio frequency signal from the first phase shifter 114a and the second phase shifter 114b, respectively, into a higher-power signal to be transmitted. In the illustrated example, each of the first PA 116a and the second PA 116b is an electronic amplifier that includes functionality that can be enabled and / or disabled by the radar controller 108. Additionally, each of the first PA 116a and the second PA 116b includes a programmable gain that can be adjusted by the radar controller 108. Also, each of the first PA 116a and the second PA 116b includes introducing binary phase modulation into the signals received from the first phase shifter 114a and the second phase shifter 114b, respectively. In this way, depending on the application, the first PA 116a can be configured to be enabled and / or disabled to introduce binary phase modulation into a signal, and the second PA 116b can be configured to be enabled and / or disabled to introduce binary phase modulation into a signal. For example, each of the first PA 116a and the second PA 116b multiplies the signals received from each of the first phase shifter 114a and the second phase shifter 114b by a signal that oscillates between a negative signal and a positive signal at a predetermined frequency (e.g., 1 MHz). In other examples, depending on the application, each of the first PA 116a and the second PA 116b can be a class A, AB, B, C, F, or E amplifier. When the first PA 116a and the second PA 116b are enabled for binary phase modulation, the signals transmitted by each of the first PA 116A and the second PA 116b are frequency modulated to add 1 MHz to the frequency of the signal generated by the LO 110.

[0037] In Figure 1In the illustrated example, each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d is an electronic amplifier that amplifies the signal received from the transmission network 104 without adding additional noise to the signal. In the illustrated example, each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d includes functionality that will be enabled and / or disabled by the radar controller 108. Also, in the illustrated example, each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d includes a peak detector that detects the peak frequency in the signal flowing through each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d. Each of the peak detectors in each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d is sampled by the radar controller 108. In other examples, depending on the application, each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d may be a class A, AB, B, C, F, or E amplifier.

[0038] In Figure 1In the illustrated example, each of the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, and the fourth signal mixer 122d is a circuit that mixes the signals received from the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d, respectively, with the signal generated by the LO 110. For example, each of the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, and the fourth signal mixer 122d subtracts the frequency of the signal generated by the LO 110 from the frequencies of the signals received from the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d, respectively. In other examples, each of the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, and the fourth signal mixer 122d adds the frequency of the signal generated by the LO 110 to the frequencies of the signals received from the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d, respectively. In additional examples, each of the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, and the fourth signal mixer 122d multiplies the frequency of the signal generated by the LO 110 by the frequencies of the signals received from the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d, respectively. Regardless of the method of mixing the signals, the output of each of the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, and the fourth signal mixer 122d is a signal at an application-specific intermediate frequency (IF).

[0039] In Figure 1In the illustrated example, each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d includes a variable gain amplifier bandpass filter. Each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d filters out unwanted frequencies from the signal such that the signal is filtered to a desired carrier frequency having a bandwidth wide enough to encompass the sidebands (e.g., the information transmitted by the signal). The center frequency of each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d can be tuned based on a signal (e.g., a control signal) from the radar controller 108. Each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d is a multiplexer to which a plurality of filters are coupled. In this manner, a voltage value (e.g., a binary value) generated by the radar controller 108 selects a filter combination on the multiplexer to select the center frequency of each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d. In other examples, each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d can be a low-pass filter, a high-pass filter, a network of low-pass and high-pass filters, or a combination thereof.

[0040] In Figure 1 the illustrated example, each of the first ADC 126a, the second ADC 126b, the third ADC 126c, and the fourth ADC 126d is a device that converts an analog signal received from each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d, respectively, and converts the analog signal into a digital signal that is transmitted to the radar controller 108. For example, each of the first ADC 126a, the second ADC 126b, the third ADC 126c, and the fourth ADC 126d can be an application specific circuit.

[0041] In Figure 1 the illustrated example, in operation, when testing the radar SoC in the radar SoC test system 100, the radar controller 108 executes the machine-readable instructions 128. In additional or alternative examples, the radar controller 108 executes other machine-readable instructions to control the radar SoC 102.

[0042] In Figure 1In the illustrated example, the radar controller 108 may test the radar SoC to identify the radar SoC's ability to measure the distance, gain, and phase mismatch between the transmitters of the radar SoC and the gain and phase mismatch between the receivers of the radar SoC. For example, the radar controller 108 will transmit a signal (e.g., a control signal) to the LO 110 to generate a frequency-modulated continuous waveform (FMCW). The FMCW is modulated such that the frequency of the waveform ramps (e.g., from seventy-seven gigahertz (77 GHz) to eighty-one gigahertz (81 GHz)) between a first frequency and a second frequency over a defined period (e.g., 130 microseconds (μs)). For example, generating the FMCW allows the sensed signal to overcome in-chip leakage in the radar SoC under test, which can make it difficult to distinguish the sensed signal from in-chip leakage when only a continuous waveform is generated. Additionally or alternatively, the radar controller 108 will transmit a signal to one or both of the first PA 116a and the second PA 116b to enable binary phase modulation in one or both of the first PA 116a and the second PA 116b (e.g., to generate a modulated FMCW). Moreover, in operation, the radar controller 108 will transmit a signal to the first PA 116a to enable the output of the first PA 116a, transmit signals to the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d to enable the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d. When the first PA 116a, the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d are enabled, the FMCW is transmitted from the LO 110 to each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d via the transmission network 104 through the first PA 116a.

[0043] In Figure 1In the illustrated example, in operation, each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d obtains the received FMCW signal and amplifies the received FMCW signal. In operation, each of the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, and the fourth signal mixer 122d mixes the respective received FMCW signals from the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d with the FMCW signal from the LO 110 to generate a respective IF signal. In operation, each of the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d filters the respective IF signal generated by the first signal mixer 122a, the second signal mixer 122b, the third signal mixer 122c, and the fourth signal mixer 122d to obtain the desired frequency determined by the respective signal from the radar controller 108. In operation, each of the first ADC 126a, the second ADC 126b, the third ADC 126c, and the fourth ADC 126d converts the respective filtered IF signal from an analog signal to a digital signal and transmits the converted filtered IF signal to the radar controller 108.

[0044] In the illustrated example, in operation, the radar controller 108 processes the converted filtered IF signal in response to receiving (e.g., obtaining) the converted filtered IF signal and generates performance characteristics of the radar SoC 102. The performance characteristics are based on the received FMCW. For example, the performance characteristics are generated from the converted filtered IF signal, and the converted filtered IF signal is generated based on the received FMCW. After generating the performance characteristics corresponding to the first PA 116a (e.g., the first transmitter 112a), the radar controller 108 determines whether the quality of the performance characteristics of the currently measured transmitter meets a threshold. If the radar controller 108 determines that the quality of the performance characteristics meets the threshold, then the radar controller 108 determines that all transmitters have been tested. However, if the radar controller 108 determines that the performance characteristics do not meet the threshold, then the radar controller 108 generates a signal indicating that the radar SoC will stop production and transmits the signal to the remote device 106. In response to the signal from the radar controller 108, the remote device 106 removes the radar SoC from the production line, or causes the radar SoC to be removed from the production line thereby.

[0045] If not all transmitters (e.g., first transmitter 112a and second transmitter 112b) have been tested, then the radar controller 108 deactivates the currently tested transmitter and activates the next transmitter to be tested. For example, the radar controller 108 deactivates the first PA 116a and activates the second PA 116b by transmitting signals to the first PA 116a and the second PA 116b and generates performance characteristics of the next transmitter. If all transmitters have been tested, then the radar controller 108 generates a signal indicating that the radar SoC can continue to be produced for shipping and / or storage, and transmits the signal to the remote device 106. In response to the signal from the radar controller 108, the remote device 106 transfers the radar SoC to be shipped and / or stored, or causes the radar SoC to be shipped and / or stored thereby.

[0046] In Figure 1 the illustrated example, the radar controller 108 may test the radar SoC to identify the compression point of the amplifier in the radar SoC. For example, the radar controller 108 programs the LO 110 to generate a continuous waveform (CW) at a desired frequency (e.g., a frequency of seventy-seven gigahertz (77 GHz)). In operation, the radar controller 108 activates the first transmitter 112a and the first receiver 118a by sending signals to enable the first PA 116a and the first LNA 120a. In operation, the radar controller 108 sets the first transmitter 112a to modulate the CW at a predetermined frequency (e.g., 10 kHz) to generate a modulated CW. The radar controller 108 sets the first transmitter 112a to modulate the CW by setting the first phase shifter 114a to change the phase (e.g., phase angle) of the CW at a constant rate (e.g., 360° / 100 μs). Alternatively, the radar controller 108 sets the first transmitter 112a to modulate the CW by setting the first PA 116a to enable binary phase modulation.

[0047] In Figure 1In the illustrated example, in operation, the radar controller 108 sets the first transmitter 112a to sweep the gain of the first transmitter 112a by changing a gain control variable in the first PA 116a such that the gain of the first PA 116a changes from a first value (e.g., 12 dBm) to a second value (e.g., -18 dBm). In operation, the radar controller 108 measures the power of the CW received at the first LNA 120a (e.g., the first received CW) relative to the gain control variable of the first PA 116a. After receiving the output of the first ADC 126a, the radar controller 108 calculates the FFT of the signal output from the first ADC 126a and the peak frequency of the FFT relative to the power of the gain control variable. In operation, the radar controller 108 determines whether all receivers (e.g., the first receiver 118a, the second receiver 118b, the third receiver 118c, the fourth receiver 118d) have been tested.

[0048] In Figure 1 the illustrated example, in operation, the radar controller 108 repeats the testing of each receiver and when all receivers have been tested, the radar controller 108 combines the LNA data and the ADC data of each tested receiver. Next, the radar controller 108 identifies the ADC power corresponding to the compression point of each receiver. For example, the compression point corresponds to the point at which the gain of the receiver decreases by one (1) decibel (dB) from its maximum value (e.g., the P1dB point). In Figure 1 the example, when the power of the first ADC 126a is 1 dB lower than the highest value measured for the power of the first ADC 126a, the compression point at which the gain of the receiver decreases by one (1) dB from its maximum value corresponds to the power of the first LNA 120a. If the value of the compression point (e.g., the P1dB point) satisfies the threshold, then the radar controller 108 generates a signal indicating that the radar SoC can continue to be produced for shipping and / or storage and transmits the signal to the remote device 106. However, if the radar controller 108 determines that the compression point (e.g., the P1dB point) does not satisfy the threshold, then the radar controller 108 generates a signal indicating that the radar SoC will stop production and transmits the signal to the remote device 106. In response to the signal from the radar controller 108, the remote device 106 removes the radar SoC from the production line based on the signal from the radar controller 108, transfers the radar SoC to be shipped and / or stored, thereby causing the radar SoC to be removed from the production line, or thereby causing the radar SoC to be shipped and / or stored.

[0049] In Figure 1In the illustrated example, the radar controller 108 may test the radar SoC via an alternative test to identify the compression point of the amplifier in the radar SoC. For example, the radar controller 108 programs the LO 110 to generate a CW at a desired frequency (e.g., 77 GHz). In operation, the radar controller 108 enables the first transmitter 112a and the first receiver 118a by sending signals to the first PA 116a and the first LNA 120a to enable the first PA 116a and the first LNA 120a. In operation, the radar controller 108 sets the second transmitter 112b to modulate the CW at a predetermined frequency (e.g., 4 MHz). The radar controller 108 sets the second transmitter 112b to modulate the CW by setting the second phase shifter 114b to change the phase of the CW at a constant rate. The radar controller 108 deactivates the second PA 116b by transmitting a signal to deactivate the second PA 116b. The radar controller 108 enables the internal feedback path between the second phase shifter 114b and the first LNA 120a by transmitting a signal to the second phase shifter 114b to switch the connection between the transmission network 104 and the internal feedback path.

[0050] In Figure 1In the illustrated example, in operation, the radar controller 108 sets the first transmitter 112a to sweep the gain of the first transmitter 112a by changing the gain control variable in the first PA 116a such that the gain of the first PA 116a changes from a first value (e.g., 12 dBm) to a second value (e.g., -18 dBm). In operation, the radar controller 108 measures the power of the CW received at the first LNA 120a relative to the gain control variable of the first PA 116a. For example, the signal received at the first LNA 120a is a combined CW that includes the signal generated by the first transmitter 112a and the signal generated by the second transmitter 112b. In this example, the first LNA 120a receives the signal generated by the first transmitter 112a as the first received CW, and the first LNA 120a receives the signal generated by the second transmitter 112b as the second received CW, and combines the first received CW and the second received CW to generate the combined CW. After receiving the output of the first ADC 126a, the radar controller 108 calculates the FFT of the signal output from the first ADC 126a and the peak frequency of the FFT relative to the power of the gain control variable. In operation, the radar controller 108 determines whether all receivers (e.g., the first receiver 118a, the second receiver 118b, the third receiver 118c, the fourth receiver 118d) have been tested. The radar controller 108 repeats the test for each receiver and when all receivers have been tested, the radar controller 108 combines the LNA data and the ADC data of each tested receiver. Then, the radar controller 108 identifies the P1dB point. If the value of the P1dB point meets the threshold, then the radar controller 108 generates a signal indicating that the radar SoC can continue to be produced for shipping and / or storage, and transmits the signal to the remote device 106. However, if the radar controller 108 determines that the P1dB point does not meet the threshold, then the radar controller 108 generates a signal indicating that the radar SoC will stop production and transmits the signal to the remote device 106. In response to the signal from the radar controller 108, the remote device 106 removes the radar SoC from the production line based on the signal from the radar controller 108, transfers the radar SoC to be shipped and / or stored, thereby causing the radar SoC to be removed from the production line, or thereby causing the radar SoC to be shipped and / or stored.

[0051] Figure 2 is configured to perform Figure 9 、 10The block diagram of the radar controller 108 of the instance modulator manager 200, instance signal analyzer 202, and instance alert generator 204 with instructions of 11 and 12. The radar controller 108 includes one or more integrated circuits. In other instances, the radar controller 108 includes, for example, one or more logic circuits, microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), controllers from any desired family or manufacturer, or any other type of computing device. The radar controller 108 can be a semiconductor-based (e.g., silicon-based) device. In some instances, the radar controller 108 can be implemented on a single die, multiple dies, or a die separate from other components of the radar SoC 102.

[0052] The radar controller 108 of the illustrated instance includes a radar processor 212. The radar processor 212 of the illustrated instance is a DSP. The instance radar processor 212 is hardware. In other instances, the radar processor 212 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor can be a semiconductor-based (e.g., silicon-based) device. In this instance, the processor implements the instance modulator manager 200, instance signal analyzer 202, and instance alert generator 204.

[0053] The radar processor 212 of the illustrated instance includes local memory 213 (e.g., cache). The radar processor 212 of the illustrated instance communicates with the main memory including volatile memory 214 and non-volatile memory 216 via a bus 218. The volatile memory 214 can be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), dynamic random access memory and / or any other type of random access memory device. The non-volatile memory 216 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 214, 26 is controlled by a memory controller.

[0054] The radar controller 108 of the illustrated instance further includes an interface circuit 220. The interface circuit 220 can be implemented by a serial flash interface, a power management integrated circuit (PMIC) interface, a controller area network (CAN) interface, a CAN with flexible data rate (CAN-FD) interface, a universal asynchronous receiver-transmitter (UART) interface, a low-voltage differential signaling (LVDS) interface, a hardware-in-the-loop (HIL) interface.

[0055] In the illustrated example, one or more interface devices 222 are connected to interface circuit 220. Interface device 222 allows data and / or commands to be typed into radar processor 212. Interface device 222 may be implemented by, for example, a desktop computer, a laptop computer, remote device 106, LO 110, first phase shifter 114a, second phase shifter 114b, first PA 116a, second PA 116b, first LNA 120a, second LNA 120b, third LNA 120c, fourth LNA 120d, first filter 124a, second filter 124b, third filter 124c, fourth filter 124d, first ADC 126a, second ADC 126b, third ADC 126c, fourth ADC 126d.

[0056] The interface circuit 220 of the illustrated example also includes communication devices such as a serial flash interface circuit, a PMIC interface circuit, a CAN interface circuit, a CAN-FD interface circuit, a UART circuit, an LVDS interface circuit, a HIL interface circuit.

[0057] The radar controller 108 of the illustrated example also includes one or more mass storage devices 228 for storing software and / or data. Examples of such mass storage devices 228 include non-transitory computer-readable storage devices or storage disks such as non-volatile memories (e.g., ROM, electrically erasable programmable ROM (EEPROM), flash memory, etc. and / or any other type of ROM device), etc., including software and / or firmware.

[0058] Figure 1 Machine-readable instructions 128 may be stored in mass storage device 228, volatile memory 214, non-volatile memory 216, and / or on a removable non-transitory computer-readable storage medium such as a CD or DVD. For example, Figure 9 machine-readable instructions 900, Figure 10 the subroutine of block 908, Figure 11 machine-readable instructions 1100, Figure 12 machine-readable instructions 1200 may be implemented by Figure 1 machine-readable instructions 128.

[0059] In Figure 2In the illustrated example, the example modulator manager 200 controls the transmitters and receivers that generate and / or receive signals in a radar SoC (such as radar SoC 102). For example, the modulator manager 200 programs the LO 110 to generate FMCW signals and CW signals. Also, the example modulator manager 200 programs one or both of the first phase shifter 114a and the second phase shifter 114b to enable and / or disable one or both of the first phase shifter 114a and the second phase shifter 114b. Also, the example modulator manager 200 programs the first phase shifter 114a and the second phase shifter 114b to adjust the phase of the signal generated by the LO 110. In addition, the example modulator manager 200 programs the first phase shifter 114a and the second phase shifter 114b to switch which of the first phase shifter 114a and the second phase shifter 114b couples to one of the first LNA 120a, the second LNA 120b, the third LNA 120c, or the fourth LNA 120d.

[0060] In Figure 2 In the illustrated example, the example modulator manager 200 programs one or both of the first PA 116a and the second PA 116b to enable and / or disable one or both of the first PA 116a and the second PA 116b. Also, the example modulator manager 200 programs one or both of the first PA 116a and the second PA 11bb to enable and / or disable binary phase modulation in one or both of the first PA 116a and the second PA 116b. In addition, the example modulator manager 200 programs the first gain control variable and the second gain control variable (such as the TX_Backoff_1 variable, the TX_Backoff_2 variable, etc.) of the first PA 116a and the second PA 116b to control the gain of the first PA 116a and the second PA 116b, respectively. For example, the modulator manager 200 controls the gain of the first PA 116a such that the output power of the first PA 116a is equal to the peak output power minus the first gain control variable (e.g., TX_Output_Power_1 = 12 dBm – TX_Backoff_1). Also, the modulator manager 200 controls the gain of the second PA 116b such that the output power of the second PA 116b is equal to the peak output power minus the second gain control variable (e.g., TX_Output_Power_2 = 12 dBm – TX_Backoff_2).

[0061] In Figure 2In the illustrated example, the modulator manager 200 programs one or more of the first filter 124a, the second filter 124b, the third filter 124c, or the fourth filter 124d to select the frequencies received at each of the first receiver 118a, the second receiver 118b, the third receiver 118c, or the fourth receiver 118d, respectively. The modulator manager 200 transmits a signal corresponding to each of the signals generated to control each of the LO 110, the first phase shifter 114a, the second phase shifter 114b, the first PA 116a, the second PA 116b, the first filter 124a, the second filter 124b, the third filter 124c, and the fourth filter 124d to the example signal analyzer 202.

[0062] In Figure 2 the illustrated example, the example signal analyzer 202 processes and analyzes signals received by the receivers of the radar SoC (e.g., radar SoC 102). Moreover, the example signal analyzer 202 receives signals (e.g., control signals) corresponding to signals generated by the local oscillator and / or modulated by the transmitter from the example modulator manager 200.

[0063] In Figure 2 the illustrated example, the example signal analyzer 202 generates performance characteristics based on signals received from the first LNA 120a, the second LNA 120b, the third LNA 120c, the fourth LNA 120d, the first ADC 126a, the second ADC 126b, the third ADC 126c, and the fourth ADC 126d. For example, the performance characteristics are based on FMCW signals and / or CW signals. For example, the example signal analyzer 202 generates a fast Fourier transform (FFT) of each of the signals received from the first ADC 126a, the second ADC 126b, the third ADC 126c, and the fourth ADC 126d. The example signal analyzer 202 identifies the peak frequencies in the FFT of each of the first ADC 126a, the second ADC 126b, the third ADC 126c, and the fourth ADC 126d. The example signal analyzer 202 determines whether the frequency of the peak frequency meets a threshold of a predetermined frequency (e.g., a threshold frequency) of the peak frequency (e.g., whether it is within the threshold). For example, the predetermined peak frequency corresponds to the length of the transmission path associated with the transmission network 104 and the control signal used to generate FMCW or CW with the LO 110. The predetermined peak frequency corresponding to FMCW is calculated by the example signal analyzer 202 based on Equation 1:

[0064]

[0065] In Figure 2In the illustrated example, FMCW slope The variable corresponds to the slope of the FMCW signal and is equal to 30 MHz / μs. L TP The variable corresponds to the length of the transmission path and is equal to ten centimeters (cm). The c variable corresponds to the speed of light and is equal to 3 * 10 8 m / s. The predetermined peak frequency f is equal to 10 kHz. The threshold is 4 kHz above and / or below the predetermined peak frequency. The example threshold corresponds to an acceptable performance range for the performance of a radar SoC for detecting an object at a certain distance. For example, the predetermined peak frequency corresponds to the intermediate IF.

[0066] In Figure 2 In the illustrated example, the example signal analyzer 202 calculates the gain and phase for each pair of transmitters and receivers being tested. The example signal analyzer 202 calculates the gain and phase mismatch for each transmitter (e.g., first transmitter 112a, second transmitter 112b, etc.) and each receiver (e.g., first receiver 118a, second receiver 118b, third receiver 118c, fourth receiver 118d, etc.) in the radar SoC using the gain and phase measurements for each pair of transmitters and receivers being tested. For example, the signal analyzer 202 sets the first pair of transmitter and receiver (e.g., first transmitter 112a and first receiver 118a) as the reference pair. The example signal analyzer 202 determines the amplitude (e.g., gain) of the peak frequency for each of the transmitter and receiver in the transmitter and receiver pair and the phase at the peak frequency for each of the transmitter and receiver in the transmitter and receiver pair. For example, the gain and phase mismatch are determined based on Equations 2 and 3:

[0067] Gain MM(TXm,RXn) = Peak_dBm(TXm,RXn) – Peak__dBm(TX1,RX1)

[0068] Equation - 2

[0069] Phase MM(TXm,RXn) = Peak_Phase(TXm,RXn) – Peak_Phase(TX1,RX1)

[0070] Equation - 3

[0071] In Figure 2In the illustrated example, the gain MM(TXm,RXn) variable corresponds to the gain mismatch of the transmitter m and receiver n pair. The Peak_dBm(TXm,RXn) variable corresponds to the gain of the transmitter m and receiver n pair at the peak frequency. The Peak_dBm(TX1,RX1) variable corresponds to the gain of the reference transmitter and receiver pair (e.g., the first transmitter 112a and the first receiver 118a) at the peak frequency. The phase MM(TXm,RXn) variable corresponds to the phase mismatch of the transmitter m and receiver n pair. The Peak_Phase(TXm,RXn) variable corresponds to the phase of the transmitter m and receiver n pair at the peak frequency. The Peak_Phase(TX1,RX1) variable corresponds to the phase of the reference transmitter and receiver pair (e.g., the first transmitter 112a and the first receiver 118a) at the peak frequency. The signal analyzer 202 determines whether the gain and phase mismatches meet the threshold of acceptable mismatch (e.g., whether they are within the threshold). For example, gain and phase mismatches that do not meet the threshold correspond to a poor ability of the radar SoC to determine the direction of an object and are undesirable.

[0072] In Figure 2 the illustrated example, the example signal analyzer 202 calculates the signal-to-noise ratio (SNR) at each receiver (e.g., the first receiver 118a, the second receiver 118b, the third receiver 118c, the fourth receiver 118d, etc.). For example, the signal analyzer 202 calculates the power of the passband of the desired frequency (e.g., the center frequency of each of the first filter 124a, the second filter 124b, the third filter 124c, the fourth filter 124d) and the average power of the passbands of all other bandwidths that do not correspond to the desired frequency. For example, the SNR of each receiver is calculated based on equations 4, 5, and 6:

[0073]

[0074]

[0075]

[0076] In Figure 2 the illustrated example, the Power RXm variable corresponds to the power of the passband of the desired frequency at receiver m. The variable corresponds to the power at the peak frequency of receiver m. Power RXm Noise variable corresponds to the power of the noise at receiver m. The variable corresponds to the average power of the passbands of all other bandwidths that do not correspond to the desired frequency of receiver m. SNR RXmThe variable corresponds to the signal-to-noise ratio at receiver m. The Peak_Phase(TX1,RX1) variable corresponds to the phase of the peak frequency of a reference transmitter and receiver pair (e.g., the first transmitter 112a and the first receiver 118a). The signal analyzer 202 determines whether the SNR at each receiver meets (e.g., is higher than) a threshold. For example, an SNR higher than the threshold corresponds to the ability of the radar SoC to clearly detect an object across various distances.

[0077] In Figure 2 the illustrated example, if the example signal analyzer 202 determines that any of the peak frequencies measured at each of the receivers does not meet the threshold of a predetermined peak frequency on the receiver (e.g., outside the threshold), the gain and phase mismatch of any of the receivers does not meet the threshold of an acceptable mismatch (e.g., outside the threshold), or the SNR at each receiver does not meet (e.g., is lower than) the threshold, then the example signal analyzer 202 indicates that the radar SoC under test has undesirable performance characteristics. However, if the example signal analyzer 202 determines that all of the peak frequencies measured at the receivers meet the threshold of the predetermined peak frequency (e.g., within the threshold), the gain and phase mismatch of all of the receivers meet the threshold of an acceptable mismatch (e.g., within the threshold), or the SNR at each receiver meets (e.g., is higher than) the threshold, then the example signal analyzer 202 indicates that the radar SoC under test has desirable performance characteristics.

[0078] In Figure 2 the illustrated example, the example signal analyzer 202 measures the power at each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d (e.g., at its output), and stores the power at each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d relative to the varying gain on one or both of the first PA 116a and the second PA 116b. The example signal analyzer 202 also stores the power at the peak frequency determined in the FFT at each receiver (e.g., the first receiver 118a, the second receiver 118b, the third receiver 118c, the fourth receiver 118d) relative to the varying gain on one or both of the first PA 116a and the second PA 116b.

[0079] In Figure 2In an example, the signal analyzer 202 combines the power at each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d with respect to the varying gain on one or both of the first PA 116a and the second PA 116b and the power at the peak frequency determined in the FFT at each receiver with respect to the varying gain on one or both of the first PA 116a and the second PA 116b to produce a set of data corresponding to the power at the peak frequency determined in the FFT at each receiver with respect to the varying gain on one or both of the first PA 116a and the second PA 116b relative to the power at each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d.

[0080] In Figure 2 In an example, after determining the set of data corresponding to the power at the peak frequency determined in the FFT at each receiver with respect to the varying gain on one or both of the first PA 116a and the second PA 116b relative to the power at each of the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d, the example signal analyzer 202 identifies the compression point (e.g., the P1dB point) of each receiver. The example signal analyzer 202 determines whether the P1dB point of each receiver meets a threshold. If the compression point (e.g., the P1dB point) of any of the receivers does not meet the threshold, then the example signal analyzer 202 indicates that the radar SoC under test has unsatisfactory performance characteristics. However, if the compression points (e.g., the P1dB points) of all receivers meet the threshold, then the example signal analyzer 202 indicates that the radar SoC under test has desirable performance characteristics.

[0081] In Figure 2 In the illustrated example, the example alert generator 204 generates a status signal based on the quality of the performance characteristics. Further, the example alert generator 204 transmits the status signal to the remote device 106 to cause the remote device 106 to remove the radar SoC under test from the production line, transfer the radar SoC under test to be shipped and / or stored, thereby causing the radar SoC under test to be removed from the production line or thereby causing the radar SoC under test to be shipped and / or stored.

[0082] Figure 3 is a block diagram showing Figure 1 further details of the transmission network 104. Example systems and methods similar to the methods, apparatuses, and systems described above for testing a transceiver are described in U.S. Patent Application Serial No. 15 / 005,638, which is hereby incorporated by reference in its entirety.

[0083] Figure 3 Describe an example loopback test mode of the transmission network 104. The transmission network 104 includes an input coupler 300, a power divider 302, a power combiner 304, an output coupler 306, and a loopback line 308.

[0084] In the loopback test mode, the input coupler 300 of the transmission network 104 is used to couple output signals from one or more transmitters (such as the first transmitter 112a, the second transmitter 112b, etc.) to one or more receivers (such as the first receiver 118a, the second receiver 118b, the third receiver 118c, the fourth receiver 118d, etc.).

[0085] In the illustrated example, the radar controller 108 sends control signals to each of the first transmitter 112a and the second transmitter 112b to continuously enable each of the first transmitter 112a and the second transmitter 112b. The output of each of the first transmitter 112a and the second transmitter 112b is provided to the power combiner 304. Then, the power combiner 304 sends the combined output signal 310 to the output coupler 306.

[0086] In the loopback test mode, the output coupler 306 couples the combined output signal 310 as the coupled output signal 312 to the loopback line 308. The output coupler 306 has a known transfer function, where the coupled output signal 312 will have a predetermined functional relationship with the combined output signal 310 with respect to predetermined parameters. Non-limiting examples of the predetermined parameters include amplitude, phase, frequency, and combinations thereof.

[0087] The coupled output signal 312 is provided to the input coupler 300 via the loopback line 308. Then, the input coupler 300 provides the coupled output signal 312 as the signal 314 to the power divider 302. The input coupler 300 has a known transfer function, where the signal 314 will have a predetermined functional relationship with the coupled output signal 312 with respect to predetermined parameters. Non-limiting examples of the predetermined parameters include amplitude, phase, frequency, and combinations thereof. The power divider 302 distributes the signal 314 to all receivers (such as the first receiver 118a, the second receiver 118b, the third receiver 118c, the fourth receiver 118d).

[0088] During the test sequence, the transfer function of each of the power combiner 304, the output coupler 306, the input coupler 300, and the power divider 302 is known. In some embodiments, these transfer functions can be determined as part of a test hardware calibration procedure. In addition, the transfer function of each of the first transmitter 112a, the second transmitter 112b, the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d is expected.

[0089] In the illustrated example, the radar controller 108 sends control signals to one or more of the first transmitter 112a or the second transmitter 112b to continuously enable each of the first transmitter 112a or the second transmitter 112b. The control signal not only enables the first transmitter 112a or the second transmitter 112b, but also indicates what signals the first transmitter 112a or one or more of the second transmitters 112b are to transmit. Specifically, the control signal provides information related to the parameters of the signal to the transmitter, non-limiting examples of such parameters including amplitude, frequency, phase, duration, etc.

[0090] For the sake of brevity, consider the case where the first transmitter 112a and all the receivers (such as the first receiver 118a, the second receiver 118b, the third receiver 118c, the fourth receiver 118d) are tested. In this case, the transmission functions of the first transmitter 112a, the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d are expected. As previously mentioned, if each of the first transmitter 112a and the second transmitter 112b operates correctly, then it has known and expected transmission functions.

[0091] Thus, based on the control signal and the known transmission function of the first transmitter 112a, the signal provided from the first transmitter 112a to the power combiner 304 and the signal transmitted by the first transmitter 112a should have an expected functional relationship. Similarly, based on the known transmission function of the power combiner 304, the combined output signal 310 and the signal provided to the power combiner 304 should have a known functional relationship.

[0092] Based on the known transmission function of the output coupler 306, the combined output signal 310 and the coupled output signal 312 should have a known functional relationship. In addition, based on the known transmission function of the input coupler 300, the signal 314 and the coupled output signal 312 should have a known functional relationship. Additionally, based on the known transmission function of the power divider 302, the signals received at each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d and the signal 314 should have a known functional relationship.

[0093] The corresponding expected output signals from each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d, corresponding to the control signal sent to the first transmitter 112a, are based on the known transfer functions of each of the power combiner 304, the output coupler 306, the input coupler 300, and the power divider 302, and the expected transfer functions of the first transmitter 112a and each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d. In an example embodiment, these expected output signals from the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d are stored in the radar controller 108.

[0094] In this manner, the actual output signals from each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d are provided to the radar controller 108. In some embodiments, the actual output signals from each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d are encoded. Any known method of transmitting output signals from each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d can be implemented as long as the radar controller 108 can distinguish which output signal corresponds to which of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d.

[0095] In Figure 3 the example of, then the radar controller 108 compares the actual output signals from each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d with the corresponding expected output signals from each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d.

[0096] If the actual output signal of any one of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d does not match the expected output signal within a predetermined threshold, then the receiver in question is not performing correctly. In Figure 3 the loopback test method of, if the actual output signal of any one of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d does not match the expected output signal within a predetermined threshold, then: a) the receiver in question is not performing correctly; b) the first transmitter 112a is not performing correctly; or c) some combination of the receiver in question and the first transmitter 112a is not performing correctly.

[0097] Regarding a transmission network (e.g., transmission network 104) in aspects according to the examples described herein, all transmitters (e.g., first transmitter 112a and second transmitter 112b) and all receivers (e.g., first receiver 118a, second receiver 118b, third receiver 118c, and fourth receiver 118d) can be easily tested during production.

[0098] Figure 4 is a graphical illustration of an example fast Fourier transform (FFT) output versus frequency graph 400. The example FFT output versus frequency graph 400 represents FFT data for identifying peak frequencies in signals received by signal analyzer 202 from one or more of first ADC 126a, second ADC 126b, third ADC 126c, and fourth ADC 126d when one or more of first transmitter 112a and second transmitter 112b do not modulate the signal (e.g., an FMCW signal) generated by LO 110 via binary phase modulation. The FFT output versus frequency graph 400 includes example amplitude axis 402, example frequency axis 404, example peak frequency 406, example threshold region 408, example passband 410 for the desired frequency, and example passband 412 for all other bandwidths not corresponding to the desired frequency.

[0099] In Figure 4 the illustrated example, amplitude axis 402 represents the amplitude of the frequencies in the output of the FFT calculated by example signal analyzer 202 (e.g., amplitude in dB). Frequency axis 404 represents the frequency range in the output of the FFT calculated by example signal analyzer 202 (e.g., frequency in Hz). The range of amplitude axis 402 is from 0 dB to -120 dB, and the range of frequency axis 404 is from -600 kHz to 600 kHz.

[0100] In Figure 4 the illustrated example, example peak frequency 406 is at a frequency of 10 kHz. For example, Figure 4 the peak frequency 406 illustrated in Figure 4 corresponds to the round-trip distance (e.g., the round-trip path external to the radar SoC under test) calculated by example signal analyzer 202. In the example of

[0101] In Figure 4 the illustrated example, when determining the SNR of the signal received from one or more of the first ADC 126a, the second ADC 126b, the third ADC 126c, or the fourth ADC 126d, the example passband of the desired frequency 410 corresponds to the passband of the signal power used by the signal analyzer 202 to calculate the peak frequency. When determining the SNR of the signal received from one or more of the first ADC 126a, the second ADC 126b, the third ADC 126c, or the fourth ADC 126d, the passbands of all other bandwidths that do not correspond to the desired frequency 412 correspond to the passband of the power of the noise used by the signal analyzer 202 to calculate the noise. The signal analyzer 202 determines the SNR of the signal received from one or more of the first ADC 126a, the second ADC 126b, the third ADC 126c, or the fourth ADC 126d using the signal power and the noise power.

[0102] Figure 5 is a graphical illustration of the example FFT output versus frequency chart 500. The example FFT output versus frequency chart 500 represents the FFT data for identifying the peak frequency in the signal received by the signal analyzer 202 from one or more of the first ADC 126a, the second ADC 126b, the third ADC 126c, and the fourth ADC 126d when one or more of the first transmitter 112a and the second transmitter 112b modulate the signal (such as an FMCW signal) generated by the LO 110. For example, when the signal is modulated by binary phase modulation, the example FFT output versus frequency image 500 represents the FFT data used by the signal analyzer 202 to identify the peak frequency in the signal. In this example, the signal is modulated by binary phase modulation to simulate measuring distance in an application environment. For example, the signal analyzer 202 can determine how the radar SoC will determine a greater distance (such as 100 meters, 50 meters, etc.) without actually transmitting the signal across the greater distance. To simulate the greater distance, the example modulator manager 200 enables binary phase modulation in one or more of the first PA 116a or the second PA 116b. The example binary phase modulation in the first PA 116a and the second PA 116b modulates the signal transmitted by the first PA 116a and the second PA 116b at 1 MHz. The FFT output versus frequency chart 500 includes an example amplitude axis 502, an example frequency axis 504, an example peak frequency 506, an example threshold region 508, an example passband 510 of the desired frequency, and an example passband 512 of all other bandwidths that do not correspond to the desired frequency.

[0103] In Figure 5In the illustrated example, the amplitude axis 502 represents the amplitude of the frequencies in the output of the FFT calculated by the example signal analyzer 202 (e.g., the amplitude in dB). The frequency axis 504 represents the frequency range in the output of the FFT calculated by the example signal analyzer 202 (e.g., the frequency in Hz). The range of the amplitude axis 502 is from 0 dB to -120 dB, and the range of the frequency axis 504 is from 250 kHz to 1.25 MHz.

[0104] In Figure 5 the illustrated example, the example peak frequency 506 is at a frequency of 1 MHz plus 10 kHz. For example, when simulating an object at a specific distance in an analog application, Figure 5 the peak frequency 506 illustrated in Figure 5 corresponds to the echo distance calculated by the example signal analyzer 202. In

[0105] In Figure 5 the illustrated example, when determining the SNR of the signals received from one or more of the first ADC 126a, the second ADC 126b, the third ADC 126c, or the fourth ADC 126d, the example passband of the desired frequency 510 corresponds to the passband of the signal power used by the signal analyzer 202 to calculate the peak frequency. When determining the SNR of the signals received from one or more of the first ADC 126a, the second ADC 126b, the third ADC 126c, or the fourth ADC 126d, the passbands of all other bandwidths that do not correspond to the desired frequency 512 correspond to the passband of the power of the noise used by the signal analyzer 202 to calculate the noise. The signal analyzer 202 uses the signal power and the noise power to determine the SNR of the signals received from one or more of the first ADC 126a, the second ADC 126b, the third ADC 126c, or the fourth ADC 126d.

[0106] Figure 6is a graphical illustration of the power output of an exemplary low-noise amplifier (LNA) versus the gain of a power amplifier (PA) graph 600. The exemplary LNA power input versus PA gain graph 600 represents the power of the peak frequency detected by the signal analyzer 202 at the input of the first LNA 120a versus the gain of the first PA 116a as the exemplary modulator manager 200 changes the TX_Backoff_1 variable. The TX_Backoff_1 variable corresponds to a programmable setting of the first transmitter 112a that can be programmed with a value corresponding to a value for reducing the gain of the first transmitter 112a. The LNA power input versus PA gain graph 600 includes an exemplary LNA power axis 602, an exemplary PA gain axis 604, and an exemplary LNA input power curve 606. The LNA power axis 602 corresponds to the power of the signal output from the first LNA 120a.

[0107] In Figure 6 the illustrated example, the LNA input power curve 606 represents the power of the signal received at the input of the first LNA 120a and measured by the signal analyzer 202. As the modulator manager 200 adjusts the gain of the first PA 116a and modulates the signal generated by the LO 110, the signal analyzer 202 measures the power of the peak frequency at the input of the first LNA 120a. As the gain of the first PA 116a is changed and the signal generated by the LO 110 is modulated, the magnitude of the power of the signal detected by the signal analyzer 202 at the first LNA 120a decreases, as Figure 6 shown in.

[0108] Figure 7 is a graphical illustration of the power output of an exemplary analog-to-digital converter (ADC) versus the gain of a PA graph 700. The exemplary ADC power output versus PA gain graph 700 represents the power of the peak frequency detected by the signal analyzer 202 at the first ADC 126a versus the gain of the first PA 116a as the exemplary modulator manager 200 changes the TX_Backoff_1 variable. The ADC power output versus PA gain graph 700 includes an exemplary ADC power axis 702, an exemplary PA gain axis 704, an exemplary ADC_LNA compression curve 706, an exemplary 0.5 dB variation curve 708, and an exemplary 1 dB variation curve 710. During a certain operation of an amplifier, the power input to the amplifier (e.g., the first LNA 120a) has a linear relationship with the output power of the amplifier (e.g., the first LNA 120a). Compression occurs when the power input to the amplifier increases to cause a non-linear relationship between the output power of the amplifier and the output of the amplifier.

[0109] In Figure 7In the illustrated example, the ADC_LNA compression curve 706 represents the output of the first ADC 126a measured by the signal analyzer 202. The power output of the first ADC 1236a corresponds to the power output of the first LNA 120a. As the modulator manager 200 adjusts the gain of the first PA 116a and the signal generated by the LO 110 is modulated, the signal analyzer 202 measures the power of the peak frequency output by the first LNA 120a at the first ADC 126a. After collecting the power of the peak frequency at the first ADC 126a for varying gains across the first PA 116a, the example signal analyzer 202 determines the maximum (e.g., relative to Figure 7 the maximum of the sampled data shown therein) power of the first ADC 126a (e.g., corresponding to the maximum power of the first LNA 120a), the power that is 0.5 dB lower than the maximum power of the first ADC 126a, and the power that is 1 dB lower than the maximum power of the first ADC 126a. In Figure 7 the illustrated example, the 0.5 dB variation curve 708 represents the power at which the power of the first ADC 126a is 0.5 dB lower than the maximum power of the first ADC 126a (e.g., corresponding to the power of the first LNA 120a that is 0.5 dB lower than the maximum power of the first LNA 120a). In Figure 7 the illustrated example, the 1 dB variation curve 710 represents the power at which the power of the first ADC 126a is 1 dB lower than the maximum power of the first ADC 126a (e.g., corresponding to the power of the first LNA 120a that is 1 dB lower than the maximum power of the first LNA 120a).

[0110] Figure 8 is a graphical illustration of the example ADC power output versus LNA power input chart 800. The example ADC power output versus LNA power input chart 800 represents the power of the peak frequency detected by the signal analyzer 202 from the first ADC 126a versus the power of the peak frequency detected by the signal analyzer 202 at the first LNA 120a as the example modulator manager 200 changes the TX_Backoff_1 variable. The ADC power output versus LNA power input chart 800 includes an example ADC power axis 802, an example LNA power 804, an example ADC_LNA compression curve 806, an example 0.5 dB variation curve 808, an example 1 dB variation curve 810, and example P0.5dB point 812 and example P1dB point 814. In Figure 8In the illustrated example, the ADC_LNA compression curve 806 represents the output of the first LNA 120a measured by the signal analyzer 202 at the first ADC 126a. As the modulator manager 200 adjusts the gain of the first PA 116a, the signal analyzer 202 measures the power of the peak frequency output by the first LNA 120a at the first ADC 126a. The P0.5dB point 812 is at the point where the ADC_LNA compression curve 806 intersects the 0.5dB variation curve 808. When the power output of the first ADC 126a is 0.5dB lower than its expected maximum power, the P0.5dB point 812 represents the power output of the first ADC 126a corresponding to the gain value of the first LNA 120a. The P1dB point 814 is at the point where the ADC_LNA compression curve 806 intersects the 1dB variation curve 810. When the power output of the first ADC 126a is 1dB lower than its maximum value, the P1dB point 814 represents the power output of the first ADC 126a corresponding to the gain value of the first LNA 120a.

[0111] In Figure 8 the illustrated example, by combining the first LNA 120a data represented in Figure 6 with the first ADC 126a data represented in Figure 7 the example signal analyzer 202 circumvents the attenuation caused by the first filter 124a and reliably detects the P0.5dB point 812 and the P1dB point 814. In some examples, the example modulator manager 200 may deactivate the second PA 116b and enable the internal feedback path between the second phase shifter 114b and the first LNA 120a, continuously change the phase of the signal generated by the LO 110 with the second phase shifter 114b, and calculate Figure 6 , 7 and the same data represented in 8. By enabling the internal feedback path between the second phase shifters 114b and continuously changing the phase of the signal generated by the LO 110 with the second phase shifter 114b, the modulator manager 200 enables the signal analyzer 202 to reduce interference in the detected signal (e.g., caused by in-chip leakage) and produce a more accurate analysis of the performance characteristics.

[0112] Although an example manner of implementing Figure 2 the radar controller 108 is illustrated in Figure 1 one or more of the elements, processes, and / or devices illustrated in Figure 2 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Additionally, the example modulator manager 200, the example signal analyzer 202, the example alert generator 204, and / or more generally Figure 2The radar controller 108 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, the example modulator manager 200, the example signal analyzer 202, the example alert generator 204, and / or more generally Figure 2 any one of the radar controllers 108 can be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs). When reading any of the apparatus or system claims of this patent to cover pure software and / or firmware implementations, the example modulator manager 200, the example signal analyzer 202, the example alert generator 204, and / or more generally Figure 2 at least one of the radar controllers 108 is hereby expressly defined to include a non-transitory readable storage device or storage disk, such as a memory, a digital versatile disk (DVD), a compact disc (CD), a Blu-ray disc, etc., containing software and / or firmware. Additionally, Figure 1 and 2 the radar controller 108 can include one or more elements, processes, and / or devices in addition to or instead of Figure 2 the elements, processes, and / or devices described therein, and / or can include more than one of any or all of the described elements, processes, and devices. As used herein, the phrase “communicating,” including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but also includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or a single event.

[0113] represents a flowchart for implementing Figure 1 and 2 the radar controller 108 of example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof is shown in Figure 9 、 10 、11, and 12. The example machine-readable instructions can be one or more executable programs or portions of an executable program that can be executed by a computer processor of the radar controller 108 described, for example, in conjunction with Figure 1 and 2 the radar controller 108. The example program can be embodied in software stored on a non-transitory computer-readable storage medium or memory associated with the radar controller 108, such as a CD-ROM, a floppy disk, a hard disk drive, a DVD, a Blu-ray disc, but its entire program and / or portions thereof can alternatively be executed by a device different from the radar controller 108 and / or embodied in firmware or dedicated hardware. Additionally, although the example program is referenced in Figure 9 、10 The flowchart descriptions set forth in FIGS. 11 and 12 are illustrative, but many other methods of implementing the radar controller 108 may alternatively be used. For example, the order of execution of the blocks may be changed, and / or some of the described blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0114] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a packed format, etc. The machine-readable instructions described herein may be stored as data (e.g., portions of instructions, code, representations of code, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be chunked and stored on one or more storage devices and / or computing devices (e.g., servers). The machine-readable instructions may need to be installed, modified, adapted, upgraded, combined, augmented, configured, decrypted, decompressed, unpacked, distributed, reassigned, etc. in order to be directly readable and / or executable by a computing device and / or another machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and stored on separate computing devices, where the parts form a set of executable instructions that implement a program such as the programs described herein when decrypted, decompressed, and combined. In another example, the machine-readable instructions may be stored in a state that is readable by a computer, but libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc. may need to be added in order to execute the instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., store settings, input data, record network addresses, etc.) before the machine-readable instructions and / or the corresponding program can be executed in whole or in part. Accordingly, the described machine-readable instructions and / or corresponding programs encompass such machine-readable instructions and / or programs regardless of the particular format or state in which the machine-readable instructions and / or programs are stored or otherwise at rest or in transit.

[0115] As mentioned above, Figure 9 、 10The example processes of 11 and 12 can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on a non-transitory computer and / or machine-readable medium such as a hard disk drive, flash memory, read-only memory, optical disk, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk where information is stored for any duration (e.g., for an extended period of time, permanently, for a brief moment, for temporary buffering and / or for caching of information). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable storage device and / or storage disk and to exclude propagated signals and to exclude transmission media.

[0116] As used herein, the terms "comprising" and "including" (and all of their forms and tenses) are open-ended terms. Thus, whenever a claim uses any form of "comprising" or "including" (e.g., comprise / comprising, include / including, have, etc.) as a preamble or within any kind of claim statement, there may be additional elements, terms, etc., without falling outside the scope of the corresponding claim or statement. As used herein, when the phrase "at least" is used as a transitional term in, for example, the preamble of a claim, it is open-ended in the same manner as the terms "including" and "comprising" are open-ended. When used, the term "and / or" in the form of, for example, A, B, and / or C refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, and (7) A and B and C. As used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A and B" refers to an embodiment that includes (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B. Similarly, as used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A or B" refers to an embodiment that includes (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B. As used herein in the context of describing the performance / execution of a process, instruction, action, activity, and / or step, the phrase "at least one of A and B" refers to an embodiment that includes (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B. Similarly, as used herein in the context of describing the performance / execution of a process, instruction, action, activity, and / or step, the phrase "at least one of A or B" refers to an embodiment that includes (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B.

[0117] Figure 9 is a flowchart of example machine-readable instructions that may be executed to implement Figure 1 and 2 radar controller 108 to test radar SoC 102. For example, Figure 9 example machine-readable instructions may be executed to test a radar SoC (such as radar SoC 102) to determine performance characteristics related to the radar SoC's ability to determine distance, the receiver signal quality of the radar SoC, and the gain and phase mismatch of the transmitter and receiver of the radar SoC.

[0118] In Figure 9 the illustrated example, Figure 9 example machine-readable instructions 900 begin at block 902, where example modulator manager 200 sets LO 110 (such as example modulator manager 200 sets the local oscillator generator) to generate FMCW. For example, modulator manager 200 sets LO 110 to generate a continuous waveform from 77 GHz to 81 GHz over a period of 130 μs. At block 904, example modulator manager 200 enables binary phase modulation on the first transmitter. For example, example modulator manager 200 enables binary phase modulation on the first PA 116a at a frequency of 1 MHz. At block 906, example modulator manager 200 enables the first transmitter to transmit and enables all receivers to receive the signal generated by the local oscillator. For example, modulator manager 200 enables the first PA 116a to transmit the signal generated by LO 110, and modulator manager 200 enables the first LNA 120a, the second LNA 120b, the third LNA 120c, and the fourth LNA 120d.

[0119] In Figure 9 the illustrated example, at block 908, example signal analyzer 202 generates performance characteristics of the receivers under test based on the transmitted signal received at each of the receivers. For example, example signal analyzer 202 generates performance metrics for the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d based on the FMCW received at each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d. Also, example signal analyzer 202 indicates the performance characteristics of the receivers under test as being related to the currently tested transmitter (such as the first transmitter, the second transmitter, the nth transmitter, etc.).

[0120] At block 910, instance alert generator 204 determines whether the quality of the performance characteristics of the currently tested transmitter and receiver meets a performance threshold. If alert generator 204 determines that the performance characteristics of the currently tested transmitter and receiver meet the threshold (block 910: Yes), then machine-readable instructions 900 proceed to block 912. If alert generator 204 determines that the performance characteristics of the currently tested transmitter and receiver do not meet the performance threshold (block 910: No), then machine-readable instructions 900 proceed to block 918.

[0121] At block 912, instance signal analyzer 202 determines whether all transmitters in the tested radar SoC have been tested. If instance signal analyzer 202 determines that not all transmitters have been tested (block 912: No), then machine-readable instructions 900 proceed to block 914. If instance signal analyzer 202 determines that all transmitters have been tested (block 912: Yes), then machine-readable instructions 900 proceed to block 916. At block 914, instance modulator manager 200 deactivates the currently tested transmitter and activates the next transmitter to be tested. For example, modulator manager 200 deactivates first PA 116a and activates second PA 116b. After block 914, machine-readable instructions 900 proceed to block 908. At block 916, instance alert generator 204 generates a signal indicating that the tested radar SoC can continue production. At block 918, instance alert generator 204 generates a signal indicating that the tested radar SoC will stop production. At block 920, instance alert generator 204 transmits one or more of the signal indicating that the tested radar SoC can continue production or the signal indicating that the tested radar SoC will stop production to a remote device such as remote device 106. After block 920, machine-readable instructions 900 end.

[0122] Figure 10 is represented as executable to implement Figure 1 and 2 of radar controller 108 to be at Figure 9Flowchart of example machine-readable instructions that generate performance characteristics of a radar SoC (e.g., radar SoC 102) at block 908. The subroutine of block 908 begins at block 1000, where example signal analyzer 202 computes the FFT of the signal received from the current DUT receiver in the DUT radar SoC. For example, signal analyzer 202 computes the FFT of the signal received from first ADC 126a. At block 1002, example signal analyzer 202 identifies the peak frequency in the FFT of the signal received from the current DUT receiver in the DUT radar SoC. At block 1004, example signal analyzer 202 determines whether the peak frequency in the FFT of the signal received from the current DUT receiver meets a threshold of a predetermined peak frequency. For example, signal analyzer 202 determines whether the peak frequency in the FFT of the signal received from first receiver 118a is within 4 kHz of a predetermined peak frequency (e.g., 10 kHz). If example signal analyzer 202 determines that the peak frequency meets the threshold of the predetermined peak frequency (block 1004: yes), then the subroutine of block 908 continues to block 1006. If example signal analyzer 202 determines that the peak frequency does not meet the threshold of the predetermined peak frequency (block 1004: no), then the subroutine of block 908 continues to block 1022.

[0123] In Figure 10 the illustrated example, at block 1006, example signal analyzer 202 computes the SNR of the signal received from the current DUT receiver in the DUT radar SoC. For example, signal analyzer 202 computes the SNR of the signal received from first ADC 126a. At block 1008, example signal analyzer 202 determines whether the SNR of the signal received from the current DUT receiver meets a threshold. For example, the threshold corresponds to an SNR value high enough to ensure that the DUT radar SoC has sufficient clarity (e.g., resolution) to detect an object at a certain distance. If example signal analyzer 202 determines that the SNR of the signal received from the current DUT receiver meets (e.g., is at or above) the threshold (block 1008: yes), then the subroutine of block 908 continues to block 1010. If example signal analyzer 202 determines that the SNR of the signal received from the current DUT receiver does not meet (e.g., is below) the threshold (block 1008: no), then the subroutine of block 908 continues to block 1022. At block 1010, example signal analyzer 202 computes the gain and phase of the current DUT transmitter and receiver pair. For example, signal analyzer 202 computes the gain and phase of first transmitter 112a and first receiver 118a pair.

[0124] In Figure 10In an example, at block 1012, the example signal analyzer 202 determines whether the signals received at each receiver have been analyzed. For example, the signal analyzer 202 determines whether the FMCW received at each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d has been analyzed. If the signal analyzer 202 determines that any of the signals received at each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d has not been analyzed (block 1012: No), then the subroutine of block 908 proceeds to block 1014. However, if the signal analyzer 202 determines that the signals received at each of the first receiver 118a, the second receiver 118b, the third receiver 118c, and the fourth receiver 118d have been analyzed (block 1012: Yes), then the subroutine of block 908 proceeds to block 1016.

[0125] In Figure 10 In an example, at block 1014, the example signal analyzer 202 iterates from the currently measured receiver to another receiver to be tested. For example, if the signal analyzer 202 is currently analyzing the third receiver 118c and determines at block 1012 that the signals received from each of the first receiver 118a, the second receiver 118b, and the third receiver 118c have been analyzed but the signal received from the fourth receiver 118d has not been analyzed, then the signal analyzer 202 iterates at block 1014 from analyzing the signal received from the third receiver 118c to analyzing the signal received from the fourth receiver 118d. After block 1014, the subroutine of block 908 proceeds to block 1000.

[0126] In Figure 10In the illustrated example, at block 1016, example signal analyzer 202 calculates the gain and phase mismatch for each transmitter and receiver pair. For example, signal analyzer 202 calculates the gain and phase mismatch between a reference transmitter-receiver pair (e.g., first transmitter 112a and first receiver 118a) and another transmitter and receiver pair (e.g., the m-th transmitter and the n-th receiver). At block 1018, example signal analyzer 202 determines whether the gain and phase mismatch for each transmitter and receiver pair meets a threshold. For example, the threshold corresponds to an acceptable mismatch that allows the radar SoC under test in the example to maintain correct operation. If example signal analyzer 202 determines that the gain and phase mismatch for all transmitter and receiver pairs meets (e.g., is at or below) the threshold (block 1018: yes), then the subroutine of block 908 proceeds to block 1020. If example signal analyzer 202 determines that the gain and phase mismatch for any of the transmitter and receiver pairs does not meet (e.g., is above) the threshold (block 1018: no), then the subroutine of block 908 proceeds to block 1022.

[0127] In Figure 10 the illustrated example, at block 1020, example signal analyzer 202 indicates that the radar SoC under test has desired performance characteristics. For example, the desired performance characteristics correspond to acceptable operating characteristics that satisfy the expected performance in the application. After block 10120, the example subroutine of block 908 returns to machine-readable instruction 900 at block 910. At block 1022, example signal analyzer 202 indicates that the radar SoC under test has undesirable performance characteristics. For example, the undesirable performance characteristics correspond to unacceptable operating characteristics that do not satisfy the expected performance in the application. After block 1022, the example subroutine of block 908 returns to machine-readable instruction 900 at block 910.

[0128] Figure 11 is a flowchart of example machine-readable instructions that may be executed to implement Figure 1 and 2 radar controller 108 to alternatively test radar SoC 102. For example, Figure 11Example machine-readable instructions may be executed to test a radar SoC (e.g., radar SoC 102) to determine performance characteristics related to the linearity of the gain of one or more power amplifiers in the radar SoC under test. Example machine-readable instructions 1100 begin at block 1102, where example modulator manager 200 sets a local oscillator to generate a CW. For example, example modulator manager 200 sets LO 110 to generate a CW at 77 GHz. At block 1104, example modulator manager 200 enables a first transmitter and a first receiver. For example, example modulator manager 200 enables first PA 116a and first LNA 120a. At block 1106, example modulator manager 200 sets the first transmitter to modulate the CW at a predetermined frequency. For example, the predetermined frequency may be 10 kHz. For example, at block 1106, example modulator manager 200 sets first PA 116a to modulate the CW with binary phase modulation. In other examples, at block 1106, example modulator manager 200 sets first phase shifter 114a to adjust the phase of the CW at a constant rate (e.g., 360° / 100 μs).

[0129] In Figure 11 the illustrated example, at block 1108, example modulator manager 200 sweeps the gain of the first transmitter. For example, modulator manager 200 sweeps the TX_Backoff_1 variable of first PA 116a from 0 dB to 30 dB. At block 1110, example signal analyzer 202 measures the power at the LNA of the currently tested receiver. For example, signal analyzer 202 measures the power of the peak frequency at first LNA 120a with a millimeter wave peak detector. At block 1112, example signal analyzer 202 calculates the FFT of the signal received from the ADC of the currently tested receiver. For example, signal analyzer 202 calculates the FFT of the signal received from first ADC 126a. At block 1114, example signal analyzer 202 identifies the power corresponding to the peak frequency in the FFT of the signal received from the currently tested receiver. For example, signal analyzer 202 identifies the power corresponding to the peak frequency in the FFT of the signal received from first ADC 126a. At block 1116, example signal analyzer 202 determines whether all tested receivers have been tested. If example signal analyzer 202 determines that all tested receivers have been tested (block 1116: yes), then machine-readable instructions 1100 proceed to block 1120. If example signal analyzer 202 determines that not all tested receivers have been tested (block 1116: no), then machine-readable instructions 1100 proceed to block 1118.

[0130] In Figure 11In the illustrated example, at block 1118, example modulator manager 200 deactivates the currently tested receiver and enables the next receiver to be tested. For example, modulator manager 200 deactivates first LNA 120a and enables second LNA 120b. After block 1118, machine-readable instructions 1100 proceed to block 1108. At block 1120, example signal analyzer 202 combines the LNA data and the ADC data for each receiver. For example, at block 1120, example signal analyzer 202 populates a data structure that correlates the power of the peak frequency at first ADC 126a with the power of the peak frequency at first LNA 120a. At block 1122, example signal analyzer 202 identifies the compression point for each receiver (e.g., the compression point of the LNA for each receiver). For example, example signal analyzer 202 identifies the P1dB point measured at first ADC 126a. The P1dB point corresponds to the LNA power at which the power of the ADC is 1 dB lower than the maximum power of the ADC. In an additional or alternative example, example signal analyzer 202 identifies the P0.5dB point measured at first ADC 126a. The P0.5dB point corresponds to the LNA power at which the power of the ADC is 0.5 dB lower than the maximum power of the ADC.

[0131] In Figure 11 the illustrated example, at block 1124, example signal analyzer 202 determines whether the compression point meets a threshold. For example, the signal analyzer determines whether the P1dB point meets the threshold. In an additional or alternative example, example signal analyzer 202 determines whether the P0.5dB point meets the threshold. If example signal analyzer 202 determines that the compression point meets the threshold (block 1124: Yes), then machine-readable instructions 1100 proceed to block 1126. If example signal analyzer 202 determines that the compression point does not meet the threshold (block 1124: No), then machine-readable instructions 1100 proceed to block 1128. In an additional or alternative example, block 1124 is repeated for an alternative compression point.

[0132] In Figure 11 the illustrated example, at block 1126, example signal analyzer 202 indicates that the radar SoC under test has desired performance characteristics. After block 1126, machine-readable instructions 1100 proceed to block 1130. At block 1128, example signal analyzer 202 indicates that the radar SoC under test has undesirable performance characteristics. After block 1128, machine-readable instructions 1100 proceed to block 1130. At block 1130, example alert generator 204 transmits a signal to remote device 106 based on the quality of the performance characteristics. After block 1130, example machine-readable instructions 1100 end.

[0133] Figure 12 is representative of executable to implementFigure 1 and 2 a flowchart of example machine-readable instructions to alternatively test the radar SoC 102 with a radar controller 108. For example, Figure 12 the example machine-readable instructions may be executed to test a radar SoC (e.g., radar SoC 102) to determine performance characteristics related to the linearity of the gain of one or more power amplifiers in the radar SoC under test. The example machine-readable instructions 1200 begin at block 1202, where an example modulator manager 200 sets a local oscillator to generate a CW. For example, the example modulator manager 200 sets the LO 110 to generate a CW at 77 GHz. At block 1204, the example modulator manager 200 enables a first transmitter and a first receiver. For example, the example modulator manager 200 enables the first PA 116a and the first LNA 120a. At block 1206, the example modulator manager 200 deactivates a phase shifter of the first transmitter. For example, the modulator manager 200 deactivates the first phase shifter 114a. At block 1208, the example modulator manager 200 sets a second transmitter to modulate the CW at a predetermined frequency. For example, the predetermined frequency may be 10 kHz. For example, at block 1208, the example modulator manager 200 sets the second PA 116b to modulate the CW with binary phase modulation. In other examples, at block 1208, the example modulator manager 200 sets the second phase shifter 114b to adjust the phase of the CW at a constant rate (e.g., 360° / 100 μs).

[0134] At Figure 12In the illustrated example, at block 1210, example modulator manager 200 deactivates the power amplifier of the second transmitter. For example, modulator manager 200 deactivates second PA 116b. At block 1212, example modulator manager 200 enables the internal feedback path between the second transmitter and the first receiver. For example, modulator manager 200 enables the internal feedback path between second phase shifter 114b and first LNA 120a. At block 1214, example modulator manager 200 sweeps the gain of the first transmitter. For example, modulator manager 200 sweeps the TX_Backoff_1 variable of first PA 116a from 0 dB to 30 dB. At block 1216, example signal analyzer 202 calculates the FFT of the signal received from the ADC of the current DUT receiver. For example, signal analyzer 202 calculates the FFT of the signal received from first ADC 126a. At block 1218, example signal analyzer 202 identifies the power corresponding to the peak frequency in the FFT of the signal received from the current DUT receiver. For example, signal analyzer 202 identifies the power corresponding to the peak frequency in the FFT of the signal received from first ADC 126a. At block 1220, example signal analyzer 202 measures the power at the LNA of the receiver. For example, signal analyzer 202 measures the power of the peak frequency at first LNA 120a using a millimeter wave peak detector. At block 1222, example signal analyzer 202 determines whether all DUT receivers have been tested. If example signal analyzer 202 determines that all DUT receivers have been tested (block 1222: yes), then machine-readable instructions 1200 proceed to block 1226. If example signal analyzer 202 determines that not all DUT receivers have been tested (block 1222: no), then machine-readable instructions 1200 proceed to block 1224.

[0135] In Figure 12In the illustrated example, at block 1224, example modulator manager 200 deactivates the currently DUT receiver and activates the next receiver to be tested. For example, modulator manager 200 deactivates first LNA 120a and activates second LNA 120b. After block 1224, machine-readable instructions 1200 proceed to block 1214. At block 1226, example signal analyzer 202 combines the LNA data and the ADC data for each receiver. For example, at block 1226, example signal analyzer 202 populates a data structure that correlates the power of the peak frequency at first ADC 126a with the power of the peak frequency at first LNA 120a. At block 1228, example signal analyzer 202 identifies the compression point for each receiver. For example, example signal analyzer 202 identifies the P1dB point measured at first ADC 126a. The P1dB point corresponds to the LNA power at which the power of the ADC is 1 dB lower than the maximum power of the ADC. In an additional or alternative example, example signal analyzer 202 identifies the P0.5dB point measured at first ADC 126a. The P0.5dB point corresponds to the LNA power at which the power of the ADC is 0.5 dB lower than the maximum power of the ADC.

[0136] In Figure 12 the illustrated example, at block 1230, example signal analyzer 202 determines whether the compression point meets a threshold. For example, example signal analyzer 202 determines whether the P1dB point meets the threshold. In an additional or alternative example, example signal analyzer 202 determines whether the P0.5dB point meets the threshold. If example signal analyzer 202 determines that the compression point meets the threshold (block 1230: yes), then machine-readable instructions 1200 proceed to block 1232. If example signal analyzer 202 determines that the compression point does not meet the threshold (block 1230: no), then machine-readable instructions 1200 proceed to block 1234. In an additional or alternative example, block 1230 is repeated for the P0.5dB point.

[0137] In Figure 12 the illustrated example, at block 1232, example signal analyzer 202 indicates that the DUT radar SoC has desired performance characteristics. After block 1232, machine-readable instructions 1200 proceed to block 1236. At block 1234, example signal analyzer 202 indicates that the DUT radar SoC has undesirable performance characteristics. After block 1234, machine-readable instructions 1200 proceed to block 1236. At block 1236, example alert generator 204 transmits a signal to remote device 106 based on the quality of the performance characteristics. After block 1236, example machine-readable instructions 1200 end.

[0138] In view of the foregoing, it should be understood that example methods, apparatuses, and articles for reducing the cost associated with testing a radar integrated circuit have been described. Moreover, the example methods, apparatuses, and articles described herein provide high-confidence testing of a radar integrated circuit during production without the need for external active electrical components. The examples described herein allow testing of a radar SoC for measuring distance during production. In addition, the examples described herein provide testing of a radar SoC with FMCW during production. Moreover, the examples described herein provide testing of a radar SoC with an FMCW signal, binary phase modulation, and phase-shift modulation. For example, some alternative methods cannot test a radar SoC during production because they rely on external active electrical components to test the radar SoC. In addition, some alternative methods cannot test a radar SoC during production because such methods do not account for in-chip leakage and / or additional frequencies introduced by the transmission network (e.g., transmission network 104).

[0139] It should also be understood from the foregoing that example methods, apparatuses, and articles for reducing the requirements for expensive millimeter-wave testing equipment have been described. In addition, the examples described herein use a combination of an external transmission network (e.g., transmission network 104) and an internal feedback path (e.g., first internal feedback path 115a, second internal feedback path 115b) to measure P1dB and / or other compression points. In addition, the described examples allow testing of a radar SoC with a built-in transmitter in the radar SoC under test. The described methods, apparatuses, and articles improve the efficiency of using a computing device by testing a radar SoC during production to reduce the power wasted in continuing to produce a defective radar SoC. The described methods, apparatuses, and articles improve the efficiency of using a computing device by reducing the computational waste associated with processing radio frequency signals connected through a defective radar SoC. The described methods, apparatuses, and articles accordingly relate to one or more improvements in the operation of a computer.

[0140] Example methods, apparatuses, systems, and articles for testing a radar integrated circuit are described herein. Additional examples and combinations thereof include the following: Example 1 includes a radar circuit that includes: a local oscillator (LO); a transmitter coupled to the LO and configured to be coupled to a transmission network; a receiver configured to be coupled to the transmission network; and a controller coupled to the LO, the transmitter, and the receiver, the controller for causing the LO to generate a frequency-modulated continuous waveform (FMCW), causing the transmitter to modulate the FMCW into a modulated FMCW, causing the transmitter to transmit the modulated FMCW via the transmission network and the receiver to obtain a received FMCW from the transmission network, and in response to obtaining the received FMCW from the receiver, generating performance characteristics of the radar circuit based on the received FMCW.

[0141] Example 2 includes the radar circuit according to Example 1, wherein the controller is used to test the radar circuit during production of the radar circuit.

[0142] Example 3 includes the radar circuit according to Example 1, wherein the controller is configured to cause the transmitter to modulate the FMCW via binary phase modulation.

[0143] Example 4 includes the radar circuit according to Example 1, wherein the FMCW is a signal that ramps from approximately seventy-seven gigahertz to approximately eighty-one gigahertz.

[0144] Example 5 includes the radar circuit according to Example 1, wherein the receiver is a first receiver, the radar circuit further includes a second receiver, and wherein the performance characteristics include characteristics from the group consisting of: the signal-to-noise ratio of the received FMCW at one of the first receiver or the second receiver, the signal power of the received FMCW at one of the first receiver or the second receiver, and the gain and phase mismatch between the first receiver and the second receiver.

[0145] Example 6 includes the radar circuit according to Example 5, wherein the controller is configured to transmit a status signal to a device to cause the device to act on the radar circuit based on the quality of the performance characteristics, and when the status signal indicates that production of the radar circuit is to be stopped, the device will stop production of the radar circuit.

[0146] Example 7 includes the radar circuit according to Example 6, wherein the quality of the performance characteristics is based on thresholds corresponding to characteristics from the group consisting of: the value of the signal-to-noise ratio, the value of the signal power, and the value of the gain and phase mismatch.

[0147] Example 8 includes a method for testing a radar circuit including an oscillator, a transmitter, and a receiver, the method including: generating, by the oscillator, a frequency-modulated continuous waveform (FMCW); modulating, by the transmitter, the FMCW to produce a modulated FMCW; transmitting, by the transmitter, the modulated FMCW via a transmission network; receiving, by the receiver, a received FMCW from the transmission network based on the modulated FMCW; and generating, in response to the received FMCW, performance characteristics of the radar circuit based on the received FMCW.

[0148] Example 9 includes the method according to Example 8, wherein the radar circuit under test is during production of the radar circuit.

[0149] Example 10 includes the method according to Example 8, wherein the transmitter modulates the FMCW via binary phase modulation.

[0150] Example 11 includes the method according to Example 8, wherein the FMCW is a signal that ramps from approximately seventy-seven gigahertz to approximately eighty-one gigahertz.

[0151] Example 12 includes the method according to Example 8, wherein the receiver is a first receiver, the radar circuit further includes a second receiver, and wherein the performance characteristic includes a characteristic from the group consisting of: the signal-to-noise ratio of the received FMCW at one of the first receiver or the second receiver, the signal power of the received FMCW at one of the first receiver or the second receiver, and the gain and phase mismatch between the first receiver and the second receiver.

[0152] Example 13 includes the method according to Example 12, which further includes transmitting a status signal to a device to cause the device to act on the radar circuit based on the quality of the performance characteristic, and when the status signal indicates that the production of the radar circuit is to be stopped, the device will stop producing the radar circuit.

[0153] Example 14 includes the method according to Example 13, wherein the quality of the performance characteristic is based on a threshold corresponding to a characteristic from the group consisting of: the value of the signal-to-noise ratio, the value of the signal power, and the value of the gain and phase mismatch.

[0154] Example 15 includes an apparatus for testing a radar circuit including an oscillator, a transmitter, and a receiver, the apparatus comprising: a modulator manager for causing the oscillator to generate a frequency-modulated continuous waveform (FMCW), causing the transmitter to modulate the FMCW into a modulated FMCW, causing the transmitter to transmit the modulated FMCW via a transmission network and the receiver to obtain a received FMCW from the transmission network; and a signal analyzer for generating a performance characteristic of the radar circuit based on the FMCW in response to obtaining the received FMCW from the receiver.

[0155] Example 16 includes the apparatus according to Example 15, wherein the apparatus is for testing the radar circuit during the production of the radar circuit.

[0156] Example 17 includes the apparatus according to Example 15, wherein the modulator manager is for causing the transmitter to modulate the FMCW via binary phase modulation.

[0157] Example 18 includes the apparatus according to Example 15, wherein the FMCW is a signal that ramps from approximately seventy-seven gigahertz to approximately eighty-one gigahertz.

[0158] Example 19 includes the apparatus according to Example 15, further comprising an alarm generator for transmitting a status signal to the device to act on the radar circuit based on the quality of the performance characteristics, and when the status signal indicates that the production of the radar circuit is to be stopped, the device will stop producing the radar circuit.

[0159] Example 20 includes the apparatus according to Example 15, wherein the receiver is a first receiver, the radar circuit further includes a second receiver, and wherein the performance characteristics include characteristics from the group consisting of: the signal-to-noise ratio of the received FMCW at one of the first receiver or the second receiver, the signal power of the received FMCW at one of the first receiver or the second receiver, and the gain and phase mismatch between the first receiver and the second receiver.

[0160] Example 21 includes a radar circuit, comprising: a local oscillator (LO); a first transmitter coupled to the LO and configured to be coupled to a transmission network; a receiver configured to be coupled to the transmission network; a second transmitter coupled to the LO and coupled to the receiver via a feedback path; and a controller coupled to the LO, the first transmitter, the second transmitter, and the receiver, the controller for causing the LO to generate a continuous wave (CW), causing the first transmitter to transmit the CW via the transmission network, causing the receiver to obtain a first received CW from the transmission network, setting the second transmitter to adjust the phase angle of the CW to generate a modulated CW, enabling the second transmitter to transmit the modulated CW to the receiver via the feedback path, wherein the receiver will further be used to combine the first received CW from the first transmitter and the modulated CW from the second transmitter into a combined CW, and in response to obtaining the combined CW from the receiver, generating the performance characteristics of the radar circuit based on the combined CW.

[0161] Example 22 includes the radar circuit according to Example 21, wherein the controller is used to test the radar circuit during production of the radar circuit.

[0162] Example 23 includes the radar circuit according to Example 21, wherein the CW is a signal having a frequency of about seventy-seven gigahertz.

[0163] Example 24 includes the radar circuit according to Example 21, wherein the performance characteristics include the compression point of the receiver.

[0164] Example 25 includes the radar circuit according to Example 24, wherein the controller is configured to transmit a status signal to the device to cause the device to act on the radar circuit based on the quality of the performance characteristics.

[0165] Example 26 includes the radar circuit according to Example 25, wherein when the status signal indicates that the production of the radar circuit is to be stopped, the device will stop producing the radar circuit.

[0166] Example 27 includes the radar circuit according to Example 25, wherein the quality of the performance characteristics is based on a threshold value corresponding to the compression point.

[0167] Example 28 includes a method for testing a radar circuit including an oscillator, a first transmitter, a second transmitter, and a receiver, the method comprising: generating a continuous waveform (CW) by the oscillator; transmitting the CW by the first transmitter via a transmission network and the receiver to obtain a first received CW from the transmission network; adjusting the phase angle of the CW to a modulated CW by the second transmitter; transmitting the modulated CW by the second transmitter via a feedback path to the receiver, the receiver being configured to combine the first received CW from the first transmitter and the modulated CW into a combined CW; and generating performance characteristics of the radar circuit based on the combined CW in response to obtaining the combined CW from the receiver.

[0168] Example 29 includes the method according to Example 28, wherein the radar circuit under test is during the production of the radar circuit.

[0169] Example 30 includes the method according to Example 28, wherein the CW is a signal having a frequency of approximately seventy-seven gigahertz.

[0170] Example 31 includes the method according to Example 28, wherein the performance characteristics include the compression point of the receiver.

[0171] Example 32 includes the method according to Example 31, further comprising transmitting a status signal to a device to cause the device to act on the radar circuit based on the quality of the performance characteristics.

[0172] Example 33 includes the method according to Example 32, wherein when the status signal indicates that the production of the radar circuit is to be stopped, the device will stop producing the radar circuit.

[0173] Example 34 includes the method according to Example 32, wherein the quality of the performance characteristics is based on a threshold value corresponding to the compression point.

[0174] Example 35 includes an apparatus for testing a radar circuit including an oscillator, a first transmitter, a second transmitter, and a receiver. The apparatus includes: a modulator manager configured to cause the oscillator to generate a continuous wave (CW), cause the first transmitter to transmit the CW via a transmission network and the receiver to obtain a first received CW from the transmission network, cause the second transmitter to adjust a phase angle of the CW to a modulated CW, cause the second transmitter to transmit the modulated CW to the receiver via a feedback path, the receiver being configured to combine the first received CW from the first transmitter and the modulated CW from the second transmitter into a combined CW; and a signal analyzer configured to, in response to obtaining the combined CW from the receiver, generate performance characteristics of the radar circuit based on the combined CW.

[0175] Example 36 includes the apparatus according to Example 35, wherein the apparatus is for testing the radar circuit during production of the radar circuit.

[0176] Example 37 includes the apparatus according to Example 35, wherein the CW is a signal having a frequency of approximately seventy-seven gigahertz.

[0177] Example 38 includes the apparatus according to Example 35, further including an alarm generator to transmit a status signal to a device to cause the device to act on the radar circuit based on a quality of the performance characteristics.

[0178] Example 39 includes the apparatus according to Example 38, wherein when the status signal indicates that production of the radar circuit is to be stopped, the device will stop production of the radar circuit.

[0179] Example 40 includes the apparatus according to Example 35, wherein the performance characteristics include a compression point of the receiver.

[0180] Although specific example methods, apparatuses, and articles have been described herein, the scope of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatuses, and articles that fairly fall within the scope of the claims of this patent.

Claims

1. A radar circuit, which comprises: a local oscillator LO; a first transmitter coupled to the LO and configured to be coupled to an external transmission network; a receiver configured to be coupled to the external transmission network; a second transmitter coupled to the LO and coupled to the receiver via an internal feedback path; and a controller coupled to the LO, the first transmitter, the second transmitter, and the receiver, wherein the controller is configured to: cause the LO to generate a continuous waveform CW; cause the first transmitter to transmit the CW via the external transmission network; cause the receiver to obtain a first received CW from the external transmission network; set the second transmitter to adjust the phase angle of the CW to generate a modulated CW; enable the second transmitter to transmit the modulated CW to the receiver via the internal feedback path, wherein the receiver is further configured to combine the first received CW from the first transmitter and the modulated CW from the second transmitter into a combined CW; and in response to obtaining the combined CW from the receiver, generate performance characteristics of the radar circuit based on the combined CW.

2. The radar circuit according to claim 1, wherein the controller is configured to test the radar circuit during production of the radar circuit.

3. The radar circuit according to claim 1, wherein the CW is a signal having a frequency of seventy-seven gigahertz.

4. The radar circuit according to claim 1, wherein the performance characteristics include the compression point of the receiver.

5. The radar circuit according to claim 4, wherein the controller is configured to transmit a status signal to a device to cause the device to act on the radar circuit based on the quality of the performance characteristics.

6. The radar circuit according to claim 5, wherein when the status signal indicates that production of the radar circuit is to be stopped, the device will stop production of the radar circuit.

7. The radar circuit according to claim 5, wherein the quality of the performance characteristics is based on a threshold corresponding to a value of the compression point.

8. A method for testing a radar circuit including an oscillator, a first transmitter, a second transmitter, and a receiver, the method comprises: generating a continuous waveform CW by the oscillator; transmitting the CW by the first transmitter via an external transmission network; obtaining a first received CW by the receiver from the external transmission network; adjusting the phase angle of the CW to a modulated CW by the second transmitter; transmitting the modulated CW to the receiver by the second transmitter via an internal feedback path; combining the first received CW from the first transmitter and the modulated CW from the second transmitter into a combined CW at the receiver; and in response to obtaining the combined CW from the receiver, generating performance characteristics of the radar circuit based on the combined CW.

9. The method according to claim 8, wherein the radar circuit under test is during production of the radar circuit.

10. The method according to claim 8, wherein the CW is a signal having a frequency of seventy-seven gigahertz.

11. The method according to claim 8, wherein the performance characteristic includes the compression point of the receiver.

12. The method according to claim 11, further comprising transmitting a status signal to a device to cause the device to act on the radar circuit based on the quality of the performance characteristic.

13. The method according to claim 12, wherein when the status signal indicates that production of the radar circuit is to be stopped, the device will stop producing the radar circuit.

14. The method according to claim 12, wherein the quality of the performance characteristic is based on a threshold corresponding to the value of the compression point.

15. An apparatus for testing a radar circuit including an oscillator, a first transmitter, a second transmitter, and a receiver, wherein the apparatus comprises: a modulator manager for: causing the oscillator to generate a continuous waveform CW; causing the first transmitter to transmit the CW via an external transmission network and the receiver to obtain a first received CW from the external transmission network; causing the second transmitter to adjust the phase angle of the CW to a modulated CW; causing the second transmitter to transmit the modulated CW to the receiver via an internal feedback path, wherein the receiver is configured to combine the first received CW from the first transmitter and the modulated CW from the second transmitter into a combined CW; and a signal analyzer for generating a performance characteristic of the radar circuit based on the combined CW in response to obtaining the combined CW from the receiver.

16. The apparatus according to claim 15, wherein the apparatus is configured to test the radar circuit during production of the radar circuit.

17. The apparatus according to claim 15, wherein the CW is a signal having a frequency of seventy-seven gigahertz.

18. The apparatus according to claim 15, further comprising an alarm generator for transmitting a status signal to a device to cause the device to act on the radar circuit based on the quality of the performance characteristic.

19. The apparatus according to claim 18, wherein when the status signal indicates that production of the radar circuit is to be stopped, the device will stop producing the radar circuit.

20. The apparatus according to claim 15, wherein the performance characteristic includes the compression point of the receiver.

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