Bump Connection Placement in Quantum Devices in a Flip Chip Configuration

Abstract

Within the layout of the first surface in the flip-chip configuration, a bump restriction region is mapped according to a set of bump placement constraints, wherein the first bump placement constraint specifies a range of allowable distances between bumps in the layout of the first surface and qubit chip components, and wherein the second bump placement constraint specifies a range of allowable distances between bumps in the layout of the second surface in the flip-chip configuration and qubit chip components. Conductive material is deposited outside the bump restriction region to form bumps, wherein the bumps include conductive structures that electrically couple signals between the first surface and the second surface and are positioned according to the set of bump placement constraints.

Description

Technical Field

[0001] The present invention generally relates to methods, systems, and computer program products for component placement in quantum devices. More specifically, the present invention relates to methods, systems, and computer program products for bump connection placement in quantum devices in a flip-chip configuration. Background Art

[0002] In the following, unless explicitly distinguished in usage, the “Q” prefix in a word or phrase indicates a reference to the word or phrase in the context of quantum computing.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, a branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, taking on more than one state at a time and interacting with other particles at great distances. Quantum computing exploits these quantum phenomena to process information.

[0004] The computers we use today are called conventional computers (also referred to herein as "conventional" computers or conventional nodes, or "CNs"). Conventional computers use conventional processors, which are manufactured using semiconductor materials and technologies, semiconductor memory, and magnetic or solid-state storage devices, which is known as the von Neumann architecture. Specifically, the processors in conventional computers are binary processors, that is, they operate on binary data represented by 1s and 0s.

[0005] Quantum processors (q-processors) use the singularities of entangled quantum bit devices (complexly referred to herein as "qubits," multiple "qubits") to perform computational tasks. In the specific field of quantum mechanics, matter particles can exist in multiple states, such as "on," "off," and both "on" and "off" at the same time. While binary computing using semiconductor processors is limited to using only ON and OFF states (equivalent to 1 and 0 in binary code), quantum processors utilize these quantum states of matter to output signals that can be used for data calculations.

[0006] Traditional computers encode information in bits. Each bit can take on a value of 1 or 0, and these 1s and 0s act as on / off switches that ultimately drive the computer's functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both 1 and 0 at the same time. Entanglement means that qubits in superposition can be related to each other in a nonclassical way; that is, the state of one bit (whether it is 1 or 0 or both) can depend on the state of another bit, and more information can be determined when two qubits are entangled than when they are processed separately.

[0007] Using these two principles, qubits operate as more complex information processors, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers. IBM has successfully built and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines Corporation in the United States and other countries).

[0008] In known semiconductor manufacturing techniques, superconducting and semiconductor materials are used to create superconducting devices, such as qubits. Superconducting devices typically use one or more layers of different materials to achieve the device's performance and functionality. The material layers can be superconducting, conducting, semiconducting, insulating, resistive, inductive, capacitive, or have any number of other properties. Different methods may be necessary to form different material layers, depending on the nature of the material, its shape, size, or placement, other materials adjacent to it, and many other considerations.

[0009] Superconducting devices are typically planar, ie, where superconducting structures are fabricated on a single plane. Non-planar devices are three-dimensional (3D) devices where some structures are formed above or below a given fabrication plane.

[0010] The q-processor is implemented as more than one set of qubits. The qubits are fabricated as a lattice of coplanar devices on a single fabrication plane.

[0011] Superconducting qubit architectures typically arrange multiple qubits in a lattice structure in a single plane. The qubits are coupled to each other using resonant lines (also called "buses"). Read lines are used to read the quantum state of the qubits.

[0012] All resonant lines are coplanar (in the same plane) with the qubits. As a result, qubits located in the interior, non-peripheral regions of the lattice structure must be accessed orthogonally to the fabrication plane of the lattice. The non-peripheral regions or areas of the lattice are regions located inside the perimeter of the lattice. This way of accessing the interior qubits for modifying or reading the quantum state of the qubits is called "breaking the plane." Because breaking the plane can lead to performance degradation in quantum processors and increase the complexity of superconducting quantum circuits, quantum device implementations require careful design considerations when breaking the plane.

[0013] As the number of qubits in a quantum device increases, it becomes more difficult to arrange the qubits without interrupting the plane to access the internal qubits. For example, a sixteen-qubit device can have its qubits arranged in two parallel rows of eight qubits each, without internal qubits. However, a 24-qubit device with three parallel rows of eight qubits, each coupled in a square lattice layout, has internal qubit rows that cannot be accessed from the periphery of the arrangement within the circuit plane. Similarly, simply increasing the length of the two parallel rows (for example, using two parallel rows of twelve qubits each) results in the quantum device having undesirable additional area and the additional complexity of connecting the qubits at one end of the row to the qubits at the other end of the row. In addition, long runs of such connections require additional qubit operations and result in increased execution time for quantum algorithms. Summary of the Invention

[0014] Illustrative embodiments provide a method, system, and computer program product. Embodiments include a method for mapping a bump restriction region within a layout on a first surface in a flip-chip configuration according to a set of bump placement constraints, wherein the first bump placement constraint specifies a range of allowable distances between bumps in the layout on the first surface and qubit chip components, and wherein the second bump placement constraint specifies a range of allowable distances between bumps in the layout on the second surface in the flip-chip configuration and qubit chip components. Embodiments deposit a conductive material outside the bump restriction region to form bumps, wherein the bumps include conductive structures that electrically couple signals between the first surface and the second surface and are positioned according to the set of bump placement constraints.

[0015] Embodiments include a computer usable program product comprising one or more computer readable storage devices and program instructions stored on at least one of the one or more storage devices.

[0016] Embodiments include a computer system comprising one or more processors, one or more computer-readable memories, and one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Certain novel features which are believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, together with its preferred mode of use, further objects and advantages, will be best understood by reference to the following detailed description of illustrative embodiments taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 depicts a block diagram of a network of data processing systems in which the illustrative embodiments may be implemented;

[0019] Figure 2 depicts a block diagram of a data processing system in which the illustrative embodiments may be implemented;

[0020] Figure 3 depicts a block diagram of an example configuration for bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment;

[0021] Figure 4 depicts another block diagram of an example configuration for bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment;

[0022] Figure 5 depicts an example of bump connection placement in a quantum device in a flip-chip configuration according to an illustrative embodiment;

[0023] Figure 6 depicts another example of bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment;

[0024] Figure 7 depicts another example of bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment;

[0025] Figure 8 depicts another example of bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment;

[0026] Figure 9 depicts a flow chart of an example process for bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment;

[0027] Figure 10 another flow chart depicting an example process for bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment; and

[0028] Figure 11 Another flow chart depicts an example process for bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment. DETAILED DESCRIPTION

[0029] An internal qubit is a qubit that is not located on the periphery of the qubit configuration in the quantum device; in other words, the qubit is located at a physical location other than the periphery of the qubit configuration in the quantum device. The illustrative embodiments recognize that one solution for accessing internal qubits is to configure the quantum device in a flip-chip configuration. A flip-chip configuration, or simply flip-chip, interconnects a surface of a device or chip with another surface of a second chip using bumps that have been deposited on one or both surfaces so that the two surfaces are parallel to each other and the bumps on one surface are connected to corresponding bumps or surface locations on the second surface. A bump is a conductive structure formed three-dimensionally on a two-dimensional surface using at least a conductive material and, in some cases, a superconducting material. One property of a bump as contemplated herein is that the bump structure protrudes away from the two-dimensional surface in an orthogonal direction so that an electrical connection can be made at the bump from an orthogonal direction.

[0030] Typically, the bottom surface of one chip is connected to the top surface of a second chip, but other arrangements are possible and contemplated within the scope of the illustrative embodiments.In one embodiment, the height of the bump structure provides the desired amount of physical separation between the two surfaces.

[0031] In particular, in a quantum device flip-chip configuration, one chip (e.g., the bottom chip) typically includes elements that enable qubit connectivity, such as qubits and bus resonators. A second chip (e.g., the top chip) typically includes input / output elements that enable reading out individual qubits, such as qubit readout circuits and qubit write operations. Although one chip may be referred to as the bottom chip and the other chip as the top chip for convenience herein, and elements of a quantum device are described with reference to one chip or the other, or one surface or the other surface of a chip, any element of a quantum device may be arranged on any surface of any chip in any orientation of one or both chips.

[0032] The bumps of the quantum device in the flip chip configuration connect the ground planes of each chip in the flip chip together, suppressing spurious electromagnetic modes and improving signal integrity. Although most bumps connect the ground plane, some bumps can connect signals from one chip to another. The bumps also improve the mechanical integrity of the flip chip package by helping to physically hold the two chips together. In one embodiment, the material used to form the bumps is selected not only based on the material's electrical properties but also based on the material's mechanical properties, such as ductility and softness.

[0033] The illustrative embodiments recognize that to maintain the integrity of signal and ground planes, there are placement constraints on active components on each facing surface of a flip chip and on the bumps connecting the two surfaces. Quantum device circuit elements include qubits, resonators, filters, charging lines, buses, and other signal connection elements. Circuit elements on one surface must not touch, be closer than a specified threshold separation distance, or overlap circuit elements on other surfaces. Bumps must be placed at least a specified distance from circuit elements on each connected surface. Bump placement should be as uniform as possible across the surfaces, and the design should accommodate as many bumps as possible. In other words, the bump-to-bump distance in a given area should be roughly equal, and the bump-to-bump distance in that area should be minimized while meeting any design or manufacturing constraints. Furthermore, each bump on one surface must align with the corresponding bump or location on the other surface within a specified tolerance, so that corresponding locations can be electrically coupled to each other using each bump. Such constraints are typically incorporated into a set of design rules governing specific flip-chip configurations.

[0034] The illustrative embodiments also recognize that as the size of quantum devices increases, for example, when quantum devices grow beyond a few dozen qubits, placing components and bumps in a flip-chip configuration is too complex to be performed manually without violating any set of design rules. Components on one surface must be placed relative to components on the other surface. Bumps on one surface must be aligned with corresponding bumps or positions on the other surface. Moving one component or bump may require moving other components or bumps, and additional components or bumps may also need to be moved to meet different design rule constraints. In addition, design rule consistency checks for complex chip layouts must be completed in an automated manner; people cannot identify areas where there are not enough bumps or where bumps are placed too close to components, making it impossible to achieve the consistent, error-free approach required for robust device design. Therefore, the illustrative embodiments recognize that automated component and bump placement, design rule consistency checks, and bump adjustments are needed.

[0035] The illustrative embodiments recognize that currently available tools or solutions do not address these needs or provide adequate solutions to these needs. The illustrative embodiments used to describe the present invention generally address and solve the above-mentioned problems and other problems related to bump connection placement in quantum devices in a flip-chip configuration.

[0036] The embodiments may be implemented as a software application.The application implementing the embodiments may be configured as a modification of an existing quantum device design system, as a separate application operating in conjunction with an existing quantum device design system, as a standalone application, or some combination thereof.

[0037] In particular, some demonstrative embodiments provide a method of performing automated component and bump placement, design rule compliance checking, and bump tuning.

[0038] An embodiment receives as input a design specification for a quantum device in a flip-chip configuration. The design specification includes a plurality of qubits and connectivity requirements between qubits. Connectivity requirements are requirements for which qubits must be connected to which other qubits. Operations between qubits can only be performed on qubits that are connected to each other. As a result, while not all qubits in a quantum device need to be connected to each other, the more qubits that are connected to each other, the fewer additional operations are required to move information between qubits. For example, when a qubit communicates with only two other qubits, the qubit connectivity may be considered sparse. In another example, when a qubit communicates with four, five, or six other qubits, the qubit connectivity may be considered dense.

[0039] Based on the number of qubits and the connectivity requirements between the qubits, embodiments estimate the total area required per surface to implement the final flip-chip configuration. For example, if each qubit occupies one unit of area, a quantum device with fifty qubits will use less total area than a quantum device with one hundred qubits. Furthermore, while denser connectivity can lead to more efficient quantum devices, this additional connectivity also requires additional buses and additional chip area for these additional buses.

[0040] The design specifications also include bump information for the flip chip. The bump information includes the size of each bump (the diameter within the surface and the height above the surface plane). The bump information also includes the bump spacing (i.e., the center-to-center distance between a bump and an adjacent bump). The bump size and spacing specified for a specific flip chip depend on the size of the components in the quantum device, the accuracy with which the components and bumps can be placed on the flip chip surface, signal and ground integrity considerations, and other considerations. In a non-limiting example, a design specification specifies a 100 micron bump diameter and a 200 micron bump spacing, thereby generating 300 to 600 bumps in the resulting flip chip based on the total chip area.

[0041] The embodiment also receives as input a plurality of design rule sets for quantum devices in a flip-chip configuration. A design rule set controls the placement of circuit elements on each surface of the flip-chip. For example, the design rule set may specify minimum or maximum dimensions for a particular element, minimum spacing between one element and another, or between one type of element and a different type of element, etc.

[0042] Another set of design rules controls the placement of components on one surface of the flip chip relative to the placement of components on the other surface of the flip chip. For example, this set of design rules may specify that components on one surface cannot overlap components on another surface, or that components on one surface must be a minimum distance from components on another surface.

[0043] A third set of design rules governs the relative placement of bumps and circuit components on each surface of the flip chip. For example, the third set of design rules may specify that bumps must have a minimum distance from components on either surface, or that bumps must have a minimum distance from one type of component and another minimum distance from another type of component.

[0044] Referring to a set of design rules, an embodiment places all required components on one surface of the flip chip. Referring to a set of design rules, this embodiment then places all required components on the opposite surface of the flip chip, ensuring that any rules regarding relative component placement are followed. In particular, one embodiment places all qubits and coupling elements on the bottom chip, and then places all write and read elements on the top chip, ensuring that all design rules regarding component overlap and minimum distances are followed. Another embodiment places all write and read elements on the top chip, and then places all qubits and coupling elements on the bottom chip. Another embodiment interleaves the component placement on each surface, rather than placing components on one surface at a time.

[0045] Once all components on both surfaces have been placed, embodiments place bumps. Embodiments composite the component layout on one flip-chip surface with the component layout on the other flip-chip surface. As used herein, composite refers to combining visual elements from separate sources into a single layout or image. Thus, the composite layout includes every component on both surfaces. Because no bump should contact a circuit component, embodiments define each area occupied by a circuit element in the composite layout as part of a bump-restricted area. Because each bump should be separated from each circuit element by a minimum distance, embodiments expand the bump-restricted area in the composite layout by any applicable minimum distance. The minimum distance can vary depending on the type of component. For example, the minimum distance to a qubit can be greater than the minimum distance to a bus. One or more minimum distances are specified in the design rules governing the relative placement of bumps and components. Additionally, embodiments adjust the bump-restricted area, expanding or shrinking it, so that any resulting bump will comply with any applicable design rules.

[0046] One embodiment places bumps by overlapping a composite layout with uniformly tiled bumps at a specified bump spacing, and then removing any bumps that fall at least partially within a bump restriction area. In one embodiment, the tiling is orthogonal. In another embodiment, the tiling is non-orthogonal. The embodiment also remembers which bumps were removed for possible restoration. This method results in uniform bump spacing throughout the composite layout, which is desirable. However, because bumps that even partially overlap the bump restriction area are removed, the resulting composite layout may include fewer bumps than desired.

[0047] Another embodiment places bumps by defining a bump placement area. The bump placement area includes all composite layouts that are not within the bump restriction area. This embodiment then places a uniformly tiled set of bumps within the bump placement area. Because the bumps are placed within the defined bump placement area, there are no bumps that fall at least partially within the bump restriction area to create overlap. However, because the bump placement area may include non-contiguous areas, the bumps will be uniform within each area, but not necessarily uniform across the entire chip. Similarly, although bump removal is not required, portions of the bump placement area may be too small to contain bumps. Such areas without bumps are undesirable.

[0048] Once the embodiment has performed the initial bump placement, the embodiment checks whether the bump placement complies with the design rule set. If the bump or component does not comply with the design rules, the embodiment adjusts the position of the bump or component, or adds or removes bumps to produce a final composite layout that complies with the design rules.

[0049] Specifically, embodiments check whether the removed bump at least partially falls within the bump restriction area. The bump overlap area is the bump area within the bump restriction area divided by the total bump area, optionally converted to a percentage. If the bump overlap area is below the overlap threshold specified in the design rules, embodiments restore the bump but move the bump in the x-direction, y-direction, or both to a position where the bump no longer overlaps the bump restriction area. For example, if the bump overlap area is 10% and the overlap threshold specified in the design rules is 20%, embodiments restore the bump but adjust the bump's position to a position where the bump no longer overlaps the bump restriction area.

[0050] Embodiments also examine composite layouts for areas without bumps, or for areas with a number of bumps or a bump density (i.e., the number of bumps per unit area) below a threshold specified in the design rules. One embodiment searches the composite layout for element patterns corresponding to patterns that may have a number of bumps or a bump density below the threshold specified in the design rules. For example, an island is a portion of a ground plane that is electrically isolated from the rest of the ground plane because the portion is not connected to or does not have sufficient connections to another portion of the ground plane as specified in the design rules. An island requires at least a threshold number of bumps or at least a threshold bump density to reliably form a connection to electrical ground. As another example, a tip is a narrow line of metal that, due to its shape, is too narrow to accommodate at least a threshold number of bumps or at least a threshold bump density required to reliably connect the tip to electrical ground. Islands and tips are two non-limiting examples of types of areas within a chip layout for a flip-chip configuration that may have a number of bumps or a bump density below the threshold specified in the design rules. Other types of areas are also possible and contemplated within the scope of exemplary embodiments.

[0051] If an embodiment finds an area with a bump count or bump density below a threshold specified in a design rule, the embodiment adjusts the position of bumps or components, or adds or removes bumps, to produce a final composite layout that does comply with the design rule. For example, if component placement results in a portion of the bump placement area being too small to contain a sufficient number of bumps, the embodiment can move the component to another position in the x-direction, the y-direction, or both, so that the resulting bump placement area no longer has a portion that is too small to contain a sufficient number of bumps.

[0052] If the embodiment adjusts the position of the bump or circuit element, or adds or removes a bump, the embodiment rechecks that the adjusted layout now complies with the design rule set. If the bump or element still does not comply with the design rules, the embodiment repeats the adjustment and checking process until a final composite layout is generated that does comply with the design rules.

[0053] In the field of quantum device design systems, currently available methods for placing bump connections in quantum devices in flip-chip configurations as described herein are not feasible. When implemented on a device or data processing system, the methods of the embodiments described herein comprise substantial advancements in the functionality of the device or data processing system in performing automated component and bump placement, design rule compliance checking, and bump tuning.

[0054] By way of example only, the illustrative embodiments are described with respect to certain types of surfaces, configurations, qubit connection elements, qubit readout elements, bumps, adjustments, insertions, removals, measurements, devices, data processing systems, environments, components, and applications. Any particular representation of these and other similar artifacts is not intended to limit the invention. Any suitable representation of these and other similar artifacts may be selected within the scope of the exemplary embodiments.

[0055] Furthermore, the illustrative embodiments may be implemented with respect to any type of data, data source, or access to a data source over a data network. Within the scope of the present invention, any type of data storage device may provide data to embodiments of the present invention locally at a data processing system or over a data network. Where embodiments are described using mobile devices, within the scope of the illustrative embodiments, any type of data storage device suitable for use with a mobile device may provide data to such embodiments locally at the mobile device or over a data network.

[0056] The illustrative embodiments are described using specific codes, designs, architectures, protocols, layouts, schematics, and tools, which are examples only, rather than limitations of the illustrative embodiments. In addition, for clarity of description, specific software, tools, and data processing environments are used in some instances to describe the illustrative embodiments only as examples. The illustrative embodiments can be used in conjunction with other comparable or similar purpose structures, systems, applications, or architectures. For example, within the scope of the present invention, other comparable mobile devices, structures, systems, applications, or their architectures can be used in conjunction with such embodiments of the present invention. The illustrative embodiments can be implemented with hardware, software, or a combination thereof.

[0057] The examples in this disclosure are for clarity of description only and are not intended to limit the illustrative embodiments. Additional data, operations, actions, tasks, activities, and manipulations can be envisioned from this disclosure and can be considered within the scope of the illustrative embodiments.

[0058] Any advantages listed herein are merely examples and are not intended to limit the illustrative embodiments. Additional or different advantages may be achieved by specific illustrative embodiments. Furthermore, specific illustrative embodiments may have some, all, or none of the advantages listed above.

[0059] With reference to the accompanying drawings, and in particular with reference to Figure 1 and 2 , these figures are illustrative diagrams of data processing environments in which illustrative embodiments may be implemented. Figure 1 and 2This is merely an example and is not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Specific implementations may make many modifications to the depicted environments based on the following description.

[0060] Figure 1 A block diagram depicts a network of data processing systems in which the illustrative embodiments may be implemented. Data processing environment 100 is a computer network in which the illustrative embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between various devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired or wireless communication links or fiber optic cables.

[0061] Client or server are merely example roles for certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles for these data processing systems. Server 104 and server 106 are coupled to network 102 along with storage unit 108. Software applications may be executed on any computer in data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as servers 104 or 106 or clients 110, 112, or 114 may contain data and may have software applications or software tools executing thereon.

[0062] By way of example only, and without implying any limitation on such architecture, Figure 1 Certain components that may be used in example implementations of the embodiments are depicted. For example, servers 104 and 106 and clients 110, 112, 114 are depicted as servers and clients, for example only, and not to imply limitation to client-server architectures. As another example, an embodiment may be distributed across multiple data processing systems and data networks as shown, while another embodiment may be implemented on a single data processing system within the scope of the illustrative embodiments. Data processing systems 104, 106, 110, 112, and 114 also represent example nodes in clusters, partitions, and other configurations suitable for implementing the embodiments.

[0063] Device 132 is an example of a device described herein. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a fixed or portable form of client 110, a wearable computing device, or any other suitable device. Figure 1 Any software application executing in another data processing system in may be configured to execute in device 132 in a similar manner. Figure 1 Any data or information stored or generated in another data processing system in may be configured to be stored or generated in device 132 in a similar manner.

[0064] Application 105 implements the embodiments described herein. Application 105 can be executed in any of servers 104 and 106, clients 110, 112, and 114, and device 132.

[0065] Servers 104 and 106, storage unit 108, clients 110, 112, and 114, and device 132 may be coupled to network 102 using wired connections, wireless communication protocols, or other suitable data connections. Clients 110, 112, and 114 may be, for example, personal computers or network computers.

[0066] In the depicted example, server 104 can provide data, such as boot files, operating system images, and applications to clients 110, 112, and 114. In this example, clients 110, 112, and 114 can be clients to server 104. Clients 110, 112, 114, or some combination thereof, can include their own data, boot files, operating system images, and applications. Data processing environment 100 may include additional servers, clients, and other devices not shown.

[0067] In the described example, data processing environment 100 can be the Internet. Network 102 can represent the set of networks and gateways that use Transmission Control Protocol / Internet Protocol (TCP / IP) and other protocols to communicate with each other. At the core of the Internet is the backbone of data communication links between master nodes or host computers, including thousands of commercial, government, educational and other computer systems that route data and messages. Of course, data processing environment 100 also can be implemented as many different types of networks, such as, for example, intranets, local area networks (LANs) or wide area networks (WANs). Figure 1 It is intended as an example, not as an architectural limitation for the different illustrative embodiments.

[0068] In addition to other purposes, data processing environment 100 can be used to realize the client-server environment in which exemplary embodiments can be realized. The client-server environment enables software applications and data to be distributed across a network so that the application works by using the interactivity between the client data processing system and the server data processing system. Data processing environment 100 can also adopt a service-oriented architecture in which the interoperable software components distributed across a network can be packaged together as consistent business applications. Data processing environment 100 can also take the form of a cloud, and adopt the cloud computing model of service delivery to realize the convenient on-demand network access to the shared pool of configurable computing resources (for example, network, network bandwidth, server, processing, memory, storage, application, virtual machine and service), which can be quickly supplied and released with minimal management effort or with the interaction of the provider of service.

[0069] refer to Figure 2 , which depicts a block diagram of a data processing system in which the illustrative embodiments may be implemented. Data processing system 200 is an example of a computer, such as Figure 1 Servers 104 and 106, or clients 110, 112, and 114, or another type of device, in which computer usable program code or instructions implementing the processes may be provided for exemplary embodiments.

[0070] Data processing system 200 also represents a data processing system or configuration thereof, such as Figure 1 The data processing system 132 in the embodiment may contain computer usable program code or instructions that implement the processes of the exemplary embodiments. The data processing system 200 is described as a computer only as an example and is not limited thereto. Without departing from the general description of the operation and functionality of the data processing system 200 described herein, the computer may be used in a manner such as Figure 1 Implementations in the form of other devices for device 132 may modify data processing system 200 , such as by adding a touch interface, and even removing certain depicted components from data processing system 200 .

[0071] In the depicted example, data processing system 200 employs a hub architecture including a north bridge and memory controller hub (NB / MCH) 202 and a south bridge and input / output (I / O) controller hub (SB / ICH) 204. Processing unit 206, main memory 208, and graphics processor 210 are coupled to north bridge and memory controller hub (NB / MCH) 202. Processing unit 206 may include one or more processors and may be implemented using one or more heterogeneous processor systems. Processing unit 206 may be a multi-core processor. In some implementations, graphics processor 210 may be coupled to NB / MCH 202 via an accelerated graphics port (AGP).

[0072] In the depicted example, local area network (LAN) adapter 212 is coupled to south bridge and I / O controller hub (SB / ICH) 204. Audio adapter 216, keyboard and mouse adapter 220, modem 222, read-only memory (ROM) 224, universal serial bus (USB) and other ports 232, and PCI / PCIe devices 234 are coupled to south bridge and I / O controller hub 204 via bus 238. Hard disk drive (HDD) or solid state drive (SSD) 226 and CD-ROM 230 are coupled to south bridge and I / O controller hub 204 via bus 240. PCI / PCIe devices 234 may include, for example, Ethernet adapters, add-in cards, and PC Cards for notebook computers. PCI uses a card bus controller, while PCIe does not. ROM 224 may be, for example, a flash binary input / output system (BIOS). Hard drive 226 and CD-ROM 230 may use, for example, an integrated drive electronics (IDE), a serial advanced technology attachment (SATA) interface, or variations such as external SATA (eSATA) and micro SATA (mSATA). Super I / O (SIO) device 236 may be coupled to south bridge and I / O controller hub (SB / ICH) 204 via bus 238.

[0073] Memories, such as main memory 208, ROM 224, or flash memory (not shown), are some examples of computer-usable storage devices. Hard disk drives or solid-state drives 226, CD-ROMs 230, and other similarly available devices are some examples of computer-usable storage devices that include computer-usable storage media.

[0074] An operating system runs on processing unit 206. The operating system coordinates and provides Figure 2 The operating system may be a commercially available operating system for any type of computing platform, including but not limited to server systems, personal computers, and mobile devices, and controls the various components within data processing system 200. An object-oriented or other type of programming system may operate in conjunction with the operating system and provide calls to the operating system from programs or applications executing on data processing system 200.

[0075] for operating systems, object-oriented programming systems, and systems such as Figure 1The instructions for the applications or programs in application 105 are located on a storage device, such as in the form of code 226A on hard drive 226, and may be loaded into at least one of one or more memories, such as main memory 208, for execution by processing unit 206. The processes of the illustrative embodiments may be performed by processing unit 206 using computer-implemented instructions, which may be located in a memory, such as, for example, main memory 208, read-only memory 224, or in one or more peripheral devices.

[0076] Furthermore, in one embodiment, code 226A may be downloaded from remote system 201B via network 201A, where similar code 201C is stored on storage device 201D. In another embodiment, code 226A may be downloaded to remote system 201B via network 201A, where the downloaded code 201C is stored on storage device 201D.

[0077] Figures 1 to 2 The hardware in may vary depending on the implementation. Figures 1 to 2 In addition to or in place of the hardware described in the accompanying drawings, other internal hardware or peripheral devices such as flash memory, equivalent non-volatile memory, or optical disk drives may be used. Furthermore, the processes of the illustrative embodiments may be applied to a multi-processor data processing system.

[0078] In some illustrative examples, data processing system 200 may be a personal digital assistant (PDA), which is typically configured with flash memory to provide non-volatile memory for storing operating system files and / or user-generated data. A bus system may include one or more buses, such as a system bus, an I / O bus, and a PCI bus. Of course, a bus system may be implemented using any type of communication structure or architecture that provides for the transfer of data between different components or devices attached to the structure or architecture.

[0079] The communication unit may include one or more devices for sending and receiving data, such as a modem or a network adapter. A memory may be, for example, main memory 208 or a cache, such as found in north bridge and memory controller hub 202. A processing unit may include one or more processors or CPUs.

[0080] Figures 1 to 2 The examples described in and above are not meant to imply architectural limitations. For example, data processing system 200 may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a mobile or wearable device.

[0081] Where a computer or data processing system is depicted as a virtual machine, virtual appliance, or virtual component, the virtual machine, virtual appliance, or virtual component uses virtualized representations of some or all of the components depicted in data processing system 200 to operate in the manner of data processing system 200. For example, in the virtual machine, virtual appliance, or virtual component, processing unit 206 is represented as a virtualized instance of all or some number of hardware processing units 206 available in the host data processing system, main memory 208 is represented as a virtualized instance of all or some portion of main memory 208 available in the host data processing system, and hard disk 226 is represented as a virtualized instance of all or some portion of hard disk 226 available in the host data processing system. In this case, the host data processing system is represented by data processing system 200.

[0082] refer to Figure 3 , which depicts a block diagram of an example configuration for bump connection placement in a quantum device in a flip-chip configuration, in accordance with an illustrative embodiment. Application 300 is Figure 1 An example of application 105, and in Figure 1 104 and 106 , clients 110 , 112 and 114 , and device 132 .

[0083] Application 300 receives as input a design specification for a quantum device in a flip-chip configuration. The design specification includes a number of qubits and connectivity requirements between the qubits. Based on the number of qubits and the connectivity requirements between the qubits, an embodiment estimates the total area required for each surface to implement the final flip-chip configuration. Application 300 also receives as input a plurality of design rule sets for the quantum device in a flip-chip configuration. Referring to the design rule sets, component placement module 310 places all required components on one surface of the flip-chip. Referring to the design rule sets, module 310 then places all required components on the opposite surface of the flip-chip, ensuring that any rules regarding relative component placement are followed.

[0084] Once all components on both surfaces have been placed, the bump layout module 320 places the bumps. Specifically, module 320 composites the component layout on one flip chip surface with the component layout on the other flip chip surface. Because no bump should touch a component, each area occupied by a component is defined as part of a bump confinement region in composite layout module 320. Because each bump should be separated from each component by a minimum distance, the bump confinement region is expanded by any applicable minimum distance in composite layout module 320. The minimum distance can vary depending on the type of component. For example, the minimum distance to a qubit can be greater than the minimum distance to a bus. One or more minimum distances are specified in the design rules governing the relative placement of bumps and components. In addition, module 320 adjusts the bump confinement region, expanding or shrinking it, so that any generated bump will comply with any applicable design rules.

[0085] In one embodiment, module 320 places bumps by overlaying uniformly tiled bumps with the composite layout at a specified bump pitch, and then removes any bumps that fall at least partially within the bump restriction area. Module 320 also remembers which bumps were removed for possible recovery.

[0086] In another implementation, module 320 places bumps by defining a bump placement region. The bump placement region includes all composite layouts that are not within the bump restriction region. Module 320 then places a uniformly tiled set of bumps within the bump placement region.

[0087] Once module 320 has performed the initial bump placement, a bump rule checker module 330 checks whether the bump placement complies with the design rule set. If the bump or component does not comply with the design rules, an adjustment module 340 adjusts the position of the bump or component, or adds or removes bumps, to produce a final composite layout that complies with the design rules.

[0088] refer to Figure 4 , which depicts another block diagram of an example configuration for bump connection placement in a quantum device in a flip-chip configuration, in accordance with an illustrative embodiment. In particular, Figure 4 Depicts Figure 3 More details of the adjustment module 340 are given in FIG.

[0089] The overlap search module 410 checks whether the removed bump falls at least partially within the bump restriction area. If the overlap area of the bump is below the overlap threshold specified in the design rules, the bump recovery module 430 recovers the bump but moves the bump in the x-direction, the y-direction, or both to a position where the bump no longer overlaps the bump restriction area.

[0090] The bump sufficiency module 420 also checks the composite layout for areas without bumps, or for areas with a bump count or bump density (i.e., the number of bumps per unit area) below a threshold specified in the design rules. In one embodiment, the module 420 searches the composite layout for component patterns, such as islands or tips, that correspond to patterns that may have a bump count or bump density below the threshold specified in the design rules.

[0091] If module 420 finds an area with a bump count or bump density below a threshold specified in the design rules, then bump adjustment module 440 and component adjustment module 450 work together to adjust the positions of bumps or components, or add or remove bumps, to produce a final composite layout that does comply with the design rules.

[0092] refer to Figure 5 , which depicts an example of bump connection placement in a quantum device in a flip-chip configuration according to an illustrative embodiment. This example can be used Figure 3 This is achieved by using the application 300 in FIG.

[0093] Specifically, Figure 5 The steps of bump placement performed by application 300 are depicted. Step 502 illustrates the uniform tiling of bumps, such as bump 520, at a specified bump spacing, in preparation for overlapping the composite layout. Step 504 depicts the uniform tiling of bumps composited with bump confinement region 540, i.e., the composite layout of components on one flip chip surface with the layout of components on another flip chip surface. Step 506 illustrates the uniform tiling of bumps composited with an expanded bump confinement region 560 and an expansion of bump confinement region 540 to ensure that each bump is separated from each component by a minimum distance. As shown, bump 562 partially overlaps with the expanded bump confinement region 560, while bump 520 does not. Step 508 illustrates the resulting layout after removing any bumps (such as bump 562) that at least partially fall within the now expanded bump confinement region. As depicted, bump 562 no longer exists in region 580.

[0094] refer to Figure 6 , which depicts another example of bump connection placement in a quantum device in a flip-chip configuration according to an illustrative embodiment. This example can be used Figure 3 This is achieved by using the application 300 in FIG.

[0095] Specifically, Figure 6The steps of bump placement performed by application 300 are depicted. Step 602 depicts bump confinement area 620, which is defined by compounding the component layout on one flip chip surface with the component layout on the other flip chip surface. Step 604 shows an expanded bump confinement area 640, which is expanded to ensure that each bump is separated from each component by a minimum distance. Step 606 depicts bump placement area 662, which includes all compounded layouts that are not within expanded bump confinement area 640. Step 608 depicts a uniformly tiled set of bumps, such as bump 680, within bump placement area 662. Because the bumps are placed within bump placement area 662, there are no bumps that fall at least partially within the bump confinement area to create overlap.

[0096] refer to Figure 7 , which depicts another example of bump connection placement in a quantum device in a flip-chip configuration according to an illustrative embodiment. This example can be used Figure 3 Steps 506 and 508, bump 562 and region 580 are implemented in the application 300. Figure 5 Steps 506 and 508, bump 562, and region 580 are the same.

[0097] Specifically, Figure 7 The option of overlapping bump recovery performed by application 300 is depicted. As shown in step 506, bump 562 within region 580 partially overlaps component 706 in the expanded bump restriction region 560. Step 508 shows the resulting layout after removing any bumps (such as bump 562) that at least partially fall within the now expanded bump restriction region. Therefore, in step 508, bump 562 no longer exists in region 580.

[0098] Because the overlap area of bump 562 is below the overlap threshold specified in the design rules, the application restores bump 562, but moves bump 562 in the x-direction, y-direction, or both to a position where the bump no longer overlaps the bump limit area. As a result, option 710 shows bump 562 moved to the right. Alternatively, the application restores bump 562, but moves an element such as element 706 in the x-direction, y-direction, or both to a position where bump 562 no longer overlaps the bump limit area. As a result, option 720 depicts element 706 moved to the left. However, moving element 706 in option 720 requires removing the additional bump.

[0099] refer to Figure 8 , which depicts another example of bump connection placement in a quantum device in a flip-chip configuration according to an illustrative embodiment. This example can be used Figure 3 This is achieved by using the application 300 in FIG.

[0100] In particular, Figure 8 Options are depicted for identifying areas without bumps. Specifically, in layout 810, bumps such as bump 802 are placed near component 814. However, the application identifies area 812 as an area without bumps. Therefore, option 820 depicts bumps added to area 812, such as bump 820. Similarly, option 820 depicts new component 834, rearranging component 814 to occupy a smaller area. Additional bumps, such as bump 820, have been added to the area thus available.

[0101] refer to Figure 9 , which depicts a flow chart of an example process for bump connection placement in a quantum device in a flip-chip configuration, according to an illustrative embodiment. Process 900 may be performed at Figure 3 The application 300 is implemented in FIG.

[0102] In block 902, the application places the qubit chip component within a layout on a first surface in a flip-chip configuration according to a set of placement rules governing placement of the qubit chip component. In block 904, the application places the qubit chip component within a layout on a second surface in a flip-chip configuration according to a set of placement rules governing placement of the qubit chip component and relative placement of the components. In block 906, the application maps a bump restriction region within the first surface layout according to a set of bump placement constraints. In block 908, the application places a set of evenly spaced bumps within the bump restriction region according to the set of bump placement constraints. In block 910, the application checks the bump placement against the set of bump placement constraints. In block 912, if necessary, the application adjusts the position of the bumps or components or adds bumps to comply with the set of bump placement constraints. In block 914, the application connects each bump within the first surface layout with a corresponding bump within the second surface layout to form a flip-chip configuration. The application then terminates.

[0103] refer to Figure 10 , which depicts another flow chart of an example process for bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment. Figure 10 Depicts Figure 9 More details on box 908 in .

[0104] In block 1002, the application places a set of equally spaced bumps within a layout of one of the surfaces according to the set of bump placement constraints. In block 1004, the application removes any placed bumps that fall at least partially within the bump constraint region. The application then ends.

[0105] refer to Figure 11 , which depicts another flow chart of an example process for bump connection placement in a quantum device in a flip-chip configuration in accordance with an illustrative embodiment. Figure 11Depicts Figure 9 More details of another embodiment of block 908 in FIG.

[0106] In block 1102, the application maps a bump placement region within the layout of the first surface and outside the bump restriction region. In block 1104, the application places a set of equally spaced bumps within the bump placement region according to the bump placement restriction set. The application then ends.

[0107] Thus, in illustrative embodiments, a computer-implemented method, system or apparatus, and computer program product are provided for bump connection placement and other related features, functions, or operations in a quantum device in a flip-chip configuration. Where an embodiment or a portion thereof is described with respect to one type of device, the computer-implemented method, system or apparatus, computer program product, or a portion thereof is adapted or configured for use with an appropriate and comparable representation of that type of device.

[0108] Where embodiments are described as being implemented in an application, delivery of the application in a Software as a Service (SaaS) model may be considered within the scope of the illustrative embodiments. In a SaaS model, the ability to implement the application of the embodiments is provided to users by executing the application in a cloud infrastructure. Users can access the application using a variety of client devices through a thin client interface such as a web browser (e.g., web-based email) or other lightweight client applications. Users do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage of the cloud infrastructure. In some cases, users may not even manage or control the capabilities of the SaaS application. In some other cases, the SaaS implementation of the application may allow for limited possible exceptions to user-specific application configuration settings.

[0109] The present invention may be a system, method and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform aspects of the present invention.

[0110] A computer-readable storage medium can be a tangible device that can retain and store instructions used by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a bump structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0111] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0112] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits, or source code or object code written in any combination of one or more programming languages (including object-oriented programming languages, such as Smalltalk, C++, etc.) and procedural programming languages (such as "C" programming language or similar programming languages). The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an internet service provider through the internet). In some embodiments, in order to perform various aspects of the present invention, an electronic circuit comprising, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute the computer-readable program instructions to personalize the electronic circuit by utilizing the state information of the computer-readable program instructions.

[0113] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present invention. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0114] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can direct the computer, programmable data processing device, and / or other equipment to operate in a specific manner, such that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0115] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0116] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions noted in the box may not occur in the order noted in the figure. For example, two boxes shown in succession can actually be executed substantially simultaneously, or these boxes can sometimes be executed in the opposite order, depending on the functions involved. It will also be noted that each box in the block diagram and / or flowchart illustration and the combination of boxes in the block diagram and / or flowchart illustration can be implemented by a dedicated, hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

Claims

1. A computer-implemented method comprising: mapping a bump restriction region within a layout of a first surface in a flip-chip configuration according to a set of bump placement constraints, wherein a first bump placement constraint specifies an allowable range of distances between bumps in the layout of the first surface and qubit chip components, and wherein a second bump placement constraint specifies an allowable range of distances between bumps in the layout of a second surface in the flip-chip configuration and qubit chip components; checking the layout of the first surface for consistency with a third bump placement constraint and a fourth bump placement constraint, wherein the third bump placement constraint specifies an allowable distance range between first bumps and second bumps in the layout of the first surface, and wherein the fourth bump placement constraint specifies a minimum allowable bump density for a portion of the layout of the first surface; In response to the inspecting, adjusting a bump density of a portion of the layout of the first surface; as well as Outside the bump restriction area, a conductive material is deposited to form the bump, wherein the bump includes a conductive structure that electrically couples signals between the first surface and the second surface and is positioned according to the set of bump placement restrictions.

2. The computer-implemented method of claim 1 , further comprising: placing a set of bumps within the layout of the first surface according to a bump placement constraint, the bump placement constraint specifying a range of allowable distances between a first bump and a second bump in the layout of the first surface; as well as Bumps in the bump set that are at least partially within the bump confinement region are removed from the layout of the first surface.

3. The computer-implemented method of claim 1 , further comprising: mapping a bump placement area within the layout of the first surface, the bump placement area comprising: a portion of the layout of the first surface outside the bump confinement area; and A set of bumps are placed within the bump placement region according to a bump placement constraint that specifies an allowable distance range between a first bump and a second bump in the layout of the first surface.

4. The computer-implemented method of claim 1 , further comprising: As part of the adjustment, restoring a bump within the portion that was previously removed is used to bring the bump at least partially within the bump restriction area, the restored bump having an adjusted placement that complies with the first bump placement restriction, the second bump placement restriction, the third bump placement restriction, and the fourth bump placement restriction.

5. The computer-implemented method of claim 1 , further comprising: As part of the adjusting, a second set of bumps is added within the portion, the second set of bumps being equidistant, and placement of each bump in the second set of bumps conforming to the first, second, third, and fourth bump placement constraints.

6. The computer-implemented method of claim 1 , further comprising: As part of the adjusting, placement of bumps within the portion is changed, the adjusted bumps having new placements that comply with the first, second, third, and fourth bump placement constraints.

7. The computer-implemented method of claim 1 , further comprising: As part of the adjusting, a placement of a qubit chip component in the layout of the first surface is changed, the adjusted component having a new placement that complies with the first bump placement constraint, the second bump placement constraint, the third bump placement constraint, and the fourth bump placement constraint.

8. The computer-implemented method of claim 1 , further comprising: In response to the inspecting determining that a portion of the layout of the first surface has a bump density below the minimum allowed bump density, adjusting a placement of a qubit chip element in the layout of the second surface, the adjusted element having a new placement that complies with the first bump placement constraint, the second bump placement constraint, the third bump placement constraint, and the fourth bump placement constraint.

9. A system comprising means adapted to perform all the steps of the method according to any preceding method claim.

10. A computer program comprising instructions for performing all the steps of the method according to any preceding method claim, when said computer program is executed on a computer system.

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