Memory device architecture coupled to a system on a chip

Abstract

The present disclosure relates to a flash memory portion architecture coupled to a system on a chip (SoC) including a matrix of memory cells with associated decoding and sensing circuitry and having a structure independent structure linked to the system on a chip, and comprising: a plurality of sub-arrays forming the matrix of memory cells; sense amplifiers coupled to corresponding sub-arrays; a data buffer including a plurality of JTAG cells coupled to outputs of the sense amplifiers; scan chains connecting the JTAG cells of the data buffer together.

Description

Technical Field

[0001] The present invention relates to memory devices, and more particularly to an architecture for flash memory devices coupled to a system on a chip (SoC). More specifically, the present invention relates to a scalable and high throughput architecture for flash memory cell arrays. Background Art

[0002] Flash memory is a type of nonvolatile memory that retains stored data without requiring periodic refreshing due to the presence of electricity. Key features of flash memory are its extremely fast access time and the fact that it can be erased in blocks rather than one byte at a time. Each erasable memory block consists of a plurality of nonvolatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. Cells are read, programmed, and erased by manipulating the voltages on the access and data lines.

[0003] Non-volatile memory retains its contents when power is removed, making it ideal for storing information that must be retrieved after the system is powered on. However, non-volatile memory is typically much slower to read and write than volatile memory and often has more complex write and erase procedures. Furthermore, relatively high voltages must be applied to the cell array. The read phase is typically accomplished using a finite state machine (FSM) that regulates all timings and internal voltages.

[0004] Non-volatile flash memory is one of the fundamental building blocks in today's modern electronic systems, including SoC devices for automotive applications, particularly real-time operating systems (RTOS). The increasing importance of flash memory performance in terms of speed, power consumption, variability, non-volatility, and system reconfigurability has driven its integration into single-chip system devices. However, embedded memory implemented with SoC technology is becoming an increasingly large component in the SoC, and increasing its size beyond 128 Mbit, for example, is not feasible.

[0005] Flash memory integration introduces many issues that require careful design at both the system and circuit / technology levels. From a system perspective, the choice of the type of flash memory to be integrated into an SoC device involves several aspects depending on the specific application and requirements, most importantly yield, followed by cost, power consumption, reliability, and performance requirements. Summary of the Invention

[0006] According to aspects of the present application, a flash memory device architecture coupled to a system-on-chip (SoC) is provided. The flash memory device architecture includes a memory cell matrix with associated decoding and sensing circuitry and has a structurally independent structure linked to the SoC, and includes: a plurality of sub-arrays forming the memory cell matrix; sense amplifiers coupled to corresponding sub-arrays; a data buffer including a plurality of JTAG cells coupled to the outputs of the sense amplifiers; and a scan chain connecting the JTAG cells of the data buffer together.

[0007] According to another aspect of the present application, a nonvolatile memory architecture is provided. The nonvolatile memory architecture has a structurally independent structure obtained through memory manufacturing technology and is configured to be coupled to a system-on-chip (SoC) device through interconnect pins or pads. The nonvolatile memory architecture includes: a memory cell array formed of a plurality of sub-arrays; sense amplifiers coupled to corresponding sub-arrays of the plurality of sub-arrays; sense amplifiers coupled to the memory cells having corresponding outputs; a data buffer including a plurality of JTAG cells coupled to the outputs of the sense amplifiers; and a scan chain connecting the JTAG cells of the data buffer together.

[0008] According to another aspect of the present application, an integrated circuit is provided. The integrated circuit includes a system-on-chip (SoC) device and a nonvolatile memory device, the nonvolatile memory device being obtained as an independent die using corresponding manufacturing technologies and coupled to corresponding interconnect pins or pads, the integrated circuit comprising: a memory array including a plurality of independently addressable sub-arrays in the memory device; sense amplifiers coupled to corresponding output terminals of the sub-arrays and to a communication channel of the SoC device; and a scan chain including a modified JTAG cell coupled in parallel between the output terminals of the sense amplifiers and the communication channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] 1 is a schematic perspective view of a system-on-chip device including an embedded memory portion according to the prior art;

[0010] Figure 2 is a schematic perspective view of a system-on-chip device according to the present disclosure and including a memory component that replaces an embedded memory portion of a prior art device;

[0011] Figure 3 is a schematic diagram of a memory component according to the present disclosure;

[0012] Figure 4 yes Figure 3 A schematic diagram showing details of a memory portion shown in FIG.

[0013] Figure 4A yes Figure 4 Another schematic diagram of yet another detail of the memory portion shown in FIG;

[0014] Figure 5 is a schematic diagram of a modified JTAG unit according to the present disclosure;

[0015] Figure 6 is a schematic diagram of a set of address registers for memory words in a memory portion of the present disclosure;

[0016] Figure 7 and 8 FIG. 1 is a schematic diagram illustrating the relationship between address and data registers in the memory portion of the present disclosure. DETAILED DESCRIPTION

[0017] Monolithic memory is the simplest type of memory available for many types of controllers in FPGA-based embedded systems. The memory is implemented in the FPGA itself; therefore, no external connections are required on the board.

[0018] A field programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing.

[0019] An FPGA contains an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together, much like many logic gates that can be interconnected in different configurations. For example, logic blocks can be configured to perform complex combinational functions, or just simple logic gates like AND and XOR.

[0020] In most FPGAs, logic blocks also include memory elements, which can be simple flip-flops or more complete memory blocks. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible, reconfigurable computing to be performed in computer software.

[0021] Most modern embedded systems use some type of flash memory device for non-volatile storage. Embedded systems use memory for a range of tasks, such as storing software code and look-up tables (LUTs) for hardware accelerators.

[0022] Referring to the figures, apparatus and methods relating to non-volatile memory devices or components and host devices for such memory devices will be disclosed herein.

[0023] Descriptions of well-known components and processing techniques are omitted to avoid unnecessarily obscuring the embodiments herein. The examples used herein are intended only to facilitate an understanding of the manner in which the embodiments herein may be practiced and to further enable those skilled in the art to practice the embodiments herein. Therefore, the examples should not be construed as limiting the scope of the embodiments herein.

[0024] Flash memory is a type of nonvolatile memory that retains stored data without requiring periodic refreshing due to the presence of electricity. Flash memory can be erased in blocks rather than individual bytes at a time. Each erasable memory block includes a plurality of nonvolatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating the voltages on the access and data lines.

[0025] Currently, complex semiconductor structure technologies known as system-on-chips offer the integration of at least one embedded non-volatile memory, for example up to 128 Mbit.

[0026] FIG. 1 shows an example of a known solution for a complex system-on-chip (SoC) structure 100 , which includes a large circuit portion occupied by a conventional embedded non-volatile memory portion 110 .

[0027] This embedded non-volatile memory portion 110 includes an array of flash memory cells, indicated as an eFlash array in FIG. 1 .

[0028] For reading the memory cells of the array, a dedicated circuit portion 130 is provided, which includes an optimized read finite state machine for ensuring high read performance (eg branch prediction, fetch / prefetch, interrupt management, error correction, etc.).

[0029] To write and erase the memory cells of the array, a dedicated logic circuit portion 140 is provided, comprising a simplified Reduced Instruction Set Computer (RISC) controller or a modified finite state machine, or logic circuitry for handling programming and erase algorithms.

[0030] While advantageous in many respects, monolithic systems containing large memory arrays can have many disadvantages, as the memory portion is implemented using a process not specifically designed for memory, and possible defects in the memory array can compromise the lifespan or functionality of the entire SoC structure. Furthermore, if the SoC already has a flash memory array as embedded memory, it may be desirable to also have an extended non-volatile memory as a type of remote memory.

[0031] According to an embodiment of the present disclosure, to improve the performance of the entire SoC structure, the legacy memory portion 110 has been implemented as an independent memory device using technology specifically used to manufacture flash memory devices. This new memory component is associated with and linked to the SoC structure that partially overlaps this structure, while the corresponding semiconductor area of ​​the SoC structure is used for other logic circuits and to provide support for the independent memory portion of the overlapping structure.

[0032] Therefore, the object of the present disclosure is to propose a non-volatile memory structure that can improve access time.In any case, the system-on-chip and the associated memory devices are implemented on respective dies obtained by different lithographic processes.

[0033] As in Figure 2 As shown in FIG, according to the present disclosure, it is possible to consider that the memory portion (i.e., the old reference number 110 of FIG. 1 ) has been removed from the SoC structure, thereby allowing the corresponding semiconductor area to be used for other logic circuits and for providing support for a structurally independent memory component 210 that partially overlaps the SoC structure 200.

[0034] Memory component 210 is structured as a standalone device implemented in a single die using technology specifically designed for the manufacture of flash memory devices. Memory component 210 is a standalone structure, but it is strictly associated with a host device or SoC structure. More specifically, memory component 210 is associated with and linked to a SoC structure that partially overlaps such a structure, while the corresponding semiconductor area of ​​the SoC structure is already used for other logic circuits and is used to provide support for the partially overlapping structured standalone memory device 210, for example, via a plurality of pillars 230 or other similar alternative connections (e.g., ball grids) or using technology similar to flip-chip technology.

[0035] In one embodiment of the present disclosure, the placement of the pads of the memory component 210 has been implemented on the surface of the memory component at the periphery of the standalone flash memory device. More specifically, a plurality of pads have been implemented around the periphery of the array so that when the memory component 210 is inverted, its pads face corresponding pads of the SoC structure 200. The semiconductor area that was partially occupied by the embedded non-volatile memory in the known single-chip system device in the known solution is now dedicated to the housing of the interconnect pads corresponding to the pads of the memory component 210.

[0036] More specifically, using logic-on-pad technology, pads are built on top of the logic used to communicate with independent and overlapping memory components 210, similar to 3DN, and circuits are implemented under the array (CUA technology).

[0037] To mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), the chip is flipped so that its top surface is facing down and aligned pad-to-pad so that its pads align with matching pads on the external circuit. The solder is then reflowed to complete the interconnection.

[0038] This technology differs from wire bonding, in which the chip is mounted vertically and wires are used to interconnect the chip pads to the external circuitry.

[0039] The final configuration will be a face-to-face interconnected SoC / flash memory array, where the sense amplifiers are connected to the SoC in a direct memory access configuration.

[0040] Finally, the memory component 210 is manufactured according to user requirements within a range of values ​​that can vary depending on the available technology, for example, from at least 128 Mbit to 512 Mbit or even more, without any limitation to the applicant's rights. More specifically, the proposed external architecture allows going beyond the limitations of current eFlash (i.e., embedded Flash memory technology) and allows the integration of larger memories, such as 512 Mbit and / or 1 Gbit and / or more, depending on the memory technology and technology node.

[0041] The result of this solution is Figure 2 The new SoC structure is strictly associated with a new structurally independent memory component 210, which is coupled to the SoC structure 200, for example, by a plurality of coupling elements 230 (e.g., pillars) and by ball grids, flip chip technology, face-to-face interconnects (coils), etc. In one embodiment, the coupling elements are pillars 230, which are arranged in the semiconductor region 220 previously dedicated to the embedded memory portion 110 of FIG. 1 .

[0042] In one embodiment of the present disclosure, a memory component 210 for a SoC structure 200 includes at least a memory portion and a logic circuit portion for interacting with the memory portion and the SoC structure 200. The memory component 210 is a structurally independent semiconductor device that is coupled to and partially overlaps with the system-on-chip structure 210. A logic circuit 240 is integrated into the SoC structure 200 to cooperate with the logic circuit portion of the memory component 210.

[0043] The coupling between SoC structure 200 and memory component 210 is made by interconnecting a plurality of corresponding pads or pin terminals that face each other in the circuit layout such that the pad alignment is maintained even if the size of memory component 210 is modified.

[0044] In one embodiment of the present disclosure, the arrangement of the pads of the memory component 210 is implemented on the surface of the memory component 210. More specifically, the pads are arranged above the array so that when the memory component 210 is turned over, its pads face the corresponding pads of the SoC structure 200. The semiconductor area 220 that is partially occupied by the embedded non-volatile memory in the known monolithic system structure 100 is dedicated to the housing of the interconnect pads corresponding to the pads of the memory component 210.

[0045] Even larger sized memory components can be supported by and interconnected to the pads of the SoC structure 200, thereby maintaining the location and misalignment of their interconnect pads.

[0046] In the context of the present disclosure, the SoC structure 200 has its top surface linked to the reverse side of the memory component 210, with pads of the SoC structure 200 aligned with matching pads of the reverse memory component.

[0047] Alternatively, the structurally independent memory components 210 can be coupled to the SoC structure 200 in a face-to-face manner. If face-to-face coupling is used, stacks of memory components of the same size can be overlapped to achieve a stacked structure, where each independent component is addressed by the logic circuit system of the SoC structure 200 through a corresponding identification address.

[0048] The semiconductor area 220 previously occupied by the embedded memory portion 110 is now used to implement additional functionality and prepare the semiconductor device for logic-on-pad technology. The expression "logic-on-pad" means providing a logic circuit system that overlaps some of the connection pads located internally to the first or basic level represented by the complete semiconductor product (i.e., SoC structure 200).

[0049] Thus, memory component 210 represents an upper layer coupled and interconnected to the base SoC structure 200. Memory component 210 partially overlaps the SoC structure surface, thereby covering at least the semiconductor area 220 previously occupied by embedded memory portion 110. However, memory component 210 has a larger capacity that can cover a larger semiconductor area than semiconductor area 220. In this regard, the size of the overlapping memory component 210 is greater than the size of the overlapping semiconductor area 220 dedicated to interconnection with such overlapping memory component 210. In other words, the area of ​​the overlapping memory component 210 is greater than the semiconductor area 220 of the SoC structure 200 dedicated to interconnection pads for the memory component 210.

[0050] Furthermore, for better functionality of the SoC structure 200, even the logic circuit portion 140 of FIG. 1 , which includes a modified finite state machine or RISC in the system-on-chip structure 100 of FIG. 1 , may be removed and reorganized to be associated with the memory component 210. To support the write and erase phases performed on the larger memory component 210, the modified finite state machine or RISC 240 has been migrated into the memory component 210.

[0051] As previously indicated, memory component 210 includes logic circuitry portions for interacting with the memory portion and SoC structure 200 .

[0052] The separation and optimization of the logic circuit portion further allows for enhancement of the functionality of the entire SoC structure 200 , thereby obtaining an independent semiconductor memory component 210 coupled to the SoC structure 200 .

[0053] Thus, this independent semiconductor memory component 210 comprises at least a memory portion (preferably a non-volatile memory portion) and an associated modification finite state machine 240, both of which are incorporated into a semiconductor product coupled to the SoC structure 200. In this case, the logic embedded in the SoC is the read logic: extract data, correct data, refine, and execute.

[0054] As will appear later in this disclosure, DMA capability is provided to the memory component 210 with the interface logic JTAG TAP using a modified JTAG unit along with flexible TDI, secure access, address buffers, and other features for handling communications with the SoC structure 200 .

[0055] In other words, both the non-volatile memory portion and the associated logic circuit portion are integrated into a separate semiconductor memory component 210 that is coupled and connected to the SoC structure 200 .

[0056] Now, more specifically referring to Figure 3 The main structure of the memory component 310 according to the embodiment of the present disclosure will be disclosed as an example. Figure 3 Reference number 310 corresponds to Figure 2 Reference number 210.

[0057] The memory component 310 includes at least: I / O circuits, a microsequencer, a memory cell array 320, array peripherals, a charge pump architecture, an address decoder, sense amplifiers and corresponding memories, service logic for connecting all parts of the memory, and a command user interface, such as a CUI block.

[0058] The memory cell array 320 includes non-volatile flash memory cells. In one embodiment of the present disclosure, the memory component 310 implements a direct memory access type of memory to replace the embedded memory array of a conventional SoC device.

[0059] In addition, the memory component 310 is tested using the JTAG interface 350, allowing for the reuse of test tools. Therefore, the memory component 310 also includes JTAG logic 350. Figure 6 This JTAG interface 350 is disclosed in more detail.

[0060] More specifically, each memory array includes at least a JTAG interface 350 that receives standard JTAG signals as input: TMS, TCK, TDI, and data from a memory page, as in Figure 6 As shown in FIG. 1 . According to an embodiment of the present disclosure, an extended TDI is used as a flexible TDI. The flexibility is due to the fact that the number of parallel bits working as TDI depends on the selected register, i.e., K (in this example, 4) lines for the instruction register, M lines for the address register, N lines for the data register, etc., and TDI comes from the JTAG protocol, which uses TDI as the name of the signal for filling the register.

[0061] This JTAG interface 350 generates as output data, address and control signals, which are transmitted to the memory address decoder 340 and also sent to the internal flash memory controller 4300 to perform modification, test and verification operations.

[0062] The activity of the decoder 340 is enabled by a charge pump 3430 that is structured to maintain a secure voltage and timing to manage the array. The decode stage drives the data lines, while the charge pump provides a high voltage that is routed by the address decoder in the selected data line.

[0063] This decoder 340 addresses the selected memory block. An address decoder is connected to the array to select the appropriate data lines, i.e., rows and columns for each superpage. Read, modify, and any other operation uses the address decoder to properly address the byte in the memory array.

[0064] The memory blocks are connected to sense amplifiers, and the sense amplifiers of the read interface 360 ​​are connected to the SoC structure 200 using modified JTAG cells. The communication channel between the flash memory array blocks and the SoC structure 200 is represented by a control and status bus.

[0065] The output of the read interface 360 ​​is represented by an extended page containing a combined string of data cells + address cells + ECC cells. The write operation also drives the three components of the extended page (data cells + address cells + ECC cells); the ECC and address cells act as a safety mechanism to ensure that the probability of error is very small.

[0066] The total amount of bits will in the examples disclosed herein involve N+M+R bits, eg, one hundred sixty-eight pads per channel in the embodiments disclosed herein.

[0067] The memory array 320 of the memory component 310 is structured as a collection of sub-arrays. Scan chains can be connected to form unique shift registers to properly test the interconnects.

[0068] An advantage of this architecture is that it is fully scalable, where expanding and / or reducing the density of the final device is simply a matter of mirroring the subarrays and providing the corresponding interconnects in a fully scalable manner. Memory is also scalable, increasing the memory size per subarray without expanding the number of channels in the SoC.

[0069] Direct memory access allows reducing the resulting latency that the SoC may experience when reading data.

[0070] Now, looking closely at the internal structure of the memory component 210 (or 310), it should be noted that the architecture of the memory array 320 is structured as a collection of sub-arrays 420, as shown in FIG. Figure 4 The schematic diagram is shown in Figure 3 Reference number 320 corresponds to Figure 4 Reference number 420.

[0071] Each sub-array 420 is independently addressable within the memory device 310. Each sub-array 420 contains a plurality of memory blocks 460 (e.g., Figure 4A (depicted in ).

[0072] In this way, access times are significantly reduced and the overall throughput of the memory component is improved, given smaller sectors compared to known solutions. The reduction in initial latency occurs at the block level, as the row and column lines, associated read path latencies, and external communications are optimized. Initial latency is the time required for the first valid data to be available after an address has been issued.

[0073] In the embodiments disclosed herein, the memory array is structured to have a plurality of sub-arrays 420 corresponding to the number of cores, and therefore the number of corresponding communication channels, of the associated SoC structure 200. For example, at least four memory sub-arrays 420 are provided, one for each communication channel with a corresponding core of the SoC structure 200.

[0074] The host device or system-on-chip (SoC) structure 200 typically includes more than one core, and each core is coupled to a corresponding bus or channel for receiving and transmitting data to the memory component 210 or 310. A common reference will be made to multiple K buses of N data bits.

[0075] Thus, in this embodiment, each sub-array 420 accesses a corresponding channel to communicate with a corresponding core of the SoC structure 200. The results of the memory blocks are driven directly to the SoC without the use of high power output buffers and optimization paths.

[0076] An advantage of this architecture is that it is very scalable, where expanding and / or reducing the density of the final device is simply a matter of mirroring the subarrays and creating connections, or increasing the number of tiles per subarray (which is the available density per core).

[0077] In an embodiment of the present disclosure, each independently addressable location of a block of each memory sub-array 420 addresses an extended page 450, which will also be defined hereinafter by the term superpage, which means a double extended page.

[0078] As a non-limiting example, this extended page 450 includes a string comprising a first group of at least N bits, e.g., one hundred and twenty-eight (128) bits for I / O data exchange with the SoC structure 200, plus at least a second group of M bits, e.g., twenty-four (24) address bits and a final or third group of at least R bits, e.g., sixteen (16) ECC bits. The M address bits (24 address bits in this example) are sufficient to address up to 2 gigabit of available memory space.

[0079] According to the present disclosure, the output of the sense amplifier SA prepares a double extended page at a time, ie, according to the size of the memory array, the super page 450 includes multiple bits given by a double combination of the three sets of data bits, address bits and ECC bits mentioned above.

[0080] In the specific but non-limiting example disclosed herein, each extended page 450 includes at least 168 bits obtained by combining the above three groups of N+M+R=128+24+16 data, address and ECC bits and each super page consists of a pair of extended pages, i.e., a group of 168×2 bits.

[0081] Just to give a non-limiting numerical example, each row of memory block 460 includes sixteen extended pages. Thus, the resulting row includes 2688 bits from the combination of 16 independently addressable extended pages, and each extended page includes 168 bits, or in other words, the combination of eight super pages.

[0082] In an embodiment of the present disclosure, the output of the general subarray 420 is formed by combining the following sequence: N data cells plus M address cells plus R ECC cells. In this non-limiting example, the total amount of bits will involve 168 pads per channel, such as Figure 6 As shown in the example.

[0083] The combined string of data cells + address cells + ECC cells allows for implementation of safe coverage of the bus as required by the standard, as the ECC covers the entire bus communication (data cells + address cells), while the presence of the address cells provides confidence that the data comes exactly from the addressed location of the controller.

[0084] The sense amplifiers SA of each sub-array 420 are connected to the scan chain of the modified JTAG cell 480 , thereby connecting all output terminals of one sub-array 420 together, as disclosed below.

[0085] Due to the memory architecture of the present disclosure, it is possible to move from a parallel mode for retrieving data and addresses from the memory sub-array 420 to a serial mode for checking the interconnection between the memory component 210 and the associated SoC structure 200. In addition, the SoC structure 200 has the ability to read once a '1' and once a '0' to perform testing and can also analyze the memory results, using the scan chain to scan out the data.

[0086] It should be further noted that each sub-array 420 includes an address register connected to a data buffer register, similar to the architecture used in DRAM memory devices, ie, DDRX type DRAM.

[0087] As will become apparent in the following paragraphs of this disclosure, the output of each sub-array 420 sense amplifier SA is latched by internal circuitry to allow the sense amplifier to perform further internal read operations to prepare for the second nibble or group of 168 bits. This second nibble is transferred to the output of the flash memory array 320 using an additional enable signal (i.e., an internal clock signal or ADV signal; ADV = address data valid, in which case the signal is load_data[1:0], depending on the address flip-flop) that transfers the content read at the sense amplifier level to the host device or SoC device 200.

[0088] In other words, the internal sense amplifiers prepare two extended pages 450, and when the first page is ready to be shifted in (or also shifted out), the read operation of the second page associated with the same address is performed internally. This allows the preparation of from 5 to 8 double words (in this example), which is typical in RTOS applications. In any case, the disclosed structure can be expanded to allow multi-page reads while shifting out the read pages.

[0089] The sense amplifier SA is directly connected to a modified JTAG cell 480 which will be disclosed in more detail later, so that the JTAG structure and the sense amplifier are integrated into a single circuit portion. This allows the delay in propagating the output of the memory array to the SoC to be minimized.

[0090] Reporting only numerical examples based on the embodiments disclosed herein, it can be noted that each address in the address buffer is linked to a data buffer, for example containing N data bits (i.e. 128 bits). However, the SoC may need up to 2*N bits at a time (i.e. 256 bits, without address bits and ECC), so the data buffer will be replicated to enable shifting, assuming address 0 of subarray 0 is used:

[0091] The first pass of the first group of N bits: Data 0_0_H[127:0]

[0092] Second pass of the second group of N bits: Data 0_0_L[127:0]

[0093] The above instructions apply to standard readouts, eg for security purposes and data integrity / correction.

[0094] In one embodiment, the address buffer is implemented using a modified JTAG cell 480, as will be seen below.

[0095] According to one embodiment of the present disclosure, a flash memory device architecture coupled to a monolithic system-on-chip is disclosed, the flash memory device architecture including a matrix of memory cells with associated decoding and sensing circuitry and having a structurally independent structure coupled and linked to the monolithic system-on-chip, and comprising:

[0096] - a plurality of sub-arrays forming said memory cell matrix;

[0097] - a sense amplifier coupled to a corresponding sub-array;

[0098] - a data buffer comprising a plurality of JTAG cells coupled to the output of the sense amplifier;

[0099] - a scan chain connecting the JTAG cells of the data buffer together.

[0100] As previously described, the sense amplifier SA of each sub-array 420 and the scan chain 430 (with Figure 4 ) are connected so that all outputs of a sub-array 420 are connected together, as shown in Figure 4 Furthermore, the sub-array scan chains 430 can be connected to form a unique chain for quickly checking the integrity of pad interconnects.

[0101] refer to Figure 4, one may consider the scan chain 430 formed by the interconnections of each JTAG cell 480 as:

[0102] PIN is coupled to the output of the sense amplifier, POUT is coupled to the corresponding data I / O of the single-chip system; SIN is the serial IN input connected to the SOUT of the previous sense amplifier, and SOUT is the serial output connected to the SIN of the next sense amplifier.

[0103] This scan chain 430 formed by interconnect cells 480 using serial input and output has several advantages:

[0104] - Allows testing of the successful interconnection between the SoC structure 10 and the memory component 1;

[0105] - Allows digital testing of sense amplifiers,

[0106] - Allows operation as a second-stage latch.

[0107] Additionally, since the cells can function as program loads to store data within the memory cell matrix, program loads are typically buffers used to drive programming operations within the array, acting as compare registers.

[0108] As will be seen later in this disclosure, when the first 128 bits are ready to be transferred to the parallel output terminals POUT of the sense amplifiers, there are internal latches coupled to the sense amplifiers that can trigger the read data of the subsequent terminals of the remaining 128 bits.

[0109] But let's proceed methodically.

[0110] The system-on-a-chip (SoC) structure 200 typically includes more than one core (not shown), and each core is coupled to a corresponding bus or channel for receiving and transmitting data to the memory component 210. Each sub-array 420 accesses a corresponding channel to communicate with a corresponding core of the SoC.

[0111] Each sub-array scan chain 430 may be connected in series to form a unique chain with another sub-array and / or may be considered a separate scan chain register.

[0112] Each sense amplifier SA of the sub-array 420 is coupled to a JTAG unit 480 .

[0113] In some embodiments of the present disclosure, the output of subarray 420 is formed by combining the following sequence: data cells plus address cells plus ECC cells. Specifically, sense amplifier SA is configured to provide and output the combined data cells, address cells, and ECC cells. In the embodiments disclosed herein, the total number of bits involves 168 pads per channel, and the memory device architecture is therefore configured to transmit a superpage via a channel comprising at least 168 pads. In other words, the subarrays within the plurality of independently addressable subarrays are thus organized into an expanded page comprising data bits, address bits, and ECC bits.

[0114] The combined string of data cells + address cells + ECC cells allows the implementation of the entire security coverage of the bus according to the standard requirements of rule ISO26262, because the ECC covers the entire bus communication (data cells + address cells), and the presence of the address cells provides confidence that the data comes exactly from the location addressed by the controller, i.e. if ADD == ADD0.

[0115] The memory device 210 may store in a non-volatile manner an initial address that must be read at system startup, ie, the entire system-on-chip or SoC structure and associated memory components 210 .

[0116] It must also be noted that the disclosed monolithic system-on-a-chip with an associated non-volatile memory portion (but no volatile RAM or DRAM) operates according to an execute-in-place (XiP) method of retrieving data from memory.

[0117] Generally speaking, in-place execution refers to a method of executing a program directly from a non-volatile memory portion rather than copying it to a volatile memory. An expansion using shared memory to reduce the total amount of memory required.

[0118] The main effect of the XiP approach is that the program text does not consume any writable memory, saving such memory for dynamic data, and all instances of the program run from a single copy and perform unconditional jumps directly from non-volatile memory.

[0119] The presence of unconditional jumps justifies the required low initial latency, which is the main root cause of performance loss in such configurations due to the double word size required between jumps, i.e., from 5 to 8 double words.

[0120] However, the non-volatile memory portion 210 must provide an interface similar to that of the CPU as a volatile memory, and said interface must provide sufficiently fast read operations with random access mode; furthermore, if a file system is present, it needs to expose appropriate mapping functions and the executing program must be linked to know the appropriate addresses of the memory portion.

[0121] The storage requirements are typically met by using a NOR flash memory section which is addressable as a single word for read operations, although in most settings it is a bit slower than ordinary RAM memory.

[0122] Typically, in an SoC that includes a RAM portion, the first-stage boot loader is a XiP program that is linked to run at the address where the flash memory chip is mapped at power-up and contains a minimal program to set up the system RAM (this depends on the components used on the individual board and cannot be generalized enough so that the appropriate sequence can be embedded in the processor hardware), and then loads the second-stage boot loader or OS kernel into RAM.

[0123] During this initialization period, writable memory may not be available, so all calculations must be performed within the processor's registers. For this reason, first-stage boot loaders are often written in assembly language and do only the minimum necessary to provide a normal execution environment for the next program. Some processors either embed a small amount of SRAM in the chip itself or allow the use of onboard cache memory as RAM to make this first-stage boot loader easier to write in a high-level language.

[0124] Due to the memory architecture of the present disclosure, it is possible to move from a parallel mode for retrieving data and addresses from the memory sub-arrays to a serial mode for checking the interconnects.

[0125] The transition from parallel mode to serial mode is managed by the JTAG interface 300. However, implementation of these dual mode operations is enabled by the specific structure of the modified JTAG unit 480 disclosed below.

[0126] refer to Figure 5 , showing a JTAG unit 500 modified according to the present disclosure. This unit 500 corresponds to Figure 4 Schematic unit 480.

[0127] The JTAG cell 500 has a first parallel input PIN terminal and a first serial input SIN terminal for receiving corresponding signals Pin and Sin. Furthermore, the JTAG cell 500 has a first parallel output terminal POUT and a first serial output terminal SOUT. The scan chain 430 allows the output of all 256 bits, as the first group is read directly from the output and the second group is prepared later.

[0128] As in Figure 5As shown in FIG, JTAG cell 500 can be considered as a box having two input terminals, PIN and SIN, and two output terminals, POUT and SOUT. Input terminal PIN is a parallel input terminal, while input terminal SIN is a serial input terminal. Similarly, output terminal POUT is a parallel output terminal, while output terminal SOUT is a serial output terminal.

[0129] Due to the serial inputs and outputs, a test program can be performed to check that there are no faulty connections between the memory component 210 and the associated SoC structure 200. Due to the parallel inputs and outputs, the same JTAG cell is used as a data buffer to complete the read phase through the sense amplifier SA.

[0130] The JTAG cell 500 comprises a boundary scan basic cell 580, which includes a pair of latches 501 and 502 and a pair of multiplexers 551 and 552. The first input multiplexer 551 and the second output multiplexer 552.

[0131] Boundary scan basic unit 580 in Figure 5 Indicated by a dotted box table, it is a dual-input terminal unit (wherein the serial input terminal corresponds to SIN and the parallel input terminal corresponds to PIN), and is a dual-output terminal unit (wherein the serial output terminal corresponds to SOUT and the parallel output terminal corresponds to POUT).

[0132] The first multiplexer 551 receives a parallel input signal Pin from a first parallel input terminal PIN at a first input terminal “0” and receives a serial input signal Sin from a first serial input terminal SIN at a second input terminal “1”.

[0133] This first multiplexer 551 is driven by the control signal ShiftDR and has an output MO1. Unit 500 has two parallel outputs, MO1 and MO2. When the JTAG clock arrives, the serial output is driven out of SOUT. SOUT is connected to a JTAG latch adjacent to the multiplexer that receives the selector signal: Mode Controller (Serial / Parallel). Essentially, the output of the latch connected to the "1" input of this multiplexer MO2 is also SOUT.

[0134] The first multiplexer output MO1 is connected to a first input of a first latch 501 which receives a clock signal ClockDR at a second input terminal.

[0135] The first latch 501 is connected to the second latch 502 in a chain form, wherein a first output terminal of the first latch 501 is connected to a first input terminal of the second latch 502 .

[0136] It should be noted that the output terminal of the first latch 501 is also the serial output terminal SOUT of the entire JTAG unit 500 .

[0137] A second input terminal of the second latch 502 receives the signal UpdateDR.

[0138] The second latch 502 has an output connected to an input of the second multiplexer 552 , in particular to a second input thereof.

[0139] This second multiplexer 552 is controlled by a mode control signal that allows switching the entire JTAG unit 500 from serial mode to parallel mode and vice versa.

[0140] In one embodiment of the present disclosure, the JTAG cell 500 further includes another pair of latches 521 and 522 provided between the parallel input terminal Pin and the second multiplexer 552. These additional latches 521 and 522 are direct-read latches (i.e., the first set of data bits) and shadow latches (i.e., the second set of 128 data bits). In other words, the JTAG cell 500 includes the boundary scan cell 580 and provides at least the additional latches 521 and 522.

[0141] These other latches are hereinafter referred to as third latch 521 and fourth latch 522. In other embodiments, longer latch chains may be used.

[0142] More specifically, the third latch 521 and the fourth latch 522 are connected in a small pipeline configuration, where the third latch 521 receives the parallel input signal Pin from the first parallel input terminal PIN on a first input terminal and receives the signal Data_Load[0] corresponding to the first data load on a second input terminal.

[0143] The fourth latch 522 receives the output of the third latch 521 on a first input terminal and receives a signal Data_Load[1] corresponding to subsequent data loading on a second input terminal.

[0144] The output of the fourth latch 522 is connected to a first input “0” of a second multiplexer 552 , which generates an output signal of a parallel output terminal POUT at its output terminal MO2 .

[0145] If compared to a conventional JTAG cell, the JTAG cell 500 of the present disclosure may be considered a modified JTAG cell because, in addition to the presence of the boundary scan cell 580 , there are two additional latches, a third latch 521 and a fourth latch 522 .

[0146] Now, since this JTAG cell 500 is coupled to the output of each sense amplifier SA of the memory sub-array 420, it can be considered as a data buffer containing a page of data, in this example containing at least one hundred and twenty-eight (128) bits, for reading the combined memory page from four sub-arrays 420 at a time.

[0147] However, as previously reported, the communication channel between the memory component and the SoC structure may require up to 256 bits at a time (i.e., two combined memory words), and the JTAG unit 500 has been modified to replicate only the internal latches to enable shifting the first or upper portion of the 128 bits of data to be read along with the second or lower portion of the data to be accessed. Obviously, in this context, "upper" means the portion of data loaded previously, while "lower" means the portion of data loaded later.

[0148] Those skilled in the art will understand that in situations where there is a need to improve the number of bits transmitted to the SoC structure over the communication channel, the number of internal latches of the modified JTAG cell 500 can be increased. For example, the above structure can be expanded depending on the page size required for a specific implementation of the memory controller.

[0149] In order to explain the way data is transferred in the data buffer, it has to be imagined that when data is loaded in one of the two latches 521 or 522, the other latch is in standby state but ready to receive the subsequent data portion.

[0150] Thus, a first segment containing 128 bits is transferred to the SoC structure for a first data refinement, while the read phase does not stop because another portion of 128 bits is ready to be loaded into the latches at the following clock signal.

[0151] In this example, each data buffer contains 128 modified JTAG cells 500, and the common Data_Load[1:0] is a generated signal to allow capturing the full 256 bits, that is: according to the proposed implementation: eight double words DW (four subarrays for each double word).

[0152] When performing a read operation in a specific data buffer, signal generation is internally controlled and the signal is controlled by the SoC structure to allow the read phase to be performed with 128 bits of parallelism.

[0153] The main benefit of this memory architecture is that each buffer can contain an entire double word DW, leaving the sense amplifier free to read another memory location.

[0154] The presence of the modified JTAG cell 500 as the output of the sense amplifier is particularly important, thus allowing:

[0155] a. Using boundary scan as a method to check the interconnection between the SoC 10 and the flash memory array component 1;

[0156] b. Implementing DMA memory access as a direct connection to the sense amplifier and controller;

[0157] c. It allows preparing the sense amps for a second 256-bit wide page plus address plus ECC close to the page write.

[0158] Another advantage is given by the possibility of employing a boundary scan test architecture comprising a modified JTAG cell 500, thereby obtaining Figure 5 A new and special boundary scan test architecture is shown in the schematic diagram of FIG. This is a further advantage because for this test only one output needs to be driven, and this is achieved using the signal TCK and the data stored in the cell. Scan chain testing requires the SoC 10 to test the outputs of the scan chain.

[0159] Those skilled in the art will understand that in situations where there is a need to improve the number of bits transferred to the SoC structure over the communication channel, the number of internal latches of the modified JTAG cell can be increased. For example, the above structure can be expanded depending on the size of the memory device.

[0160] In order to explain the way in which data are transferred in the data buffer, it has to be imagined that when data is loaded in one of the two latches 221 or 222, the other latch is in standby state but ready to receive the subsequent data portion.

[0161] Thus, a first segment containing 128 bits is transferred to the SoC structure for a first data refinement, while the read phase does not stop because another portion of 128 bits is ready to be loaded into the latches at the following clock signal.

[0162] Each data buffer contains 128 modified JTAG cells 500, and the common Data_Load[1:0] is a signal generated to allow capturing the entire 256 bits, that is to say: according to the proposed implementation: eight double words DW.

[0163] When performing a read operation in a specific data buffer, signal generation is internally controlled and the signal is controlled by the SoC structure to allow the read phase to be performed with 128 bits of parallelism.

[0164] The main benefit of this memory architecture is that each buffer can contain an entire double word DW, leaving the sense amplifier free to read another memory location.

[0165] The IEEE 1532 standard enables in-system programming using IEEE 1149 as the primary interface protocol. The need for very low initial latency and high throughput drives the following scheme for addressing 420 per subarray. The key is that program data load time is not of interest, and a serial interface using standards IEEE 1149 and 1532 can be used. Low latency is driven by appropriate block size and optimizations in the data path. The data path is typically an internal gate connecting the array to the output pads.

[0166] Now refer to Figure 7 and 8 For an example, see the array addressing scheme in JTAG.

[0167] First reference Figure 7 , describing an array addressing scheme involving a set of instructions implemented in two ways: global address load and local address load.

[0168] The need for very low initial latency and high throughput drives the following per-subarray addressing scheme. Figure 6 The row address buffer and the corresponding row data buffer in a structure similar to DRAM are shown, but here a super page address and corresponding data are used, i.e. 168×2.

[0169] The implemented instruction set to address the implemented memory array may be of two types or levels of address; in other words: global instructions select a subarray, while local instructions select one (eg, one of four) of the address registers associated with the selected subarray.

[0170] Global address loading: In this case, all subarrays will receive the address in multiple steps using the command load_global_address_0, load_global_address_1, and so on.

[0171] Local address loading: In this case, only the addressed registers in the selected sub-array will receive the new address, ie, local_address_0_0, local_address_0_1, local_global_address_1_3, and so on.

[0172] Each sub-array will contain a set of 4x data registers, for example 4x (data + address + ECC registers), one for each address register. The 4x data registers contain a superpage, in other words: data_H + data_L (with the link to a specific address removed).

[0173] When addressing the array for a read or modify operation, the address register is connected to the address decoder. This connection is driven by the Flash memory controller during the modify phase, while the read finite state machine links them when a read is triggered. The address register is loaded using the JTAG finite state machine. When the corresponding Load_Address instruction is recognized and the Shift_DR state is in the JTAG tap, then TDI is connected to the address register.

[0174] The Global_Address_Loadx command is used to load eight nibbles of the corresponding register at the same time:

[0175] Global_Address_Load0 in the instruction register generates a load of addr0_0. For example, this command addresses subarray 0; similarly, when the JTAG interface's finite state machine is in the Shift_DR state, the corresponding subarray address registers addr1_0, addr2_0, and addr3_0 are selected using three TCK cycles.

[0176] When the finite state machine is in the Shift_DR state, Local_Address_Load0_0 in the instruction register generates a load of addr0_0 using three TCK cycles. As an example, this command addresses register 0 of the selected subarray. This means that when ShiftDR is reached, TDI is connected to the input of this shift register and TDO is connected to the output. If flexible TDI is used, only three clock cycles Tck are required to obtain the entire address in the selected address register; otherwise, 24 clock cycles Tck would be required.

[0177] These instructions (Global_Address_Load0, Global_Address_Load1, Global_Address_Load2, Global_Address_Load3) allow preloading of addresses for all channels implemented in the flash memory array. These four instructions are implemented to select one of the four subarrays. In a possible implementation with eight cores, eight commands would be required, one for each core, or a method using one command and a subarray address to select one of the cores. Thus, the introduction of these commands allows for optimized communication between the SoC structure 10 and the memory component 1, thereby enhancing transfer performance to the controller.

[0178] The instructions (Local_Address_Load0_0, ...., Local_Address3_3) allow the use of a single core / channel, avoiding the need for the controller to manage the entire set of cores when only one core is operating; the cores are independent and can use their own unique channel when needed. These instructions are used to select one of the address registers of the selected sub-array.

[0179] This last disclosed mechanism implementation ensures optimization of memory read operations.

[0180] Now refer to Figure 8 For example, if the SoC structure 200 requires up to 168x2 bits at a time, the data buffer will be replicated to enable the shift, assuming address 0 of subarray 0 is used:

[0181] The first pass of the first group of bits: Data 0_0_H[127:0]+ADD+ECC

[0182] Second pass of the second group of bits: Data 0_0_L[127:0]+ADD+ECC

[0183] The address buffer is made using the JTAG unit.

[0184] According to the standards IEEE 1149 and 1532 regarding JTAG, the protocol IEEE 1532 is used as an extended command set to operate in each sub-array, and the new sub-array structure realizes in-system programming.

[0185] From the foregoing, it will be appreciated that specific embodiments of the present disclosure have been described herein for purposes of illustration, but that various modifications may be made without departing from the scope of the present disclosure. Accordingly, the present invention is not to be limited except by the appended claims.

Claims

1. A flash memory device architecture coupled to a system-on-chip (SoC), the flash memory device architecture comprising a matrix of memory cells with associated decoding and sensing circuitry and having a structurally independent structure linked to the SoC, and comprising: - a plurality of sub-arrays forming said memory cell matrix; - a sense amplifier coupled to a corresponding sub-array and having a corresponding output; - a data buffer comprising a plurality of JTAG cells coupled to the output of the sense amplifier; - a scan chain connecting the JTAG cells of the data buffer together, - wherein one of the JTAG cells comprises a boundary scan cell and at least a first pair of latches external to the boundary scan cell, the boundary scan cell comprising an input multiplexer and an output multiplexer, and wherein the first pair of latches are connected in a pipeline between a parallel input terminal and a parallel output terminal.

2. The flash memory device architecture of claim 1, wherein each sub-array is independently addressable.

3. The flash memory device architecture of claim 1, wherein the scan chain forms a single shift register for testing interconnections between pads of a memory portion and corresponding pads of the SoC.

4. The flash memory device architecture of claim 1, wherein the JTAG cells are connected in series in the scan chain.

5. The flash memory device architecture of claim 1, wherein the boundary scan cell comprises at least a second pair of latches between the input multiplexer and the output multiplexer.

6. The flash memory device architecture of claim 1, wherein a sub-array of the plurality of sub-arrays comprises a superpage including data cells, address cells, and ECC cells.

7. The flash memory device architecture of claim 6, configured to transmit a superpage over a channel comprising at least 168 pads.

8. The flash memory device architecture of claim 1, comprising at least four sub-arrays for communicating with corresponding cores of the SoC.

9. A non-volatile memory architecture having an architecturally independent structure obtained through memory manufacturing technology and configured to be coupled to a system-on-chip (SoC) device through interconnect pins or pads, the non-volatile memory architecture comprising: - a memory cell array formed from a plurality of sub-arrays; - a sense amplifier coupled to a corresponding sub-array of the plurality of sub-arrays and having a corresponding output; - a data buffer comprising a plurality of JTAG cells coupled to the output of the sense amplifier; - a scan chain connecting the JTAG cells of the data buffer together, - wherein one of the JTAG cells comprises a boundary scan cell and at least a first pair of latches external to the boundary scan cell, the boundary scan cell comprising an input multiplexer and an output multiplexer, and wherein the first pair of latches are connected in a pipeline between a parallel input terminal and a parallel output terminal.

10. The non-volatile memory architecture of claim 9, wherein each sub-array is independently addressable.

11. The non-volatile memory architecture of claim 9, wherein the scan chain forms a single shift register for testing interconnections between pads of the non-volatile memory architecture and corresponding pads of the monolithic system on a chip.

12. The nonvolatile memory architecture of claim 9, wherein the JTAG cells are connected in series in the scan chain.

13. The non-volatile memory architecture of claim 9, wherein the boundary scan cell comprises at least a second pair of latches between the input multiplexer and the output multiplexer.

14. The nonvolatile memory architecture of claim 9, wherein a sub-array of the plurality of sub-arrays comprises a superpage including data cells, address cells, and ECC cells.

15. The non-volatile memory architecture of claim 14, further comprising a channel for transmitting at least 168 pads of a superpage.

16. An integrated circuit comprising a system-on-chip (SoC) device and a non-volatile memory device, wherein the non-volatile memory device is obtained as an independent die using corresponding manufacturing technology and is coupled to corresponding interconnect pins or pads, the integrated circuit comprising: - a memory array comprising a plurality of independently addressable sub-arrays in the non-volatile memory device; - sense amplifiers coupled to corresponding outputs of the sub-arrays and to a communication channel of the SoC device; - a scan chain comprising a modified JTAG cell coupled in parallel between the output of the sense amplifier and the communication channel, - wherein one of the modified JTAG cells comprises a boundary scan cell and at least a first pair of latches external to the boundary scan cell, the boundary scan cell including an input multiplexer and an output multiplexer, and wherein the first pair of latches are connected in a pipeline between a parallel input terminal and a parallel output terminal.

17. The integrated circuit of claim 16, wherein the sense amplifier is configured to provide an output combining the data cell, the address cell, and the ECC cell.

18. The integrated circuit of claim 16, wherein subarrays of the plurality of independently addressable subarrays are organized into extended pages comprising data bits, address bits, and ECC bits.

19. The integrated circuit of claim 16, wherein the modified JTAG cells are connected in series in the scan chain.

20. The integrated circuit of claim 16, wherein each sub-array in the memory array corresponds to a respective core of the SoC device.

21. The integrated circuit of claim 16, wherein the memory array is a flash memory array.

22. The integrated circuit of claim 16, wherein the SoC comprises a plurality of cores, each core communicating with a corresponding sub-array in the memory array using direct memory access.

23. The integrated circuit of claim 16, wherein the non-volatile memory device includes logic circuitry having a finite state machine or RISC portion for communicating with the SoC.

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