Wafer placement correction in an indexed multi-station processing chamber

Abstract

Systems and techniques for determining and using multiple biases for providing wafers to a transfer pedestal of a multi-station processing chamber are disclosed. Such techniques can be used to provide pedestal-specific biases that can be selected based on the pedestal of the multi-station chamber assigned to a particular wafer. Similar techniques can be used to provide wafer support-specific biases based on the indexer arm of the indexer assigned to a particular wafer.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] Semiconductor processing tools typically have one or more chambers, each chamber containing one or more stations. Each station may have a pedestal on which a wafer may be supported during semiconductor processing operations. In some semiconductor processing tools, a single chamber may contain multiple stations / pedestals. In some cases, such multi-station chambers may contain a rotary indexer that may be used to transfer wafers from one station / pedestal to another during various semiconductor processing operations.

[0004] The indexer typically includes a central hub and a plurality of indexer arms of equal length. The proximal end of each indexer arm is generally connected to the central hub, and a wafer support is generally located at the distal end of each indexer arm; the indexer arms are generally evenly distributed around the central hub. A rotational drive system may be provided to rotate the central hub and the plurality of indexer arms and the plurality of wafer supports attached to the plurality of indexer arms about a common rotation axis.

[0005] In a multi-station chamber with an indexer, the chamber's stations / pedestals may be arranged in a circular array about the indexer's axis of rotation such that each indexer arm may be simultaneously positioned over one of the plurality of stations / pedestals when the indexer's central hub is rotated into any of a first set of angular positions, and such that each indexer arm may be simultaneously positioned between two adjacent stations / pedestals when the indexer's central hub is rotated into any of a second set of angular positions. During semiconductor processing operations, the indexer may be rotated into an angular position in the second set of angular positions, thereby stowing each indexer arm between adjacent pairs of the plurality of stations / pedestals. When semiconductor operations are completed, the wafers may be lifted off their respective pedestals by, for example, a plurality of lift pins extending from the pedestals, and the indexer may then be rotated into an angular position in the first set of angular positions to position each wafer support at the distal end of each indexer arm under a corresponding wafer in the plurality of wafers that have been lifted. The plurality of lift pins may then be retracted to their respective pedestals, thereby lowering each wafer onto a wafer support of an indexer arm positioned beneath each wafer. The indexer may then be rotated to position each wafer over another of the plurality of pedestals, at which point the plurality of lift pins of the pedestal may again be extended to lift the wafer off the wafer support of the indexer arm. The indexer may then be rotated again into one of the second set of angular positions and the plurality of lift pins retracted to lower the wafer onto its respective pedestal.

[0006] The present disclosure relates to novel systems and techniques for improving wafer processing uniformity in a multi-station processing chamber. Summary of the invention

[0007] Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. The following non-limiting implementations should be considered part of the specification; other implementations will be apparent from the entire contents of this specification and the drawings.

[0008] In some implementations, an apparatus may be provided that includes a first chamber having an indexer and N pedestals arranged in a circular array centered on a rotation axis of the indexer. One of the N pedestals of the first chamber may be a transfer pedestal, each pedestal of the first chamber may be configured to support a wafer, N may be an integer greater than 1, the first chamber may include an active wafer centering system associated with the transfer pedestal, and the first chamber may be a multi-station semiconductor processing chamber. The apparatus may also include: a wafer handling robot having a robotic arm configured to provide a single wafer to the transfer pedestal of the first chamber; and a controller including one or more processors and one or more memory devices. The one or more processors, the one or more memory devices, the wafer handling robot, the indexer of the first chamber, and the active wafer centering system of the first chamber may be operably connected to each other, and the one or more memory devices may store computer executable instructions for controlling the one or more processors to: a) select one of the N pedestals of the first chamber as a destination pedestal of the first chamber for a first wafer; b) select a first pedestal deviation associated with the destination pedestal of the first chamber from the group of N pedestal deviations of the first chamber, the first chamber Each of the group of N pedestal deviations is associated with a different pedestal of the N pedestals of the first chamber; c) obtaining information representing the horizontal position of the center of the first wafer from the active wafer centering system of the first chamber; d) determining a first end effector deviation associated with the first wafer based at least in part on the information representing the horizontal position of the center of the first wafer obtained from the active wafer centering system of the first chamber; and e) causing the robot arm to provide the first wafer to the transfer pedestal of the first chamber based on the first pedestal deviation and the first end effector deviation.

[0009] In some implementations of the apparatus, the first chamber, the one or more processors, and the one or more memory devices may be operably connected to each other, and the one or more memory devices may store additional computer executable instructions for further controlling the one or more processors to: f) cause the indexer of the first chamber to move the first wafer from the transfer base of the first chamber to the destination base of the first chamber; and g) cause the first chamber to perform one or more semiconductor processing operations on the first wafer on the destination base of the first chamber.

[0010] In some implementations of the apparatus, the first chamber, the one or more processors, and the one or more memory devices may be operably connected to each other, the transfer base of the first chamber may be the destination base of the first chamber, and the one or more memory devices may store an additional plurality of computer-executable instructions for further controlling the one or more processors to cause the first chamber to process the first wafer while the first wafer is on the destination base of the first chamber.

[0011] In some implementation schemes of the device, the first chamber, the one or more processors, and the one or more memory devices may be operably connected to each other, and the one or more memory devices may store additional computer-executable instructions, which are used to further control the one or more processors to: perform (a) to (e) for each of N wafers, wherein a different pedestal among the N pedestals of the first chamber is selected as the destination pedestal of the first chamber for each of the N wafers; cause the indexer of the first chamber to move each of the first to Mth wafers of the N wafers to the destination pedestal of the first chamber selected for each of the first to Mth wafers, wherein M=N-1, and the transfer pedestal of the first chamber is the destination pedestal of the first chamber for the Nth wafer; and when each of the N wafers is supported by the corresponding destination pedestal of the first chamber, cause the first chamber to perform one or more semiconductor processing operations on the N wafers.

[0012] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer-executable instructions for further controlling the one or more processors to perform the following operations for each of the N pedestals of the first chamber: obtaining the pedestal deviation associated with the pedestal of the first chamber; and storing the pedestal deviation associated with the pedestal of the first chamber in a data structure that associates each pedestal deviation with the corresponding pedestal of the N pedestals of the first chamber.

[0013] In some implementations of the device, N may be equal to four.

[0014] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to: f) select one of the N pedestals of the first chamber as a destination correction pedestal of the first chamber for a first correction wafer; g) obtain information representing the horizontal position of the center of the first correction wafer from the active wafer centering system; h) cause the robot arm to provide the first correction wafer to the transfer pedestal of the first chamber; i) cause the first chamber to perform a correction process, the correction process comprising performing one or more semiconductor processing operations on the first correction wafer; and j) obtain a preliminary pedestal deviation of the destination correction pedestal for the first chamber based at least in part on the information representing the non-uniformity of the first correction wafer obtained from the correction process in (i) and the horizontal position of the center of the first correction wafer.

[0015] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to perform the following operations: between performing (h) and (i), causing the indexer of the first chamber to move the first correction wafer from the transfer base of the first chamber to the destination correction base of the first chamber.

[0016] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to perform the following operations: using the preliminary pedestal deviation as a pedestal deviation for the destination correction pedestal of the first chamber.

[0017] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to: k) obtain information representing the horizontal position of the center of a second correction wafer from the active wafer centering system associated with the transfer base of the first chamber; l) cause the robot arm to provide the second correction wafer to the transfer base of the first chamber; m) cause the first chamber to perform the correction processing on the second correction wafer; and n) determine a pedestal deviation for the destination correction pedestal based at least in part on information representing the non-uniformity of the second correction wafer, information representing the non-uniformity of the first correction wafer, the horizontal position of the center of the first correction wafer, and the horizontal position of the center of the second correction wafer.

[0018] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to: determine a processing condition for the chamber, and perform (b) by selecting the first pedestal deviation associated with the destination pedestal of the first chamber from a group of N pedestal deviations of the first chamber associated with the processing condition, wherein there are multiple groups of N pedestal deviations for the first chamber, each group being associated with a different processing condition.

[0019] In some implementations of the apparatus, one of the N pedestals of the first chamber may be a second transfer pedestal, the first chamber may include a second active wafer centering system associated with the second transfer pedestal, the wafer handling robot may have an additional robotic arm configured to provide a single wafer to the second transfer pedestal of the first chamber; and the one or more memory devices may store additional multiple computer executable instructions for further controlling the one or more processors to perform the following operations: f) select one of the N pedestals of the first chamber as a destination pedestal of the first chamber for an additional wafer; g) select a pedestal from the N second pedestals of the first chamber that is offset from the first pedestal; h) obtaining information representing the horizontal position of the center of the additional wafer from the second active wafer centering system of the first chamber; i) determining a second end effector deviation associated with the additional wafer based at least in part on the information representing the horizontal position of the center of the additional wafer obtained from the second active wafer centering system of the first chamber; and j) causing the additional robot arm to provide the additional wafer to the second transfer pedestal of the first chamber based on the pedestal deviation and the second end effector deviation.

[0020] In some implementations of the apparatus, the apparatus may further include: a second chamber having an indexer and R pedestals arranged in a circular array centered on the rotation axis of the indexer. In such an implementation, one of the R pedestals of the second chamber may be a transfer pedestal of the second chamber, each pedestal of the second chamber may be configured to support a wafer, R may be an integer greater than 1, the second chamber may include an active wafer centering system associated with the transfer pedestal of the second chamber, and the second chamber is a multi-station semiconductor processing chamber. In addition, the one or more processors, the one or more memory devices, the wafer handling robot, the indexer of the second chamber, and the active wafer centering system of the second chamber may be operably connected to each other, and the one or more memory devices may store additional multiple computer executable instructions for further controlling the one or more processors to perform the following operations: f) select one of the R pedestals of the second chamber as a destination pedestal of the second chamber for an additional wafer; g) select a corresponding second pedestal associated with the destination pedestal of the second chamber from the set of R second pedestal deviations of the second chamber pedestal deviation, each second pedestal deviation of the second chamber being associated with a different pedestal of the R pedestals of the second chamber; h) obtaining information representing a horizontal position of a center of the additional wafer from the active wafer centering system of the second chamber; i) determining a second end effector deviation associated with the additional wafer based at least in part on the information representing the horizontal position of the center of the additional wafer obtained from the active wafer centering system of the second chamber; and j) causing the robot arm to provide the additional wafer to the transfer pedestal of the second chamber based on the second pedestal deviation and the second end effector deviation.

[0021] In some implementations of the apparatus, the indexer arm may include a plurality of indexer arms, each indexer arm may be connected at one end to a central hub of the indexer and have a wafer support at the other end, the wafer support being configured to rotate relative to the indexer about a corresponding rotation axis, and the one or more memory devices may store additional plurality of computer executable instructions for further controlling the one or more processors to: f) select a wafer support from the plurality of wafer supports supported by the indexer arm as a destination wafer support for the first chamber for a second wafer; g) select a wafer support from a group of N wafer support deviations that is adjacent to the destination wafer support of the first chamber; h) obtaining information representing a horizontal position of a center of the second wafer from the active wafer centering system of the first chamber; i) determining a first end effector deviation associated with the second wafer based at least in part on the information representing the horizontal position of the center of the second wafer obtained from the active wafer centering system of the first chamber; and j) causing the wafer handling robot to provide the second wafer to the transfer base of the first chamber based at least in part on the first wafer support deviation and the first end effector deviation.

[0022] In some implementations, an apparatus may be provided that includes a first chamber having an indexer and N pedestals arranged in a circular array centered on a rotation axis of the indexer. One of the N pedestals of the first chamber may be a transfer pedestal, each pedestal of the first chamber may be configured to support a wafer, N may be an integer greater than 1, the first chamber may include an active wafer centering system associated with the transfer pedestal, the first chamber may be a multi-station semiconductor processing chamber, and the indexer may have N indexer arms, each indexer arm having: i) a proximal end connected to a central hub, the central hub being configured to rotate about a first axis; and ii) a distal end supporting a wafer support, the wafer support being configured to rotate relative to the indexer arm about a corresponding second axis. The apparatus may also include: a wafer handling robot having a robotic arm configured to provide a single wafer to the transfer pedestal of the first chamber; and a controller including one or more processors and one or more memory devices. The one or more processors, the one or more memory devices, the wafer handling robot, the indexer of the first chamber, and the active wafer centering system of the first chamber may be operably connected to each other, and the one or more memory devices may store computer executable instructions for controlling the one or more processors to: a) select a wafer support from the plurality of wafer supports supported by the indexer arm as a destination wafer support of the first chamber for a first wafer; b) select a first wafer support deviation associated with the destination wafer support of the first chamber from a group of N wafer support deviations; difference, each wafer support deviation being associated with a different wafer support among the plurality of wafer supports; c) obtaining information representing a horizontal position of a center of the first wafer from the active wafer centering system of the first chamber; d) determining a first end effector deviation associated with the first wafer based at least in part on the information representing the horizontal position of the center of the first wafer obtained from the active wafer centering system of the first chamber; and e) causing the wafer handling robot to provide the first wafer to the transfer base of the first chamber based at least in part on the first wafer support deviation and the first end effector deviation.

[0023] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to: f) after (e), rotate the indexer to align the corresponding second axis of the destination wafer support with the center of the first wafer; g) place the first wafer on the destination wafer support, wherein the center of the first wafer is aligned with the second axis of the destination wafer support; h) after (g), rotate the indexer to move the first wafer from a station of the first chamber having the transfer base to another station of the first chamber having a base that is not the transfer base; i) place the first wafer on the base of the other station; j) between (g) and (i), rotate the wafer support for the first wafer about the corresponding second axis relative to the indexer arm supporting the wafer support; and k) cause the first chamber to perform one or more semiconductor processing operations on the first wafer while the first wafer is on the base of the other station.

[0024] In some implementations of the apparatus, the one or more memory devices may store additional multiple computer executable instructions for further controlling the one or more processors to perform the following operations for each of the second to Nth wafers: f) selecting a wafer support from the plurality of wafer supports supported by the indexer arm as a destination wafer support for the first chamber for the wafer; g) selecting a corresponding wafer support deviation associated with the destination wafer support for the first chamber for the wafer from the group of N wafer support deviations; h) obtaining information representing the horizontal position of the center of the wafer from the active wafer centering system of the first chamber; i) determining a horizontal position of the wafer based at least in part on the information obtained from the active wafer centering system of the first chamber. j) causing the wafer handling robot to provide the wafer to the transfer base of the first chamber based at least in part on the corresponding wafer support deviation for the wafer and the corresponding end effector deviation for the wafer; k) after (j), rotating the indexer to align the corresponding second axis of the destination wafer support for the wafer with the center of the wafer; and l) causing the wafer to be placed on the destination wafer support for the wafer, wherein the center of the wafer is aligned with the second axis of the destination wafer support for the wafer.

[0025] In some implementations of the apparatus, each pedestal of the first chamber may be associated with a corresponding station of the first chamber, and the one or more memory devices may store additional multiple computer-executable instructions for further controlling the one or more processors to perform the following operations: (m) after (l), causing the indexer to uniformly move each of the N wafers from the station of the first chamber where each of the N wafers was located before (m) to the station of the first chamber where another of the N wafers was located before (m); (n) causing each of the N wafers to be placed on the pedestal of the station into which the wafer was moved in (m); (o) between (l) and (n), causing the destination wafer support for each of the wafers to rotate the corresponding wafer about the second axis of the destination wafer support relative to the indexer arm supporting the destination wafer support; and (p) after (n), causing the first chamber to perform one or more processing operations on the N wafers.

[0026] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to perform the following operations: repeating (l) to (p) one or more times.

[0027] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for further controlling the one or more processors to perform the following operations: repeating (l) to (p) N times or more.

[0028] In some implementation schemes of the apparatus, the one or more memory devices may store additional multiple computer executable instructions for controlling the one or more processors to perform the following operations: f) select one of the N wafer supports as the destination correction wafer support of the first chamber for the first correction wafer; g) obtain information representing the horizontal position of the center of the first correction wafer from the active wafer centering system; h) cause the robot arm to provide the first correction wafer to the transfer base of the first chamber; i) cause the indexer to rotate so that the destination correction wafer support is positioned below the first correction wafer; j) cause the first correction wafer to be placed on the destination correction wafer support; k) cause the destination correction wafer support to rotate. The support and the first correction wafer supported thereby are rotated by a first angular amount along a first direction around the corresponding second axis; l) the robot arm is caused to retract the first correction wafer from the first chamber; m) information representing an updated horizontal position of the center of the first correction wafer is obtained from the active wafer centering system; n) the wafer support deviation for the destination correction wafer support is determined based at least in part on the horizontal position of the center of the first correction wafer, the updated horizontal position of the center of the first correction wafer, the first angular amount and the first direction; and o) the wafer support deviation for the destination correction wafer support associated with the wafer support serving as the destination correction wafer support is stored in a data structure.

[0029] In some implementations of the apparatus, the one or more memory devices may store an additional plurality of computer executable instructions for controlling the one or more processors to perform the following operations; repeating (f) to (o) N-1 times, wherein each repetition uses a different one of the wafer supports as the destination correction wafer support. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Various implementations disclosed herein are illustrated by way of example and not limitation in the accompanying drawings in which like reference numerals refer to similar elements.

[0031] Figure 1 Several different types of single chamber multi-station processing techniques are shown.

[0032] Figure 2 An indexer is shown that features a wafer support that is rotatable relative to a plurality of indexer arms that support the wafer support.

[0033] Figures 3-1 to 3-5 Shown are side views of an exemplary transfer base, indexer arm, and wafer handling robot during various temporary wafer transfer stages.

[0034] Figure 4 An example of wafer edge thickness after the correction process is shown.

[0035] Figure 5 A flow chart showing such a multi-station pedestal deviation determination technique.

[0036] Figure 6 A flow chart is shown of a technique for placing a wafer in a multi-station chamber in preparation for processing in a static mode.

[0037] Figure 7 An example of a multi-station chamber with multiple pedestals under deviation conditions is shown, along with the resulting pedestal deviations shown.

[0038] Figure 8 A flow chart is shown of a technique for determining wafer support deflection using a multi-station chamber under specific processing conditions.

[0039] Figures 9 to 12 The calibration wafer is shown during various states of the above-described technique when it is positioned in such a manner that the calibration wafer is centered on the rotation axis of the wafer support.

[0040] Figures 13 to 16 The calibration wafer is shown during various states of the above technique when it is positioned in a manner that causes it to be not centered on the rotation axis of the wafer support.

[0041] Fig.17 An exemplary technique for loading a wafer in preparation for processing using either such mode is shown.

[0042] Figures 18 to 21 The chamber is shown for various processing mode conditions and representative wafer uniformity associated with such conditions.

[0043] Fig. 22 An example of a multi-chamber tool is shown.

[0044] The drawings herein are generally not drawn to scale, but various aspects of the drawings, such as those described below, may be drawn to scale. DETAILED DESCRIPTION

[0045] The wafer placement and wafer placement correction techniques and equipment discussed in this article can be widely applied to various single-chamber multi-station processing technologies. Figure 1 Several different types of single chamber multi-station processing techniques are shown.

[0046] exist Figure 1 , a four-station semiconductor processing chamber 102 is shown during various groups of semiconductor processing operations according to various multi-station processing techniques. Figure 11 shows four different techniques (each technique is shown in a different row), each technique having four sets of semiconductor processing operations (each operation is shown in a different column). In each technique, four wafers (A, B, C, and D) are initially loaded into chamber 102 so that they have the same position and orientation (the orientation of each wafer is represented by a small triangle on the outer circumference of the wafer). An indexer (not shown) can be used to position the wafers on their respective initial susceptors and (in some techniques) to move the wafers between susceptors between sets of processing operations.

[0047] In a first technique representing a typical multi-station chamber operation, between each set of semiconductor processing operations, the chamber's indexer can simultaneously move multiple wafers from their respective stations to the next station in a rotating sequence; this technique may be referred to herein as a "conventional indexing mode." Thus, wafer A may be placed on the lower left pedestal / station for the first set of processing operations, then moved to the upper left pedestal / station for the second set of processing operations, then moved to the upper right pedestal / station for the third set of processing operations, and then moved to the lower right pedestal / station for the fourth set of processing operations. Wafers B, C, and D may be moved between stations in a similar manner, but each wafer may start in / on a different initial station / pedestal. Because the indexer also causes each wafer to rotate 90° as it moves it from one station to an adjacent station, each wafer's orientation relative to the overall chamber is also rotated 90° each time it moves from one pedestal to an adjacent pedestal. Thus, each wafer does not change orientation as it rotates from one station to another, viewed in a radial coordinate system centered on the indexer's axis of rotation. Thus, the same edge of each wafer may be closest to the chamber center (and the indexer's axis of rotation), regardless of which station / pedestal it is placed on. If there is a radial process non-uniformity that exhibits radial non-uniformity relative to the chamber center, this will cause the wafer to develop a repeating similar radial non-uniformity pattern at each station / pedestal, thereby exacerbating the non-uniformity. Conventional indexing schemes may be used, for example, when each station in a multi-station chamber is configured to perform a different set of processing operations.

[0048] The second technique involves using a multi-station chamber, effectively equivalent to four discrete processing chambers. Each wafer A, B, C, and D may be loaded onto a respective susceptor using an indexer and then may remain on its respective susceptor during the first, second, third, and fourth sets of operations. The orientation or position of each wafer is not changed between each set of processing operations; this mode of operation may be referred to as a "static mode."

[0049] The third technique is similar to the second technique, but each wafer is rotated relative to the station / pedestal on which it is placed between each set of processing operations; however, the wafer is not moved from one station to another between each set of processing operations. The third technique rotates each wafer, for example, 90° relative to the overall chamber between each set of processing operations, thereby averaging out any radial non-uniformities that develop on the wafer after processing the wafer using the first, second, third, and fourth sets of processing operations. This third technique may be referred to herein as a "static in-place rotation mode."

[0050] In a fourth technique, each wafer is not transferred from its respective pedestal to the next pedestal between each set of processing operations, but the wafers are subjected to additional rotations (beyond the rotation provided by the indexer to move the wafers from one station to another via rotation) between each set of processing operations. For example, the indexer may rotate each wafer 90° as the wafers move from one pedestal to another via rotation, and may rotate an additional 90° (clockwise or counterclockwise) so that a different quadrant edge of each wafer is closest to the rotation axis of the indexer for each set of semiconductor processing operations. This mode may be referred to herein as an "indexed in-place rotation mode."

[0051] It should be understood that the techniques discussed herein and the examples provided above focus on a multi-station chamber having four stations / pedestals, but the techniques and apparatus discussed herein can also be used in multi-station chambers having more or fewer stations / pedestals, including chambers having two stations, three stations, five stations, six stations, and more than six stations. However, a four-station chamber is the most common type of rotary indexing multi-station chamber because it provides the most economical use of floor space per wafer and is therefore the focus of the examples herein.

[0052] Both the static mode and the conventional indexing mode can be implemented in a multi-station chamber with a conventional indexer, which is an indexer that can only rotate multiple indexer arms in unison around the rotation axis of the indexer to move wafers from one station to another. However, the static in-place rotation mode and the indexing in-place rotation mode additionally require a mechanism for rotating each wafer around its central axis without moving the wafer from one station to another. Such a mechanism can be provided, for example, by using an indexer with an additional rotation axis or by using a base, such as an indexer that can rotate each wafer support around a corresponding rotation axis relative to the indexer arm supporting the wafer support, such as a base that provides a mechanism for rotating the wafer placed thereon in situ, such as a torsion pad or the like. Therefore, a multi-station chamber configured for performing either in-place rotation mode can also generally perform the static mode or the conventional indexing mode simply by not using a mechanism that allows the wafer to rotate around its central axis without having to move the wafer from one station to another. Depending on which mode is selected, a particular semiconductor processing tool incorporating a multi-station chamber of the type discussed herein may be used to perform all of the modes discussed above, or a particular semiconductor processing tool including a multi-station chamber of the type discussed herein may only be configured to perform a subset of such modes. For example, a semiconductor processing tool having a multi-station chamber including a "conventional" indexer, such as an indexer that does not have the ability to rotate a wafer about its own axis relative to an indexer arm (or otherwise does not have the ability to rotate a wafer about its own center without having to move the wafer from station to station) will not be able to be easily used to perform either a static rotate-in-place mode or an indexed rotate-in-place mode.

[0053] An indexer with an additional axis may be, for example, a new type of indexer recently developed by the assignee of the present disclosure that features wafer supports that can be configured to rotate relative to the indexer arms that support them. Figure 2 An example of such an indexer is shown. It can be seen that the indexer 214 has a plurality of indexer arms 216 arranged in a circle about a central hub 220, each indexer arm 216 having a wafer support 228 connected thereto and bearings that allow the wafer support 228 to rotate relative to the indexer arm 216 about a rotation axis 230 that is positioned to align with the center of a wafer supported by the wafer support 228 (assuming the wafer is perfectly placed on the wafer support 228).

[0054] In some such indexers, each wafer support 228 is connected to an actuator hub 218 by a tie rod 222, the actuator hub 218 being configured to rotate about the indexer's rotational axis; the actuator hub 218 can rotate about the rotational axis 226 of the indexer 214 independently of the central hub 220 of the indexer 214 to which the indexer arm 216 is attached. The tie rods 222, the rotatable wafer supports 228, the actuator hubs 218, and the indexer arms 216 form sets of four-bar linkages that can rotate the rotatable wafer supports 228 in unison with respect to their respective indexer arms 216 when the actuator hubs 218 rotate relative to the central hubs 220. However, when both the actuator hubs 218 and the central hubs 220 rotate in unison, the indexer 214 behaves similarly to a conventional indexer, i.e., moves wafers from one station to another without providing additional rotation beyond that provided by conventional indexers. Indexers having additional rotation axes other than the central rotation axis of the indexer, such as separate rotation axes of the wafer support, are discussed in depth in U.S. Patent No. 10,109,517 issued on October 23, 2018, all of which is incorporated herein by reference.

[0055] The wafer placement correction techniques discussed herein are particularly applicable to static mode, static spin-in-place mode, and indexed spin-in-place mode.

[0056] In general, when a wafer is placed in a semiconductor processing chamber, it is generally desirable to place the wafer in a position that is centered on a pedestal that receives the wafer. After the semiconductor processing chamber is installed, a wafer handling robot used to transfer a wafer from a location outside the semiconductor processing chamber to the semiconductor processing chamber is usually "trained" as part of the chamber setup process. During training, the wafer handling robot can be equipped with a calibration fixture that can replace the wafer that the wafer handling robot is designed to support. The calibration fixture can be fixed, for example, to the end effector of a wafer handling robot that is typically used to transfer wafers. The calibration fixture can be designed to dock with a feature on a transfer pedestal of the processing chamber (or dock with another fixture that can be fixed thereto) so that the wafer handling robot can be manually (or automatically) moved to a specific position relative to the transfer pedestal; the term "transfer pedestal" or "transfer station" is used herein to refer to a station or pedestal of a processing chamber that is positioned as the first station or pedestal that a wafer introduced into the processing chamber will encounter after being introduced into the processing chamber. It should be understood that when referring to a wafer "placed" on a transfer pedestal herein, such placement may include wafer placement, where the wafer rests directly on the pedestal upper surface, such as where it would be during semiconductor processing operations, but it may also include "temporary placement," where the wafer may be supported in midair by a plurality of lift pins of the pedestal but never actually lowered onto the pedestal upper surface, such as when a wafer is placed on a transfer pedestal and then moved from the transfer pedestal to another pedestal by an indexer almost immediately after such placement. It should also be understood that a transfer pedestal may also serve as the last stop or pedestal that a wafer introduced into a processing chamber will encounter before being removed from the processing chamber by a wafer handling robot.

[0057] Figures 3-1 to 3-5 A side view of an exemplary transfer base, indexer arm, and wafer handling robot during various interim wafer transfer stages is shown. Figure 3-1 3, a wafer 336 is supported by an end effector 350 of a robotic arm 348 of a wafer handling robot. The wafer 336 has been positioned above a transfer base 310, and an indexer arm 316 having a wafer support 328 at its distal end is positioned adjacent the transfer base 310. The transfer base 310 may have a plurality of lift pins 308 that may be retracted to avoid potential collisions with the end effector 350 and / or the wafer 336 as the robotic arm 348 moves the end effector 350 and wafer 336 into position above the transfer base 310.

[0058] exist Figure 3-2 In FIG. 3 , a plurality of lift pins 308 have been extended from the transfer base 310 to lift the wafer 336 away from the end effector 350, thereby allowing the robot arm 348 to provide the wafer 336 to the transfer base 310. Figure 3-3, the robot arm 348 has retracted the end effector 350 from under the wafer 336.

[0059] exist Figure 3-4 In the embodiment of the present invention, the indexer arm 316 can be rotated so that the wafer support 328 is located below the wafer 336. Finally, in Figure 3-5 3, the plurality of lift pins 308 may be lowered and the wafer 336 may be placed onto the wafer support 328 of the indexer arm 316. It should be appreciated that in certain implementations, the wafer 336 may also be lowered into direct contact with the upper surface of the transfer pedestal 310, with the upper surface of the transfer pedestal 310 being held stationary relative to the plurality of lift pins 308 before the wafer is transferred to the wafer support 328. Either scenario is considered herein as providing the wafer to the transfer pedestal.

[0060] In most multi-station chambers, only one or two of the multiple stations / pedestals of the chamber are transfer pedestals, and the remaining pedestals can only have wafers placed thereon via operation of an indexer, i.e., by placing the wafer into a transfer station of the chamber and then moving the wafer to the final destination pedestal via operation of an indexer.

[0061] During training, the calibration fixture may be mechanically secured in a particular position via contact between features of the calibration fixture and the transfer pedestal (or another fixture mounted to the transfer pedestal). Once the wafer handling robot has been placed in what is considered a desirable position relative to the pedestal (e.g., where the wafer handling robot would be when the wafer is placed so that it is centered on the pedestal), the wafer handling robot may be "taught" that position, e.g., by causing the wafer handling robot to store coordinates of that position (or, for example, various angular positions of each link in the robot arm) relative to a particular position (e.g., "center of pedestal"). This is used to enable the wafer handling robot to learn where the pedestal is located relative to the coordinate system in which the wafer handling robot operates, thereby enabling the wafer handling robot to accurately place the wafer relative to the pedestal.

[0062] While the calibration fixture used to teach the wafer handling robot may be fixed relative to the end effector of the wafer handling robot and may therefore be constantly positioned relative to the end effector of the wafer handling robot, the actual wafer placed on the end effector of the wafer handling robot does not benefit from the mechanical fixation used to maintain the calibration fixture in place and accurately positioned relative to the end effector. In practice, such a wafer may be placed on the wafer handling robot and have some variation relative to the end effector. Thus, if the wafer is not centered on the position of the end effector (the end effector is centered on the center of the pedestal in the "taught" position), the wafer will similarly not be centered on the center of the pedestal when the wafer handling robot is guided back to the taught position.

[0063] To account for this variation in placement of the wafer relative to the end effector, semiconductor processing chambers are typically configured with active wafer centering (AWC) systems. Such systems are typically located outside the chamber because the environment within the chamber during processing operations may damage such sensors or otherwise interfere with their operation. In most systems, the AWC is positioned above and / or below the chamber's load port so that wafers placed into the chamber by a wafer handling robot can interact with the AWC system when entering or leaving the chamber. A typical AWC system uses multiple beam sensors, each of which is configured with an optical emitter to direct a beam of light along a vertical direction and an optical sensor positioned to detect the beam of light. When one of the multiple beams of light is interrupted by an object, such as a wafer, that passes through the beam of light, the optical sensor detects the beam interruption. The robotic arm position awareness provided by the AWC system, together with the sensors of the wafer handling robot, can determine the location of the center of the wafer relative to a particular reference frame.

[0064] For example, after a wafer handling robot has been trained, the wafer handling robot may be caused to retrieve a wafer from a chamber via an AWC system (in this example, the AWC system is assumed to be an AWC with two optical sensors, although other types of AWC systems may be used) along a particular path; as the wafer passes through the AWC system, four beam events will occur, one for each of the two optical sensors when the edge of the wafer interrupts the optical sensor's beam, and another when the edge of the wafer ceases to interrupt the beam. For each such beam event, the horizontal (XY) position of a reference point of the wafer handling robot relative to the end effector may be obtained, such as a reference point position aligned with where the center of a wafer ideally placed on the end effector would be located (although any reference point that remains fixed in space relative to the end effector may be used), thereby providing a set of XY coordinates that may be used with the wafer diameter and the distance between the optical sensors to determine the center position of the wafer relative to the particular path followed by the wafer handling robot as it passes through the AWC system. When such wafer center determination is performed, for example, using a calibration fixture (which may be similar in shape to the wafer and have the same diameter as the wafer), this provides the wafer handling robot with two coordinates that it can use to ensure that future wafers can be correctly centered on, for example, a pedestal during a placement operation. In short, the wafer handling robot, through a position sensor, can know the position of the end effector relative to the wafer centered on the pedestal (e.g., the position has been taught using the calibration fixture), the position of the end effector relative to the XY wafer center determined by the calibration fixture through the AWC system, and the action required to move the wafer between the two positions. Therefore, if the wafer is placed at a position on the end effector of the wafer handling robot that is considered to be perfectly placed, i.e., the wafer is centered where it should be, then the AWC system should provide the same XY wafer center measurement data for the wafer as it passes through the AWC system along the specific path obtained by the calibration fixture. The wafer handling robot can then move to the exact same XY position that it was taught for the pedestal placement operation to provide the wafer to the pedestal and thereby center the wafer on the pedestal.

[0065] However, if the wafer is not perfectly placed on the end effector, the AWC system will provide different XY wafer center measurements for the wafer as it passes through the AWC system along the path used by the calibration fixture than the XY wafer center associated with the calibration fixture. If the wafer handling robot moves the wafer along the same path used by the calibration fixture, the wafer center will be similarly placed relative to the desired pedestal center when the wafer handling robot presents the wafer to the pedestal. To correct such placement, the wafer handling robot may be caused to adjust the target position of the end effector relative to the reference point of the pedestal from the calibrated position to a new position that is offset from the calibrated position by a deviation vector equal to the deviation vector between the two wafer center points measured by the AWC (i.e., the calibrated wafer center point and the current wafer center point).

[0066] For example, if the calibration fixture has an overall dish shape and is secured to the end effector so that the center of the dish is positioned where the center of the wafer is expected to be when the wafer is supported by the end effector, the reference point associated with the end effector may be selected as the center of the calibration fixture. Thus, when teaching the wafer handling robot the XY position of the center of the base, the reference point associated with the end effector is centered on the center of the base. Similarly, when the calibration fixture passes through the AWC system, the measured center point of the calibration fixture and the reference point associated with the end effector are co-located. If, after teaching the wafer handling robot, the wafer is placed on the end effector so that the horizontal position of the center of the wafer determined by the AWC system when the wafer handling robot translates the wafer along a particular path deviates by an (X, Y) deviation of (1 mm, 2 mm) from the horizontal position of the center of the calibration fixture measured by the AWC system, the wafer handling robot may be controlled to adjust the target destination of the reference point associated with the end effector by a calibration deviation of (-1 mm, -2 mm) which causes the reference point to no longer be aligned with the center of the base but to center the center of the wafer on the center of the base for the placement operation. The correction deviation originates from and is used to correct for the initial displacement of the wafer when it is placed on the end effector, and is therefore referred to herein as "end effector deviation".

[0067] In some multi-station semiconductor processing chambers, the chamber may be under processing conditions, such as at elevated temperatures and / or reduced pressures, which may cause the chamber and the equipment contained therein to experience small displacements compared to non-processing conditions. For example, during the teaching of a wafer handling robot, the processing chamber may typically be maintained at room temperature and atmospheric pressure (which may generally be considered a non-processing condition) because a technician must access the interior of the chamber during the teaching process to ensure alignment of the calibration fixture. However, during actual semiconductor processing operations, the chamber may reach temperatures of hundreds of degrees Celsius, which may cause potentially significant thermal expansion displacements in the chamber. Similarly, when the chamber is under vacuum conditions, the pressure imbalance between the atmospheric pressure outside the chamber and the vacuum environment inside the chamber may cause the chamber wall to deflect, which in turn may cause displacement of portions of the chamber and the equipment supported thereby. Thus, for example, the susceptor position may shift, the length of the indexer arm may increase, etc. Therefore, when the chamber is under certain processing conditions, using the chamber under non-processing conditions to teach the center position of the susceptor of the wafer handling robot may no longer be valid, and when the chamber is under certain processing conditions, a wafer placed at the center point may no longer be centered on the susceptor.

[0068] To adjust for such displacements, one or more correction processes may be performed under process conditions to determine one or more correction biases that may be used in addition to the end effector biases to ensure that the wafer is placed in a centered position on the pedestal. To perform the correction process, the wafer handling robot may provide a correction wafer (which may be a normal wafer designated for the correction process) to the transfer pedestal of the multi-station chamber when the chamber is under the desired process conditions; the AWC system may determine the horizontal position of the center of the correction wafer as the correction wafer is transferred through the AWC system during such conditions. If desired, the wafer handling robot may, for example, apply an end effector bias to offset any misalignment between the correction wafer and the end effector. It should be understood, however, that the application of an end effector bias during loading of the correction wafer is optional for reasons that will become apparent as a result of the discussion below.

[0069] Once the calibration wafer has been provided to the transfer pedestal, one or more calibration processing operations may be performed thereon. Such operations may include, for example, deposition or etching operations intended to deposit or remove a layer of material having a circumferentially uniform thickness across the surface of the calibration wafer. Although there may be some radial variation in film thickness, after calibration processing has been completed, the circumferential thickness of the wafer, i.e., the thickness of the calibration wafer along any circular path centered on the center of the calibration wafer, should theoretically be constant or nearly constant, e.g., with a variation of less than 0.1%. However, if the calibration wafer is not centered on the pedestal, the circumferential variation in wafer thickness may increase when calibration processing is completed.

[0070] Figure 4An example of wafer edge thickness after a correction process is shown; the graph shows the circumferential thickness at a radius of approximately 147 mm of a 300 mm diameter correction wafer as a function of angular position about the circumference of the correction wafer. Two graphs are shown, one with "×" data points (401) representing a first correction process using a first correction wafer, and the other with "+" data points (403) representing a second correction process using a second correction wafer. As can be seen, the circumferential thickness of the first correction wafer varies in a generally sinusoidal manner, with the maximum thickness (shown by the diamond-shaped marker) occurring at approximately the 45° position and the minimum thickness (shown by the circular marker) occurring at approximately the 225° position. The maximum and minimum wafer thicknesses about the circumference of the first correction wafer can be defined as Figure 4 The vector shown by the double-arrow line 405 in the first calibration wafer 436 shown in the lower half passes through the center of the pedestal 406; the shading provided in the first calibration wafer diagram represents an area of ​​equal wafer thickness centered on the center of the pedestal. This vector establishes the angular direction of the deviation between the center of the first calibration wafer and the center of the pedestal; the size of the difference between the maximum and minimum thicknesses can be roughly proportional to the size of the deviation center of the first calibration wafer from the center of the pedestal.

[0071] After the calibration process and subsequent edge thickness measurement (which may be performed, for example, on a measuring instrument located outside the chamber) on the first calibration wafer, a correction offset that the wafer handling robot may apply may be determined for future wafers to be transferred to the transfer pedestal, thereby centering such wafers on the pedestal center. The correction offset (referred to herein as a "pedestal offset") may be determined based at least in part on the offset between the pedestal center and the center of the first calibration wafer and the horizontal position of the center of the first calibration wafer as measured by the AWC system. Thus, when the chamber is in normal loading operation under processing conditions and a wafer is placed on the end effector of the wafer handling robot and passes through the AWC system, the wafer handling robot may move the end effector to a position based on the "taught" position but taking into account the end effector offset (to account for variability in wafer placement relative to the end effector) and the pedestal offset (to account for variability in the position of the pedestal relative to the AWC system under processing conditions as compared to the position of the pedestal relative to the AWC system under non-processing conditions to which the wafer handling robot was taught).

[0072] In some cases, the pedestal deviations are tested on a second calibration wafer and then further optimized if necessary. For example, the second calibration wafer may be placed on the end effector of a wafer handling robot and provided to a transfer pedestal (the horizontal wafer center position of the second calibration wafer is obtained using the AWC system during the process) using the end effector deviations and pedestal deviations used for the second calibration wafer so that the wafer center is positioned at the estimated center position derived from the first calibration wafer data. The same or similar calibration process is then performed on the second calibration wafer, and the second calibration wafer is then removed from the chamber and evaluated using the same measurement tool as described above to obtain circumferential thickness data such as Figure 4 As can be seen, the pedestal deviation derived from the first corrected wafer thickness improves wafer uniformity, but the circumferential uniformity of the second corrected wafer still has room for improvement.

[0073] If the second calibration wafer results do not confirm that the susceptor deviation based on the first calibration wafer results accurately centers the second calibration wafer on the susceptor, the susceptor deviation may be optimized based on the results of the first and second calibration wafer data. For example, the horizontal distance between the horizontal positions of the center points of the first and second calibration wafers determined by the AWC system may be proportional to the difference in non-uniformity between the first and second calibration wafers, so that a more accurate susceptor deviation may be determined and used to update the susceptor deviation.

[0074] If the chamber is operated under a variety of different process conditions, a calibration process may be performed for each process condition where it is desired to establish a pedestal deviation.

[0075] In the context of a multi-station chamber, susceptor deviation may be determined in much the same manner as described above for each separate susceptor in the chamber. Figure 5A flow chart of such a multi-station pedestal deviation determination technique is shown. In block 502, a calibration wafer may be provided to a transfer pedestal by a wafer handling robot; the AWC system may determine the center position of the calibration wafer relative to the AWC system during such conditions. In block 504, an indexer may selectively move the calibration wafer away from the transfer pedestal and to a pedestal for which pedestal deviation is to be determined (this operation may be omitted if the pedestal for which pedestal deviation is to be determined is the transfer pedestal itself). In block 506, the calibration process discussed above may be performed on the calibration wafer where the pedestal supports the calibration wafer (and where pedestal deviation is to be determined). In block 508, an indexer may optionally move the calibration wafer from the pedestal for which pedestal deviation is to be determined back to the transfer pedestal (as with block 504, this operation may be omitted if the pedestal for which pedestal deviation is to be determined is the transfer pedestal itself). In block 510, uniformity information is obtained on the calibration wafer, for example using a metrology instrument, and then, in block 512, a pedestal deviation is determined for a pedestal supporting the calibration wafer during the calibration process based on the uniformity information of the calibration wafer and the XY position of the calibration wafer determined by the AWC system in block 502. In block 514, the pedestal deviation may be stored in a memory associated with identification information of the pedestal supporting the calibration wafer during the calibration process. In block 516, it is determined whether there are further pedestal deviations to be obtained; if so, the technique may return to block 502 and repeat the technique to determine pedestal deviations for additional pedestals, or perform the technique again for the same pedestal to optimize the pedestal deviations already determined for that pedestal. If it is determined in block 516 that no further pedestal deviation determination is needed, the technique may proceed to block 518, where normal wafer loading may begin to begin wafer processing operations at a manufacturing level.

[0076] In general, the indexer can be controlled to move in a consistent manner for wafer movement operations, including both in the process of determining pedestal deviations and later wafer placement operations (which are part of normal processing). For example, in a four-station multi-station chamber, the indexer can be rotated 90° for each wafer movement operation (to move the wafer to the next pedestal / station). Ideally, the rotational motion of the indexer when moving a wafer from one station to the next can be 360° / N, where N is the number of stations / pedestals arranged around the indexer's rotation axis.

[0077] It should be understood that the above techniques for determining end effector deviations and base deviations are merely exemplary techniques and other techniques may be used. Regardless of how the end effector deviations and / or base deviations are determined, the manner in which such end effector deviations and base deviations may be used to support static mode processing following such determinations is substantially the same, as described below. Figure 6 discussed.

[0078] Figure 6A flow chart is shown of a technique for placing a wafer in a multi-station chamber in preparation for processing in a static mode. Figure 6 The technique may begin at block 602, where a wafer is selected for processing in a multi-station chamber. At block 604, a pedestal in the multi-station chamber may be selected as a destination pedestal for the selected wafer. The term "destination pedestal" as used herein for a wafer generally refers to a station / pedestal where the wafer is located during semiconductor processing operations in the context of a static mode or a static in-place rotation mode.

[0079] Once a destination pedestal has been selected for the wafer in block 604, a corresponding pedestal deviation may be obtained for the destination pedestal in block 606. For example, a controller of the multi-station chamber may select the corresponding pedestal deviation from a database that associates the pedestal deviation with the corresponding pedestal of the multi-station chamber.

[0080] Once the destination pedestal and the associated pedestal offset have been selected in block 606, the selected wafer may be loaded onto the end effector of the wafer handling robot to place the wafer onto the transfer pedestal of the multi-station chamber in block 608. The selected wafer may also be placed onto the end effector of the wafer handling robot before selecting the destination pedestal or the corresponding pedestal offset.

[0081] Once the selected wafer has been placed on the end effector of the wafer handling robot, the horizontal position of the center of the selected wafer relative to the AWC system of the multi-station chamber can be determined in box 610 as previously discussed, and the horizontal position can be used in box 612 to determine the end effector deviation of the selected wafer.

[0082] In block 614, the wafer handling robot provides and positions the selected wafer to a transfer pedestal of the multi-station chamber based at least in part on the pedestal deviation selected for the destination pedestal and the end effector deviation determined for the selected wafer.

[0083] In block 616, it is determined whether the transfer pedestal is also a destination pedestal; if not, the technique may proceed to block 618, causing the indexer of the multi-station chamber to move the wafer from the transfer pedestal to the destination pedestal. In some implementations, the action of moving the selected wafer from the transfer pedestal to the destination pedestal may occur in multiple stages, with additional wafers being provided to the transfer pedestal between each stage, and each wafer going to a different pedestal in the plurality of pedestals. In some such implementations, the selected wafer may be continuously supported by the indexer, or in other implementations, the selected wafer may be placed on another pedestal of the multi-station chamber and then picked up again by the indexer for continued movement. After the selected wafer has been moved to its corresponding destination pedestal or at least moved away from the transfer pedestal, the technique may return to block 602, where the technique is repeated for additional selected wafers until the transfer pedestal is selected as the destination pedestal. When the transfer pedestal is selected as the destination pedestal, the technique may proceed to block 620, using the fully loaded multi-station chamber to process the loaded wafers.

[0084] If desired, you can also Figure 6 The technology is used for a partially loaded multi-station chamber, omitting loading wafers into unused stations. In addition, in some implementations, the multi-station chamber may have two pedestals used as transfer pedestals. In such implementations, the multi-station chamber may have an AWC system dedicated to each transfer pedestal and may have two pedestal deviations for each destination pedestal, each pedestal deviation for a particular destination pedestal being determined for a different one of the two transfer pedestals. In such implementations, the pedestal deviations selected for the destination pedestals may be selected from a database that associates each pedestal deviation with a different combination of pedestals and transfer pedestals to be used to load wafers into the multi-station chamber; when the wafer is to be placed on the selected transfer pedestal and moved to the selected destination pedestal, the wafer may be placed on the selected transfer pedestal using the pedestal deviations corresponding to the selected transfer pedestal and the selected destination pedestal.

[0085] Available Figure 6 The technology ensures that each wafer is ultimately placed into a specific position on its destination pedestal so that the center of the wafer is centered relative to the destination pedestal, which can generally provide the highest level of wafer uniformity during a static mode of wafer processing.

[0086] Figure 7 An example of a multi-station chamber with multiple pedestals under deviation conditions is shown, along with the resulting pedestal deviations shown. Figure 7, a multi-station chamber 702 includes four stations 704, each having a pedestal 706 (station 704-1, for example, has pedestal 706-1, and so on). The dashed circle in each station 704 represents the position of each pedestal 706 within the corresponding station 704 when the multi-station chamber 702 is not under processing conditions, such as when the multi-station chamber 702 is at room temperature and a pressure condition equal to atmospheric pressure. In this particular example, each pedestal 706 is centered within the corresponding station 704 when the multi-station chamber 702 is not under processing conditions. The thick solid outline of the pedestal 706 represents the position of the pedestal 706 when the pedestal 706 is displaced (such as may occur when the chamber 702 is under processing conditions). The dashed crosshairs in the middle of each dashed circle represent the central position of each pedestal 706 when the chamber 702 is not under processing conditions. The solid crosshairs in the middle of each pedestal 706 (with numbers 1, 2, 3 or 4 next to them associating them with different stations 704 / pedestals 706) indicate the center position of the displaced pedestal 706 when the chamber 702 is in processing conditions.

[0087] In the case of station 704-1, in addition to solid crosshairs showing base 706-1, there are solid crosshairs showing bases 706-2, 704-3, and 704-4. The solid crosshairs of bases 706-2, 704-3, and 704-4 in station 704-1 represent the center points of bases 706-2, 704-3, and 704-4 when bases 706-2, 704-3, and 704-4 are rotated 90° (starting from station 704-2), 180° (starting from station 704-3), or 270° (starting from station 704-4) about the indexer rotation axis 726 of the indexer 714; the solid crosshairs of base 706-1 directly represent the center point of the untranslated base 706-1. The dashed crosshair with a "0" next to it in station 704-1 represents the center of pedestal 706-1 in the undisplaced state, which in this example corresponds to the "taught" center of pedestal 706-1 to which wafer handling robot 746 will transfer the wafer to center the wafer on pedestal 706-1. Based on the previous discussion of such destinations, pedestal 706-1 is considered a transfer pedestal in this example.

[0088] The chamber 702 is also configured with an AWC system 742 having two optical sensors 744 in this example configured to register when an edge of a wafer (such as a wafer 736 supported by an end effector 750 and a robotic arm 748 of a wafer handling robot 746) intersects a light beam emitted by either optical sensor 744 to allow determination of the center of the wafer 736 relative to the AWC system 742. Center points 1', 2', 3', 4', and 0' represent center points 1, 2, 3, and 4 shown in station 704-1 and the undisplaced center point of the pedestal 706-1, which are displaced along a displacement vector associated with the displacement vector used by the wafer handling robot 746 when providing a wafer to the transfer pedestal 706-1. As shown in the details provided in the lower right figure, each displaced pedestal center point can be positioned relative to the "taught" center point of the transfer pedestal when rotationally moved about the indexer rotation axis 726 so that a corresponding displacement vector is defined between the taught center point and each of the four "displaced" pedestal center points. These displacement vectors represent the pedestal deviations required to ensure that a wafer centered on the 0' "taught" center point of the undisplaced transfer pedestal will be centered on a particular destination pedestal. For example, if wafer 736 is to be provided to pedestal 706-2 and the wafer is positioned such that its center point coincides with the 0' center point when evaluated by the AWC system 742, the wafer handling robot 746 positions the end effector 750 so that the center of wafer 736 is offset from the 0' position by the displacement vector defined between the 0' and 0 crosshairs (representing the displacement required to align the wafer center with the center of pedestal 706-1 in the undisplaced state, the center of pedestal 706-1 in the undisplaced state being represented by Figure 7 ) and the base deviation defined between the 0' center point and the 2' center point. The displacement vector and the base deviation may be applied separately, for example, as two discrete actions, or a new displacement vector may be calculated that represents the total displacement combined with the original displacement vector and the base deviation. Similarly, if the wafer is not perfectly centered over the center point 0' when evaluated by the AWC system 742, additional end effector deviations may similarly be considered in the movement of the wafer handling robot 746 when placing the wafer.

[0089] While the above techniques may be applied to wafer placement in the context of a multi-station chamber configured to perform static mode processing on a wafer, different techniques may be implemented in the context of static in-place rotation mode processing and / or indexed in-place rotation mode processing using an indexer with an additional rotation axis. When static in-place rotation mode processing and / or indexed in-place rotation mode processing are performed using an indexer with an additional rotation axis, wafer support deviations may be used instead of pedestal deviations. In such in-place rotation modes, if the wafer is not centered on the rotation center of the wafer support for performing in-place wafer rotation, the wafer may experience a continuously increasing misalignment as the wafer support is continuously used to perform wafer retrieval, rotation, and placement operations. In order to minimize or reduce such misalignment effects, the wafer may be assigned to a specific indexer arm, and then the wafer support deviation associated with the specific indexer arm may be used to adjust the positioning of the wafer relative to the transfer pedestal so that when the selected indexer arm retrieves the wafer from the transfer pedestal, the wafer will be centered on the rotation axis of the wafer support at the end of the selected indexer arm. When the wafer is positioned in this manner, rotation of the wafer support relative to the indexer arm results in little or ideally no movement of the center point of the wafer from the position before such rotation to the position after such rotation. In such implementations, the same indexer arm may be used to transfer the wafer during its residence in the chamber, thereby ensuring continued alignment of the wafer center with the rotational axis of the wafer support associated with wafer support deflections.

[0090] Figure 8A flow chart of a technique for determining wafer support deviation in a multi-station chamber under specific processing conditions is shown. The technique begins at block 802, where a calibration wafer may be loaded onto an end effector of a wafer handling robot configured to place a wafer into a multi-station chamber having an indexer having a rotatable wafer support that can be used to rotate the wafer relative to the indexer arm. In block 804, an indexer arm of the indexer for which wafer support deviation is to be determined may be selected. In block 806, the calibration wafer may be passed through an AWC system of the multi-station chamber and a horizontal position of the calibration wafer relative to a wafer center of the AWC system may be determined; then, in block 808, the calibration wafer may be provided to a wafer support of the selected indexer arm. For example, the wafer handling robot may cause the wafer to be provided to a transfer pedestal of the multi-station chamber, where a plurality of lift pins of the transfer pedestal may be extended and lift the calibration wafer off the end effector of the wafer handling robot. The wafer handling robot may then retract the end effector from beneath the calibration wafer, after which the indexer may be rotated so that the selected indexer arm is positioned so that the axis of rotation of the wafer support of the selected indexer arm and the center of the transfer base are substantially aligned when viewed along the vertical axis, and substantially aligned with the wafer support of the selected indexer arm beneath the calibration wafer. The plurality of lift pins may then be retracted into the transfer base and the calibration wafer lowered onto the wafer support of the selected indexer arm.

[0091] Once the correction wafer is loaded onto the wafer support, the wafer support may be rotated relative to the indexer arm to which the wafer support is attached at a predetermined angle in block 810. For example, for an indexer having four indexer arms, the wafer support may be rotated 90° relative to the indexer arm to which it is mounted, but other rotation angles may also be used; the indexer arm itself may remain stationary while the wafer support of the indexer arm is rotated. After such rotation, the end effector of the wafer handling robot retrieves the correction wafer and the correction wafer is passed through the AWC system again in block 812 to determine the horizontal position of the correction wafer relative to the wafer center of the AWC system after the wafer support rotated the correction wafer by the predetermined angle. When the correction wafer is provided to the transfer base and retrieved and passed through the AWC system to obtain the horizontal position of the wafer center of the correction wafer, the wafer handling robot may follow the same movement path so that the only displacement of the correction wafer center relative to the AWC system before and after the rotation is due to the misalignment between the wafer center and the rotation axis of the wafer support.

[0092] After determining the rotation angle of the wafer support before and after the correction wafer rotation and the horizontal position of the correction wafer center relative to the wafer center of the AWC system, the horizontal distance between the correction wafer center and the rotation axis of the wafer support can be determined using trigonometry and geometric relationships to determine the wafer support deviation. For example, if the horizontal distance between two correction wafer center point measurements is x and the rotation angle is θ, the horizontal distance between either of the two correction wafer center points and the rotation axis of the wafer support can be determined according to r=x·atan(θ), which horizontal distance may be referred to herein as the "radial distance" or r. Once the radial distance is known, two potential answers for the location of the rotation axis (the rotation axis is offset to the reference frame of the AWC system in the opposite way that the wafer center is offset from its pre-rotation horizontal position to its horizontal position on the wafer support) can be determined by finding the intersection between two circles, each of which has a radius equal to the radial distance r and each of which is centered at a different horizontal position in the horizontal position of the correction wafer determined by the AWC system. The correct location of the rotation axis can be selected from these two possible answers by considering the direction of rotation and the relative position of the two horizontal center positions. For example, if the direction of rotation of the wafer support is clockwise, the correct rotation axis answer can be determined by, for example, rotating the horizontal center point of the calibration wafer before rotating the calibration wafer about each of the two potential axes of rotational position by the same angular amount and in the same manner as applied to the wafer support; the correct rotation axis will be represented by the rotational position of the calibration wafer after rotation of the horizontal position aligned with the horizontal position of the calibration wafer. The rotation axis position determined in this manner is actually the rotation axis position based on the displaced coordinate system; but if the wafer is positioned with its center point co-located with the rotation axis determined above, and then the wafer handling robot moves the wafer in the same manner as used during the calibration process, the wafer center point will be aligned with the rotation center of the wafer support of the indexer arm.

[0093] Once the rotational axis position of the wafer support relative to the AWC system has been established, the wafer support deviation may be determined in block 814 based on the magnitude and direction of the vector between the "taught" position of the pedestal center (or some other reference frame) and the rotational axis position of the wafer support relative to the AWC system.

[0094] In block 816, it is determined whether additional required wafer support deviations need to be determined; if so, the technique may return to block 802 to further determine such wafer support deviations for wafer supports of other indexer arms. Once wafer support deviations have been determined for each indexer arm, the technique may proceed to block 818, where normal wafer handling operations may begin.

[0095] It should be understood that Figure 8 The technique can be performed with a multi-station chamber under one or more processing conditions, and such wafer support deviations can be determined for each processing condition that may be expected to exist when a wafer is introduced into the multi-station chamber. In addition, if there are two potential wafer loading points, such as two transfer pedestals, two different AWC systems can be used to determine different sets of wafer support deviations, one AWC system for a first transfer pedestal and another AWC system for a second transfer pedestal.

[0096] For further understanding, Figures 9 to 12 The calibration wafer is shown during various states of the above-described technique when the calibration wafer is placed in a centered manner onto the rotation axis of the wafer support. Figures 13 to 16 The calibration wafer is shown during various states of the above-described technique when the calibration wafer is placed in a non-centered manner onto the rotation axis of the wafer support.

[0097] exist Fig. 9 In the embodiment of the present invention, a wafer handling robot having an end effector 950 transfers a wafer 936 through an AWC system 942 having an optical sensor 944 that can be used to determine a horizontal position 938 of the wafer 936 relative to the center of the wafer of the AWC system 942. The wafer handling robot can then provide the wafer to a wafer support 928 that can be attached to an indexer arm 916, such as Fig.10 , the indexer arm 916 is positioned above the pedestal 906 of the multi-station chamber 902. A wafer 936 is provided to the wafer support 928 in a particular orientation, as indicated by the triangular indicator along the upper edge of the wafer 936.

[0098] After the wafer 936 is provided to the wafer support 928, as shown in FIG. Fig.11 As shown in FIG. 9 , wafer support 928 and wafer 936 may be rotated a predetermined amount about rotation axis 930. In this particular case, the rotation angle is 90°, such that the triangular indicator mark shown rotates from the 12 o'clock position (the position of wafer support 928 is shown as a gray dashed line) to the 3 o'clock position.

[0099] After the wafer 936 and wafer support 928 are rotated a specified amount, the end effector 950 may be caused to retract the wafer 936 and pass the wafer 936 again through the AWC system 942, thereby obtaining a second measurement of the wafer center of the wafer 936 relative to the AWC system 942. In this case, there is perfect alignment between the center of the wafer 936 and the rotation axis 930, so no center displacement of the wafer 936 due to the rotation has occurred.

[0100] exist Fig.13 In Fig. 9In the same manner, wafer 936 is provided to wafer support 928. However, multi-station chamber 902 is subjected to processing conditions which may cause wafer support 928 and its rotation axis 930 to deviate, for example, due to thermal expansion of indexer arm 916. Fig. 9 The old position of the wafer support 928 is shown as a light grey dashed line for reference. Fig. 9 As shown, as the wafer passes through the AWC system 942, the AWC system 942 can determine the center position 938 of the wafer 936 relative to the AWC system 942.

[0101] like Fig.10 As shown in Fig.14 The wafer 936 may be placed on the wafer support 928 as shown in FIG. Fig.15 The wafer support 928 shown in FIG. 1 can be rotated a predetermined amount about the rotation axis 930 relative to the indexer arm 916, thereby rotating the wafer 936 about the rotation axis 930 by the same amount, such as 90°. After such rotation, the wafer support 928 can be rotated a predetermined amount about the rotation axis 930 relative to the indexer arm 916, thereby rotating the wafer 936 by the same amount, such as 90°. Fig.16 936 is shown in FIG. 94 , where the end effector 950 is retracted from the wafer support 928 and the wafer 936 is passed through the AWC system 942 to obtain a second measurement of a horizontal position 938′ of the center of the wafer relative to the AWC system 942. Due to the fact that the center of the wafer 936 is misaligned with the rotation axis 930 of the wafer support 928, the rotation of the wafer 936 about the rotation axis 930 causes the center of the wafer 936 to be offset compared to the horizontal position 938 of the center of the wafer 936 before the rotation, as evidenced by the positional shift of the horizontal position 938′ of the center of the wafer 936 after the rotation.

[0102] As shown in the details of the horizontal positions 938 / 938' of the center of the wafer 936 before and after rotation in the lower right figure, two potential answers are shown for the horizontal position of the rotation axis (930' and 930") relative to the horizontal position 938 and 938' of the center point, each of which is equidistant from the two horizontal positions 938 / 938' of the wafer center of the wafer 936, and the angle between the lines connecting the two horizontal positions 938 / 938' of the wafer center of the wafer 936 and each of the potential answers 930' and 930" is equal to the rotation angle experienced by the wafer 936, which is 90° in this example. If the direction of rotation experienced by the wafer 936 is taken into account, such as clockwise in this example, it is obvious that the horizontal position 930' of the rotation axis is the only valid answer of the two potential answers. Once the position of wafer support 928 relative to rotational axis 930' of AWC system 942 is known, wafer support deviation can be determined based on the horizontal position of rotational axis 930' relative to a "taught" horizontal position that functions as a default starting point for each wafer placement operation.

[0103] The techniques are similar in nature to those discussed in U.S. Patent Application No. 16 / 000,734, the entire contents of which are incorporated herein by reference for all purposes. While U.S. Patent Application No. 16 / 000,734 is generally directed to techniques for determining the position of the rotation axis of a "lift pad" or "twist pad" type wafer rotation device (which is a wafer support that is raised off a pedestal, lifts the wafer, rotates the wafer, and then lowers the wafer again onto the same pedestal) and the appropriate bias that can be used to place a wafer on such a twist pad type device, the techniques of interest can be used with other mechanisms that can be used to rotate a wafer about its own axis, such as an indexer having a rotatable wafer support at the end of its indexer arm.

[0104] Once the wafer support deviations are determined, they may be stored in association with information identifying the indexer arm / wafer support for which they are determined and / or information indicating the rotational position of the indexer associated with the wafer support deviation, e.g., the rotational position of the indexer when the calibration wafer is placed on and removed from the wafer support (which will determine which indexer arm / wafer support will be located under the wafer). In the case of a torsion pad type wafer rotator (e.g., the wafer rotator is continuously fixed relative to the chamber, and the indexer rotates relative to the chamber and wafer rotator), the determined wafer support deviations are still determined based on the rotational axis of the wafer rotator, and not each is associated with a different indexer arm. In such cases, each determined wafer support deviation may be stored and associated with the base containing the type of wafer rotator associated with the wafer support deviation. Thus, for example, if four wafer support deviations are determined, and each wafer support deviation is associated with a different twist pad type wafer rotation device contained within a corresponding pedestal, then when a wafer is to be placed on a transfer pedestal, the wafer support deviation associated with the particular destination pedestal may be used. Similar techniques may also be used in an apparatus where the wafer rotation device is the same device as the pedestal, such as where the entire pedestal may be configured to rotate.

[0105] Additional discussion of twist pad type wafer rotation devices can be found in U.S. Patent Nos. 9,960,068 and 9,892,956 and U.S. Patent Publication No. 2018 / 0158716, all of which are incorporated herein by reference.

[0106] Once a complete set of wafer support deviations are determined, normal wafer handling operations involving an indexed in-place rotation mode or a static in-place rotation mode may be performed using the multi-station chamber for which the wafer support deviations were determined, utilizing an indexer having a rotatable wafer support. Fig.17An exemplary technique for loading a wafer in preparation for processing using either such mode is shown.

[0107] exist Fig.17 In the process, the technique may begin at block 1702 with selecting a wafer for loading. In block 1704, the selected wafer is assigned to a selected destination wafer support / indexer arm of the indexer; the destination wafer support / indexer arm is the wafer support / indexer arm that will typically support the wafer during rotation of the wafer relative to the indexer arm and / or movement between stations. As previously discussed, the destination wafer support / indexer arm in this type of processing mode typically remains constant for the wafer during the residence time that the wafer resides in the multi-station chamber.

[0108] In block 1706, the wafer support deviation for the selected wafer support / indexer arm of the indexer may be obtained, for example, by looking up the wafer support deviation in a database that associates each wafer support deviation with a corresponding indexer arm / wafer support of the indexer. In block 1708, the selected wafer may be loaded onto an end effector of a wafer handling robot, and then in block 1710, a horizontal position of a center of the selected wafer relative to an AWC system of a multi-station chamber may be determined, and in block 1712, an end effector deviation for the selected wafer may be determined based at least in part on the horizontal position of the center of the selected wafer relative to the AWC system.

[0109] Once the end effector deviation for the selected wafer has been determined and the appropriate wafer support deviation for the selected indexer arm / wafer support has been obtained, the wafer handling robot can be controlled in box 1714 to provide the selected wafer to the transfer base of the multi-station chamber (it is assumed here that the multi-station chamber has only a single transfer station; multi-station chambers with multiple transfer bases will be discussed later).

[0110] In block 1716, the indexer may optionally be rotated to position the selected destination wafer support under the selected wafer. This operation, as well as the operations of blocks 1718 and 1720, may be omitted if desired during the loading process for the last wafer to be loaded before the wafer processing operation begins. Once the selected destination wafer support is positioned under the selected wafer, the selected wafer may be lowered onto the destination wafer support in block 1718 by, for example, retracting a plurality of lift pins used to support the selected wafer above the transfer pedestal to transfer the selected wafer to the destination wafer support. The indexer may then be caused to rotate the selected destination wafer support, and thereby the selected wafer supported thereby, to a position where the selected wafer will not be disturbed when additional wafers are provided to the transfer pedestal.

[0111] In block 1722, it is determined whether additional wafers need to be loaded into the multi-station chamber. If additional wafers do not need to be loaded into the multi-station chamber, the technique may proceed to block 1724, where a wafer processing operation is started. If additional wafers need to be loaded into the multi-station chamber, the technique may return to block 1702, select a different wafer and repeat the technique.

[0112] As with pedestal deviations, if multiple processing conditions are expected to be encountered in common during various wafer loading operations, a separate set of wafer support deviations may be determined for each processing condition, thereby allowing wafers to be accurately placed on the wafer support of the indexer regardless of which particular one of the multiple processing conditions may be applied. In addition, if multiple transfer pedestals are provided in a multi-station chamber, there may be different AWC systems and different sets of wafer support deviations associated with each transfer pedestal. Thus, in a four-station system with two transfer pedestals and a 4-arm indexer, there may be 8 sets of wafer support deviations associated with a given processing condition, one set for each indexer arm / wafer support of the indexer for wafers to be provided to the first transfer pedestal, and one set for each indexer arm / wafer support of the indexer for wafers to be provided to the second transfer pedestal.

[0113] The following will refer to Figures 18 to 21 The uniformity advantages of using the wafer placement techniques discussed above are discussed in more detail. Figures 18 to 21 Each figure in FIG. 180 shows a multi-station chamber 1802 having four stations (stations 1, 2, 3, and 4, starting with station 1 in the lower left corner and proceeding in a clockwise direction).

[0114] Fig.18 Chamber 1802 is shown in a conventional indexing mode, wherein an indexer (not shown) that does not allow independent rotation of the wafer relative to the indexer arm transfers wafers 1836 between stations (in Figures 18 to 21 , movement between stations is represented by large arrows between stations, while small radius arrows between stations represent rotation of the wafer relative to the indexer arm supporting it between processing stages at different stations, or lack of such rotation if represented by circle-bar notation). Thus, regardless of which station a wafer is currently located at or will be moved to, the wafer will generally reside at approximately the same radial orientation, e.g., with the same side (e.g., the arcuate edge between points A and B on each wafer) closest to the center of rotation of the indexer. As a result, misalignment between the center of the wafer and the center of the pedestal (as shown exaggerated for ease of viewing) can result in wafer non-uniformity such as Fig.18 As shown in the diagram.

[0115] Fig.19Chamber 1802 is shown in an indexed, rotate-in-place mode, wherein wafers 1836 have been provided to transfer pedestals so that the center of each wafer is perfectly or nearly perfectly centered on the rotation axis of the wafer support of an indexer arm used to transfer the wafer to a pedestal in a multi-station chamber, for example, using appropriate wafer support deviations; and further, so that the pedestal center and the rotation axis of the wafer support are perfectly or nearly perfectly positioned so that the rotation axes of all wafer supports are simultaneously aligned with the center of the corresponding pedestal in a horizontal plane. Thus, no matter which pedestal the wafer is moved to, the center of each wafer can be substantially perfectly aligned with the center of each pedestal. This situation may occur, for example, when the pedestal deviations and the wafer support deviations happen to be the same or nearly the same. As shown in FIG. Fig.19 As shown in the bottom graph, this results in extremely uniform circumferential wafer thickness, in this case due to each wafer being perfectly or nearly perfectly centered on each pedestal during each stage of processing. Furthermore, any small non-uniformities that may arise are averaged across all four quadrants of each wafer as each wafer moves from one station to the next and rotates relative to the indexer arm between each processing stage.

[0116] Fig. 20 The index rotation mode is shown as being more likely to occur, where each wafer is presented to the transfer pedestal using the wafer support offset for the selected indexer arm so that the center of each wafer is aligned with the rotation axis of the respective wafer support, but the rotation axis of the wafer support may not be perfectly aligned with the center of the pedestal. This can occur due to factors such as the fact that the indexer arm and the multi-station chamber may experience different amounts of thermal expansion, making it impossible to achieve perfect alignment. Fig.19 Thus, between each processing stage, each wafer can be rotated relative to the indexer arm by the indexer's in-situ rotation mechanism, which can have the effect of averaging out any pedestal-related non-uniformities without causing the center of the wafer to "wander" relative to the axis of rotation of the wafer support selected for that wafer from its original position relative to the axis of rotation. The result, as seen in the lower left corner of the illustration, is not as good as Fig.19 The ideal situation is uniform, but still better than Fig.18 The traditional translocation pattern is greatly improved.

[0117] Fig.21 Chamber 1802 is shown in indexed rotation mode, where the wafer is not subject to wafer support deviation before being provided to the transfer pedestal. Therefore, the center of the wafer is not aligned with the rotation axis of the wafer support selected for that wafer, which causes the wafer to "wander" from its starting position to any position relative to the rotation axis each time it is transferred from one station to the next. This causes wafer uniformity to be poor compared to Fig. 20 The observed non-uniformity is very obvious. Fig. 20The benefits of the above techniques were confirmed.

[0118] It will be appreciated that the above techniques may be implemented in a manner such that the use of pedestal and / or wafer support deviations is not immediately apparent. For example, while the above discussion has focused on applying pedestal or wafer support deviations to a common "origin" (which "origin" may be used as a reference frame for each wafer placement, which is then adjusted using appropriate end effector deviations in conjunction with appropriate pedestal or wafer support deviations to properly position the wafer in preparation for transfer to a particular pedestal or indexer wafer support), such as a calibration wafer center point (determined by the AWC system) used in teaching a wafer handling robot, the above techniques may also be implemented in a manner such as using multiple pedestal-specific or wafer support-specific origins / reference frames and selecting the appropriate such origins or reference frames for use in determining a particular wafer placement. It will be appreciated, however, that such techniques are still essentially the concept of using pedestal and / or wafer support deviations. Each such pedestal-specific or wafer-support-specific origin / reference frame will deviate to some degree from a common reference frame (e.g., a point in a coordinate system fixed in space relative to the multistation chamber); this deviation may correspond to a pedestal deviation or wafer-support deviation, depending on the nature of the origin / reference frame in question. Thus, the values ​​stored for a particular pedestal- or wafer-support-specific origin / reference frame that can be looked up and used to guide each wafer placement actually already have the corresponding pedestal deviation or wafer-support deviation applied. Thus, any wafer placement based on such a pedestal-specific or wafer-support-specific origin / reference frame is also essentially based on the appropriate corresponding pedestal deviation or wafer-support deviation.

[0119] It should also be understood that the various techniques discussed herein generally involve determining wafer position and various other position information relative to a reference frame located outside the multi-station room (such as a reference frame based on an AWC system), and then actually translating such position information through the movement of the wafer handling robot, the wafer handling robot can be very accurately controlled to cause it to perform the same translation operation for each wafer placement (although it may be modified based on various applicable biases). For example, if the default translation operation performed by the wafer handling robot causes a +400mm translation along the horizontal Y axis but no translation along the horizontal X axis relative to a reference point fixed to the end effector of the wafer handling robot when providing a wafer to the transfer pedestal, the wafer handling robot will perform such translation with each wafer placement operation without using end effector bias, pedestal bias, wafer support bias, or other biases. However, if it is determined that an end effector deviation of -2 mm in the X direction and +3 mm in the Y direction is required coupled with a base deviation of +1 mm in the X direction and -2 mm in the Y direction, the wafer handling robot may perform three discrete (X, Y) translation operations, such as (0 mm, 400 mm), then (-2 mm, 3 mm), then (1 mm, -2 mm) (although any order of such translations may be used, the end result is the same). Alternatively, a new displacement vector may be calculated and used, the new displacement vector being the sum of such displacements, such as (1 mm, 401 mm). Generally speaking, the coordinates determined by the AWC system or determined based on such coordinates need to be converted to corresponding positions in the multi-station chamber associated with the transfer base to properly place the wafer in the multi-station chamber.

[0120] The selection of the particular initial reference frame used is somewhat arbitrary, and in the example described above, the reference frame was established based on data points obtained during the wafer handling teaching operation, but it will be understood that any number of reference frames may be used so long as they are fixed relative to the system used to obtain measurements of the horizontal position of the center of the wafer during the calibration operation and the actual wafer loading operation in preparation for processing.

[0121] A semiconductor processing tool including a multi-station chamber (as discussed herein) may include a controller that may include one or more processors and one or more memory devices operably connected to each other and that may be configured to control various operational aspects of the semiconductor processing tool, including, for example, movement of a wafer handling robot, operation of an AWC system to obtain measurement points from a wafer passing through the AWC system, operation of lift pins, indexers, and other equipment (e.g., torsion pads, rotatable wafer supports on indexers) that may be located in each multi-station chamber, and the like. Such a controller may, for example, store in one or more memory devices a plurality of computer executable instructions to control the one or more processors to perform any of the techniques discussed herein, including, for example, causing semiconductor processing work to be processed in a multi-station chamber in any of the operating modes discussed herein, and also selecting appropriate pedestal deviations or wafer support deviations for a given wafer placement depending on the selected operating mode. Such a controller may also be configured with computer executable instructions for controlling the one or more processors to perform some or all of the correction processes discussed herein that may be used to determine pedestal deviations and / or wafer support deviations in certain circumstances.

[0122] For example, in determining wafer support deflection, the controller may be configured to reference Figure 8 All operations discussed, therefore, may be performed using data from the AWC system and the positioning sensors of the indexer arm and wafer handling robot and the technology may not benefit from the use of any external equipment. Figure 5 In the case of determining the base deviation by the technique of Figure 5 pedestal deviation to be determined. For example, to obtain wafer uniformity measurements with sufficient resolution to estimate the appropriate pedestal deviation to be determined, a measuring instrument may be required that is not normally included as a standard equipment component in such tools due to cost. In this case, the measuring instrument may be a separate component of the equipment that can be moved from tool to tool or located in the laboratory for separate evaluation of wafer uniformity. Data from the uniformity measurement may be fed directly to the controller so that the controller can then determine the relevant pedestal deviation, or the pedestal deviation may be determined elsewhere, for example by a measuring tool or other computing device that has access to the obtained uniformity data. In such cases, after obtaining such information, the controller may simply receive information indicating the expected pedestal deviation.

[0123] It should also be further understood that the techniques discussed herein for a multi-station chamber may also be applied to a tool containing multiple multi-station chambers. Fig. 22 An example of a semiconductor processing tool having multiple multi-station chambers is shown. Fig. 22, a semiconductor processing tool is shown including four multi-station chambers 2202, each of which has four stations / pedestals (pedestals not shown, but which may be similar to other pedestals shown herein) disposed around an indexer 2214. One of the pedestals / stations in each chamber 2202 may be designated as a transfer pedestal / transfer station, which may be configured to receive a wafer from or provide a wafer to a wafer handling robot having a robot arm 2248 and an end effector 2250 and located in a transfer chamber 2270, which is connected to each chamber 2202 in a manner such that a wafer can enter each chamber 2202 through an opening in each chamber 2202. Each chamber 2202 may have an AWC system 2242, which may be used by a controller 2264 to obtain wafer center measurements as the wafer passes through the AWC system 2242. The controller 2264 may have one or more processors 2266 and one or more memory devices 2268 as discussed above, which may be operably connected to each other and to the various equipment components discussed above. In this implementation, there may also be multiple robotic arms to provide wafers to multiple transfer bases at one time.

[0124] As described above, the controller may be part of a system that may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more pedestals for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronic devices for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronic device may be referred to as a "controller" that can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the controller may be programmed to control any of the processes disclosed herein, as well as various parameters that affect semiconductor processing, such as the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0125] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various individual settings (or program files) that define operating parameters for performing specific processing on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0126] In some implementations, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or may be all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a processing recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., processing and control as described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits remotely (e.g., at a base level or as part of a remote computer), which combine to control processing on the chamber.

[0127] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0128] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0129] As used herein, the term "wafer" may refer to a semiconductor wafer or substrate, or other similar types of wafers or substrates.

[0130] It should also be understood that the use of sequential indicators, such as (a), (b), (c), etc., herein is for organizational purposes only and is not intended to convey any particular order or importance of the items associated with each sequential indicator. For example, "(a) obtaining information related to a vector; and (b) obtaining information related to a position" should include obtaining information related to a position before obtaining information related to a vector, obtaining information related to a vector before obtaining information related to a position, and obtaining information related to a position while obtaining information related to a vector. However, there may be certain situations in which certain items associated with sequential indicators may require a specific order in nature, such as "(a) obtaining information related to a velocity; (b) determining a first acceleration based on the information related to the velocity; and (c) obtaining information related to a position"; in this example, (a) must be performed before (b) because (b) depends on the information obtained in (a), but (c) may be performed before or after either (a) or (b).

[0131] Various modifications to the implementations depicted in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the implementations shown herein, but rather to the widest scope consistent with this disclosure, the principles and novel features disclosed herein.

[0132] Certain features described in this specification in the context of separate implementations may be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may be implemented separately in multiple implementations or in any suitable subcombination. Furthermore, while the features described above may be implemented in a particular combination and even in an initially claimed manner, one or more features from a claimed combination may in some cases be implemented apart from that combination, and the claimed combination may be a subcombination or a variation of a subcombination.

[0133] Similarly, although the operations in the diagram are presented in a specific order, this should not be understood as such operations must be implemented in the specific order shown or all the operations shown must be implemented to achieve the desired result. In addition, the accompanying drawings can schematically show one or more exemplary processes in the form of a flow chart. However, other operations not shown can be included in the schematically shown exemplary processes. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the operations shown. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-mentioned implementation scheme should not be understood as requiring such separation in all implementation schemes, and should be understood as that the program components and system can be generally integrated in a single software product or packaged in multiple software products. In addition, other implementation schemes fall within the scope of the following claims. In some cases, the actions described in the claims can be implemented in different orders and still obtain the desired results.

Claims

1. A semiconductor processing device comprising: a first chamber having an indexer and N pedestals arranged in a circular array centered about a rotation axis of the indexer, wherein one of the N pedestals of the first chamber is a transfer pedestal, each pedestal of the first chamber is configured to support a wafer, N is an integer greater than 1, the first chamber includes an active wafer centering system associated with the transfer pedestal, and the first chamber is a multi-station semiconductor processing chamber; a wafer handling robot having a robotic arm configured to provide a single wafer to the transfer pedestal of the first chamber; as well as A controller comprising one or more processors and one or more memory devices, wherein: The one or more processors, the one or more memory devices, the wafer handling robot, the indexer of the first chamber, and the active wafer centering system of the first chamber are operably connected to each other, and The one or more memory devices store computer executable instructions for controlling the one or more processors to: a) selecting one of the N susceptors of the first chamber as a destination susceptor of the first chamber for a first wafer; b) selecting a first pedestal deviation associated with the destination pedestal of the first chamber from a set of N pedestal deviations of the first chamber, each pedestal deviation of the set of N pedestals of the first chamber being associated with a different pedestal of the N pedestals of the first chamber; c) obtaining information representing the horizontal position of the center of the first wafer from the active wafer centering system of the first chamber while the first wafer is on the robot arm; d) determining a first end effector deviation associated with the first wafer based at least in part on the information representative of the horizontal position of the center of the first wafer obtained from the active wafer centering system of the first chamber; e) enabling the robot arm to provide the first wafer to the transfer base of the first chamber based on the first base deviation and the first end effector deviation; f) causing the indexer of the first chamber to move the first wafer from the transfer pedestal of the first chamber to the destination pedestal of the first chamber; and g) causing the first chamber to perform one or more semiconductor processing operations on the first wafer on the destination pedestal in the first chamber.

2. The apparatus according to claim 1, wherein: The transfer base of the first chamber is the destination base of the first chamber, and The one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to cause the first chamber to process the first wafer while the first wafer is on the destination pedestal of the first chamber.

3. The apparatus of claim 1 , wherein the one or more memory devices store additional computer executable instructions for further controlling the one or more processors to: performing (a) to (e) for each of N wafers, wherein a different one of the N pedestals of the first chamber is selected as the destination pedestal of the first chamber for each of the N wafers; causing the indexer of the first chamber to move each of first to M-th wafers of the N wafers to the destination pedestal of the first chamber selected for each of the first to M-th wafers, wherein M=N-1, and the transfer pedestal of the first chamber is the destination pedestal of the first chamber for the N-th wafer; and The first chamber is caused to perform one or more semiconductor processing operations on the N wafers while each of the N wafers is supported by a corresponding destination susceptor of the first chamber.

4. The apparatus of claim 1 , wherein the one or more memory devices store additional computer executable instructions for further controlling the one or more processors to: f) selecting one of the N pedestals of the first chamber as a destination calibration pedestal of the first chamber for a first calibration wafer; g) obtaining information from the active wafer centering system representing the horizontal position of the center of the first correction wafer; h) causing the robot arm to provide the first calibration wafer to the transfer base of the first chamber; i) subjecting the first chamber to a calibration process, the calibration process comprising performing one or more semiconductor processing operations on the first calibration wafer; and j) obtaining a preliminary susceptor deviation for the destination calibration susceptor of the first chamber based at least in part on information representing non-uniformity of the first calibration wafer resulting from the calibration process performed in (i) and the horizontal position of the center of the first calibration wafer.

5. The apparatus of claim 4 , wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: between performing (h) and (i), cause the indexer of the first chamber to move the first correction wafer from the transfer pedestal of the first chamber to the destination correction pedestal of the first chamber.

6. The apparatus of claim 4, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to perform the following operations: using the preliminary pedestal deviation as a pedestal deviation for the destination correction pedestal of the first chamber.

7. The apparatus of claim 4, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: k) obtaining information indicative of the horizontal position of the center of a second calibration wafer from the active wafer centering system associated with the transfer pedestal of the first chamber; l) enabling the robot arm to provide the second calibration wafer to the transfer base of the first chamber; m) causing the first chamber to perform the calibration process on the second calibration wafer; and n) determining a susceptor deviation for the destination correction susceptor based at least in part on information representing the non-uniformity of the second correction wafer, the information representing the non-uniformity of the first correction wafer, the horizontal position of the center of the first correction wafer, and the horizontal position of the center of the second correction wafer.

8. The apparatus of claim 1 , wherein one of the N pedestals of the first chamber is a second transfer pedestal, the first chamber includes a second active wafer centering system associated with the second transfer pedestal, the wafer handling robot has an additional robotic arm configured to provide a single wafer to the second transfer pedestal of the first chamber; and the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: f) selecting one of the N susceptors of the first chamber as a destination susceptor of the first chamber for an additional wafer; g) selecting a corresponding pedestal offset associated with the destination pedestal of the first chamber from N second pedestal offsets of the first chamber, each pedestal offset of the first chamber being associated with a different pedestal of the N pedestals of the first chamber; h) obtaining information from the second active wafer centering system of the first chamber indicative of the horizontal position of the center of the additional wafer; i) determining a second end effector deviation associated with the additional wafer based at least in part on the information representative of the horizontal position of the center of the additional wafer obtained from the second active wafer centering system of the first chamber; and j) causing the additional robot arm to provide the additional wafer to the second transfer pedestal of the first chamber based on the pedestal deviation and the second end effector deviation.

9. The apparatus of claim 1, further comprising: a second chamber having an indexer and R pedestals in a circular array centered about a rotation axis of the indexer, wherein one of the R pedestals of the second chamber is a transfer pedestal of the second chamber, each pedestal of the second chamber is configured to support a wafer, R is an integer greater than 1, the second chamber includes an active wafer centering system associated with the transfer pedestal of the second chamber, and the second chamber is a multi-station semiconductor processing chamber; The one or more processors, the one or more memory devices, the wafer handling robot, the indexer of the second chamber, and the active wafer centering system of the second chamber are operably connected to each other, and The one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: f) selecting one of the R susceptors of the second chamber as a destination susceptor of the second chamber for an additional wafer; g) selecting a corresponding second pedestal deviation associated with the destination pedestal of the second chamber from a set of R second pedestal deviations of the second chamber, each second pedestal deviation of the second chamber being associated with a different pedestal of the R pedestals of the second chamber; h) obtaining information from the active wafer centering system of the second chamber indicative of the horizontal position of the center of the additional wafer; i) determining a second end effector deviation associated with the additional wafer based at least in part on the information representative of the horizontal position of the center of the additional wafer obtained from the active wafer centering system of the second chamber; and j) causing the robot arm to provide the additional wafer to the transfer pedestal of the second chamber based on the second pedestal deviation and the second end effector deviation.

10. The apparatus of claim 1, wherein: The indexer arm comprises a plurality of indexer arms, Each indexer arm is connected at one end to the central hub of the indexer and has a wafer support at the other end, the wafer support being configured to rotate relative to the indexer about a corresponding rotation axis, and The one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: f) selecting a wafer support from the plurality of wafer supports supported by the indexer arm as a destination wafer support of the first chamber for a second wafer; g) selecting a first wafer support deviation associated with the destination wafer support of the first chamber from a set of N wafer support deviations, each wafer support deviation being associated with a different wafer support of the plurality of wafer supports; h) obtaining information indicative of the horizontal position of the center of the second wafer from the active wafer centering system of the first chamber; i) determining a first end effector deviation associated with the second wafer based at least in part on the information representative of the horizontal position of the center of the second wafer obtained from the active wafer centering system of the first chamber; as well as j) causing the wafer handling robot to provide the second wafer to the transfer pedestal of the first chamber based at least in part on the first wafer support deviation and the first end effector deviation.

11. The apparatus of any one of claims 1-10, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: obtaining a pedestal deviation associated with a pedestal of the first chamber; and The pedestal deviations associated with the pedestals of the first chamber are stored in a data structure associating each pedestal deviation with a corresponding pedestal of the N pedestals of the first chamber.

12. The apparatus according to any one of claims 1-10, wherein N is equal to 4.

13. The apparatus of any one of claims 1-10, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: determining processing conditions for the chamber, and (b) is performed by selecting the first pedestal deviation associated with the destination pedestal of the first chamber from a group of N pedestal deviations of the first chamber associated with the process condition, wherein there are multiple groups of N pedestal deviations for the first chamber, each group being associated with a different process condition.

14. A semiconductor processing apparatus comprising: A first chamber having an indexer and N pedestals arranged in a circular array centered on a rotation axis of the indexer, wherein one of the N pedestals of the first chamber is a transfer pedestal, each pedestal of the first chamber is configured to support a wafer, N is an integer greater than 1, the first chamber includes an active wafer centering system associated with the transfer pedestal, the first chamber is a multi-station semiconductor processing chamber, and the indexer has N indexer arms, each indexer arm having: i) a proximal end connected to a central hub, the central hub configured to rotate about a first axis; and ii) a distal end supporting a wafer support configured to rotate relative to the indexer arm about a corresponding second axis; a wafer handling robot having a robotic arm configured to provide a single wafer to the transfer pedestal of the first chamber; as well as A controller comprising one or more processors and one or more memory devices, wherein: The one or more processors, the one or more memory devices, the wafer handling robot, the indexer of the first chamber, and the active wafer centering system of the first chamber are operably connected to each other, and The one or more memory devices store computer executable instructions for controlling the one or more processors to: a) selecting a wafer support from the plurality of wafer supports supported by the indexer arm as a destination wafer support of the first chamber for a first wafer; b) selecting a first wafer support deviation associated with the destination wafer support of the first chamber from a set of N wafer support deviations, each wafer support deviation being associated with a different wafer support of the plurality of wafer supports; c) obtaining information indicative of the horizontal position of the center of the first wafer from the active wafer centering system of the first chamber; d) determining a first end effector deviation associated with the first wafer based at least in part on the information representative of the horizontal position of the center of the first wafer obtained from the active wafer centering system of the first chamber; as well as e) causing the wafer handling robot to provide the first wafer to the transfer pedestal of the first chamber based at least in part on the first wafer support deviation and the first end effector deviation.

15. The apparatus of claim 14, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: f) after (e), rotating the indexer to align the corresponding second axis of the destination wafer support with the center of the first wafer; g) placing the first wafer onto the destination wafer support, wherein a center of the first wafer is aligned with the second axis of the destination wafer support; h) after (g), rotating the indexer to move the first wafer from a station of the first chamber having the transfer pedestal to another station of the first chamber having a pedestal that is not the transfer pedestal; i) causing the first wafer to be placed on the susceptor of the other station; j) between (g) and (i), rotating the wafer support for the first wafer about the corresponding second axis relative to the indexer arm supporting the wafer support; and k) causing the first chamber to perform one or more semiconductor processing operations on the first wafer while the first wafer is positioned on the susceptor of the other station.

16. The apparatus of claim 14, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to perform the following operations for each of the second through Nth wafers: f) selecting a wafer support from a plurality of said wafer supports supported by said indexer arm as a destination wafer support of said first chamber for said wafer; g) selecting, from said set of N wafer support deviations, a corresponding wafer support deviation associated with said destination wafer support of said first chamber for said wafer; h) obtaining information indicative of the horizontal position of the center of the wafer from the active wafer centering system of the first chamber; i) determining a corresponding end effector deviation for the wafer based at least in part on the information representative of the horizontal position of the center of the wafer obtained from the active wafer centering system of the first chamber; j) causing the wafer handling robot to provide the wafer to the transfer pedestal of the first chamber based at least in part on the corresponding wafer support deviation for the wafer and the corresponding end effector deviation for the wafer; k) after (j), rotating the indexer to align the corresponding second axis of the destination wafer support for the wafer with the center of the wafer; and 1) causing the wafer to be placed onto the destination wafer support for the wafer, wherein the center of the wafer is aligned with the second axis of the destination wafer support for the wafer.

17. The apparatus of claim 16, wherein: Each pedestal of the first chamber is associated with a corresponding station of the first chamber, and The one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: (m) after (l), causing the indexer to uniformly move each of the N wafers from the station of the first chamber where each of the N wafers was located before (m) to a station of the first chamber where another of the N wafers was located before (m); (n) causing each of the N wafers to be placed on the pedestal of the station into which the wafer was moved in (m); (o) between (l) and (n), causing the destination wafer support for each of the wafers to rotate the corresponding wafer about the second axis of the destination wafer support relative to the indexer arm supporting the destination wafer support; and (p) after (n), causing the first chamber to perform one or more operations on the N wafers.

18. The apparatus of claim 17, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: Repeat (l) to (p) one or more times.

19. The apparatus of claim 17, wherein the one or more memory devices store an additional plurality of computer executable instructions for further controlling the one or more processors to: Repeat (l) to (p) N times or more.

20. The apparatus of claim 14, wherein the one or more memory devices store an additional plurality of computer executable instructions for controlling the one or more processors to: f) selecting one of the N wafer supports as a destination calibration wafer support of the first chamber for a first calibration wafer; g) obtaining information from the active wafer centering system representing the horizontal position of the center of the first correction wafer; h) causing the robot arm to provide the first calibration wafer to the transfer base of the first chamber; i) rotating the indexer so that the destination calibration wafer support is located below the first calibration wafer; j) causing the first calibration wafer to be placed on the destination calibration wafer support; k) rotating the destination calibration wafer support and the first calibration wafer supported thereby by a first angular amount along a first direction about the corresponding second axis; l) causing the robot arm to retract the first calibration wafer from the first chamber; m) obtaining information from the active wafer centering system representing an updated horizontal position of the center of the first correction wafer; n) determining the wafer support deviation for the destination correction wafer support based at least in part on the horizontal position of the center of the first correction wafer, the updated horizontal position of the center of the first correction wafer, the first angular quantity, and the first direction; and o) storing the wafer support offset for the destination correction wafer support associated with the wafer support being the destination correction wafer support in a data structure.

21. An apparatus according to claim 20, wherein the one or more memory devices store an additional plurality of computer executable instructions for controlling the one or more processors to perform the following operations; repeating (f) to (o) N-1 times, wherein each repetition uses a different wafer support among the wafer supports as the destination correction wafer support.

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