Three-dimensional integrated structure and method of forming the same

Abstract

A semiconductor device is provided. The semiconductor device includes a first substrate layer having a first side on which a device is formed. In the semiconductor device, a first dielectric structure is formed over the first side of the first substrate layer in which the device is positioned. The first dielectric structure includes a bottom surface in contact with the first side of the first substrate layer. A portion of the bottom surface of the first dielectric structure is not covered by the first substrate layer. The semiconductor device further includes a first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned on the same side of the bottom surface of the first dielectric structure. The first electronic structure is bonded to the first dielectric structure.

Description

BACKGROUND

[0001] As critical dimensions of devices in integrated circuits are scaled to the limits of common memory cell technology, designers have been looking for techniques to stack multiple planes of memory cells to achieve greater storage capacity and to achieve lower cost-per-bit. 3D-NAND memory devices are exemplary devices that stack multiple planes of memory cells to achieve greater storage capacity and to achieve lower cost-per-bit. In an X-tacking architecture of a 3D-NAND memory device, peripheral circuits that handle data I / O as well as memory cell operations are handled on a separate wafer (CMOS wafer) using a logic technology node (i.e., 14 nm, 7 nm) that enables the desired I / O speed and functionality. Once processing of the cell array wafer is complete, the two wafers are electrically connected by millions of metal vertical interconnect channels (VIA) that are formed simultaneously across the entire wafer in one process step. By using an innovative cross-stacking architecture, the peripheral circuits are now above the cell array chip formed in the cell array wafer, which enables a much higher NAND bit density with a limited increase in total cost compared to a related 3D NAND. SUMMARY

[0002] The present disclosure describes embodiments generally related to structures and methods for three-dimensional monolithic integration (3D) of multiple functions into a functional block vertically stacked by one or more chips.

[0003] According to an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device can include a first substrate layer having a first side, a device formed over the first side. In the semiconductor device, a first dielectric structure can be formed over the first side of the first substrate layer in which the device is positioned. The first dielectric structure can include a bottom surface in contact with the first side of the first substrate layer. Further, a portion of the bottom surface of the first dielectric structure can not be covered by the first substrate layer. The semiconductor device can further include a first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned on a same side of the bottom surface of the first dielectric structure. The first electronic structure can be further bonded to the first dielectric structure.

[0004] In some embodiments, the first electronic structure can be bonded to the bottom surface of the first dielectric structure through a polycrystalline silicon layer by a laser annealing process, where the polycrystalline silicon layer can be positioned between the first electronic structure and the first dielectric structure and configured to act as a substrate layer for the first electronic structure.

[0005] In some embodiments, the first electronic structure can be formed from a portion of the first substrate layer.

[0006] In some embodiments, the device can include at least one of a field effect transistor, a diode, a bipolar junction transistor, a capacitor, a resistor, or an inductor.

[0007] In some embodiments, the device can include a memory cell. The memory cell can include a stack of alternating insulating layers and word lines positioned over a first side of a first substrate layer and arranged in a first dielectric structure. The memory cell can include a channel structure extending from the first side of the first substrate layer and extending through the insulating layers and the word lines. The memory cell can also include a word line contact positioned over the first side of the first substrate layer and extending from one of the word lines.

[0008] The semiconductor device can include a first contact structure extending from the first side of the first substrate layer and extending through the first dielectric structure. The semiconductor device can include a through-silicon via (TSV) formed in the first substrate layer, where the TSV can extend through the first substrate layer and contact the first contact structure. The semiconductor device can include a first metal line formed over a top surface of the first dielectric structure opposite the bottom surface. The first metal line can be coupled to one of the channel structure, the first contact structure, and the word line contact. Further, a pad structure can be positioned over the TSV and coupled to the TSV.

[0009] The semiconductor device can include a second dielectric structure formed over a first side of a second substrate layer, where the first side of the first substrate layer and the first side of the second substrate layer can face each other in alignment.

[0010] The semiconductor device can include a transistor formed in the first side of the second substrate layer and positioned in the second dielectric structure. The transistor can be configured to operate the memory cell. In the semiconductor device, a second metal line can be formed over the second dielectric structure and coupled to the first metal line such that the memory cell is coupled to the transistor.

[0011] The semiconductor device can include a source / drain (S / D) contact extending from an S / D region of the transistor, a gate contact extending from a gate structure of the transistor, and a second contact structure extending from the first side of the second substrate layer and extending through the second dielectric structure. The second metal line can be coupled to one of the S / D contact, the gate contact, and the second contact structure. The first metal line can be coupled to the second metal line through a bond via positioned between the first metal line and the second metal line.

[0012] In some embodiments, the first electronic structure can include one of a logic circuit, a memory circuit, and an analog circuit.

[0013] In some embodiments, the semiconductor device can include a second electronic structure positioned on uncovered portions of a bottom surface of the first dielectric structure and coupled to the first electronic structure, and a third electronic structure that can be coupled to the transistor through the first and second contact structures.

[0014] According to another aspect of the disclosure, a method for manufacturing a semiconductor device is provided. In the method, a device can be formed on a first side of a first substrate layer. A first dielectric structure can be formed on the first side of the first substrate layer such that the device is positioned in the first dielectric structure, where the first dielectric structure can include a bottom surface in contact with the first side of the first substrate layer. Further, a portion of the first substrate layer can be removed such that a portion of the bottom surface of the first dielectric structure is not covered by the first substrate layer. Subsequently, a first electronic structure can be bonded to the first dielectric structure, where the first electronic structure can be positioned on uncovered portions of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned on a same side of the bottom surface of the first dielectric structure.

[0015] In some embodiments, the first electronic structure can include one of a logic circuit, a memory circuit, and an analog circuit, and the device can include at least one of a field effect transistor, a diode, a bipolar junction transistor, a capacitor, a resistor, an inductor, or a memory cell.

[0016] In the method, to bond the first electronic structure, a polysilicon layer can be formed on the uncovered portions of the bottom surface of the first dielectric structure. The first electronic structure can be positioned on the polysilicon layer. Subsequently, an annealing process can be performed such that the polysilicon layer can connect the first electronic structure and the first dielectric structure and act as a substrate layer for the first electronic structure.

[0017] In some embodiments, the annealing process includes a laser annealing process. The laser process can have a laser energy greater than 0.1 J / cm 2 , a laser beam wavelength in a range from 350 nm to 650 nm, a process time per pulse in a range from 10 fs to 1 us. The laser process can be a continuous laser annealing process or a pulsed laser annealing process.

[0018] In some embodiments, the first electronic structure can be formed from a portion of the first substrate layer.

[0019] In some embodiments, forming the device can include forming a memory cell over the first side of the first substrate layer. The memory cell can include a stack of alternating insulating layers and word lines positioned over the first side of the first substrate layer and arranged in the first dielectric structure. The memory cell can also include a channel structure extending from the first side of the first substrate layer and extending through the insulating layers and the word lines. The memory cell can also include a word line contact positioned over the first side of the first substrate layer and extending from one of the word lines.

[0020] In the method, a first contact structure can be formed extending from the first side of the first substrate layer and extending through the first dielectric structure. A TSV can be formed in the first substrate layer, where the TSV can extend through the first substrate layer and contact the first contact structure. A first metal line can be formed over a top surface of the first dielectric structure opposite the bottom surface, where the first metal line can be coupled to one of the channel structure, the first contact structure, and the word line contact. Further, a pad structure can be formed over the TSV and coupled to the TSV.

[0021] In the method, a second dielectric structure can be formed over the first side of the second substrate layer, where the first side of the first substrate layer and the first side of the second substrate layer can face each other in alignment. A transistor can be formed in the first side of the second substrate layer. The transistor can be positioned in the second dielectric structure and configured to control the memory cell. A second metal line can be formed over the second dielectric structure. The second metal line can be coupled to the first metal line such that the memory cell is coupled to the transistor.

[0022] In the method, a source / drain (S / D) contact can be formed extending from an S / D region of the transistor. A gate contact can be formed extending from a gate structure of the transistor. A second contact structure can be formed extending from the first side of the second substrate layer and extending through the second dielectric structure. A second metal line can be coupled to one of the S / D contact, the gate contact, and the second contact structure. The first metal line can be coupled to the second metal line by a bond via. The bond via can be positioned between the first metal line and the second metal line.

[0023] In some embodiments, a second electronic structure can be formed over an uncovered portion of the bottom surface of the first dielectric structure and coupled to the first electronic structure, and a third electronic structure can be formed coupled to the transistor through the first contact structure and the second contact structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] Aspects of the disclosure can be understood more readily by reference to the following detailed description when taken in connection with the accompanying drawings. Note that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 is a perspective view of a 3D monolithic integrated structure in a related example according to example embodiments of the present disclosure.

[0026] Figure 2 is a cross-sectional view of a 3D integrated structure according to example embodiments of the present disclosure.

[0027] Figures 3-8 is a cross-sectional view of various intermediate steps of fabricating a 3D integrated structure according to example embodiments of the present disclosure.

[0028] Figure 9 is a flowchart of a process for fabricating a 3D integrated structure according to example embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forms in which a first feature is on or over a second feature in the following description can include embodiments in which the first and second features are in direct contact, and can also include embodiments in which additional features can be present between the first and second features such that the first and second features do not make direct contact. Furthermore, the present disclosure can refer to a number of references to a drawing in various examples. Such repetition is for simplicity and clarity and does not itself impose a relationship between the various embodiments and / or configurations discussed.

[0030] Also for ease of description, spatial terms such as "below," "under," "lower," "above," "upper" and the like can be used with respect to the illustrated orientation of an element or feature as shown in the figures. Unless otherwise specified, spatial terms are intended to encompass different orientations of the device in use or operation, such as by a mobile computer. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial terms used herein can be interpreted accordingly.

[0031] Three-dimensional monolithic integration (3D) integrates multiple functions into functional blocks vertically stacked by one or more chips. 3D monolithic integration can be the next important direction to break the bottleneck of Moore's Law in manufacturing faster, lower cost, and smaller chips. Currently, some technical difficulties include that the process temperature after metal interconnection manufacturing cannot be too high, and the requirements of wafer bonding alignment and high through-silicon via (TSV) density limit the application of 3D monolithic integration.

[0032] In 3D monolithic integration, a donor wafer cleaving process can be applied to stack two chips on top of each other. In this process, the top wafer (or top layer) can undergo a hydrogen implantation process, where hydrogen ions are implanted beneath a device layer disposed above the top wafer to form a cleavage surface. During a subsequent separation process, the cleavage surface can act as a guide for cleaving the top wafer. Furthermore, the top wafer can be flipped to bond with the bottom wafer (or bottom layer). A cleaving process (or separation process) such as annealing (e.g., at 400°C) or lateral mechanical force can be applied to remove a portion of the top wafer along the cleavage surface. Thus, the device layer and the remaining portion of the top wafer can be bonded to the bottom wafer. The donor wafer cleaving process requires high temperatures during the cleaving process, which can potentially affect the devices in the bottom wafer. Additionally, the TSV process introduced in subsequent steps has limitations in terms of connection density and number.

[0033] Figure 1 Another exemplary embodiment of 3D monolithic integration is shown, wherein a laser annealing process can be applied to form the 3D monolithic integrated structure 100. For example... Figure 1 As shown, the 3D monolithic integrated structure (or structure) 100 may include a bottom structure (or bottom layer) 102 and a top structure (or top layer) 104. The bottom structure 102 may include a plurality of FinFETs 106 on a substrate 101, a plurality of M1 layers 108 positioned on and coupled to the FinFETs 106, and a plurality of M2 layers 110 positioned on and coupled to the M1 layers 108. The top structure 104 may include a plurality of FinFETs 112 on the M2 layers 110, a plurality of M1 layers 114 positioned on and coupled to the FinFETs 112, and a plurality of M2 layers 116 positioned on and coupled to the M1 layers 114. To bond the bottom structure 102 and the top structure, an amorphous silicon (a-Si) layer can be formed between the interface 103 of the bottom structure 102 and the top structure 104. A laser annealing process can then be applied to the structure 100 by guiding a laser beam through it. The a-Si layer can be heated by the laser energy transmitted by the laser beam and thus transformed into polycrystalline silicon. The polycrystalline silicon can then bond (or glue) the bottom structure 102 and the top structure 104 to each other. Laser annealing offers a low-cost, high-volume bonding process, but it is generally suitable for integrating similar types of structures (or modules). For example, as... Figure 1 As shown, both the bottom structure 102 and the top structure 104 are logical structures.

[0034] In yet another exemplary embodiment of 3D monolithic integration, for example, several wafers (or dies) can be stacked and bonded together to form a stacked structure through bonding vias. However, such a stacked structure requires a complex design. In addition, spatial matching is difficult to unify, and spatial utilization is reduced.

[0035] In the present disclosure, a 3D integrated structure, such as an X-tacking structure, is provided to integrate different / multiple modules (or device structures) based on a laser annealing process. The X-tacking structure can apply a TSV-free architecture, thereby avoiding the challenges associated with the density and number of connection vias for TSVs. In addition, the X-tacking structure can also be compatible with the integration of multiple modules (or device chips, device structures) with different types, through which high spatial utilization efficiency can be obtained. The laser annealing process can also address the impact of high temperature on the reliability of metal interconnections. In addition, based on the design of the X-tacking structure, the X-tacking structure can be applied to bond one or more wafers.

[0036] Figure 2 An exemplary embodiment of the structure 200 is shown. In Figure 2 In an exemplary embodiment of the structure 200, the structure 200 can be an X-tacking structure that integrates a 3D-NAND memory device and one or more other electronic structures (or modules) 200C-200F to implement multiple functions. The one or more electronic structures 200C-200F can include various types of structures, such as a logic electronic structure (e.g., a logic chip, a logic module, or a logic circuit), a memory electronic structure (e.g., a memory, a memory chip, or a memory module), and / or an analog electronic structure (e.g., an analog chip, an analog module, or an analog circuit). The 3D-NAND memory device can include a structure 200A and a structure 200B, where the structure 200B is positioned above and bonded to the structure 200A. In Figure 2 In an embodiment of the structure 200, the structure 200A can be a CMOS structure (or CMOS module) 200A formed on a CMOS substrate (or CMOS wafer) 202, and the structure 200B can be a memory cell structure (or memory cell module) 200B formed on a cell substrate (cell substrate layer or cell wafer) 230.

[0037] Still referring to Figure 2The CMOS structure 200A can include a plurality of transistors (e.g., 204 and 206) formed in the first side 202a of the CMOS substrate 202 and positioned in the bottom dielectric structure 222. The plurality of transistors can be covered by the isolation layer 220 and spaced apart from each other by one or more shallow trench isolations (STIs) 208. The plurality of transistors can form a peripheral circuit configured to operate memory cells of a 3D-NAND memory device, such as processing data I / O and memory cell operations. In Figure 2 In example embodiments, for example, the transistor 204 can be an n-type transistor and the transistor 206 can be a p-type transistor. The transistor 204 can include a first source / drain (S / D) region 210 and a second S / D region 212 doped with n-type dopants and extending into the CMOS substrate 202 from the first side 202a. The first S / D region 210 and the second S / D region 212 can be further positioned in a p-type well 214. The transistor 204 can also include a gate structure 216 positioned over the first side 202a of the CMOS substrate 202 and arranged between the first and second S / D regions 210 and 212. Similarly, the transistor 206 can include a first S / D region 213 and a second S / D region 215 doped with p-type dopants and positioned in an n-type well 217, and a gate structure 211 positioned between the first and second S / D regions 213 and 215.

[0038] The CMOS structure 200A can include a plurality of S / D contacts (e.g., 218a, 218c) extending from the source / drain (S / D) regions (e.g., 210 and 212) of the plurality of transistors, a plurality of gate contacts (e.g., 218b and 218d) extending from the gate structures (e.g., 211 and 216) of the plurality of transistors, and a plurality of bottom contacts 226, such as shown by 226a and 226d, extending from the first side 202a of the CMOS substrate 202 and through the bottom dielectric structure 222. The CMOS structure 200A can further include a plurality of bottom metal lines 228, such as shown by 228a-228e, formed over the bottom dielectric structure 222 and coupled to the plurality of S / D contacts (e.g., 218a and 218c), the plurality of gate contacts (e.g., 218b and 218d), and the plurality of bottom contacts 226. The bottom metal lines 228 can be further disposed in a back end of line (BEOL) dielectric stack 224. The bottom metal lines 228 can include one or more metal layers (e.g., Ml layer and M2 layer) stacked over the bottom dielectric structure 222 and coupled to each other by a plurality of vias positioned between the one or more metal layers.

[0039] In Figure 2In embodiments, the S / D contacts, gate contacts, and bottom contacts can be made of conductive materials such as W, Co, Ru, etc. The bottom metal lines 228 can be made of Cu, Al, W, etc. The isolation layer 220 and the STI 208 can be made of dielectric materials such as SiO, SiN, etc. The bottom dielectric structure 222 can include one or more dielectric layers such as SiO, SiN, TEOS, BPSG, PSG, USG, etc.

[0040] The memory cell structure 200B can include a stack of alternating insulating layers 232 and word lines 234 positioned over the first side 230a of the cell substrate 230 in a stepped configuration and disposed in a top dielectric structure 242, a plurality of channel structures 236 extending from the first side 230a of the cell substrate 230 and extending through the insulating layers 232 and the word lines 234, and a plurality of word line contacts 240 positioned over the first side 230a of the cell substrate 230 and extending from the word lines 234. Additionally, one or more channel contacts 238 can be formed over the first side 230a of the cell substrate 230 and extending from the plurality of channel structures 236.

[0041] The top dielectric structure 242 can have a first surface (or bottom surface) 242a in contact with the first side 230a of the cell substrate 230, and a second surface (or top surface) 242b opposite the first surface 242a. A portion of the first surface 242a of the top dielectric structure 242 can be exposed or not covered by the cell substrate 230.

[0042] The memory cell structure 200B can further include a plurality of top contacts 241 (e.g., shown by 241a and 241b), and a plurality of TSVs 250. The plurality of top contacts 241 can extend from the first side 230a of the cell substrate 230 and extend through the top dielectric structure 242. The plurality of TSVs 250 can be formed in the cell substrate 230 and further extend through the cell substrate 230 and contact the plurality of top contacts (e.g., 241a). The memory cell structure 200B can include a plurality of top metal lines 246 formed over the second surface 242b of the top dielectric structure 242, e.g., shown by 246a-246d. The plurality of top metal lines 246 can be positioned in the BEOL dielectric layer 244 and coupled to the plurality of channel structures 236, the plurality of top contacts 241, the plurality of word line contacts 240, and the one or more channel contacts 238. Further, one or more pad structures 252 can be positioned over the plurality of TSVs 250 and coupled to the plurality of TSVs 250.

[0043] In some embodiments, the insulating layer 232 can be made of oxide and the word line 234 can be made of a conductive material such as W. The word line contact 240, the top contact 241 can be made of W, Co, Ru, etc. The top dielectric structure 242 can include one or more dielectric layers such as SiO, SiN, TEOS, BPSG, PSG, USG, etc. The plurality of top metal lines 246 can be made of Cu, Al, W, etc. The TSV 250 can be made of Cu, W, etc.

[0044] In the X-tacking structure 200, the CMOS structure 200A and the memory cell structure 200B can be coupled to each other to form a 3D-NAND memory device, where the memory cell structure 200B can include memory cells for data storage and the CMOS structure 200A can include peripheral circuits to handle data I / O as well as memory cell operations such as program, erase, and read. As Figure 2 illustrated, the CMOS structure 200A and the memory cell structure 200B can be coupled to each other through the plurality of top metal lines 246 and the plurality of bottom metal lines 228, where the plurality of top metal lines 246 and the plurality of bottom metal lines 228 can be in contact with each other through a plurality of bond vias (not shown) positioned between the plurality of top metal lines 246 and the plurality of bottom metal lines 228. The bond vias can include Cu, W, Al, Ti, TiN, etc.

[0045] The X-tacking structure 200 can further include a plurality of electronic structures such as electronic structures 200C-200F. As Figure 2 illustrated, a portion of the first surface 242a of the top dielectric structure 242 can not be covered by the cell substrate 230, and the electronic structures 200C-200E can be positioned on the uncovered portion of the first surface 242a of the top dielectric structure 242. The electronic structures 200C-200E can be further bonded to the top dielectric structure 242, for example, through a polysilicon layer 258, and spaced apart from each other by the isolation layer 248. To bond the electronic structures 200C-200E to the top dielectric structure 242, the polysilicon layer 258 can be formed on the uncovered portion of the first surface 242a of the top dielectric structure 242. The electronic structures 200C-200E can be positioned on the polysilicon layer 258, and a laser annealing process can be performed where a laser beam can be directed to the uncovered portion of the first surface 242a of the top dielectric structure 242. The polysilicon layer 258 can then be heated by the laser energy transmitted by the laser beam and thus bond (or glue) the electronic structures 200C-200E and the top dielectric structure 242 to each other. Note that the polysilicon layer 258 can also act as a substrate for the electronic structures 200C-200E.

[0046] In another example, the plurality of electronic structures can include one or more electronic structures formed from or based on a portion of the unit substrate 230 at the second side 230b of the unit substrate 230. For example, the electronic structure 200F can be formed based on a portion of the unit substrate 230 that is in contact with the plurality of channel structures 236.

[0047] The electronic structures 200C-200F can be logic electronic structures (e.g., logic chips, logic modules, or logic circuits), memory electronic structures (e.g., memories, memory chips, memory circuits, or memory modules), analog electronic structures (e.g., analog chips, analog modules, or analog circuits), etc. The electronic structures 200C-200F can provide a variety of functions. For example, a logic electronic structure can be a microcontroller unit (MCU) that can include one or more processing cores that can execute firmware to operate memory cells for reading, erasing, or programming. An analog electronic structure can include an analog sensor circuit that is part of a read circuit for reading data from memory cells. Thus, in the X-tacking structure 200, a variety of functions can be integrated by stacking a plurality of electronic structures (e.g., 200A-200F).

[0048] In some embodiments, one or more of the electronic structures 200C-200F can be part of a memory cell module of a 3D-NAND memory device. Thus, one or more of the electronic structures 200C-200F can also include a plurality of memory cells and work with the memory cell structure 200B for data storage. In some embodiments, one or more of the electronic structures 200C-200F can be part of a CMOS module of a 3D-NAND memory device configured to operate memory cells. Thus, one or more of the electronic structures 200C-200F can include a plurality of transistors such as high voltage transistors and work with the CMOS structure 200A to operate memory cells.

[0049] In some embodiments, a first electronic structure (e.g., 200C) and a second electronic structure (e.g., 200D) of the plurality of electronic structures can be coupled to each other through a package via (e.g., 254) and a package metal line (e.g., 256). In some embodiments, a third electronic structure (e.g., 200E) of the plurality of electronic structures can be coupled to one of the plurality of transistors in the CMOS structure 200A through or based on one of the plurality of top contacts (e.g., 241b) and one of the plurality of second contacts (e.g., 226d).

[0050] It should be noted that structure 200B is not limited to memory cell structures. Structure 200B can also include other electronic structures, such as logic electronic structures or analog electronic structures. Thus, structure 200B can include devices including field effect transistors, diodes, bipolar junction transistors, capacitors, resistors, inductors, etc., or combinations thereof. Structure 200B can also be a DRAM structure or other external circuitry. Similarly, structure 200A is not limited to CMOS structures. Structure 200A can be a DRAM structure, a NAND structure, or other external circuitry.

[0051] Further, Figure 2 are merely examples. Structure 200 is not limited to X-tacking structures. For example, structure 200 can include a peripheral portion under a core array (PUC) portion, where the peripheral portion is formed over a top surface of a substrate and the core array portion is formed over the peripheral portion. Further, electronic structures (e.g., 200C-200E) can be formed over the core array portion or disposed over an opposite bottom surface of the substrate. In another embodiment, structure 200 can include only structure 200B, over which multiple electronic structures (e.g., 200C-200F) can be positioned over uncovered portions of the first surface of the top dielectric structure. In yet another embodiment, structure 200 can include one or more substrates over which devices are formed, which can be stacked under structure 200A or over structure 200B.

[0052] Figures 3-8 Cross-sectional views showing various intermediate steps of fabricating an X-tacking structure are shown. As Figure 3 shown, a CMOS structure 200A can be formed. CMOS structure 200A can have a similar structure as CMOS structure 200A shown in FIG. 1. CMOS structure 200A can be formed over a substrate 202. CMOS structure 200A can include a plurality of CMOS devices 204 formed over substrate 202. CMOS devices 204 can include field effect transistors, diodes, bipolar junction transistors, capacitors, resistors, inductors, etc., or combinations thereof. CMOS structure 200A can also include a plurality of interconnects 206 formed over CMOS devices 204. Interconnects 206 can be formed of a conductive material, such as copper, tungsten, etc. CMOS structure 200A can also include a plurality of dielectric structures 208 formed over CMOS devices 204 and interconnects 206. Dielectric structures 208 can include one or more dielectric layers, such as silicon dioxide, silicon nitride, etc. Figure 2The memory cell structure 200B' can include a cell substrate 330 having a first side 330a and an opposing second side 330b. Similar to the memory cell structure 200B, the memory cell structure 200B' can include a stack of alternating insulating layers 232 and word lines 234 positioned over the first side 330a of the cell substrate 330 in a stepped configuration. A top dielectric structure 242 is formed over the first side 330a of the cell substrate 330 such that the insulating layers 232 and the word lines 234 are disposed in the top dielectric structure 242. A plurality of channel structures 236 extend from the first side 330a of the cell substrate 330 and extend through the insulating layers 232 and the word lines 234. A plurality of word line contacts 240 are positioned over the first side 330a of the cell substrate 330 and extend from the word lines 234. A plurality of top contacts 241 (e.g., shown by 241a and 241b) extend from the first side 330a of the cell substrate 330 and extend through the top dielectric structure 242. Further, a plurality of top metal lines 246 (e.g., shown by 246a-246d) can be formed over a second surface 242b of the top dielectric structure 242, where the plurality of top metal lines 246 can be coupled to the plurality of channel structures 236, the plurality of top contacts 241, and the plurality of word line contacts 240.

[0053] The CMOS structure 200A and the memory cell structure 200B' can be formed based on various semiconductor fabrication processes, which can include film deposition processes (e.g., chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, diffusion processes, atomic layer deposition (ALD) processes, and / or sputtering processes), etching processes (e.g., wet etching processes and / or dry etching processes), photolithography processes, chemical mechanical planarization (CMP) processes, metrology processes, defect detection processes, parameter measurement processes, and / or the like.

[0054] In Figure 4 The plurality of bonding vias (not shown) can be formed over the top metal lines 246 and / or the bottom metal lines 228 (e.g., 228a-228e). Subsequently, a thermal process can be applied to bond the top metal lines 246 with the bottom metal lines 228 through the bonding vias. Further, the cell substrate 330 can be thinned down from the second side 330b of the cell substrate 330. Thus, the cell substrate 330 can become a cell substrate 330' having a first side 330'a and an opposing second side 330' b. To thin down the cell substrate 330, a CMP process or a blanket etching process can be applied, which can remove a portion of the cell substrate 330 from the second side 330b.

[0055] In Figure 5In this process, a portion of the unit substrate 330' can be removed. Therefore, the unit substrate 330' becomes a unit substrate 230 or a unit substrate layer having a first side 230a and an opposing second side 230b. Furthermore, a portion of the first surface 242a of the top dielectric structure 242 is not covered by the unit substrate 230. A polysilicon layer 258 can be formed on the uncovered first surface 242a of the top dielectric structure 242. To form the polysilicon layer 258, various deposition processes can be applied, such as low-pressure CVD, PVD, sputtering, or ALD processes. To remove a portion of the unit substrate 330', a patterning process including photolithography and etching can be applied. The photolithography process can form a photoresist pattern covering a portion of the unit substrate 330', and subsequently, an etching process can be applied to remove the portion of the unit substrate 330' not covered by the photoresist pattern.

[0056] exist Figure 6 In this process, multiple electronic structures 200C-200E can be positioned on a polysilicon layer 258, where the polysilicon layer 258 can serve as a substrate for the electronic structures 200C-200E. Furthermore, an annealing process, such as laser annealing process 600, can be applied to the memory cell structure 200B'. Laser annealing process 600 directs a laser beam to the uncovered portion of the first surface 242a of the top dielectric structure 242. The polysilicon layer 258 can then be heated by the laser energy transmitted by the laser beam, thus bonding (or gluing) the electronic structures 200C-200E and the top dielectric structure 242 together.

[0057] In some embodiments, the laser annealing process may include a laser source capable of generating a laser beam with a wavelength ranging from 350 nm to 650 nm. For example, the laser source may generate a violet laser beam with a wavelength from 375 nm to 405 nm, a green laser beam with a wavelength from 520 nm to 532 nm, or a red laser beam with a wavelength from 635 nm to 650 nm. The laser beam may have a wavelength greater than 0.1 J / cm². 2 The laser energy. The laser process can be a continuous laser annealing process, in which a laser beam can be directed to the memory cell structure 200B' for a continuous duration. The laser process can also be a pulsed laser annealing process, in which a pulsed laser beam can be directed to the memory cell structure 200B', wherein each of the pulsed laser beams can have a duration from 10 fs to 1 μs.

[0058] It should be noted that one or more electronic structures may be formed from or based on a portion of the unit substrate 230 at the second side 230b of the unit substrate 230. For example, the electronic structure 200F may be formed based on a portion of the unit substrate 230 that is in contact with the channel structure 236.

[0059] The plurality of electronic structures can have internal connections in which two or more electronic structures can be connected to each other and external connections in which one or more electronic structures can be coupled to transistors in the CMOS structure 200A. For example, as shown, the electronic structure 200C and the electronic structure 200D can be coupled to each other through a package via (e.g., 254) and a package metal line (e.g., 256). In another example, the electronic structure 200E can be coupled to the CMOS structure 200A through a connection channel formed by the top contact 241b, the top metal line 246d, the bottom metal line 228e, and the bottom contact 226d. It is noted that in order to form the package via (e.g., 254) and the package metal line (e.g., 256), an isolation layer 248 can be formed on top of the electronic structures 200C-200D. A patterning process can be applied to form via openings and metal line openings, and a deposition process can be applied to fill the via openings and the metal line openings with a conductive material to form the package via (e.g., 254) and the package metal line (e.g., 256). Figure 7

[0060] In Figure 8 , a memory cell structure 200B can be formed in which a plurality of TSVs 250 can be formed in the cell substrate 230 and one or more pad structures 252 can be formed on top of and coupled to the plurality of TSVs 250. The plurality of TSVs 250 can extend through the cell substrate 230 and contact a plurality of top contacts (e.g., 241a). The pad structure 252 can be a test pad to which a probe box from a test tool can be applied. The pad structure 252 can also be a bond pad to which an external component (e.g., a package chip) can be interconnected.

[0061] The memory cell structure 200B and the CMOS structure 200A can form an X-tacking structure 200 that can be the same as the X-tacking structure 200 in Figure 2 . For example, Figure 8 The X-tacking structure 200 in

[0062] Figure 9 is a flowchart of an exemplary process 900 for fabricating a semiconductor device. The process 900 starts at S901 and then proceeds to S910. At S910, a device can be formed on a first side of a first substrate layer that includes a second side opposite the first side.​

[0063] In some embodiments, the plurality of electronic structures can include one of a logic circuit, a memory circuit, and an analog circuit, and the device can include at least one of a field effect transistor, a diode, a bipolar junction transistor, a capacitor, a resistor, an inductor, or a memory cell.

[0064] In some embodiments, forming the device can include forming a memory cell over the first side of the first substrate layer. The memory cell can include a stack of alternating insulating layers and word lines positioned over the first side of the first substrate layer and arranged in the first dielectric structure in a staircase configuration. The memory cell can also include a plurality of channel structures extending from the first side of the first substrate layer and extending through the insulating layers and the word lines. The memory cell can also include a plurality of word line contacts positioned over the first side of the first substrate layer and extending from the word lines.

[0065] Process 900 then proceeds to S920. At S920, a first dielectric structure can be formed over the first side of the first substrate layer such that the device is positioned in the first dielectric structure, where the first dielectric structure can include a first surface in contact with the first side of the first substrate layer and a second surface opposite the first surface. In some embodiments, S910 and S920 can be performed as described with reference to Figure 3

[0066] At S930, a portion of the first substrate layer can be removed such that a portion of the first surface of the first dielectric structure is not covered by the first substrate layer. In some embodiments, the first substrate layer can be thinned down from the second side of the first substrate layer before the portion of the first substrate layer is removed such that the portion of the first surface of the first dielectric structure is not covered by the first substrate layer. In some embodiments, S930 can be performed as described with reference to Figure 4 and Figure 5

[0067] Process 900 can then proceed to S940, where a plurality of electronic structures can be subsequently bonded to the first dielectric structure. The plurality of electronic structures can be positioned over the uncovered portion of the first surface of the first dielectric structure and spaced apart from each other. In some embodiments, S940 can be performed as described with reference to Figure 6

[0068] In process 900, to bond the plurality of electronic structures, a polysilicon layer can be formed over the uncovered portion of the first surface of the first dielectric structure. The plurality of electronic structures can be positioned over the polysilicon layer. An annealing process can be subsequently performed such that the polysilicon layer can connect the plurality of electronic structures and the first dielectric structure and act as a substrate layer for the plurality of electronic structures.

[0069] ​​​In some embodiments, the annealing process includes a laser annealing process. The laser process can have a laser energy greater than 0.1 J / cm 2 , a laser beam wavelength in a range from 350 nm to 650 nm, a process time per pulse in a range from 10 fs to 1 us. The laser process can be a continuous laser annealing process or a pulsed laser annealing process.

[0070] In some embodiments, one of the plurality of electronic structures can be formed from a portion of the first substrate layer. Similarly, one of the plurality of electronic structures can be a logic circuit, a memory circuit, or an analog circuit.

[0071] In some embodiments, one or more of the plurality of electronic structures can be part of a peripheral circuit configured to operate a memory cell. Accordingly, one or more of the plurality of electronic structures can include a plurality of transistors, such as high voltage transistors of the peripheral circuit.

[0072] In process 900, as shown in Figure 8 , a plurality of first contact structures can be formed to extend from a first side of the first substrate layer and through the first dielectric structure. A plurality of TSVs can be formed in the first substrate layer, where the plurality of TSVs can extend through the first substrate layer and contact the plurality of first contact structures. A plurality of first metal lines can be formed over a second surface of the first dielectric structure, where the plurality of first metal lines can be coupled to the plurality of channel structures, the plurality of first contact structures, and the plurality of word line contacts. Further, one or more pad structures can be formed over the plurality of TSVs and coupled to the plurality of TSVs.

[0073] In process 900, as shown in Figure 3 , a second dielectric structure can be formed over a first side of a second substrate layer, where the first side of the first substrate layer and the first side of the second substrate layer can be aligned facing each other. A plurality of transistors can be formed in the first side of the second substrate layer. The plurality of transistors can be positioned in the second dielectric structure and configured to control a memory cell. A plurality of second metal lines can be formed over the second dielectric structure. The plurality of second metal lines can be coupled to the plurality of first metal lines such that the memory cell is coupled to the plurality of transistors. In some embodiments, the plurality of transistors can form a peripheral circuit to operate the memory cell formed over the first side of the first substrate layer.

[0074] In process 900, as shown in Figure 3As shown, a plurality of S / D contacts can be formed extending from the S / D regions of the plurality of transistors. A plurality of gate contacts can be formed extending from the gate structures of the plurality of transistors. A plurality of second contact structures can be formed extending from the first side of the second substrate layer and through the second dielectric structure. A plurality of second metal lines can be coupled to the plurality of S / D contacts, the plurality of gate contacts, and the plurality of second contact structures. A plurality of first metal lines can be coupled to the plurality of second metal lines through a plurality of bonding vias. The plurality of bonding vias can be positioned between the plurality of first metal lines and the plurality of second metal lines.

[0075] In some embodiments, as shown, a first electronic structure and a third electronic structure of the plurality of electronic structures can be coupled to one another, and a fourth electronic structure of the plurality of electronic structures can be coupled to one of the plurality of transistors through one of the plurality of first contact structures and one of the plurality of second contact structures. Figure 8

[0076] It is noted that the process 900 is not limited to X-tacking structures. It can be applied to other structures, such as PUC structures. Further, one or more substrates can be positioned below the second substrate layer or above a first structure layer on which the devices are formed on the one or more substrates. The devices formed on the first substrate layer can also be DRAM structures or other external circuitry. Further, DRAM structures, NAND structures, or other external circuitry can also be formed on the first side of the second substrate layer.

[0077] It is noted that additional steps can be provided before, during, and after the process 900, and that some of the steps described can be replaced, eliminated, or executed in a different order for additional embodiments of the process 900. In subsequent process steps, various additional interconnect structures (e.g., metallization layers with conductive lines and / or VIAs) can be formed on the X-tacking structure (e.g., 200). Such interconnect structures electrically connect the X-tacking structure (e.g., 200) with other contact structures and / or active devices to form functional circuitry. Additional device features, such as passivation layers, input / output structures, etc., can also be formed.

[0078] ​The various embodiments described herein provide several advantages over related examples. The present disclosure provides an X-tacking structure that integrates different / multiple modules (or device structures) based on a laser annealing process. The X-tacking structure can apply a TSV-free architecture, which can address the density and number of connection vias associated with TSVs. The X-tacking structure can also be compatible with the integration of multiple modules (or device chips, device structures), which can achieve high spatial utilization efficiency. The laser annealing process can address the impact of high temperature on metal interconnection reliability. Moreover, based on the design of the X-tacking structure, the X-tacking structure can be applied to bond one or more wafers.

[0079] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device comprising: a first substrate layer having a first side, a device formed on the first side; a first dielectric structure formed on the first side of the first substrate layer in which the device is positioned, the first dielectric structure including a bottom surface in contact with the first side of the first substrate layer, a portion of the bottom surface of the first dielectric structure not covered by the first substrate layer; and a first electronic structure positioned on the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned on the same side of the bottom surface of the first dielectric structure, the first electronic structure further bonded to the first dielectric structure, wherein the first electronic structure includes one of a logic electronic structure, a memory electronic structure, and an analog electronic structure.

2. The semiconductor device according to claim 1, wherein The first electronic structure is bonded to the bottom surface of the first dielectric structure by a polysilicon layer positioned between the first electronic structure and the first dielectric structure.

3. The semiconductor device according to claim 1, further comprising a fourth electronic structure, wherein, The fourth electronic structure is formed from a portion of the first substrate layer.

4. The semiconductor device according to claim 1, wherein The device includes at least one of a field effect transistor, a diode, a bipolar junction transistor, a capacitor, a resistor, or an inductor.

5. The semiconductor device according to claim 1, wherein The device includes a memory cell, the memory cell further comprising: a stack of alternating insulating layers and word lines positioned on the first side of the first substrate layer in a staircase configuration and disposed in the first dielectric structure, a channel structure extending through the insulating layers and the word lines, and a word line contact positioned on the first side of the first substrate layer and extending from one of the word lines.

6. The semiconductor device of claim 5, further comprising: a first contact structure extending from the first side of the first substrate layer and through the first dielectric structure; a through silicon via (TSV) formed in the first substrate layer, the TSV extending through the first substrate layer and in contact with the first contact structure; a first metal line formed on the first side of the first substrate layer and disposed on a top surface of the first dielectric structure opposite the bottom surface, the first metal line coupled to one of the channel structure, the first contact structure, and the word line contact; and a pad structure positioned on and coupled to the TSV.

7. The semiconductor device of claim 6, further comprising: a second dielectric structure formed on a first side of a second substrate layer, the first side of the first substrate layer and the first side of the second substrate layer aligned; a transistor formed in the first side of the second substrate layer and positioned in the second dielectric structure; and a second metal line formed on the second dielectric structure and coupled to the first metal line such that the memory cell is coupled to the transistor.

8. The semiconductor device of claim 7, further comprising a source / drain (S / D) contact extending from an S / D region of the transistor; a gate contact extending from a gate structure of the transistor; and a second contact structure extending from the first side of the second substrate layer and through the second dielectric structure, wherein: the second metal line is coupled to one of the S / D contact, the gate contact, and the second contact structure, and the first metal line is coupled to the second metal line by a bond via positioned between the first metal line and the second metal line. The apparatus further includes a peripheral circuit.

9. The semiconductor device according to claim 5, wherein 10. The semiconductor apparatus of claim 8, further comprising: a second electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure and coupled to the first electronic structure, and a third electronic structure coupled to the transistor by the first contact structure and the second contact structure.

11. A method for fabricating a semiconductor apparatus, comprising: forming an apparatus over a first side of a first substrate layer; forming a first dielectric structure over the first side of the first substrate layer such that the apparatus is positioned in the first dielectric structure, the first dielectric structure including a bottom surface in contact with the first side of the first substrate layer; removing a portion of the first substrate layer such that a portion of the bottom surface of the first dielectric structure is uncovered by the first substrate layer; and bonding a first electronic structure to the first dielectric structure, the first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned on a same side of the bottom surface of the first dielectric structure, wherein the first electronic structure includes one of a logic electronic structure, a memory electronic structure, and an analog electronic structure. The apparatus includes at least one of a field effect transistor, a diode, a bipolar junction transistor, a capacitor, a resistor, an inductor, or a memory cell. Bonding the first electronic structure further includes:

12. The method of claim 11, wherein, forming a polysilicon layer over the uncovered portion of the bottom surface of the first dielectric structure; 13. The method of claim 11, wherein, positioning the first electronic structure over the polysilicon layer; and performing an anneal process to cause the polysilicon layer to connect the first electronic structure and the first dielectric structure and to act as a substrate layer for the first electronic structure. The anneal process includes a laser anneal process including: a laser beam wavelength in a range from 350 nm to 650 nm, 14. The method of claim 13, wherein, a process time per pulse in a range from 10 fs to 1 us, and greater than 0.1 J / cm 2 of laser energy, one of a continuous laser anneal process and a pulsed laser anneal process.

15. The method of claim 11, further comprising: forming a fourth electronic structure from a portion of the first substrate layer.

16. The method of claim 11, wherein: forming the apparatus further includes forming a memory cell over the first side of the first substrate layer, and the memory cell includes: a memory cell including a memory material positioned over the first side of the first substrate layer, and a second electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure and coupled to the first electronic structure, and a third electronic structure coupled to the transistor by the first contact structure and the second contact structure. a stack of alternating insulating layers and word lines positioned over the first side of the first substrate layer and disposed in the first dielectric structure, a channel structure extending from the first side of the first substrate layer and extending through the insulating layers and the word lines, and a word line contact positioned over the first side of the first substrate layer and extending from one of the word lines.

17. The method of claim 16, further comprising: forming a first contact structure extending from the first side of the first substrate layer and extending through the first dielectric structure; forming a through-silicon via (TSV) in the first substrate layer, the TSV extending through the first substrate layer and in contact with the first contact structure; forming a first metal line over the first side of the first substrate layer and disposed on a top surface of the first dielectric structure opposite the bottom surface, the first metal line coupled to one of the channel structure, the first contact structure, and the word line contact; and forming a pad structure positioned over and coupled to the TSV.

18. The method of claim 17, further comprising: forming a second dielectric structure over a first side of a second substrate layer, the first side of the first substrate layer and the first side of the second substrate layer aligned to face each other; forming a transistor in the first side of the second substrate layer, the transistor positioned in the second dielectric structure; and forming a second metal line over the second dielectric structure, the second metal line coupled to the first metal line to couple the memory cell to the transistor.

19. The method of claim 18, further comprising: forming a source / drain (S / D) contact extending from an S / D region of the transistor; forming a gate contact extending from a gate structure of the transistor; and forming a second contact structure extending from the first side of the second substrate layer and extending through the second dielectric structure, wherein: the second metal line is coupled to one of the S / D contact, the gate contact, and the second contact structure, and the first metal line is coupled to the second metal line by a bond via positioned between the first metal line and the second metal line.

20. The method of claim 19, further comprising: forming a second electronic structure over the uncovered portion of the bottom surface of the first dielectric structure, the second electronic structure coupled to the first electronic structure, and forming a third electronic structure over the uncovered portion of the bottom surface of the first dielectric structure, the third electronic structure coupled to the transistor through the first contact structure and the second contact structure. ​ ​ ​

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