Operation module, pipeline optimization method and related products

Abstract

The present application discloses a computing module, a pipeline optimization method and related products, which are applied to a combined processing device, which includes an electronic device, an interface device, other processing devices and a storage device, and the electronic device may include one or more computing devices, which can be configured to execute the pipeline optimization method. The use of the embodiments of the present application can save computing resources.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a computing module, a pipeline optimization method and related products. Background Art

[0002] In traditional processor design, a single pipeline is used to implement multiple computing functions in the same computing module. The pipeline generally has only one entrance and one exit, uses the same computing path, and transmits data and control signals between each pipeline stage in the pipeline through a handshake protocol. However, such a design will cause different types of computing instructions to pass through all pipeline stages. Even if no operation is performed in some pipeline stages, and only data and control information are transmitted as is, they still need to pass through all pipeline stages, resulting in computing delays and reduced computing efficiency. Summary of the invention

[0003] The embodiments of the present application provide a computing module, a pipeline optimization method and related products, which can reduce computing delays and improve computing efficiency.

[0004] In a first aspect, an embodiment of the present application provides a computing module, wherein the computing module includes K pipelines, P pipeline inlets, and Q pipeline outlets, wherein K, P, and Q are all integers greater than or equal to 2; each of the K pipelines includes a plurality of pipeline stages, and each pipeline stage corresponds to at least one computing circuit;

[0005] The operation module is used to configure the operation circuit, pipeline inlet and pipeline outlet according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation corresponding to the target instruction according to the target pipeline path.

[0006] In a second aspect, an embodiment of the present application further provides a pipeline optimization method, which is applied to a computing module, wherein the computing module includes K pipelines, P pipeline inlets, and Q pipeline outlets, wherein K, P, and Q are all integers greater than or equal to 2; each of the K pipelines includes a plurality of pipeline stages, and each pipeline stage corresponds to at least one computing circuit; the method includes:

[0007] Get target instructions;

[0008] According to the computing resources required by the target instruction, the operation circuit, the pipeline inlet and the pipeline outlet are configured to obtain a corresponding target pipeline path;

[0009] The operation corresponding to the target instruction is performed according to the target pipeline path.

[0010] In a third aspect, an embodiment of the present application further provides a neural network chip, which includes a computing module as described in any aspect of the first aspect, or is used to execute the method described in the second aspect.

[0011] In a fourth aspect, an embodiment of the present application further provides a board, the board comprising: a storage device, an interface device, a control device, and a neural network chip as described in the third aspect;

[0012] Wherein, the neural network chip is connected to the storage device, the control device and the interface device respectively;

[0013] The storage device is used to store data;

[0014] The interface device is used to realize data transmission between the chip and external equipment;

[0015] The control device is used to monitor the state of the chip.

[0016] In a fifth aspect, an embodiment of the present application further provides an electronic device, which includes a computing module as described in any one of the first aspect, or the electronic device is used to execute the method as described in the second aspect, or the electronic device includes a neural network chip as described in the third aspect, or the electronic device includes a board as described in the fourth aspect.

[0017] In a sixth aspect, an embodiment of the present application further provides a pipeline optimization device, which is applied to a computing module, wherein the computing module includes K pipelines, P pipeline inlets, and Q pipeline outlets, wherein K, P, and Q are integers greater than or equal to 2; each of the K pipelines includes a plurality of pipeline stages, and each pipeline stage corresponds to at least one computing circuit; the method includes: an acquisition unit, a configuration unit, and an execution unit, wherein:

[0018] The acquisition unit is used to acquire the target instruction;

[0019] The configuration unit is used to configure the operation circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction to obtain a corresponding target pipeline path;

[0020] The execution unit is used to execute the calculation operation corresponding to the target instruction according to the target pipeline path.

[0021] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps described in the second aspect of the embodiment of the present application.

[0022] In an eighth aspect, an embodiment of the present application provides a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute some or all of the steps described in the second aspect of the embodiment of the present application. The computer program product may be a software installation package.

[0023] The embodiments of the present application have the following beneficial effects:

[0024] It can be seen that in the operation module, pipeline optimization method and related products involved in the embodiments of the present application, the operation module includes K pipelines and P pipeline entrances and Q pipeline exits, K, P, Q are all integers greater than or equal to 2, each of the K pipelines includes multiple pipeline stages, and each pipeline stage corresponds to at least one operation circuit. The operation module is used to configure the operation circuit, pipeline entrance and pipeline exit according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation corresponding to the target instruction according to the target pipeline path. In this way, the pipeline can be flexibly configured according to the computing resources required by the instruction, so that the instruction can achieve the minimum computing delay and use the least computing resources to complete the calculation in the pipeline, thereby improving the computing efficiency.

[0025] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1A A schematic diagram of the structure of a computing module provided in an embodiment of the present application;

[0028] Figure 1B A schematic diagram showing a pipeline provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a flow chart of a flow optimization method provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0031] Figure 4This is a block diagram of the functional units of a flow optimization device provided in an embodiment of the present application;

[0032] Figure 5 It is a block diagram of the functional units of a combined processing device provided in an embodiment of the present application;

[0033] Figure 6 This is a block diagram of the functional units of a board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following are detailed descriptions of each.

[0035] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0036] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] Electronic devices may include various handheld devices with wireless communication functions, vehicle-mounted devices, wireless headsets, computing devices or other processing devices connected to wireless modems, as well as various forms of user equipment (UE), mobile stations (MS), terminal devices, etc. Electronic devices may be, for example, smart phones, tablet computers, headset boxes, etc. For the convenience of description, the above-mentioned devices are collectively referred to as electronic devices.

[0038] The above-mentioned electronic equipment can be applied to the following (including but not limited to) scenarios: various electronic products such as data processing, robots, computers, printers, scanners, telephones, tablets, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, etc.; various means of transportation such as airplanes, ships, and vehicles; various household appliances such as televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, range hoods, etc.; and various medical equipment including magnetic resonance imaging, B-ultrasound, electrocardiographs, etc.

[0039] In the embodiments of the present application, the computing module may be a processor, a neural network chip, a board, the above-mentioned electronic device, etc., and may also be applied to a virtual or physical device for implementing the method described in the embodiments of the present application, which is not limited here.

[0040] In the related art, a single pipeline operation unit in a CPU has the following disadvantages:

[0041] 1. There is only one entry and exit. Different types of operation instructions must pass through all pipeline stages, even if no operation is performed in some pipeline stages, but only data and control information are passed as is;

[0042] 2. Under the condition that there is only one control signal, if the data to be processed is a vector, the operation of each element will use the control signal, which will cause the control signal to be connected to each element, and the physical feasibility is poor;

[0043] 3. For different operation instructions, different registers are used to transfer data during the calculation process, and different basic operation units are used, and the operation resources and register resources are not integrated and reused.

[0044] The operation modules described in this application (such as Figure 1A As shown in the figure), the above defects can be solved, and the pipeline can be flexibly configured so that the instruction can achieve the minimum calculation delay and complete the calculation in the pipeline with the least computing resources. In addition, the register copy function can be realized, which disperses the driving pressure of the control signal and reduces the pressure of layout and wiring in physical implementation.

[0045] The following is a detailed introduction.

[0046] See also Figure 1A , Figure 1A : is a schematic diagram of an operation module provided in an embodiment of the present application, wherein the operation module includes K pipelines, P pipeline inlets, and Q pipeline outlets, wherein K, P, and Q are all integers greater than or equal to 2; each of the K pipelines includes a plurality of pipeline stages, and each pipeline stage corresponds to at least one operation circuit;

[0047] The operation module is used to configure the operation circuit, pipeline inlet and pipeline outlet according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation corresponding to the target instruction according to the target pipeline path.

[0048] Among them, the pipeline may include multiple pipeline stages, each pipeline stage may correspond to at least one operation circuit, the operation circuit may support operations of multiple data types, and the corresponding operation circuit is selected according to the instruction requirements to complete the corresponding operation, for example, the data type may be 16-bit fixed-point data or 32-bit floating-point data, etc. For example, if the instruction is matrix addition, an adder is selected; if the instruction is matrix multiplication, a multiplier and an adder are selected, the instruction is a 16-bit fixed-point operation instruction, and the instruction is received to perform a 16-bit fixed-point operation, etc. Specifically, the operation circuit may be an arithmetic logic circuit, and / or a logic operation circuit. The arithmetic logic circuit may be at least one of the following: a multiplier unit, an adder unit. The logic operation circuit may be at least one of the following: a combinational logic circuit, a sequential logic circuit, etc., which is not limited here. The combinational logic circuit is composed of the most basic logic gate circuits, for example, an adder, a decoder, an encoder, a data selector, etc. Sequential logic circuits are circuits composed of the most basic logic gate circuits plus feedback logic circuits (output to input) or devices, such as triggers, latches, counters, shift registers, memories, etc. The above computing resources can be understood as the operation circuits that need to be called.

[0049] The data processed by the pipeline may be at least one of the following: neuron data, weight data, and bias data. The data that the pipeline can process may be at least one of the following data types: fixed-point data, integer data, discrete data, continuous data, power data, and floating-point data. The length of the data representation may be 32-bit floating-point data, 16-bit fixed-point data, 16-bit floating-point data, 8-bit fixed-point data, 4-bit fixed-point data, and the like. The data may include at least one of the following: input neuron data, weight data, and bias data.

[0050] The target instruction may be a vector instruction, and the vector instruction may be at least one of the following: a vector addition instruction, a vector addition scalar instruction, a vector subtraction instruction, a vector multiplication instruction, a vector multiplication scalar instruction, a vector division instruction, a scalar division vector instruction, an inter-vector AND instruction, an intra-vector AND instruction, an inter-vector OR instruction, an intra-vector OR instruction, a vector exponent instruction, a vector logarithm instruction, a vector greater than determination instruction, a vector equal to determination instruction, a vector NOT instruction, a vector selection merge instruction, a vector maximum value instruction, a scalar extension instruction, a scalar replacement vector instruction, a vector replacement scalar instruction, a vector retrieval instruction, a vector dot product instruction, a random vector instruction, a circular shift instruction, a vector load instruction, a vector storage instruction, a vector transfer instruction, a matrix multiplication vector instruction, a vector multiplication matrix instruction, a matrix multiplication scalar instruction, a tensor operation instruction, a matrix addition instruction, a matrix subtraction instruction, a matrix retrieval instruction, a matrix load instruction, a matrix storage instruction, and a matrix transfer instruction.

[0051] The target instruction may be a single function instruction or a combined function instruction. A single function instruction may be used to implement a single function, and a combined function instruction may be used to implement several functions (combined functions). A single function instruction or a combined instruction may be executed using one or more pipelines.

[0052] In the embodiment of the present application, the operation module may include K pipelines, P pipeline inlets and Q pipeline outlets, K, P, and Q are all integers greater than or equal to 2, each of the K pipelines includes multiple pipeline stages, each pipeline stage corresponds to at least one operation circuit, and any pipeline may include a pipeline inlet, a pipeline outlet, and t intermediate pipeline stages, where t is a natural number. For example, Figure 1B As shown, the pipeline entrance, the intermediate pipeline stage 1, the intermediate pipeline stage 2 and the pipeline exit 2 can constitute a pipeline.

[0053] In the specific implementation, different computing resources are distributed in different pipeline stages of the pipeline. For example, the multiplier units are distributed in the 3rd and 4th pipeline stages, while the adder units are distributed in the 1st and 2nd pipeline stages. Different instructions require different computing resources to execute, and not all computing resources are necessarily used. At the same time, some instructions do not need to flow to the last pipeline stage to output the result. Therefore, the entrance and exit of the instruction into the pipeline can be flexibly configured according to the computing resource usage of the instruction. For example, a single multiplication instruction can enter from the 3rd pipeline stage, and output the result from the 4th stage after the calculations are completed at the 3rd and 4th stages; for another example, a single addition instruction can enter from the 5th pipeline stage, and output the result from the 6th stage after the calculations are completed at the 5th and 6th stages. The advantage of this is that all instructions can complete the calculation in the pipeline with minimal calculation delay and using the least computing resources.

[0054] In the embodiment of the present application, the operation module adopts the above-mentioned multi-input and multi-output multi-pipeline design strategy, which saves area while solving the physical feasibility problem. Taking two pipelines as an example, the instructions to be implemented by the module can be divided into two categories according to function, reusability and balance principles, and implemented in these two pipelines respectively.

[0055] In a possible example, the operation module is used to configure the operation circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation operation corresponding to the target instruction according to the target pipeline path, specifically:

[0056] A11, obtaining a target operation type corresponding to the target instruction;

[0057] A12, determining a target operation circuit, a target pipeline entry, and a target pipeline exit corresponding to the target operation type;

[0058] A13, determining a target pipeline path corresponding to the target operation type according to the target operation circuit, the target pipeline inlet and the target pipeline outlet;

[0059] A14. Execute the calculation operation corresponding to the target instruction according to the target pipeline path.

[0060] Among them, the operation module can obtain the target operation type corresponding to the target instruction. Since each operation type requires corresponding computing resources (operation circuits) to realize the corresponding instruction functions, the target functional circuit set required for the target operation type can be determined. The target functional circuit set may include at least one operation circuit. Each pipeline stage is pre-configured with a corresponding operation circuit. Then, the corresponding pipeline stage can be found according to the target functional circuit set. Since the execution order of the target instructions determines the pipeline order of the pipeline stage, and thus also determines the execution order of the functional circuits corresponding to the pipeline stage, the pipeline order corresponding to the target operation type is the target pipeline path. The operation module can perform the operation operation of the target instruction according to the functional circuit corresponding to the target pipeline path. In this way, pipeline path planning can be realized in combination with the operation type, and computing resources can be allocated on demand, which helps to improve computing efficiency.

[0061] In a possible example, the operation module is used to configure the operation circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation operation corresponding to the target instruction according to the target pipeline path, specifically:

[0062] A21, obtaining a target operation type corresponding to the target instruction;

[0063] A22, determining a target pipeline path corresponding to the target operation type according to a preset mapping relationship between the operation type and the pipeline path;

[0064] A23. Call the functional electrical path corresponding to the target pipeline to execute the corresponding calculation operation of the target instruction.

[0065] In a specific implementation, the operation module may pre-store a mapping relationship between a preset operation type and a pipeline path, or an electronic device using the operation module may pre-store a mapping relationship between a preset operation type and a pipeline path.

[0066] Specifically, the operation module can obtain the target operation type corresponding to the target instruction, and determine the target pipeline path corresponding to the target operation type according to the mapping relationship between the preset operation type and the pipeline path. The target pipeline path can include multiple pipeline stages, and each pipeline stage corresponds to a corresponding functional circuit. Then, the functional electrical path corresponding to the target pipeline can be called to execute the corresponding operation of the target instruction. In this way, pipeline path planning can be implemented in combination with the operation type, and computing resources can be allocated on demand, which helps to improve computing efficiency.

[0067] In a possible example, when the target pipeline path corresponds to multiple pipelines, the multiple pipelines connect the pipeline outlet of the previous pipeline to the pipeline inlet of the next pipeline according to the execution sequence of the multiple pipelines.

[0068] Among them, the pipeline path may include multiple pipelines, and the multiple pipelines can flow through the multiple pipelines according to the execution order of the target instruction. Specifically, when the target pipeline path corresponds to multiple pipelines, the multiple pipelines connect the pipeline outlet of the previous pipeline to the pipeline entrance of the next pipeline according to the execution timing of the multiple pipelines, or each pipeline can also correspond to a number or have a priority. For example, each pipeline in the multiple pipelines corresponds to a priority, and the pipeline outlet corresponding to any priority is connected to the pipeline entrance corresponding to the next priority corresponding to the priority, so that multiple pipelines can work together to complete the same instruction, and different pipelines can be connected in series, making the pipeline configuration more flexible.

[0069] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and the plurality of registers can be used by instructions flowing through the registers.

[0070] In a specific implementation, for any pipeline, multiple registers may be included between its pipeline stages, and the control signals in the multiple registers may be copied, thereby realizing a subsequent register copying function.

[0071] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and each of the plurality of registers corresponds to a group of instructions.

[0072] In a specific implementation, a control signal (a control signal in a register) can correspond to a group of instructions, and a group of instructions can include one instruction or multiple instructions, so that the physical implementability is strong. Since there are multiple copy registers between pipeline stages, and a pipeline at a level may have multiple functional circuits, the instructions flowing through this pipeline level may use one of the functional circuits, so the control signal copied by the register can be for one of the functional circuits, so it corresponds to a group of instructions. For example, the first pipeline of the first pipeline is an addition circuit, and the first pipeline of the second pipeline is a data type conversion circuit. Both the addition instruction and the data type conversion instruction can flow in. At this time, the control signal copied in the multiple registers of the first pipeline stage can be the addition group, the data type conversion instruction group, or both groups.

[0073] Further, in a possible example, the multiple registers are used to replicate the same instruction.

[0074] The same instruction may be one or more instructions. For example, multiple registers may be used to copy the same instruction, or multiple registers may be used to copy the same multiple instructions.

[0075] Further, in a possible example, the multiple registers are used to copy control signals of the same operation in multiple instructions.

[0076] In a specific implementation, in an embodiment of the present application, multiple registers are used to copy control signals of the same operation in multiple instructions. For example, the control signal can be a signal sent by the microprocessor to the memory and the input / output device interface circuit, such as: read / write signal, chip select signal, interrupt response signal, etc. The control signal can also be a control signal fed back to the CPU by other components, such as: interrupt request signal, reset signal, bus request signal, device ready signal, etc. The multiple instructions can be a group of instructions.

[0077] Further, the instruction is at least one of the following, which is a single function instruction or a combined function instruction;

[0078] When the instruction is a single function instruction, the instruction is a vector instruction, and the vector instruction is at least one of the following: vector addition instruction, vector addition scalar instruction, vector subtraction instruction, vector multiplication instruction, vector multiplication scalar instruction, vector division instruction, scalar division vector instruction, inter-vector and instruction, intra-vector and instruction, inter-vector or instruction, intra-vector or instruction, vector exponent instruction, vector logarithm instruction, vector greater than judgment instruction, vector equal to judgment instruction, vector not instruction, vector selection merge instruction, vector maximum value instruction, scalar extension instruction, scalar replacement vector instruction, vector replacement scalar instruction, vector retrieval instruction, vector dot product instruction, random vector instruction, circular shift instruction), vector load instruction, vector storage instruction, vector transfer instruction, matrix multiplication vector instruction, vector multiplication matrix instruction, matrix multiplication scalar instruction, tensor operation instruction, matrix addition instruction, matrix subtraction instruction, matrix retrieval instruction, matrix load instruction, matrix storage instruction, matrix transfer instruction.

[0079] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and each of the plurality of registers corresponds to a group of data.

[0080] In a specific implementation, the control signal of each register in the multiple registers can correspond to a set of data. For example, if there are four copy registers and the data bandwidth of the subsequent pipeline processing is 1024, then one control signal in each of the four registers can correspond to the data with a processing bit width of 1024÷4=256. If there are 8 registers, one control signal in each register can correspond to the data with a processing bit width of 1024÷8=128. In this way, the physical feasibility is strong.

[0081] Furthermore, the data is at least one of the following: neuron data, weight data, and bias data.

[0082] In a possible example, the operation module is further used to group the data to be processed according to the number of registers between the adjacent pipeline stages to obtain multiple groups of data.

[0083] In a specific implementation, the operation module can group the data to be processed according to the number of registers between adjacent pipeline stages to obtain multiple groups of data, each register corresponding to a group of data. In this way, the data to be processed can be grouped according to the number of registers.

[0084] In a possible example, the instructions in the register include part or all of the instructions that require the use of the computing resources corresponding to the register.

[0085] In the specific implementation, for registers, the registers between pipeline stages can be used by all instructions flowing through the registers. For computing resources, since only one instruction will use the computing resource at the same time, all instructions using the computing resource can be designed to flow through the pipeline stage. For example, the multiplication and addition instruction enters from the third pipeline stage, uses the multiplier at the third and fourth stages, and uses the adder at the fifth and sixth stages. The advantage of this is that the use of computing resources is reduced and the utilization rate is improved.

[0086] In a possible example, when multiple instructions use the same target computing resource, the operation module is further specifically used to implement the following functions:

[0087] B1. Obtaining a first control signal corresponding to the plurality of instructions;

[0088] B2. extracting preset content of the first control signal to obtain a second control signal;

[0089] B3. Use a register copy method to copy the second control signal into multiple copies, each copy of the second control signal corresponds to a group of instructions or a group of elements.

[0090] In the specific implementation, for computing resources, if multiple instructions use the same computing resources, control signals will be needed to judge multiple situations. At the same time, for vector operations, each element in the vector needs to use a control signal when performing calculations. This will result in one control signal connecting many data signals or computing resources, causing the fan-out of the signal to be too large, which is not conducive to physical implementation. Therefore, the register replication method is used to copy the control signal corresponding to the preset content into multiple copies, each corresponding to a group of instructions or a group of elements. The preset content can be understood as the same operation corresponding to multiple instructions. For example, if multiple instructions include addition operations, the preset content can be an addition operation, thereby dispersing the driving pressure of the control signal and reducing the pressure of layout and wiring in physical implementation.

[0091] Further, let's give an example to illustrate the problem of too large fan-out of control signals. For example, a control signal corresponds to the subsequent processing of 1024-bit wide data. Assuming that the 1024-bit wide data corresponds to the storage space of A×B, if the register is not copied, the register where the control signal is located needs to be physically set at a position close to the data to ensure the driving effect of the control signal. If the distance is far physically, there may be various problems such as time delay. Because the data far away from the control signal will be extracted later, it's like this. After the control signal is copied, the data storage space of A×B is divided into multiple small storage spaces, and each physical storage space corresponds to the register where the control signal is located. This will reduce the pressure of layout and wiring on the chip and ensure the effect of signal driving.

[0092] It can be seen that in the operation module involved in the embodiment of the present application, the operation module includes K pipelines and P pipeline entrances and Q pipeline exits, K, P, Q are all integers greater than or equal to 2, each of the K pipelines includes multiple pipeline stages, and each pipeline stage corresponds to at least one operation circuit. The operation module is used to configure the operation circuit, pipeline entrance and pipeline exit according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation corresponding to the target instruction according to the target pipeline path. In this way, the pipeline can be flexibly configured according to the computing resources required by the instruction, so that the instruction can achieve the minimum computing delay and use the least computing resources to complete the calculation in the pipeline, thereby improving the computing efficiency.

[0093] With the above Figure 1A For the embodiments shown, please refer to Figure 2 , Figure 2 is a flow chart of a flow optimization method provided by an embodiment of the present application, which is applied to Figure 1A The operation module shown in the figure includes K pipelines, P pipeline inlets and Q pipeline outlets, wherein K, P and Q are integers greater than or equal to 2; each of the K pipelines includes a plurality of pipeline stages, and each pipeline stage corresponds to at least one operation circuit; as shown in the figure, the pipeline optimization method includes:

[0094] 201. Get target instructions.

[0095] 202. Configure the operation circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction to obtain a corresponding target pipeline path.

[0096] 203. Execute a calculation operation corresponding to the target instruction according to the target pipeline path.

[0097] In a specific implementation, the specific description of the above steps 201 to 203 can refer to the above description and will not be repeated here.

[0098] It can be seen that the pipeline optimization method involved in the embodiment of the present application is applied to a calculation module, which includes K pipelines and P pipeline entrances and Q pipeline exits, where K, P, and Q are all integers greater than or equal to 2, and each of the K pipelines includes multiple pipeline stages, and each pipeline stage corresponds to at least one calculation circuit. The calculation module is used to configure the calculation circuit, pipeline entrance and pipeline exit according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the calculation operation corresponding to the target instruction according to the target pipeline path. In this way, the pipeline can be flexibly configured according to the computing resources required by the instruction, so that the instruction can achieve the minimum computing delay and use the least computing resources to complete the calculation in the pipeline, thereby improving the computing efficiency.

[0099] In accordance with the above embodiment, please refer to Figure 3 , Figure 3 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. As shown in the figure, the electronic device includes a processor, a memory, a communication interface, a computing module and one or more programs. The computing module includes K pipelines and P pipeline inlets and Q pipeline outlets. The K, the P and the Q are all integers greater than or equal to 2. Each of the K pipelines includes multiple pipeline stages, and each pipeline stage corresponds to at least one computing circuit. The one or more programs are stored in the memory and are configured to be executed by the processor. In the embodiment of the present application, the program includes instructions for executing the following steps:

[0100] Get target instructions;

[0101] According to the computing resources required by the target instruction, the operation circuit, the pipeline inlet and the pipeline outlet are configured to obtain a corresponding target pipeline path;

[0102] The operation corresponding to the target instruction is performed according to the target pipeline path.

[0103] It can be seen that the electronic device involved in the embodiment of the present application includes a calculation module, which includes K pipelines and P pipeline entrances and Q pipeline exits, K, P, and Q are all integers greater than or equal to 2, and each of the K pipelines includes multiple pipeline stages, and each pipeline stage corresponds to at least one calculation circuit. The calculation module is used to configure the calculation circuit, the pipeline entrance and the pipeline exit according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the calculation operation corresponding to the target instruction according to the target pipeline path. In this way, the pipeline can be flexibly configured according to the computing resources required by the instruction, so that the instruction can achieve the minimum computing delay and use the least computing resources to complete the calculation in the pipeline, thereby improving the computing efficiency.

[0104] In a possible example, in configuring the computing circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction, obtaining the corresponding target pipeline path, and performing the computing operation corresponding to the target instruction according to the target pipeline path, the above program includes instructions for performing the following steps:

[0105] Obtaining a target operation type corresponding to the target instruction;

[0106] Determining a target operation circuit, a target pipeline entry, and a target pipeline exit corresponding to the target operation type;

[0107] Determining a target pipeline path corresponding to the target operation type according to the target operation circuit, the target pipeline inlet and the target pipeline outlet;

[0108] The computing operation corresponding to the target instruction is executed according to the target pipeline path.

[0109] In a possible example, when the target pipeline path corresponds to multiple pipelines, the multiple pipelines connect the pipeline outlet of the previous pipeline to the pipeline inlet of the next pipeline according to the execution sequence of the multiple pipelines.

[0110] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and the plurality of registers can be used by instructions flowing through the registers.

[0111] In one possible example, the multiple registers are used to replicate the same instruction.

[0112] In a possible example, the multiple registers are used to replicate control signals of the same operation in multiple instructions.

[0113] In a possible example, the instruction is at least one of the following, which is a single function instruction or a combined function instruction;

[0114] When the instruction is a single function instruction, the instruction is a vector instruction, and the vector instruction is at least one of the following: vector addition instruction, vector addition scalar instruction, vector subtraction instruction, vector multiplication instruction, vector multiplication scalar instruction, vector division instruction, scalar division vector instruction, inter-vector and instruction, intra-vector and instruction, inter-vector or instruction, intra-vector or instruction, vector exponent instruction, vector logarithm instruction, vector greater than judgment instruction, vector equal to judgment instruction, vector not instruction, vector selection merge instruction, vector maximum value instruction, scalar extension instruction, scalar replacement vector instruction, vector replacement scalar instruction, vector retrieval instruction, vector dot product instruction, random vector instruction, circular shift instruction), vector load instruction, vector storage instruction, vector transfer instruction, matrix multiplication vector instruction, vector multiplication matrix instruction, matrix multiplication scalar instruction, tensor operation instruction, matrix addition instruction, matrix subtraction instruction, matrix retrieval instruction, matrix load instruction, matrix storage instruction, matrix transfer instruction.

[0115] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and each of the plurality of registers corresponds to a group of data.

[0116] In a possible example, the operation module is further used to group the data to be processed according to the number of registers between the adjacent pipeline stages to obtain multiple groups of data.

[0117] In a possible example, the data is at least one of the following: neuron data, weight data, and bias data.

[0118] The above mainly introduces the scheme of the embodiment of the present application from the perspective of the execution process on the method side. It is understandable that, in order to realize the above functions, the electronic device includes a hardware structure and / or software module corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments provided herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0119] The embodiment of the present application can divide the electronic device into functional units according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0120] See also Figure 4 , Figure 4 : is a schematic diagram of the structure of a pipeline optimization device provided in this embodiment. The pipeline optimization device is applied to an electronic device, which includes a computing module, the computing module includes K pipelines, P pipeline inlets, and Q pipeline outlets, wherein K, P, and Q are integers greater than or equal to 2; each of the K pipelines includes multiple pipeline stages, and each pipeline stage corresponds to at least one computing circuit; the pipeline optimization device may include: an acquisition unit 401, a configuration unit 402, and an execution unit 403, wherein:

[0121] The acquisition unit 401 is used to acquire the target instruction;

[0122] The configuration unit 402 is used to configure the operation circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction to obtain a corresponding target pipeline path;

[0123] The execution unit 403 is used to execute the calculation operation corresponding to the target instruction according to the target pipeline path.

[0124] It can be seen that in the pipeline optimization device involved in the embodiment of the present application, the operation module includes K pipelines and P pipeline entrances and Q pipeline exits, K, P, Q are all integers greater than or equal to 2, each of the K pipelines includes multiple pipeline stages, and each pipeline stage corresponds to at least one operation circuit. The operation module is used to configure the operation circuit, pipeline entrance and pipeline exit according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation corresponding to the target instruction according to the target pipeline path. In this way, the pipeline can be flexibly configured according to the computing resources required by the instruction, so that the instruction can achieve the minimum computing delay and use the least computing resources to complete the calculation in the pipeline, thereby improving the computing efficiency.

[0125] In a possible example, in configuring the operation circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction, obtaining the corresponding target pipeline path, and performing the operation corresponding to the target instruction according to the target pipeline path, the pipeline optimization device is specifically used to:

[0126] Obtaining a target operation type corresponding to the target instruction;

[0127] Determining a target operation circuit, a target pipeline entry, and a target pipeline exit corresponding to the target operation type;

[0128] Determining a target pipeline path corresponding to the target operation type according to the target operation circuit, the target pipeline inlet and the target pipeline outlet;

[0129] The computing operation corresponding to the target instruction is executed according to the target pipeline path.

[0130] In a possible example, when the target pipeline path corresponds to multiple pipelines, the multiple pipelines connect the pipeline outlet of the previous pipeline to the pipeline inlet of the next pipeline according to the execution sequence of the multiple pipelines.

[0131] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and the plurality of registers can be used by instructions flowing through the registers.

[0132] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and each of the plurality of registers corresponds to a group of instructions.

[0133] In one possible example, the multiple registers are used to replicate the same instruction.

[0134] In a possible example, the multiple registers are used to replicate control signals of the same operation in multiple instructions.

[0135] In a possible example, the instruction is at least one of the following, which is a single function instruction or a combined function instruction;

[0136] When the instruction is a single function instruction, the instruction is a vector instruction, and the vector instruction is at least one of the following: vector addition instruction, vector addition scalar instruction, vector subtraction instruction, vector multiplication instruction, vector multiplication scalar instruction, vector division instruction, scalar division vector instruction, inter-vector and instruction, intra-vector and instruction, inter-vector or instruction, intra-vector or instruction, vector exponent instruction, vector logarithm instruction, vector greater than judgment instruction, vector equal to judgment instruction, vector not instruction, vector selection merge instruction, vector maximum value instruction, scalar extension instruction, scalar replacement vector instruction, vector replacement scalar instruction, vector retrieval instruction, vector dot product instruction, random vector instruction, circular shift instruction), vector load instruction, vector storage instruction, vector transfer instruction, matrix multiplication vector instruction, vector multiplication matrix instruction, matrix multiplication scalar instruction, tensor operation instruction, matrix addition instruction, matrix subtraction instruction, matrix retrieval instruction, matrix load instruction, matrix storage instruction, matrix transfer instruction.

[0137] In a possible example, adjacent pipeline stages of the K pipelines include a plurality of registers, and each of the plurality of registers corresponds to a group of data.

[0138] In a possible example, the operation module is further used to group the data to be processed according to the number of registers between the adjacent pipeline stages to obtain multiple groups of data.

[0139] In a possible example, the data is at least one of the following: neuron data, weight data, and bias data.

[0140] It can be understood that the functions of each program module of the flow optimization device of this embodiment can be specifically implemented according to the method in the above method embodiment, and its specific implementation process can refer to the relevant description of the above method embodiment, which will not be repeated here.

[0141] Figure 5 is a structural diagram showing a combined processing device 500 according to an embodiment of the present disclosure. Figure 5 As shown in FIG. 5 , the combined processing device 500 includes an electronic device 502, an interface device 504, other processing devices 506, and a storage device 508. According to different application scenarios, the electronic device may include one or more computing devices 510, which may be configured to execute the combined processing device 502 of the present invention. Figure 1A-4 The operation described.

[0142] In different embodiments, the electronic device disclosed herein may be configured to perform user-specified operations. In an exemplary application, the electronic device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the electronic device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, with respect to the electronic device disclosed herein, it may be regarded as having a single-core structure or a homogeneous multi-core structure.

[0143] In exemplary operation, the electronic device of the present disclosure can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the electronic device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the electronic device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0144] In one or more embodiments, the other processing device can serve as an interface between the electronic device disclosed herein (which can be embodied as an artificial intelligence such as a computing device related to neural network computing) and external data and control, and perform basic controls including but not limited to data transfer, starting and / or stopping the computing device, etc. In other embodiments, the other processing device can also cooperate with the electronic device to jointly complete computing tasks.

[0145] In one or more embodiments, the interface device can be used to transmit data and control instructions between the electronic device and other processing devices. For example, the electronic device can obtain input data from other processing devices via the interface device and write it into the storage device (or memory) on the electronic device chip. Further, the electronic device can obtain control instructions from other processing devices via the interface device and write them into the control cache on the electronic device chip. Alternatively or optionally, the interface device can also read data from the storage device of the electronic device and transmit it to other processing devices.

[0146] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the electronic device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the electronic device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the electronic device or other processing device.

[0147] In some embodiments, the present disclosure also discloses a chip (e.g. Figure 6 In one implementation, the chip is a system on chip (SoC) and integrates one or more Figure 5 The chip can be connected to an external interface device (such as Figure 6 The external interface device 606 shown in the figure is connected to other related components. The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as a video codec) and / or interface modules (such as a DRAM interface) may be integrated on the chip. In some embodiments, the present disclosure further discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure further discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 6 The board is described in detail.

[0148] Figure 6 FIG. 6 is a schematic diagram showing the structure of a board 600 according to an embodiment of the present disclosure. Figure 6As shown in , the board includes a storage device 604 for storing data, which includes one or more storage units 610. The storage device can be connected and data can be transmitted with the control device 608 and the chip 602 described above by means of, for example, a bus. Further, the board also includes an external interface device 606, which is configured for data relay or switching between the chip (or the chip in the chip packaging structure) and an external device 612 (such as a server or computer, etc.). For example, the data to be processed can be transmitted to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0149] In one or more embodiments, the control device in the disclosed board may be configured to regulate the state of the chip. To this end, in an application scenario, the control device may include a microcontroller unit (MCU) to regulate the working state of the chip.

[0150] According to the above combination Figure 5 and Figure 6 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0151] According to different application scenarios, the electronic equipment or device disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, transportation, household appliances, and / or medical equipment. The transportation includes airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs. The electronic equipment or device disclosed herein may also be applied to the Internet, IoT, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and medical fields. Further, the electronic equipment or device disclosed herein may also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, electronic devices or devices with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or devices with low power consumption can be applied to terminal devices and / or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0152] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present disclosure, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present disclosure may be regarded as optional embodiments, i.e., the actions or modules involved therein may not necessarily be necessary for the implementation of one or some of the schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different focuses on the description of some embodiments. In view of this, those skilled in the art may appreciate the parts that are not described in detail in a certain embodiment of the present disclosure, and may also refer to the relevant descriptions of other embodiments.

[0153] In terms of specific implementation, based on the disclosure and teaching of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented by other methods not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article divides them on the basis of considering logical functions, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0154] In the present disclosure, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

[0155] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0156] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPU, GPU, FPGA, DSP and ASIC, etc. Further, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

[0157] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps of any method described in the above method embodiments, and the above computer includes an electronic device.

[0158] The embodiment of the present application also provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, the computer program is operable to cause a computer to execute some or all of the steps of any method described in the method embodiment. The computer program product may be a software installation package, and the computer includes an electronic device.

[0159] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A computing module, characterized in that: The operation module includes K pipelines, P pipeline inlets, and Q pipeline outlets, wherein K, P, and Q are all integers greater than or equal to 2; each of the K pipelines includes a plurality of pipeline stages, and each pipeline stage corresponds to at least one operation circuit; The computing module is used to configure the computing circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the computing operation corresponding to the target instruction according to the target pipeline path; the computing resources include the computing circuit that needs to be called; Among them, in the aspect that the operation module is used to configure the operation circuit, the pipeline inlet and the pipeline outlet according to the computing resources required by the target instruction, obtain the corresponding target pipeline path, and perform the operation operation corresponding to the target instruction according to the target pipeline path, specifically: Obtaining a target operation type corresponding to the target instruction; Determining a target operation circuit, a target pipeline entry, and a target pipeline exit corresponding to the target operation type; Determining a target pipeline path corresponding to the target operation type according to the target operation circuit, the target pipeline inlet and the target pipeline outlet; The computing operation corresponding to the target instruction is executed according to the target pipeline path.

2. The computing module according to claim 1, characterized in that: Adjacent pipeline stages of the K pipelines include a plurality of registers, and each of the plurality of registers corresponds to a group of instructions.

3. The computing module according to claim 2, characterized in that: The multiple registers are used to replicate the same instruction.

4. The computing module according to claim 2, characterized in that: The plurality of registers are used to replicate control signals of the same operation in a plurality of instructions.

5. The computing module according to claim 2, characterized in that: Adjacent pipeline stages of the K pipelines include a plurality of registers, and each of the plurality of registers corresponds to a group of data.

6. The computing module according to claim 5, characterized in that: The operation module is also used to group the data to be processed according to the number of registers between the adjacent pipeline stages to obtain multiple groups of data.

7. A flow optimization method, characterized in that: Applied to a computing module, the computing module includes K pipelines, P pipeline inlets, and Q pipeline outlets, wherein K, P, and Q are all integers greater than or equal to 2; each of the K pipelines includes a plurality of pipeline stages, and each pipeline stage corresponds to at least one computing circuit; the method includes: Get target instructions; The computing circuit, the pipeline inlet and the pipeline outlet are configured according to the computing resources required by the target instruction to obtain the corresponding target pipeline path, specifically: obtaining the target computing type corresponding to the target instruction; determining the target computing circuit, the target pipeline inlet and the target pipeline outlet corresponding to the target computing type; determining the target pipeline path corresponding to the target computing type according to the target computing circuit, the target pipeline inlet and the target pipeline outlet; the computing resources include the computing circuit that needs to be called; The operation corresponding to the target instruction is performed according to the target pipeline path.

8. A neural network chip, characterized in that: The neural network chip includes the operation module as described in any one of claims 1-6, or is used to execute the method as described in claim 7.

9. A board, characterized in that: The board includes: a storage device, an interface device and a control device and a neural network chip as claimed in claim 8; Wherein, the neural network chip is connected to the storage device, the control device and the interface device respectively; The storage device is used to store data; The interface device is used to realize data transmission between the chip and external equipment; The control device is used to monitor the state of the chip.

10. An electronic device, characterized in that: The electronic device is used to execute the method as claimed in claim 7, or the electronic device includes the computing module as described in any one of claims 1-6, the electronic device includes the neural network chip as described in claim 8, or the electronic device includes the board as described in claim 9.

11. A computer-readable storage medium, characterized in that: A computer program for electronic data exchange is stored, wherein the computer program causes a computer to execute the method as claimed in claim 7.

Images