Method for implementing partitioned parallel routing using an FPGA built-in partition module

Abstract

The present application discloses a parallel routing method for partitioning by using an FPGA built-in partition module, which relates to the field of FPGAs. The FPGA implementing this method is built with a partition module. The partition module serves as a boundary to divide the programmable logic resources into several local resource areas and is connected to the programmable logic resources. For a primitive net whose net endpoints are distributed in at least two different local resource areas, the partition module can be used to split it into several nets to be routed corresponding to different local resource areas. Thus, each local resource area has its own netlist and routing resource map. Therefore, during parallel routing, the routing results in each local resource area are independent of each other and do not interfere with each other. After routing can be performed separately, the results can be directly merged globally. The running results are predictable and not affected by the netlist processing order and the design environment, which is suitable for parallel processing of routing, can effectively improve the routing efficiency, and obtain the routing results.

Description

Technical Field

[0001] The present invention relates to the field of FPGAs, and in particular to a parallel wiring method for partitioning by using a built-in partition module of an FPGA. Background Art

[0002] FPGA wiring is a process of connecting occupied logic units by using the programmable interconnection resources of a device after chip placement. When performing FPGA wiring, generally, the programmable logic resources including the interconnection resources on the FPGA are abstracted into a wiring diagram. The wiring diagram represents all the underlying modules, architectures, and interconnection resources. Then, a signal to be processed is selected in a predetermined order, and the source point and the destination point module positions related to the signal are found according to the chip placement result. A wiring algorithm such as a negotiation pathfinding algorithm is used to search the wiring diagram to find an unoccupied resource to obtain a detour path from the source point to the destination point. If no path with completely unoccupied resources is found, resources already occupied by other signals can be forcibly used to also obtain a detour path for this signal. At this time, the resource is repeatedly occupied by multiple signals to form a conflict, which needs to be resolved later. The detour path used by this signal is recorded on the wiring diagram, and the corresponding resources are marked as occupied. The above process is repeated until all signals have detour paths, and then the signals with repetitions or conflicts are re-routed to resolve the conflicts until there is no conflict situation where the routing resources are repeatedly used by multiple signals to obtain the wiring result.

[0003] With the continuous and substantial increase in the scale of FPGAs, the scale of the wiring diagram increases (i.e., the device capacity is large), and at the same time, the utilization rate of FPGAs also gradually increases. This leads to an increase in the cumulative possible paths to be considered when searching for paths during the wiring process, a large increase in the search space, and a greater difficulty in completely resolving conflicts, resulting in an excessive running time for the wiring process. And wiring occupies a large amount of running time in the FPGA application development process, and the quality of the wiring efficiency directly affects the application development efficiency and the user experience.

[0004] In order to improve the wiring efficiency and reduce the wiring time, multi-core and many-core computing platforms are often relied on currently. By means of parallelization, the running duration of the wiring process is reduced, that is, the global wiring problem is divided into multiple sub-problems. After each sub-problem is processed in parallel by the multi-core platform, the results are merged onto the global wiring diagram. However, it is found in the actual running process that the effect of this approach is not ideal, and there are the following two problems: (1) When merging after the routing of each sub-problem is completed, affected by the signals across sub-problems, new conflicts often occur, and further re-routing is required to solve the conflicts, resulting in the efficiency improvement of multi-core parallelism being lower than the theoretical expectation. For example, when adopting the 4-core parallel mode, in fact, it can only basically achieve the effect of halving the running time, and it is far from achieving the theoretical effect of reducing the running time to 1 / 4. (2) Each sub-problem runs independently. However, due to the influence of the configuration and load of the software running platform, etc., the routing time used by each core to complete each sub-problem is uncertain. This leads to the difficulty in maintaining the consistent routing order. When routing a specific signal, different paths will be obtained due to different resource occupation situations on the wiring diagram. Therefore, changing the routing order of each net will directly change the final wiring result. As a result, different conflict points will occur when the global wiring is executed multiple times for the same wiring problem, and the final wiring results obtained after conflict resolution are also different. This is unacceptable in engineering applications, especially it will cause difficulties in debugging. One approach is to forcibly stipulate the routing order of each net. However, in this case, in order to comply with the specific routing order, each core often needs to wait for each other, increasing the running time, not achieving true multi-core parallelism, and further reducing the efficiency of multi-core parallelism. Summary of the Invention

[0005] In view of the above problems and technical requirements, the present inventor proposes a parallel wiring method for partitioning by using the built-in partition module of an FPGA. The technical solution of the present invention is as follows:

[0006] A parallel wiring method for partitioning by using the built-in partition module of an FPGA. The FPGA internally includes a partition module that divides the programmable logic resources into several local resource areas. The partition module is connected to the surrounding programmable logic resources. The partition module includes several pairs of connection points connected through internal paths. The method includes:

[0007] Determine the positions of all net endpoints in each original net according to the layout result of the FPGA. The net endpoints include the source point and several destination points respectively connected thereto;

[0008] Directly use the original net in which all net endpoints are located in the same local resource area as the net to be wired and correspond it to the local resource area where it is located;

[0009] The original wire network with wire network endpoints distributed in at least two different local resource areas is split into several to-be-routed wire networks corresponding to different local resource areas by using a partition module. Each to-be-routed wire network includes the part of the original wire network in the current local resource area and the connection relationship formed between the newly added wire network endpoints at the boundary of the current local resource area by the target partition module. Each adjacent pair of to-be-routed wire networks corresponding to two local resource areas split from one original wire network are connected through a pair of connection points of the target partition module between the two local resource areas by using an internal path;

[0010] The to-be-routed wire networks corresponding to each local resource area are processed in parallel to obtain the routing result of each local resource area, and the routing results of each local resource area are merged to obtain the global routing result corresponding to the FPGA.

[0011] A further technical solution thereof is that the partition module includes several input ends and several output ends, and the input ends are selectively connected to one of the output ends through internal gating paths to form a pair of connection points.

[0012] A further technical solution thereof is that one input end of the partition module is directly connected or connected to a corresponding output end through a buffer to form a pair of connection points.

[0013] A further technical solution thereof is that the partition modules are arranged in a determinant pattern along the horizontal direction and / or the vertical direction inside the FPGA.

[0014] A further technical solution thereof is that the partition module is arranged in the central column of the main trunk of the clock tree of the FPGA.

[0015] A further technical solution thereof is that the partition module is arranged at the boundary of the clock domain of the FPGA.

[0016] A further technical solution thereof is that the FPGA is a multi-die structure, and partition modules are respectively arranged between each FPGA die.

[0017] A further technical solution thereof is that partition modules are arranged at all boundaries of a local resource area inside the FPGA, and the local resource area is used to implement a predetermined IP node.

[0018] A further technical solution thereof is that one partition module is used to implement the newly added wire network endpoints of one original wire network, or one partition module is simultaneously used to implement the newly added wire network endpoints of multiple original wire networks, and different original wire networks occupy different pairs of connection points of the partition module.

[0019] A further technical solution is that the local resource area where the source point in the original wire network is located is used as the first-level local resource area, and the adjacent local resource area in the direction from the source point to the corresponding destination point in the original wire network of the i-th level local resource area is used as the (i + 1)-th level local resource area, where i is a parameter and the starting value of i is 1;

[0020] Then, the input end of the target partition module between the i-th level local resource area and the (i + 1)-th level local resource area forms a newly added destination point within the i-th level local resource area, and the corresponding output end forms a newly added source point within the (i + 1)-th level local resource area. The source points within each level of local resource area are connected to and point to all the destination points within the current local resource area.

[0021] A further technical solution is that when determining the target partition module between the i-th level local resource area and the (i + 1)-th level local resource area:

[0022] Based on the source point within the i-th level local resource area and the reference destination points in the direction, the reference destination points in the direction include the destination points within the nearest level of local resource area to the i-th level local resource area, or the destination points within the nearest several levels of local resource areas, or the destination points within all subsequent local resource areas.

[0023] A further technical solution is that determining the target partition module based on the source point within the i-th level local resource area and the reference destination points in the direction includes:

[0024] For all the partition modules at the boundary between the i-th level local resource area and the (i + 1)-th level local resource area, respectively determine the partition module with the shortest distance to the line connecting the source point within the i-th level local resource area to each reference destination point as the candidate partition module, and take the candidate partition module with the shortest distance to the source point within the i-th level local resource area as the target partition module.

[0025] A further technical solution is that determining the target partition module based on the source point within the i-th level local resource area and the reference destination points in the direction includes:

[0026] For all the partition modules at the boundary between the i-th level local resource area and the (i + 1)-th level local resource area, determine the partition module with the shortest distance to the line connecting the source point within the i-th level local resource area to the center of gravity point formed by each reference destination point as the target partition module.

[0027] A further technical solution is that determining the target partition module based on the source point within the i-th level local resource area and the reference destination points in the direction includes:

[0028] For all partition modules at the boundary between the i-th level of local resource area and the (i + 1)-th level of local resource area, determine the partition module with the shortest distance from the connection line between the source point in the i-th level of local resource area and the predetermined reference destination point as the target partition module. The predetermined reference destination point is the reference destination point with the shortest or longest distance from the source point in the i-th level of local resource area among all reference destination points.

[0029] A further technical solution thereof is that when determining the target partition module between the i-th level of local resource area and the (i + 1)-th level of local resource area:

[0030] Determine the target partition module based on the reference destination points in the direction; the reference destination points in the direction include the destination points in the first-level local resource area closest to the i-th level of local resource area, or the destination points in several closest levels of local resource areas, or the destination points in all subsequent levels of local resource areas.

[0031] A further technical solution thereof is that determining the target partition module based on the reference destination points in the direction includes:

[0032] For all partition modules at the boundary between the i-th level of local resource area and the (i + 1)-th level of local resource area, take the partition module with the smallest sum of the total distances from all reference destination points or the shortest maximum distance as the target partition module.

[0033] A further technical solution thereof is that determining the target partition module based on the reference destination points in the direction includes:

[0034] Form a Steiner tree from all reference destination points, and take the partition module at the boundary between the i-th level of local resource area and the (i + 1)-th level of local resource area with the shortest distance from a predetermined Steiner node in the formed Steiner tree as the target partition module.

[0035] A further technical solution thereof is that when determining the target partition module between the i-th level of local resource area and the (i + 1)-th level of local resource area:

[0036] For all wire network endpoints inside the original wire network, form a minimum spanning tree in which the wire network endpoints are connected in sequence through the Prim algorithm, and take the partition module at the boundary between the i-th level of local resource area and the (i + 1)-th level of local resource area with the shortest distance from the edge spanning the current two local resource areas in the minimum spanning tree as the target partition module.

[0037] The beneficial technical effects of the present invention are:

[0038] The present application discloses a parallel routing method for partitioning using an FPGA built-in partition module. The FPGA implementing this method is built with a partition module, which serves as a boundary to divide the programmable logic resources into several local resource areas and is connected to the programmable logic resources. For a primitive net whose net endpoints are distributed in at least two different local resource areas, the partition module can be used to split it into several nets to be routed corresponding to different local resource areas. Thus, each local resource area has its own netlist and routing resource map. Therefore, during parallel routing, the routing results in each local resource area are independent of each other and do not interfere with each other. After routing separately, the results can be directly merged globally without resolving conflicts in different local resource areas. The operation result is predictable and not affected by the netlist processing order and design environment, suitable for parallel processing of routing, which can effectively improve the routing efficiency and obtain the routing result. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a layout schematic diagram of the partition module built in the FPGA of the present application and a connection schematic diagram with the programmable logic resources.

[0040] Figure 2 It is a schematic diagram of the internal structure of the partition module built in the FPGA of the present application.

[0041] Figure 3 It is another schematic diagram of the internal structure of the partition module built in the FPGA of the present application.

[0042] Figure 4 It is a flowchart schematic diagram of the parallel routing method disclosed in the present application.

[0043] Figure 5 It is a splitting schematic diagram of the primitive net in the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The following further describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0045] The present application discloses a parallel routing method for partitioning using an FPGA built-in partition module. The FPGA used to implement this method has hardware improvements compared to a conventional FPGA. In addition to including conventional programmable logic resources, an additional hardware resource is used to add a partition module. The partition module serves as a boundary to divide the programmable logic resources into several local resource areas, and the number and type of programmable logic resources included in each local resource area can be the same or different. At the same time, the partition module is connected to the surrounding programmable logic resources. The partition module includes several pairs of connection points connected through an internal path. The partition module can also be regarded as an additional interconnection resource. Thus, it is equivalent to inserting a partition module between the interconnection structures of the programmable logic resources of the existing FPGA, but still ensuring the interconnection between the programmable logic resources. The partition module is a hardware resource implemented based on conventional circuit components, so it can be realized using the manufacturing process of a conventional FPGA. It can be considered that the FPGA chip in the present application is modified by adding a partition module to an existing conventional FPGA with only programmable logic resources.

[0046] Existing FPGAs usually adopt a Column-Based architecture. The programmable logic resources are arranged in a determinant structure inside the FPGA. The programmable logic resources mainly include configurable function modules and interconnection resource modules (INT). The configurable function modules mainly include programmable logic units (CLB or PLBs) and input / output ports (IOB), and sometimes also include some other function modules, such as BRAM, DSP, PC, etc. These configurable function modules have an interconnection resource module (INT) with the same structure distributed around the configurable function module. The horizontal or vertical connections between the various configurable function modules are all connected via the INT module. Figure 1 The types and relative size relationships of different configurable function modules are not shown. Only the determinant arrangement structure and the interconnection relationship realized through the INT between them are schematically shown in a box. The partition module is set at the corresponding position of the FPGA as needed and is connected to the INT surrounded by the surrounding configurable function modules through input / output terminals. Figure 1 The shaded structure in is the partition module, which exemplarily shows the interconnection schematic diagram between the partition module and different INTs.

[0047] The partition module can be set at any suitable place inside the FPGA. A typical approach is that the partition module is arranged in a determinant pattern along the horizontal direction and / or the vertical direction inside the FPGA. For example, Figure 1 Taking the example of setting a column of partition modules along the vertical direction inside the FPGA. When choosing a specific position, one embodiment provides a method of setting the partition module in the central column of the main trunk of the clock tree of the FPGA. Another embodiment provides a method of setting the partition module at the boundary of the clock domain of the FPGA.

[0048] The FPGA in this application can be a conventional single die structure or a multi-die structure. In the FPGA, there are several FPGA dies disposed on the silicon connection layer. In this scenario, in one embodiment, the partition module is disposed between each FPGA die, and the silicon connection points of the partition module are connected to the surrounding FPGA dies. Moreover, the partition module can also be inserted into each FPGA die according to the above method.

[0049] In practical applications, partition modules are disposed at all boundaries of a local resource area inside the FPGA, that is, an area isolated from the outside is circled inside the FPGA by using the partition modules. This local resource area is used to implement a predetermined IP node, which is customized according to the method provided in this application. All the nets to be connected to this predetermined IP node need to pass through the partition module. Therefore, the performance of the predetermined IP node can be ensured to be stable because its wiring can be kept unchanged within the area.

[0050] The input end and the output end of the partition module facing outward can be disposed at each boundary where the partition module is to be laid out, and there are various implementation manners for the internal structure. In one embodiment, as Figure 2 shown. The partition module includes several input ends and several output ends. The input ends are selectively connected to one of the output ends through internal selection paths to form a pair of connection points, that is, there is no fixed corresponding relationship between the input ends and the output ends, but selection is performed through the internal selection paths, which has high flexibility. The internal selection paths can be selectively connected by using common forms such as MUX.

[0051] In another embodiment, one input end of the partition module is directly connected or connected to a corresponding output end through a buffer to form a pair of connection points, that is, there is a fixed corresponding relationship between the input end and the output end. When the input end and the output line segment are directly connected, the structure of the partition module is similar to the structure of a switch box inside the FPGA. When connected through a buffer, the schematic diagram is as Figure 3 shown.

[0052] Based on the FPGA with the built-in partition module in this application, the implemented parallel wiring method includes the following steps. Please refer to the Figure 4 flow chart shown and combine it with the Figure 5 schematic diagram shown. Figure 5 Relative to Figure 1 the structure of the programmable logic resources is simplified, and the connection relationship between the programmable logic resources and the partition module is omitted. The FPGA internally includes three columns of partition modules. The programmable logic resources are divided into four local resource areas with each column of partition modules as the boundary. Each column of partition modules is provided with several partition modules:

[0053] 1. Determine the positions of all net endpoints in each original net according to the layout result of the FPGA. The net endpoints include the source and several target points connected thereto respectively. Thus, it is possible not only to determine in which local resource area each net endpoint is located, but also to determine at which specific programmable logic resource in the local resource area it is located. The original nets to be routed may be completely located within one local resource area or may span multiple local resource areas.

[0054] 2. Directly use the original nets where all net endpoints are located within the same local resource area as the nets to be routed corresponding to the local resource area where they are located. For example Figure 5 As shown, the source point S11 of the original net Net1 and its respectively connected target points T11, T12, and T13 are all located within local resource area 1. Then, directly use the original net Net1 as the net to be routed corresponding to the local resource area 1 where it is located.

[0055] 3. Split the original nets with net endpoints distributed in at least two different local resource areas into several nets to be routed corresponding to different local resource areas by using the partition module. The nets to be routed within each local resource area include the part of the original net within the current local resource area and the connection relationship formed between the new net endpoints formed by the target partition modules at the boundary of the current local resource area.

[0056] The part of the original net within the current local resource area may or may not include the net endpoints in the original net. For example Figure 5 In the figure, the source point S21 of the original net Net2 is respectively connected to the target points T21, T22, T23, and T24. The original net Net2 includes the source point S21 and the target point T21 within local resource area 1, but does not include any original net endpoints within local resource area 2, includes the original target points T23 and T24 within local resource area 3, and includes the original target point T22 within local resource area 4.

[0057] The part of the original net within the current local resource area at least includes the signal path of the original net within this local resource area. This signal path can directly be the connection line between different net endpoints in the original net. For example Figure 5 In the figure, the part of the original net Net2 within local resource area 1 further includes the signal path between the source point S21 and the target point T21. This signal path is directly the connection line between S21 and T21 in the original net Net2. Or, this signal path is not the connection line in the original net, but reflects the transmission direction of the connection line of the original net within this local resource area. Here, the reflection does not necessarily mean that the transmission directions are exactly the same, as long as it is within an acceptable straight-line angle range. For example Figure 5Among them, the dashed lines show the connections between S21 and T22, T23, and T24 in the original wire network respectively. The signal path of the original wire network Net2 within the local resource area 2 is the signal path from S22 to S23. This signal path is not a connection in the original wire network, but the transmission direction of the connections of the original wire network Net2 within the local resource area 2 is from the local resource area 1 to the local resource area 3, and the signal path from S22 to S23 also reflects this transmission direction. Similarly, within the local resource area 3, although the signal path from S23 to T24 is not a connection in the original wire network Net2, the transmission direction from S23 to T24 is the same as the transmission direction from S21 to S24. And so on for others.

[0058] For an original wire network to be split, when a target partition module forms new wire network endpoints within the original wire network, a set of source points and target points are actually inserted. The input end of the target partition module forms a new destination point within a local resource area, and the corresponding output end forms a new source point within another local resource area. To reflect the transmission path, in this application, the local resource area where the source point in the original wire network is located is used as the first-level local resource area, and the local resource area adjacent to the i-th level local resource area in the direction from the source point to the corresponding destination point in the original wire network is used as the (i + 1)-th level local resource area, where i is a parameter and the starting value of i is 1. Thus, starting from the first-level local resource area where the source point in the original wire network is located, each newly added wire network endpoint can be determined in sequence. Then, the input end of the target partition module between the i-th level local resource area and the (i + 1)-th level local resource area forms a newly added destination point within the i-th level local resource area, and the corresponding output end forms a newly added source point within the (i + 1)-th level local resource area. The source points within each level of local resource area are connected to and point to all the destination points within the current local resource area. For example, in Figure 5 Among them, the local resource areas 1 to 4 are the first to fourth level local resource areas respectively. The input end of the target partition module between the local resource area 1 and the local resource area 2 is used as the newly added destination point T25 in the local resource area 1, and the corresponding output end of T25 is used as the newly added source point S22 in the local resource area 2. Within the target partition module, T25 is connected to and points to S22. The source point S21 in the local resource area 1 points to the newly added destination point T25, and the source point S22 in the local resource area 2 points to the destination points within this local resource area. Generally, only a set of newly added source points and destination points are formed at the cross-local resource area of the original wire network, but actually multiple sets can also be formed. For example Figure 5In [the above case], for the original wire net Net2, only a new set of source points and destination points (T25 / S22) is inserted between local resource area 1 and local resource area 2. However, actually, another new set of source points and destination points can also be inserted between local resource area 1 and local resource area 2 for the original wire net Net2. But this may lead to insufficient partition modules or increased wiring complexity. Therefore, in the following description of this application, only the example of forming a new set of source points and destination points at the cross-local-resource area of the original wire net is used for illustration.

[0059] It can be seen that when using a partition module to insert new wire net endpoints for an original wire net, actually a pair of connection points of the partition module need to be occupied. And a partition module usually can contain multiple pairs of connection points. Therefore, one partition module is used to implement the new wire net endpoints of one original wire net, or one partition module is simultaneously used to implement the new wire net endpoints of multiple original wire nets, and different original wire nets occupy different pairs of connection points of the partition module.

[0060] Generally, there are multiple partition modules between every two adjacent local resource areas. Therefore, when inserting wire net endpoints between these two local resource areas, one of the partition modules needs to be selected as the target partition module. Similarly, since the target partition module includes multiple pairs of connection points, it is actually also necessary to determine which pair of connection points to choose. However, actually the number of pairs of connection points in a target partition module is not too large, and the positions between different input / output ends are relatively close. The differences brought by choosing different connection points are not particularly significant. Moreover, in most cases, one partition module is used to implement the new wire net endpoints of one original wire net. Therefore, after selecting the target partition module, any pair of connection points can be selected to implement the wire net endpoints. Therefore, this application focuses on providing a method for selecting the target partition module from the partition modules between two local resource areas. When determining the target partition module between the i-th level local resource area and the (i + 1)-th level local resource area, it is introduced in the following three categories of situations:

[0061] 1. Determine the target partition module based on the source points in the i-th level local resource area and the reference destination points in the corresponding direction. Among them, the reference destination points in the corresponding direction include the destination points in the original wire nets in the local resource area that is the closest to the i-th level local resource area, or the destination points in the original wire nets in several closest local resource areas, or the destination points in the original wire nets in all subsequent local resource areas.

[0062] The local resource area that is the closest to the i-th level local resource area is not necessarily the (i + 1)-th level local resource area, but refers to the local resource area that contains the destination points in the original wire nets and is the closest to the i-th level local resource area among the subsequent local resource areas of the i-th level local resource area. This is because the (i + 1)-th level local resource area does not necessarily contain the destination points in the original wire nets. For example, for Figure 5For example, when i = 1, the next-level of the local resource area 1, i.e., the local resource area 2, does not contain the destination point in the original wire network. At this time, the local resource area 3 is the local resource area that contains the destination point in the original wire network and is the closest to the i-th level of the local resource area.

[0063] It is possible to use only the destination points in the original wire network within the closest level of the local resource area as the reference destination points in the corresponding direction, or use the destination points in the original wire network within the closest multiple levels of the local resource area as the reference destination points in the corresponding direction, or use the destination points in the original wire network within all the subsequent multiple levels of the local resource area as the reference destination points in the corresponding direction. For example, when i = 1, it is possible to use only T23 and T24 within the local resource area 3 as the reference destination points in the corresponding direction. It is also possible to use T23 and T24 within the local resource area 3 and T22 within the local resource area 4 as the reference destination points in the corresponding direction.

[0064] This type of method includes the following situations:

[0065] (1) For all the partition modules at the boundary between the i-th level of the local resource area and the (i + 1)-th level of the local resource area, respectively determine the partition module that is the closest in distance to the connection line from the source point within the i-th level of the local resource area to each reference destination point as the candidate partition module, and use the candidate partition module that is the closest in distance to the source point within the i-th level of the local resource area or the candidate partition module with the largest number as the target partition module.

[0066] For example, when i = 1, assuming that T23 and T24 within the local resource area 3 and T22 within the local resource area 4 are all used as the reference destination points in the corresponding direction, then determine a candidate partition module A that is the closest to the connection line from S21 to T24, determine a candidate partition module B that is the closest to the connection line from S21 to T23, and it is also candidate partition module B that is the closest to the connection line from S21 to T22. Assuming that the distance between the candidate partition module B and the source point S21 is greater than the distance between the candidate partition module A and the source point S21, then the candidate partition module A can be selected as the target partition module, thus forming a new set of wire network endpoints T25 / S22.

[0067] (2) For all the partition modules at the boundary between the i-th level of the local resource area and the (i + 1)-th level of the local resource area, respectively determine the partition module that is the closest in distance to the connection line from the source point within the i-th level of the local resource area to each reference destination point as the candidate partition module, and use the candidate partition module with the largest number as the target partition module. In the example of case (1) above, the candidate partition module B will be selected as the target partition module.

[0068] (3)For all partition modules at the boundary between the i-th level of local resource area and the (i + 1)-th level of local resource area, determine the partition module with the shortest distance from the center of gravity point formed by the source point in the i-th level of local resource area to each reference destination point as the target partition module.

[0069] For example, when i = 1, assume that T23 and T24 in local resource area 3 and T22 in local resource area 4 are used as reference destination points in their respective directions. First, determine the center of gravity point formed by T22, T23, and T24, and then determine the partition module with the shortest distance from S21 to this center of gravity point as the target partition module.

[0070] Similarly, when i = 2, it is similar. Assume that when i = 2, T23 and T24 in local resource area 3 are used as reference destination points in their respective directions. Then first determine the center of gravity point formed by T23 and T24, and then determine the partition module with the shortest distance from S22 to this center of gravity point as the target partition module.

[0071] (4)For all partition modules at the boundary between the i-th level of local resource area and the (i + 1)-th level of local resource area, determine the partition module with the shortest distance from the source point in the i-th level of local resource area to the predetermined reference destination point as the target partition module.

[0072] Among them, the predetermined reference destination point is the reference destination point with the shortest or longest distance from the source point in the i-th level of local resource area among all reference destination points. For example, when i = 1, assume that T23 and T24 in local resource area 3 and T22 in local resource area 4 are used as reference destination points in their respective directions. T24 is the reference destination point with the shortest distance from S21 among them and is used as the predetermined reference destination point. Then the partition module with the shortest distance from the line connecting S21 and T24 is used as the target partition module.

[0073] Second, determine the target partition module based on the reference destination points in the respective directions. The reference destination points in the respective directions include the destination points in the first-level local resource area closest to the i-th level of local resource area, or the destination points in several levels of local resource areas closest to it, or the destination points in all subsequent local resource areas. The meaning of the reference destination points in the respective directions is similar to that of the first category above, and this application will not elaborate further. The difference from the first category of methods is that the second category of methods no longer considers the source point in the i-th level of local resource area.

[0074] This type of method includes the following situations:

[0075] (1)For all partition modules at the boundary between the i-th level of local resource area and the (i + 1)-th level of local resource area, use the partition module with the smallest total distance sum or the shortest maximum distance from all reference destination points as the target partition module.

[0076] For example, for the case of i = 1, assume that T23 and T24 in the local resource area 3 and T22 in the local resource area 4 are used as the reference target points in their respective directions. At this time, directly calculate the sum of the distances between each partition module at the boundary between the local resource area 1 and the local resource area 2 and T22, T23, and T24 respectively, and then select the one with the smallest total distance or the shortest maximum distance as the target partition module, without considering S21 any more.

[0077] (2) Form a Steiner tree from all the reference target points, and take the partition module closest to a predetermined Steiner node in the Steiner tree formed at the boundary between the i-th level local resource area and the (i + 1)-th level local resource area as the target partition module. The predetermined Steiner node can be any Steiner node and can be customized.

[0078] Third, form a minimum spanning tree in which all the wire net endpoints inside the original wire net are connected in sequence through the Prim algorithm, and take the partition module closest to the edge that spans the current two local resource areas in the minimum spanning tree at the boundary between the i-th level local resource area and the (i + 1)-th level local resource area as the target partition module.

[0079] For example, for the original wire net Net2, the order of each wire net endpoint in the minimum spanning tree formed by connecting the wire net endpoints in sequence through the Prim algorithm is S21, T21, T24, T23, T22. Then, the edge formed between T21 and T24 in the minimum spanning tree spans the local resource area 1 and the local resource area 2, so take the partition module closest to the edge between T21 and T24 between the local resource area 1 and the local resource area 2 as the target partition module. And the edge formed between T21 and T24 in the minimum spanning tree also spans the local resource area 2 and the local resource area 3, so take the partition module closest to the edge between T21 and T24 between the local resource area 2 and the local resource area 3 as the target partition module. The edge formed between T23 and T22 in the minimum spanning tree also spans the local resource area 3 and the local resource area 4, so take the partition module closest to the edge between T23 and T22 between the local resource area 3 and the local resource area 4 as the target partition module.

[0080] In the above various cases, the Manhattan distance can be used when calculating the distance. It should be noted that when splitting an original wire net, when inserting wire net endpoints at the target partition module between different local resource areas, the same method or different methods can be used. For example, when inserting Figure 5 the wire net endpoint group T25 / S22, the first method of the first category described above can be used, and when inserting the wire net endpoint group T26 / S23, the first method of the first category described above can also be used, or it can be changed to use the first method of the second category described above. This application does not make any limitations in this regard.

[0081] Through the above method, a target partition module can be selected between different local resource areas to implement new wire network endpoints. In each local resource area, the source point is connected to and points to the destination point in the local resource area. Thus, a wire network to be routed is formed in each local resource area respectively. Each wire network to be routed includes the part of the original wire network in the current local resource area and the connection relationship formed between the new wire network endpoints formed by the target partition module at the boundary of the current local resource area. The wire networks to be routed corresponding to every two adjacent local resource areas split from an original wire network are connected through a pair of connection points of the target partition module between the two local resource areas by using an internal path. For example, four wire networks to be routed are split from the original wire network Net2, which are the wire network Net2a in the local resource area 1, the wire network Net2b in the local resource area 2, the wire network Net2c in the local resource area 3, and the wire network Net2d in the local resource area 4. The wire network Net2a includes the source point S21 and its respectively connected destination points T21 and T25. The wire network Net2b includes the source point S22 and its connected destination point T26. The wire network Net2c includes the source point S23 and its respectively connected destination points T23, T24 and T27. The wire network Net2d includes the source point S24 and its connected destination point T22. The wire network Net2a and the wire network Net2b are connected through a pair of connection points for realizing T25 / S22. The wire network Net2b and the wire network Net2c are connected through a pair of connection points for realizing T26 / S23. The wire network Net2c and the wire network Net2d are connected through a pair of connection points for realizing T27 / S24.

[0082] 4. Process the wire networks to be routed corresponding to each local resource area in parallel to obtain the routing result of each local resource area, and merge the routing results of each local resource area to obtain the global routing result corresponding to the FPGA.

[0083] Preprocess the original wire network respectively according to the above step 2 or 3 to directly obtain or split to obtain the corresponding wire networks to be routed. After the preprocessing of all original wire networks is completed, the wire networks to be routed in each local resource area can be obtained. For example, in the Figure 5 example, the local resource area 1 contains the wire network to be routed directly obtained from the original wire network Net1 and the wire network Net2a split from the original wire network Net2. The local resource area 2 contains the wire network Net2b split from the original wire network Net2. The local resource area 3 contains the wire network Net2c split from the original wire network Net2. The local resource area 4 contains the wire network Net2d split from the original wire network Net2.

[0084] Then, a multi-core processing platform is utilized to complete the routing task of the FPGA. The number of local resource areas matches the number of processing cores of the multi-core platform, and is not more than the number of processing cores. Each processing core processes the nets to be routed within a local resource area respectively, and the processing cores work in parallel. Due to the processing of this application, each local resource area has its own netlist and routing resource map. Therefore, during parallel routing, the routing results within each local resource area are independent of each other and do not interfere with each other. After routing, the results can be directly merged globally without resolving conflicts for different local resource areas. The operation result is predictable, not affected by the netlist processing order and design environment, suitable for parallel processing of routing, and can effectively improve the routing efficiency and obtain the routing result.

Claims

1. A parallel routing method for partitioning using an FPGA built-in partition module, characterized in that, The FPGA internally includes a partition module that divides programmable logic resources into several local resource areas. The partition module is connected to the surrounding programmable logic resources. The partition module includes several pairs of connection points connected through an internal path. The method includes: Determine the positions of all net endpoints in each original net according to the layout result of the FPGA. The net endpoints include a source point and several destination points respectively connected thereto; Directly use the original net with all net endpoints located in the same local resource area as the net to be routed and correspond it to the local resource area where it is located; Split the original net with net endpoints distributed in at least two different local resource areas into several nets to be routed corresponding to different local resource areas by using the partition module. Each net to be routed includes the part of the original net in the current local resource area and the connection relationship formed between the new net endpoints formed by the target partition module at the boundary of the current local resource area. Each adjacent pair of nets to be routed corresponding to two local resource areas split from one original net are connected through a pair of connection points of the target partition module between the two local resource areas by using the internal path; Process the nets to be routed corresponding to each local resource area in parallel to obtain the routing result of each local resource area, and merge the routing results of each local resource area to obtain the global routing result corresponding to the FPGA; Use the local resource area where the source point in the original net is located as the first-level local resource area, and use the adjacent local resource area in the direction from the source point to the corresponding destination point in the original net of the i-th level local resource area as the (i + 1)-th level local resource area, where i is a parameter and the starting value of i is 1; then the input end of the target partition module between the i-th level local resource area and the (i + 1)-th level local resource area forms a new destination point in the i-th level local resource area, and the corresponding output end forms a new source point in the (i + 1)-th level local resource area. The source points in each level of local resource area are connected to and point to all destination points in the current local resource area.

2. The method according to claim 1, wherein The partition module includes several input ends and several output ends. The input ends are selectively connected to one of the output ends through an internal selection path to form a pair of connection points.

3. The method according to claim 1, characterized in that, One input end of the partition module is directly connected or connected through a buffer to a corresponding output end to form a pair of connection points.

4. The method according to claim 1, wherein The partition modules are arranged in a determinant pattern along the horizontal direction and / or the vertical direction inside the FPGA.

5. The method according to claim 4, characterized in that, The partition module is arranged in the central column of the main trunk of the clock tree of the FPGA.

6. The method according to claim 4, characterized in that, The partition module is arranged at the boundary of the clock domain of the FPGA.

7. The method according to claim 1, characterized in that, The FPGA has a multi-die structure, and partition modules are respectively arranged between the FPGA dies.

8. The method according to claim 1, characterized in that, Partition modules are arranged at all boundaries of a local resource area inside the FPGA, and the local resource area is used to implement a predetermined IP node.

9. The method according to claim 1, wherein One partition module is used to implement the new net endpoints of one original net, or one partition module is simultaneously used to implement the new net endpoints of multiple original nets. Different original nets occupy different pairs of connection points of the partition module.

10. The method according to claim 1, characterized in that, When determining the target partition module between the i-th level local resource area and the (i + 1)-th level local resource area: Determine the target partition module based on the source point in the $i$-th level of local resource area and the reference destination points in the corresponding direction. The reference destination points in the corresponding direction include the destination points in the first-level local resource area closest to the $i$-th level of local resource area, or the destination points in several closest levels of local resource areas, or the destination points in all subsequent levels of local resource areas.

11. The method according to claim 10, wherein The determination of the target partition module based on the source point in the $i$-th level of local resource area and the reference destination points in the corresponding direction includes: For all partition modules at the boundary between the $i$-th level of local resource area and the $(i + 1)$-th level of local resource area, respectively determine the partition module with the shortest distance from the source point in the $i$-th level of local resource area to each reference destination point as the candidate partition module, and take the candidate partition module with the shortest distance from the source point in the $i$-th level of local resource area as the target partition module.

12. The method according to claim 10, wherein The determination of the target partition module based on the source point in the $i$-th level of local resource area and the reference destination points in the corresponding direction includes: For all partition modules at the boundary between the $i$-th level of local resource area and the $(i + 1)$-th level of local resource area, determine the partition module with the shortest distance from the source point in the $i$-th level of local resource area to the centroid point formed by each reference destination point as the target partition module.

13. The method according to claim 10, wherein The determination of the target partition module based on the source point in the $i$-th level of local resource area and the reference destination points in the corresponding direction includes: For all partition modules at the boundary between the $i$-th level of local resource area and the $(i + 1)$-th level of local resource area, determine the partition module with the shortest distance from the source point in the $i$-th level of local resource area to the predetermined reference destination point as the target partition module. The predetermined reference destination point is the reference destination point with the shortest or longest distance from the source point in the $i$-th level of local resource area among all reference destination points.

14. The method according to claim 1, wherein When determining the target partition module between the $i$-th level of local resource area and the $(i + 1)$-th level of local resource area: Determine the target partition module based on the reference destination points in the corresponding direction; the reference destination points in the corresponding direction include the destination points in the first-level local resource area closest to the $i$-th level of local resource area, or the destination points in several closest levels of local resource areas, or the destination points in all subsequent levels of local resource areas.

15. The method according to claim 14, wherein The determination of the target partition module based on the reference destination points in the corresponding direction includes: For all partition modules at the boundary between the $i$-th level of local resource area and the $(i + 1)$-th level of local resource area, take the partition module with the minimum total distance to all reference destination points or the shortest maximum distance as the target partition module.

16. The method according to claim 14, wherein The determination of the target partition module based on the reference destination points in the corresponding direction includes: Form a Steiner tree from all reference destination points, and take the partition module at the boundary between the $i$-th level of local resource area and the $(i + 1)$-th level of local resource area with the shortest distance to a predetermined Steiner node in the formed Steiner tree as the target partition module.

17. The method according to claim 1, wherein When determining the target partition module between the $i$-th level of local resource area and the $(i + 1)$-th level of local resource area: For all the net endpoints inside the original net, a minimum spanning tree in which the net endpoints are connected in sequence is formed through the Prim algorithm, and the partition module closest to the edge that spans the current two local resource areas in the minimum spanning tree at the boundary between the i-th level local resource area and the (i + 1)-th level local resource area is used as the target partition module.

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