Direct testing of encapsulated memories

Abstract

This application relates to direct testing of memory within a package. A memory subsystem package can include non-volatile memory, volatile memory that can be configured as cache memory, and a controller. The memory subsystem can support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem can forward commands received from a host device (e.g., an automated test equipment) to a memory interface of the non-volatile memory and bypass cache-related circuitry when operating in a test mode enabled. The memory subsystem can include separate conductive paths that bypass the cache memory for forwarding commands and addresses to the memory interface during testing.

Description

[0001] Cross reference

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 042,955, titled “DIRECT TESTING FOR IN-PACKAGE MEMORY,” filed June 23, 2020, in the name of Song, et al., and U.S. Patent Application No. 17 / 349,612, titled “DIRECT TESTING FOR IN-PACKAGE MEMORY,” filed June 16, 2021, in the name of Song, et al., each of which is assigned to the present assignee and each of which is hereby expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The technical field relates to direct testing for in-package memory. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically denoted by a logic 1 or a logic 0. In some examples, an individual memory cell can support more than two states, any one of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, and the like. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0006] An apparatus is described. The apparatus may include: a memory array; an interface controller coupled to the memory array and configured such that the apparatus: determines whether to enable a first mode of the apparatus; disables a cache memory circuitry of the apparatus at least in part based on the determination that the first mode is enabled; receives one or more commands associated with a first address having a first bit quantity from a host device after disabling the cache memory circuitry; generates a second address having a second bit quantity, greater than the first bit quantity, at least in part based on the first address; and performs an access operation on the memory array at least in part based on the generation of the second address.

[0007] A device is described. The device may include: a memory cell array; and an interface controller coupled to the memory cell array, the interface controller including: a host interface configured to receive commands from a host device; a cache memory management circuitry coupled to a decoder; and a memory interface circuitry coupled to both the cache memory management circuitry and the decoder, the memory interface circuitry being configured to access the memory cell array based on the commands received from the host device, wherein the interface controller is configured such that the device: receives commands from the host device, determines whether to enable a first operating mode of the device, and provides the commands directly to the memory interface circuitry via a bypass path, at least in part based on the determination that the first operating mode is enabled.

[0008] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: determine whether to enable a first mode of the device; disable a cache memory circuitry of the device at least in part based on the determination that the first mode is enabled; receive one or more commands associated with a first address having a first bit quantity from a host device after disabling the cache memory circuitry; generate a second address having a second bit quantity, greater than the first bit quantity, at least in part based on the first address; and perform an access operation on a memory array of the electronic device at least in part based on the generation of the second address. Attached Figure Description

[0009] Figure 1 The diagram illustrates an example of a system according to the invention that includes a system supporting direct testing of in-package memory.

[0010] Figure 2 This describes an exemplary system or subsystem that supports direct testing of packaged internal memory according to an example of the present invention.

[0011] Figure 3 This describes an exemplary system or subsystem that supports direct testing of packaged internal memory according to an example of the present invention.

[0012] Figure 4 This describes an exemplary process flow that supports direct testing of packaged internal memory according to an example of the present invention.

[0013] Figure 5 A block diagram of a memory device according to an embodiment of the present invention supports direct testing of in-package memory.

[0014] Figure 6 The flowchart illustrates one or more methods for supporting direct testing of packaged in-memory memory, according to examples of the present invention. Detailed Implementation

[0015] Memory dies within a package can be tested by providing test signals to the package to read data from or write data to the memory die. In some cases, such memory packages may include one or more external electrical contacts, such as ball bearings or other types of contacts, that provide direct access to the memory die and can be used to receive and transmit test signals from a test apparatus, such as an automated test equipment (ATE), for testing the memory die.

[0016] In some instances, a single package may contain a memory subsystem comprising a controller and one or more memory dies, along with other circuitry. The memory subsystem may support testing of the memory dies within the package by transmitting signals via an ATE using a host interface (e.g., a standardized I / O interface) included in the package, such as a Low Power Dual Data Rate (LPDDR) interface, instead of using dedicated electrical contacts. For example, the controller may receive test commands from the ATE (e.g., using the host interface), facilitating or inducing corresponding operations to be performed on the memory die, and providing output signals to the ATE (e.g., using the host interface). This approach can reduce the number of contacts on the package, or the number of pins on the memory die, or free up such contacts or pins for other uses.

[0017] In some instances, the memory subsystem may include cache memory circuitry (e.g., a separate memory die operating as a cache within the subsystem) to accelerate memory access. Such cache memory circuitry may introduce timing or data uncertainties into memory access operations, which may be undesirable during test operations. Therefore, in some cases, it may be necessary to directly test the functionality of the memory die within the subsystem (e.g., while avoiding the effects of the cache or other various features of the memory subsystem). In some instances, cache-related features and / or some or all of other features of the memory subsystem may be bypassed during test operations to provide ordered command operations without invalid data returns, deterministic latency, and gapless (e.g., sequential, without intervention in clock cycles or operations) access to the memory die during test operations. For example, to bypass the cache during test operations, the controller may forward commands received from the ATE to a memory interface coupled to the memory die without using cache features or circuitry, such as using conductive paths that bypass the cache memory circuitry.

[0018] In some instances, the memory die of the memory subsystem may contain a type of memory that uses a different communication protocol than that used by an interface, such as the host interface of the memory subsystem (e.g., a standardized I / O interface). For example, the memory die may be configured to use a single bit quantity to specify a row address, and the host interface may be configured or specified to receive a different number of bits to specify a row address (e.g., to activate a row of memory). For example, an 8GB FeRAM memory may use a total of 28 bits to activate a row (including bits specifying the group of FeRAM), but the memory subsystem may receive only 22 total address bits when receiving an activation command from an ATE using the host interface. Therefore, in some cases, the memory subsystem may perform protocol conversion of signals received via the host interface to convert row addresses or other communication parameters into a format suitable for the memory die.

[0019] In some instances, bypassing some or all of the cache-related features of the memory subsystem may also bypass some or all of the circuitry used for protocol conversion. Furthermore, testing the memory die via a standardized interface of the memory subsystem, rather than directly (e.g., using dedicated contacts), may introduce timing delays or other differences compared to directly testing the memory die. Therefore, the memory subsystem may include various features to perform protocol conversion and / or timing adjustments during test operations. For example, the memory subsystem may combine forwarding commands to the memory interface for test operations with appending extra bits to the row address received from the ATE to generate a row address suitable for the memory die by appending values ​​stored in the memory subsystem's registers. Other operations may also be performed by the memory subsystem during test operations to compensate for changes in the timing or behavior of the memory die or memory subsystem during test operations relative to the timing and behavior that the ATE may expect (e.g., when the cache is enabled, or when testing the memory die using dedicated contacts without a controller).

[0020] First, as referenced Figure 1 , 2 The features of the invention are described in the context of the systems and subsystems described in reference 3. Figure 4 The features of the invention are described within the context of the process flow described. These and other features of the invention are further illustrated and described with reference to device diagrams and one or more flowcharts relating to, as referenced... Figure 5 and 6 Direct testing of the packaged internal memory as described.

[0021] Figure 1 This document describes an example of a system 100 that supports direct testing of in-package memory, based on examples disclosed herein. System 100 may be contained in an electronic device, such as a computer or telephone. System 100 may include a host device 105 and a memory subsystem 110. Host device 105 may be a processor or system-on-a-chip (SoC) that interfaces with interface controller 115 and other components of the electronic device containing system 100. Memory subsystem 110 may store and provide access to electronic information (e.g., digital information, data) for host device 105. Memory subsystem 110 may include interface controller 115, volatile memory 120, and non-volatile memory 125. In some instances, interface controller 115, volatile memory 120, and non-volatile memory 125 may be contained in the same physical package, such as package 130. However, interface controller 115, volatile memory 120, and non-volatile memory 125 may be disposed on different, corresponding dies (e.g., silicon dies).

[0022] Devices in system 100 can be coupled via various wires (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring), which enables the transmission of information (e.g., commands, addresses, data) between devices. Wires can form channels, data buses, command buses, address buses, and the like.

[0023] The memory subsystem 110 can be configured to provide the advantages of non-volatile memory 125 while maintaining compatibility with host device 105, which supports protocols for different types of memory, such as volatile memory 120, and other instances. For example, non-volatile memory 125 can offer advantages (e.g., compared to volatile memory 120), such as non-volatility, higher capacity, or lower power consumption. However, host device 105 may be incompatible with or inefficiently configured with various aspects of non-volatile memory 125. For example, host device 105 may support voltage, access latency, protocols, page sizes, etc., that are incompatible with non-volatile memory 125. To compensate for the incompatibility between host device 105 and non-volatile memory 125, memory subsystem 110 may be configured with volatile memory 120, which can be compatible with host device 105 and act as a cache memory for non-volatile memory 125. Therefore, host device 105 can use the protocols supported by volatile memory 120 while also benefiting from the advantages of non-volatile memory 125.

[0024] In some instances, system 100 may be contained in, or coupled to, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, or the like. In some instances, the device may be configured for bidirectional wireless communication via a base station or access point. In some instances, the device associated with system 100 may be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some instances, the device associated with system 100 may be referred to as user equipment (UE), station (STA), mobile terminal, or the like.

[0025] Host device 105 may be configured to interface with memory subsystem 110 using a first protocol (e.g., LPDDR) supported by interface controller 115. Therefore, in some instances, host device 105 may interface directly with interface controller 115 and indirectly with non-volatile memory 125 and volatile memory 120. In alternative instances, host device 105 may interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 may also interface with other components of the electronic device comprising system 100. Host device 105 may be or include a SoC, general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In some instances, host device 105 may be referred to as a host. In some instances, host device 105 may represent or include ATE and may execute test programs on non-volatile memory 125 and / or volatile memory 120.

[0026] Interface controller 115 can be configured to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105 (e.g., based on one or more commands or requests issued by host device 105). For example, interface controller 115 can facilitate the retrieval and storage of data in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Therefore, interface controller 115 can facilitate data transfer between various sub-components, such as between at least some of host device 105, volatile memory 120, or non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol and with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0027] Non-volatile memory 125 may be configured to store digital information (e.g., data) for use in electronic devices including system 100. Therefore, non-volatile memory 125 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include FeRAM cells (e.g., non-volatile memory 125 may be FeRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a second protocol different from the first protocol used between interface controller 115 and host device 105. In some instances, non-volatile memory 125 may have a longer latency for access operations compared to volatile memory 120. For example, retrieving data from non-volatile memory 125 may take longer than retrieving data from volatile memory 120. Similarly, writing data to non-volatile memory 125 may take longer than writing data to volatile memory 120. In some instances, non-volatile memory 125 may have a smaller page size compared to volatile memory 120, as described herein.

[0028] Volatile memory 120 may be configured to operate as a cache memory for one or more components, such as non-volatile memory 125. For example, volatile memory 120 may store information (e.g., data) for an electronic device containing system 100. Therefore, volatile memory 120 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a first protocol used between interface controller 115 and host device 105.

[0029] In some instances, volatile memory 120 may have a shorter latency for access operations compared to non-volatile memory 125. For example, retrieving data from volatile memory 120 may take less time compared to retrieving data from non-volatile memory 125. Similarly, writing data to volatile memory 120 may take less time compared to writing data to non-volatile memory 125. In some instances, volatile memory 120 may have a larger page size compared to non-volatile memory 125. For example, the page size of volatile memory 120 may be 2 kilobytes (2kB) and the page size of non-volatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0030] While non-volatile memory 125 may be a higher-density memory compared to volatile memory 120, accessing non-volatile memory 125 may take longer than accessing volatile memory 120 (e.g., due to different architectures and protocols, and other reasons). Therefore, operating volatile memory 120 as a cache memory can reduce latency in system 100. As an example, access requests for data from host device 105 can be satisfied relatively quickly by retrieving data from volatile memory 120 instead of from non-volatile memory 125. To facilitate the operation of volatile memory 120 as a cache memory, interface controller 115 may include multiple buffers 135. Buffers 135 may be disposed on the same die as interface controller 115 and may be configured to temporarily store data for transfer between volatile memory 120, non-volatile memory 125, or host device 105 (or any combination thereof) during one or more access operations (e.g., store and retrieve operations).

[0031] Access operations may also be referred to as access procedures or access routines and may involve one or more sub-operations performed by one or more components of the memory subsystem 110. Examples of access operations may include: a storage operation in which data provided by the host device 105 is stored (e.g., written to) volatile memory 120 or non-volatile memory 125 (or both); and a retrieval operation in which data requested by the host device 105 is obtained (e.g., read) from volatile memory 120 or non-volatile memory 125 and returned to the host device 105.

[0032] To store data in memory subsystem 110, host device 105 can initiate a storage operation (or “stored procedure”) by issuing a storage command (also referred to as a storage request, write command, or write request) to interface controller 115. The storage command can target a set of non-volatile memory cells in non-volatile memory 125. In some instances, the set of memory cells may also be referred to as a portion of memory. Host device 105 can also provide data to be written to the set of non-volatile memory cells to interface controller 115. Interface controller 115 can temporarily store the data in buffer 135-a. After storing the data in buffer 135-a, interface controller 115 can transfer the data from buffer 135-a to volatile memory 120 or non-volatile memory 125, or both. In write-through mode, interface controller 115 can transfer data to both volatile memory 120 and non-volatile memory 125. In write-back mode, the interface controller 115 may transfer only the data to the volatile memory 120.

[0033] In either mode, interface controller 115 may identify an appropriate set of one or more volatile memory cells in volatile memory 120 for storing data associated with a store command. To do this, interface controller 115 may implement set-association mapping, where each set (e.g., a block) of one or more non-volatile memory cells in non-volatile memory 125 may be mapped to multiple sets of volatile memory cells in volatile memory 120. For example, interface controller 115 may implement an n-way associative mapping, which allows data from a set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in volatile memory 120. Thus, interface controller 115 may manage volatile memory 120 as a cache for non-volatile memory 125 by referencing n sets of volatile memory cells associated with a target set of non-volatile memory cells. As used herein, unless otherwise described or mentioned, a “set” of objects may refer to one or more of objects. Although described in relation to a set of associated mappings, the interface controller 115 can manage the volatile memory 120 as a cache memory by implementing one or more other types of mappings, such as direct mappings or associated mappings, and other instances.

[0034] After determining which n sets of volatile memory cells are associated with the target set of non-volatile memory cells, the interface controller 115 can store data in one or more of the n sets of volatile memory cells. Therefore, subsequent retrieval commands for data from the host device 105 can be efficiently satisfied by retrieving data from the lower-latency volatile memory 120 instead of from the higher-latency non-volatile memory 125. The interface controller 115 can determine which of the n sets of volatile memory 120 to store data based on one or more parameters associated with the data stored in the n sets of volatile memory 120, such as validity, age, or data modification status. Therefore, storage commands from the host device 105 can be satisfied fully (e.g., in write-back mode) or partially (e.g., in write-through mode) by storing data in volatile memory 120. In order to track data stored in volatile memory 120, interface controller 115 may store tag addresses for one or more sets of volatile memory cells (e.g., each set of volatile memory cells), the tag addresses indicating non-volatile memory cells with data stored in a given set of volatile memory cells.

[0035] To retrieve data from memory subsystem 110, host device 105 may initiate a retrieval operation (also referred to as a retrieval process) by sending a retrieval command (also referred to as a retrieval request, read command, or read request) to interface controller 115. The retrieval command may target one or more sets of non-volatile memory cells in non-volatile memory 125. Upon receiving the retrieval command, interface controller 115 may examine the requested data in volatile memory 120. For example, interface controller 115 may examine the requested data in n sets of volatile memory cells associated with the target set of non-volatile memory cells. If the requested data is stored in one of the n sets of volatile memory cells (e.g., data is stored for the target set of non-volatile memory cells), then interface controller 115 may transfer the data from volatile memory 120 to buffer 135-a (e.g., in response to determining that the requested data is stored in one of the n sets of volatile memory cells) so that it can be sent to host device 105. The term "hit" can be used to refer to a scenario where volatile memory 120 stores data requested by host device 105. If a set of n volatile memory cells does not store the requested data (e.g., the set of n volatile memory cells stores data as a set of non-volatile memory cells, except for the target set of volatile memory cells), then interface controller 115 may transfer the requested data from non-volatile memory 125 to buffer 135-a (e.g., in response to determining that the set of n volatile memory cells does not store the requested data) so that it can be transmitted to host device 105. The term "miss" can be used to refer to a scenario where volatile memory 120 does not store data requested by host device 105.

[0036] In a missed data scenario, after transferring the requested data to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120, so that subsequent read requests for the data can be satisfied through volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store data in one of n sets of volatile memory cells associated with a target set of non-volatile memory cells. However, the n sets of volatile memory cells may already contain data for other sets of non-volatile memory cells. Therefore, to retain this other data, interface controller 115 may transfer the other data to buffer 135-b so that it can be transferred to non-volatile memory 125 for storage. This process may be referred to as "retrieval," and the data transferred from volatile memory 120 to buffer 135-b may be referred to as "victimized" data. In some cases, interface controller 115 may transfer a subset of the victimized data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 may transmit one or more subsets of victim data that has been altered because the data was initially stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to an update in one memory but not in another) may, in some cases, be referred to as “modified” or “dirty” data. In some instances (e.g., when the interface controller is operating in a mode such as write-back mode), dirty data may be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0037] As described herein, memory subsystem 110 may include various features or circuitry (e.g., volatile memory 120, buffer 135-a, buffer 135-b, and / or other components of memory subsystem 110) for bypassing cache memory and associated circuitry during test operations.

[0038] Figure 2 This describes an example of a memory subsystem 200 that supports direct testing of packaged in-system memory, based on examples disclosed herein. The memory subsystem 200 may be a reference. Figure 1 An example of the described memory subsystem 110. Therefore, the memory subsystem 200 can be compared with, as referenced... Figure 1 The host device interaction is described. The memory subsystem 200 may include an interface controller 202, volatile memory 204, and non-volatile memory 206, which may be instances of interface controller 115, volatile memory 120, and non-volatile memory 125, as referenced. Figure 1 As described. Therefore, the interface controller 202 can represent as referenced.Figure 1 The described host device interfaces with volatile memory 204 and non-volatile memory 206. For example, interface controller 202 can operate volatile memory 204 as a cache for non-volatile memory 206. Operating volatile memory 204 as a cache allows the subsystem to provide the advantages of non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with the host device, which supports different protocols compared to non-volatile memory 206.

[0039] exist Figure 2 In this diagram, dashed lines between components represent data flows or data transmission paths, while solid lines between components represent command flows or command transmission paths. In some cases, the memory subsystem 200 is one of several similar or identical subsystems that can be included in an electronic device. Each subsystem may be referred to as a slice and, in some instances, may be associated with a corresponding channel of the host device.

[0040] Non-volatile memory 206 can be configured to operate as main memory for a host device (e.g., memory for long-term data storage). In some cases, non-volatile memory 206 may comprise one or more arrays of FeRAM cells. Each FeRAM cell may include a select element and a ferroelectric capacitor and can be accessed by applying appropriate voltages to one or more access lines, such as word lines, board lines, and digital lines. In some instances, a subset of FeRAM cells coupled to an active word line can be sensed, for example, in parallel or simultaneously, without having to sense all FeRAM cells coupled to an active word line. Therefore, the page size for the FeRAM array may be different from (e.g., smaller than) the DRAM page size. In the context of a memory device, a page may refer to a row of memory cells (e.g., a group of memory cells with a common row address), and the page size may refer to the number of memory cells or column addresses in a row, or the number of column addresses accessed during an access operation. Alternatively, the page size may refer to the size of data processed by various interfaces. In some cases, different memory device types may have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0041] The smaller page size of FeRAM arrays offers various efficiency advantages because individual FeRAM cells may require more power to read or write compared to individual DRAM cells. For example, the smaller page size for FeRAM arrays facilitates efficient energy use because a smaller number of FeRAM cells can be activated at minute intervals to correlated changes in information. In some instances, the page size of the array of FeRAM cells can vary, for example, dynamically (e.g., during operation of the FeRAM cell array), depending on the nature of the data and commands used for FeRAM operations.

[0042] While individual FeRAM cells may require more power to read or write compared to individual DRAM cells, FeRAM cells can maintain their stored logic states for extended periods in the absence of an external power supply because the ferroelectric material in the FeRAM cell can maintain a non-zero polarization in the absence of an electric field. Therefore, including an FeRAM array in non-volatile memory 206 can provide an efficiency advantage over volatile memory cells (e.g., DRAM cells in volatile memory 204) because it reduces or eliminates the need to perform refresh operations.

[0043] Volatile memory 204 can be configured to operate as a cache memory for non-volatile memory 206. In some cases, volatile memory 204 may comprise one or more arrays of DRAM cells. Each DRAM cell may include a capacitor containing dielectric material to store charge representing a programmable state. The memory cells of volatile memory 204 may be logically grouped or arranged into one or more memory groups (as referred to herein as “groups”). For example, volatile memory 204 may comprise sixteen groups. The memory cells of a group may be arranged in a grid or an array of intersecting columns and rows, and each memory cell can be accessed or refreshed by applying an appropriate voltage to the digital lines (e.g., column lines) and word lines (e.g., row lines) for that memory cell. A row of a group may be referred to as a page, and the page size may refer to the number of columns or memory cells in a row. As mentioned, the page size of volatile memory 204 may be different from (e.g., larger than) the page size of non-volatile memory 206.

[0044] Interface controller 202 may include various circuitry for interfacing (e.g., communicating) with other devices, such as host devices, volatile memory 204, and non-volatile memory 206. For example, interface controller 202 may include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support the transmission of information using one or more transmission protocols. For example, data bus interface 208, C / A bus interface 210, data bus interface 216, and C / A bus interface 264 may support information transmitted using a first protocol (e.g., LPDDR signaling), while data bus interface 212 and C / A bus interface 214 may support information transmitted using a second protocol. Therefore, the various bus interfaces coupled to interface controller 202 may support different data volumes or data rates.

[0045] Data bus interface 208 can be coupled to data bus 260, transaction bus 222, and buffer circuitry system 224. Data bus interface 208 can be configured to transmit and receive data on data bus 260 and to transmit and receive control information (e.g., acknowledgment / negative acknowledgment) or metadata on transaction bus 222. Data bus interface 208 can also be configured to transfer data between data bus 260 and buffer circuitry system 224. Data bus 260 and transaction bus 222 can be coupled to interface controller 202 and host device to establish a conductive path between interface controller 202 and host device. In some instances, the pin of transaction bus 222 may be referred to as a Data Mask Inversion (DMI) pin. Although shown as having one data bus 260 and one transaction bus 222, any number of data buses 260 and any number of transaction buses 222 may be coupled to one or more data bus interfaces 208.

[0046] C / A bus interface 210 can be coupled to C / A bus 226 and decoder 228. C / A bus interface 210 can be configured to transmit and receive commands and addresses on C / A bus 226. Commands and addresses received on C / A bus 226 can be associated with data received or transmitted on data bus 260. C / A bus interface 210 can also be configured to transmit commands and addresses to decoder 228, enabling decoder 228 to decode the commands and forward the decoded commands and associated addresses to command circuitry system 230.

[0047] Data bus interface 212 can be coupled to data bus 232 and memory interface circuitry 234. Data bus interface 212 can be configured to transmit and receive data on data bus 232, which can be coupled to non-volatile memory 206. Data bus interface 212 can also be configured to transfer data between data bus 232 and memory interface circuitry 234. C / A bus interface 214 can be coupled to C / A bus 236 and memory interface circuitry 234. C / A bus interface 214 can be configured to receive commands and addresses from memory interface circuitry 234 and forward commands and addresses on C / A bus 236 to non-volatile memory 206 (e.g., to a local controller of non-volatile memory 206). Commands and addresses transmitted on C / A bus 236 can be associated with data received or transmitted on data bus 232. The data bus 232 and the C / A bus 236 can be coupled to the interface controller 202 and the non-volatile memory 206, so that a conductive path is established between the interface controller 202 and the non-volatile memory 206.

[0048] Data bus interface 216 can be coupled to data bus 238 and memory interface circuitry 240. Data bus interface 216 can be configured to transmit and receive data on data bus 238, which can be coupled to volatile memory 204. Data bus interface 216 can also be configured to transfer data between data bus 238 and memory interface circuitry 240. C / A bus interface 264 can be coupled to C / A bus 242 and memory interface circuitry 240. C / A bus interface 264 can be configured to receive commands and addresses from memory interface circuitry 240 and forward commands and addresses on C / A bus 242 to volatile memory 204 (e.g., to a local controller of volatile memory 204). Commands and addresses transmitted on C / A bus 242 can be associated with data received or transmitted on data bus 238. The data bus 238 and the C / A bus 242 can be coupled to the interface controller 202 and the volatile memory 204, so that a conductive path is established between the interface controller 202 and the volatile memory 204.

[0049] In addition to the bus and bus interface for communicating with the coupled devices, the interface controller 202 may also include circuitry for operating the non-volatile memory 206 as main memory and the volatile memory 204 as cache memory. For example, the interface controller 202 may include command circuitry 230, buffer circuitry 224, cache memory management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0050] Command circuitry system 230 may be coupled to buffer circuitry system 224, decoder 228, cache memory management circuitry system 244, scheduler 248, and other components. Command circuitry system 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry system 230 may include logic 262 that processes command information (e.g., from a host device) and stores information from other components (e.g., cache memory management circuitry system 244, buffer circuitry system 224) and uses this information to generate one or more commands for scheduler 248. Command circuitry system 230 may also be configured to transmit address information (e.g., address bits) to cache memory management circuitry system 244. In some instances, logic 2622 may be a circuit configured to operate as a finite state machine (FSM).

[0051] Buffer circuitry system 224 may be coupled to data bus interface 208, command circuitry system 230, memory interface circuitry system 234, and memory interface circuitry system 234. Buffer circuitry system 224 may include a collection of one or more buffer circuits for at least some groups (if not every group) of volatile memory 204. Buffer circuitry system 224 may also include components for accessing the buffer circuits (e.g., a memory controller). In one example, volatile memory 204 may comprise sixteen groups, and buffer circuitry system 224 may comprise sixteen collections of buffer circuits. Each collection of buffer circuits may be configured to store data from or for a corresponding group of volatile memory 204 (or both). As an example, the buffer circuitry for group 0 (BK0) may be configured to store data from or for the first group of volatile memory 204 (or both), and the buffer circuitry for group 15 (BK15) may be configured to store data from or for the sixteenth group of volatile memory 204 (or both).

[0052] Each set of buffer circuits in buffer circuit system 224 may include a pair of buffers. The pair of buffers may include: one buffer (e.g., an open page data (OPD) buffer) configured to store data targeted by an access command (e.g., a store command or retrieval command) from the host device; and another buffer (e.g., a victim page data (VPD) buffer) configured to store data for a retrieval process triggered by the access command. For example, the set of buffer circuits for BK0 may include buffers 218 and 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from the host device. And buffer 220 may be configured to store data transferred from BK0 as part of a retrieval process triggered by the access command. Each buffer in the set of buffer circuits may be configured with a size (e.g., storage capacity) corresponding to the page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2kB, then the size of each buffer can be 2kB. Therefore, in some instances, the size of the buffer can be equivalent to the page size of volatile memory 204.

[0053] The cache memory management circuitry system 244 may be coupled to the command circuitry system 230, the engine 246, and the scheduler 248, as well as other components. The cache memory management circuitry system 244 may include sets of cache memory management circuitry for one or more groups (e.g., each group) of volatile memory. As an example, the cache memory management circuitry system 244 may include sixteen sets of cache memory management circuitry for BK0 through BK15. Each set of cache memory management circuitry may include two memory arrays configured to store storage information for volatile memory 204. As an example, the set of cache memory management circuitry for BK0 may include memory array 252 (e.g., a CDRAM tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM active (CDT-V) array), configured to store storage information for BK0. In some instances, the memory array may also be referred to as an array or a buffer. In some cases, the memory array may be or contain volatile memory cells, such as SRAM cells.

[0054] The stored information may include content information, validity information, or dirty information (or any combination thereof) associated with volatile memory 204. Content information (which may also be referred to as tagging information or address information) may indicate which data is stored in a set of volatile memory cells. For example, content information (e.g., tagging addresses) for a set of one or more volatile memory cells may indicate which set of one or more non-volatile memory cells currently has data stored in that set of one or more volatile memory cells. Validity information may indicate whether the data stored in the set of volatile memory cells is actual data (e.g., data with an expected order or form) or placeholder data (e.g., random or dummy data that does not have an expected or significant order). Dirty information may indicate whether the data stored in the set of one or more volatile memory cells of volatile memory 204 is different from the corresponding data stored in the set of one or more non-volatile memory cells of non-volatile memory 206. For example, dirty information can indicate whether data stored in the set of volatile memory cells has been updated relative to data stored in non-volatile memory 206.

[0055] Memory array 252 may include memory cells that store storage information (e.g., content and validity information) for an associated group (e.g., BK0) of volatile memory 204. The storage information may be stored on a per-page basis (e.g., there may be corresponding storage information for each page of an associated non-volatile memory group). Interface controller 202 may examine requested data in volatile memory 204 by referencing the storage information in memory array 252. For example, interface controller 202 may receive a retrieval command from a host device for data in a set of non-volatile memory cells in non-volatile memory 206. Interface controller 202 may use a set of one or more address bits (e.g., a set of row address bits) targeted by the access request to refer to the storage information in memory array 252. For example, using set-association mapping, interface controller 202 may refer to content information in memory array 252 to determine which set of volatile memory cells (if present) stores the requested data.

[0056] In addition to storing content information for the volatile memory cells, memory array 252 may also store validity information indicating whether data in a set of volatile memory cells is actual data (also called valid data) or random data (also called invalid data). For example, a volatile memory cell in volatile memory 204 may initially store random data and continue doing so until data is written to the volatile memory cell from a host device or non-volatile memory 206. To track which data is valid, memory array 252 may be configured to set a bit for each set of volatile memory cells when actual data is stored in that set. This bit may be called a validity bit or validity flag. Like content information, validity information stored in memory array 252 may be stored on a per-page basis. Therefore, in some instances, each validity bit may indicate the validity of data stored in the associated page.

[0057] Memory array 254 may be similar to memory array 252 and may also include memory cells that store validity information for a group (e.g., BK0) of volatile memory 204 associated with memory array 252. However, instead of a per-page basis for memory array 252, validity information stored in memory array 254 may be stored on a sub-block basis. For example, validity information stored in memory cells of memory array 254 may indicate the validity of data for a subset of volatile memory cells in a set of volatile memory cells (e.g., pages). As an example, validity information in memory array 254 may indicate the validity of each subset (e.g., 64B) of data in a data page stored in BK0 of volatile memory 204. Storing content information and validity information on a per-page basis in memory array 252 allows interface controller 202 to quickly and efficiently determine whether there are data hits or misses in volatile memory 204. The sub-block-based storage validity information allows the interface controller 202 to determine which subsets of data are retained in the non-volatile memory 206 during the repossession process.

[0058] Each cache management circuitry may also include corresponding pairs of registers coupled to command circuitry 230, engine 246, memory interface circuitry 234, memory interface circuitry 240, and the memory array for the cache management circuitry, as well as other components. For example, the cache management circuitry may include a first register (e.g., register 256, which may be an Open Page Mark (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirty information) from memory array 252 or scheduler 248-b, or both. The cache management circuitry may also include a second register (e.g., register 258, which may be a Victim Page Mark (VPT) register) configured to receive storage information from memory array 254 and scheduler 248-a, or both. Information in registers 256 and 258 may be transmitted to command circuitry 230 and engine 246 to enable decision-making through these components. For example, the command circuit system 230 can issue commands to read non-volatile memory 206 or volatile memory 204 based on content information from register 256.

[0059] Engine 246-a can be coupled to registers 256 and 258 and scheduler 248. Engine 246-a can be configured to receive stored information from various components and issue commands to scheduler 248 based on the stored information. For example, when interface controller 202 is in a first mode, such as write-through mode, engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b can initiate or facilitate data transfer from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, when interface controller 202 is in a second mode, such as write-back mode, engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b can initiate or facilitate data transfer from buffer 218 to volatile memory 204. In the case of a write-back operation, data stored in volatile memory 204 during a subsequent recovery process can eventually be transferred to non-volatile memory 206.

[0060] Engine 246-b can be coupled to register 258 and scheduler 248-a. Engine 246-b can be configured to receive stored information from register 258 and issue commands to scheduler 248-a based on the stored information. For example, engine 246-b may issue commands to scheduler 248-a to initiate or facilitate the transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of a retrieval process). If buffer 220 holds a set of data transferred from volatile memory 204 (e.g., damaged data), then engine 246-b can indicate which one or more subsets (e.g., which 64Bs) of the set of data in buffer 220 should be transferred to non-volatile memory 206.

[0061] Scheduler 248-a can be coupled to various components of interface controller 202 and can facilitate access to non-volatile memory 206 by issuing commands to memory interface circuitry system 234. Commands issued by scheduler 248-a can be based on commands from command circuitry system 230, engine 246-a, engine 246-b, or a combination of these components. Similarly, scheduler 248-b can be coupled to various components of interface controller 202 and can facilitate access to volatile memory 204 by issuing commands to memory interface circuitry system 240. Commands issued by scheduler 248-b can be based on commands from command circuitry system 230 or engine 246-a, or both.

[0062] The memory interface circuitry 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 can prompt the C / A bus interface 214 to forward commands issued by the memory interface circuitry 234 on the C / A bus 236 to a local controller in the non-volatile memory 206. Furthermore, the memory interface circuitry 234 can transmit data to or receive data from the non-volatile memory 206 on the data bus 232. In some instances, commands issued by the memory interface circuitry 234 can be supported by the non-volatile memory 206 rather than the non-volatile memory 204 (e.g., commands issued by the memory interface circuitry 234 can be different from commands issued by the memory interface circuitry 240).

[0063] The memory interface circuitry 240 can communicate with the volatile memory 204 via one or more of the data bus interface 216 and the C / A bus interface 264. For example, the memory interface circuitry 240 can prompt the C / A bus interface 264 to forward commands issued by the memory interface circuitry 240 to the local controller of the volatile memory 204 on the C / A bus 242. Furthermore, the memory interface circuitry 240 can transmit data to or receive data from the volatile memory 204 on one or more data buses 238. In some instances, commands issued by the memory interface circuitry 240 may be supported by the volatile memory 204 instead of the non-volatile memory 206 (e.g., commands issued by the memory interface circuitry 240 may differ from commands issued by the memory interface circuitry 234).

[0064] In summary, the components of interface controller 202 can operate non-volatile memory 206 as main memory and volatile memory 204 as cache memory. Such operations can be prompted by one or more access commands (e.g., read / retrieve commands / requests and write / store commands / requests) received from the host device.

[0065] In some instances, interface controller 202 may receive a store command from a host device. The store command may be received on C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The store command may include or be accompanied by address bits targeting a memory address of non-volatile memory 206. Data to be stored may be received on data bus 260 and transmitted to buffer 218 via data bus interface 208. In write-through mode, interface controller 202 may transmit data to both non-volatile memory 206 and volatile memory 204. In write-back mode, interface controller 202 may transmit data only to volatile memory 204. In either mode, interface controller 202 may first check to determine if volatile memory 204 has memory cells available for storing data. To do this, command circuitry 230 may refer to memory array 252 (e.g., using a set of memory address bits) to determine whether one or more (e.g., pages) of n sets of volatile memory cells associated with a memory address are empty (e.g., storing random or invalid data). In some cases, a set of volatile memory cells in volatile memory 204 may be referred to as a row or cache row.

[0066] If one of the n associated sets of volatile memory cells is available for storing information, then interface controller 202 can transfer data from buffer 218 to volatile memory 204 for storage in that set of volatile memory cells. However, if the associated sets of volatile memory cells are not empty, then interface controller 202 can initiate a retrieval process to free up space for data in volatile memory 204. The retrieval process may involve transferring old data (e.g., existing data) from one of the n associated sets of volatile memory cells to buffer 220. Dirty information for the old data may also be transferred to memory array 254 or register 258 for identification of a dirty subset of the old data. After the old data is stored in buffer 220, new data may be transferred from buffer 218 to volatile memory 204 and old data may be transferred from buffer 220 to non-volatile memory 206. In some cases, a dirty subset of the old data is transferred to non-volatile memory 206 and a clean subset (e.g., an unmodified subset) is discarded. The dirty subset can be identified by engine 246-b based on dirty information transferred to memory array 254 or register 258 during the recovery process (e.g., from volatile memory 204).

[0067] In another example, interface controller 202 may receive a retrieval command from a host device. The retrieval command may be received on C / A bus 225 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The retrieval command may include address bits targeting a memory address of non-volatile memory 206. Before attempting to access the target memory address of non-volatile memory 206, interface controller 202 may check to determine whether volatile memory 204 stores data. To do this, command circuitry 230 may refer to memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of a set of n volatile memory cells associated with the memory address store the requested data. If the requested data is stored in volatile memory 204, then interface controller 202 may transmit the requested data to buffer 218 for transmission to the host device on data bus 260.

[0068] If the requested data is not stored in volatile memory 204, interface controller 202 may retrieve the data from non-volatile memory 206 and transfer it to buffer 218 for transmission to the host device on data bus 260. Alternatively, interface controller 202 may transfer the requested data from buffer 218 to volatile memory 204, allowing for less latency data access during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 may first determine whether one or more of a set of n associated volatile memory cells are available for storing the requested data. Interface controller 202 may determine the availability of the n associated volatile memory cells by communicating with the relevant cache management circuitry. If the associated set of volatile memory cells is available, interface controller 202 may transfer the data from buffer 218 to volatile memory 204 without performing a retrieval process. Otherwise, interface controller 202 may transfer the data from buffer 218 to volatile memory 204 after performing a retrieval process.

[0069] The memory subsystem 200 can be implemented in one or more configurations, including single-chip and multi-chip versions. The multi-chip version may include one or more components of the memory subsystem 200, including the interface controller 202, volatile memory 204, and non-volatile memory 206 (and other components or combinations thereof), on a separate chip from the chip containing the other components of the memory subsystem 200. For example, in a multi-chip version, the corresponding separate chip may contain each of the interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, the single-chip version may contain the interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0070] In some instances, interface controller 202 may include various circuitry or features to provide direct access to non-volatile memory 206 and / or volatile memory 204 for testing purposes. For example, interface controller 202 may be configured to determine whether to enable a first mode (e.g., test mode) of memory subsystem 200, for example, based on values ​​stored in registers (e.g., mode registers that may be used to provide configuration information to interface controller 202). In response to interface controller 202 determining that the first mode is enabled, interface controller 202 may disable (e.g., bypass) cache memory circuitry and provide direct access to non-volatile memory 206. For example, if interface controller 202 determines that memory subsystem 200 is operating in test mode (e.g., enabling first mode), then interface controller 202 may bypass some or all of the blocks involved in cache memory management, including volatile memory 204, cache memory management circuitry 244, command circuitry 230, engine 246, scheduler 248, and / or other components of interface controller 202. When operating in test mode, interface controller 202 may directly forward memory access commands received from the host device to memory interface circuitry 234 via C / A bus interface 210.

[0071] Figure 3 This describes an example of a memory subsystem 300 that supports direct testing of packaged internal memory, as disclosed herein. The memory subsystem 300 may be a reference accordingly. Figure 1 and 2 Examples of the described memory subsystems 110 and 200. Therefore, memory subsystem 300 can be used with, as referenced... Figure 1 and 2 The host device interaction is described. The memory subsystem 300 may include an interface controller 302 and non-volatile memory 306, which may be instances of the interface controller 202 and non-volatile memory 206, as referenced. Figure 2 As described. In some instances, the memory subsystem 300 may also include components not described in Figure 3 The volatile memory or other components shown in the figure.

[0072] Interface controller 302 may include host interface 304 for communicating with a host device (e.g., ATE). Host interface 304 may be a reference... Figure 2 Examples of the described C / A bus interface 210 and / or data bus interface 208 may be represented by reference. Figure 2 The described C / A bus interface 210 and / or data bus interface 208 are configured to communicate with a host device using the C / A bus 308, data bus 310, and transaction bus 312, wherein the bus may be a reference bus.Figure 2 The instance of the corresponding bus described.

[0073] The interface controller 302 may include a decoder 332, a command circuit system 320, a memory interface circuit system 326, a C / A interface 328, and a data interface 330, which may be examples of decoder 228, command circuit system 230, memory interface circuit system 234, C / A interface 212, and data interface 214, as shown in the reference. Figure 2 As described. During certain operations (e.g., when the first operating mode of the memory subsystem 300 is disabled, for example, when the memory subsystem 300 is operating in a given mode, for example, in the normal operating mode), these components of the interface controller 302 may be as described in reference. Figure 2 The described operation.

[0074] Decoder 332 may be configured to receive commands from a host device and may include decoding element 314, which may be configured to decode commands received from the host device.

[0075] Decoder 332 may include command queue 316. Decoder 332 may be configured to store column access strobe (CAS) commands received from the host device in command queue 316 for subsequent execution. In some instances, CAS commands may specify memory access operations (e.g., read or write operations) and / or may specify clock synchronization operations (e.g., by including clock synchronization options, such as WS_FS, WS_RD, WS_WR). Clock synchronization commands (e.g., commands specifying clock synchronization operations) may be associated with synchronizing two clock signals used by memory subsystem 300, such as synchronizing the system clock signal and the data clock signal.

[0076] In some instances, when the memory subsystem 300 operates in test mode, CAS commands received by the memory subsystem 300 can be forwarded from the decoder 332 to the memory interface circuitry 326 (e.g., via bypass path 344 or bypass path 348). However, when the memory subsystem 300 operates in test mode (e.g., when a given operating mode is enabled), the memory interface circuitry 326 can automatically generate CAS commands.

[0077] Decoder 332 may include an activation queue (ACT) 318. Decoder 332 may store activation commands received from the ATE in activation queue 318 for subsequent execution. Activation commands can be used to open (e.g., select) rows of memory cells in non-volatile memory 306 for subsequent read or write operations, and may contain a set of address bits corresponding to rows of non-volatile memory 306 or may be associated with a set of address bits corresponding to rows of non-volatile memory 306. In some instances, activating a row of non-volatile memory 306 may be based on receiving two sequential activation commands ACT-1 and ACT-2. In some instances, ACT-1 and ACT-2 may be collectively referred to as activation commands.

[0078] In some instances, decoder 332 may contain elements not present in... Figure 3 The diagram shows one or more additional queues or circuit systems that may facilitate the operations described herein or other related operations.

[0079] As previously discussed, the interface controller 302 may determine whether to enable a first operating mode of the memory subsystem 300, such as a test mode, in which the cache memory-related circuitry is bypassed, or whether to enable a second operating mode, such as a given operating mode, in which the memory subsystem 300 uses, as described in the reference... Figure 2 The circuit system associated with the described cache memory.

[0080] Interface controller 302 may include one or more registers 334. In some instances, register 334 may be coupled to decoder 332. Register 334 may represent mode registers, such as mode registers conforming to one or more industry standards or one or more industry or partial specifications, such as LPDDR5 mode registers. For example, register 334 may include or represent LPDDR5 mode registers MR64, MR65, MR68, or other mode registers.

[0081] Interface controller 302 can determine whether to enable or disable a first operating mode based on a value read from one of registers 334, wherein the value provides an indication of the operating mode. In some instances, the host device can send a command to memory subsystem 300 to write a value into one of registers 334 (e.g., via host interface 304 and decoder 332) to provide an indication to memory subsystem 300 to enable a test mode. In response to receiving this command from the host device, interface controller 302 can write the value into one of registers 334.

[0082] In response to determining that test mode is enabled, interface controller 302 may use bypass paths (e.g., conductive paths bypassing cache memory circuitry), such as bypass path 344 or bypass path 348, and other instances, to forward commands received via host interface 304 to memory interface circuitry 326, thereby bypassing cache memory-related features of interface controller 302 (e.g., cache memory management circuitry). Memory interface circuitry 326 may receive the forwarded commands and perform one or more operations based on the commands, such as memory access to non-volatile memory 306.

[0083] When the memory subsystem 300 operates with a given operating mode enabled and the test mode disabled, the memory interface circuitry 326 can maintain a group state machine to keep time for memory access operations. When the memory subsystem 300 operates with the test mode enabled, the memory interface circuitry 326 may not be able to maintain the group state machine because the timing can instead be maintained by the host device.

[0084] In some instances, when the memory subsystem 300 operates in test mode, cross-clock domain (CDC) in the memory subsystem 300 can be bypassed to enable deterministic operation (e.g., because CDC may not be able to ensure deterministic operation).

[0085] In some instances, when decoder 332 forwards a command containing a first indication of a clock synchronization command (e.g., a clock synchronization option) to memory interface circuitry 326, either memory interface circuitry 326 or decoder 332 may store a second indication of the clock synchronization command in command queue 316. Memory subsystem 300 may then read the second indication of the clock synchronization command from command queue 316 and perform a clock synchronization operation based on the second indication of the clock synchronization command.

[0086] In some instances, when the memory subsystem 300 operates in test mode, the interface controller 302 may perform various operations associated with protocol conversion between the protocol associated with the host interface 304 (e.g., the LPDDR protocol) and the protocol associated with accessing the non-volatile memory 306.

[0087] For example, one challenge in performing direct testing of the non-volatile memory 306 may be that the non-volatile memory 306 may use a different protocol (or pin list) compared to the host interface 304. For instance, if the non-volatile memory 306 is an 8GB FeRAM memory, then the non-volatile memory 306 may use a total of 28 address bits to activate rows of the non-volatile memory 306, which may include 23 row address bits (R0 to R22), two bits for specifying the group (BG0 / 1), and three bits for specifying the subgroup within the group (BA0-2). However, the memory subsystem 300 may receive fewer bits from the host device, for example, 22 address bits (R0 to R17, BG0 / 1, BA0 / 1) from two activation commands (ACT-1 and ACT-2). Therefore, during testing of the non-volatile memory 306, in order to support row activation for the non-volatile memory 306, the memory subsystem may include circuitry or features to amplify the received row address. That is, the memory subsystem 300 may receive one or more commands associated with a first address having a first bit count and may generate a second address having a second (e.g., larger) bit count based on the first address.

[0088] For example, one or more registers 334 may be configured to store a value representing a higher row address of non-volatile memory 306 to enable protocol translation between the row address received by host interface 304 (e.g., from a host device, ATE) in an activation command and the row address used by non-volatile memory 306. For example, one of registers 334 may contain multiple bits, such as six bits, that can be used to store the higher row address of non-volatile memory 306 (e.g., row address bits R22:17). In some instances, the value representing the higher row address of non-volatile memory 306 can be read from register 334 by memory subsystem 300 and appended to the row address received via host interface 304, subsequently providing the (amplified) row address to memory interface circuitry 326.

[0089] Therefore, in some instances, when the memory subsystem 300 operates in test mode, the decoder 332 can forward ACT commands received using the host interface 304 to the memory interface circuitry 326, for example, after merging the row address and value of the ACT command, the value being, for example, a predefined value, stored in one of the registers 334 without hashing, for example, by merging a predefined MR64 value in one of the registers 334 with the row address (e.g., making R[23:0] = {MR68OP[7:0], R[15:0]}). In some instances, to change a higher row address of the non-volatile memory 306, the host device can issue a command, for example, a Mode Register Write (MRW) command, to the memory subsystem 300 to update the MR64 value (e.g., to update a value in one of the registers 334). The command may contain a value to be stored in the register 334. In response to receiving this command from the host device, the memory subsystem 300 can store the value received from the host device in the register 334.

[0090] In some instances, to support addressing a certain number of groups per cluster of nonvolatile memory 306 (e.g., to support eight groups per cluster) while memory subsystem 300 operates in test mode, a signal detected (e.g., received) at a first pin of memory subsystem 300 can be used to specify (e.g., indicate) the cluster. For example, when memory subsystem 300 operates in test mode, a pin of host interface 304 (e.g., a C / A pin, such as CA5) can be used (e.g., repurposed or reused for) to receive cluster indications instead of using, for example, R12 (e.g., the row address bit) in an activation / precharge command (e.g., ACT-1 / PRE) and the valid bits of a read / write command to determine the cluster. In some instances, the memory subsystem can detect the edge of a clock signal at the first pin and can determine the value of the cluster of nonvolatile memory 306 based on the detected edge of the clock signal. In some instances, memory subsystem 300 can append or combine the value of the cluster with the first address when a second (amplified) address is generated.

[0091] In some instances, to support dynamic page sizes during test operations, a second pin of the memory subsystem 300 can be used to receive an indication of the page size of the non-volatile memory 306. For example, when the memory subsystem 300 is operating in test mode, a pin of the host interface 304 (e.g., a C / A pin, such as CA6) can be used (e.g., repurposed or reused for) to receive an indication of the page size instead of using, for example, R13 in the ACT-1 command. The memory subsystem 300 can then perform memory accesses to the non-volatile memory 306 based on the indicated page size.

[0092] Interface controller 302 may include multiplexer 322, which may be coupled to one or more of registers 334 and to memory interface circuitry 326. Multiplexer 322 may be configured to switch between conductive paths 344 and 346 based on an indication of an operating mode received from register 334. For example, multiplexer 322 may select conductive path 344 when a test mode is enabled and conductive path 346 when a test mode is disabled. Multiplexer 322 may be configured to receive commands via the selected conductive path and provide commands to memory interface circuitry 326.

[0093] In some instances, when the memory subsystem 300 receives a write command while in test mode, the memory interface circuitry 326 may write to the buffer 340 instead of from a reference. Figure 2 The described OPD buffer (e.g., buffer 218) retrieves (e.g., reads) data to be written to nonvolatile memory 306.

[0094] In some instances, when the memory subsystem 300 receives a read command while in test mode, the memory interface circuitry 326 may return (e.g., transmit, store) data to the read response buffer 342 instead of returning it to the referenced buffer. Figure 2 The described OPD buffer (e.g., buffer 218).

[0095] In some instances, when the memory subsystem is operating in test mode, the forwarding from the LP5 mode register (e.g., one of the registers 334) to the mode register of the memory interface circuitry 326 may be omitted (e.g., stopped). This is because the memory interface circuitry 326 can change various timings associated with memory access (e.g., frequency setpoint FSP, write delay WL, read delay RL) according to the LP5 mode register.

[0096] Figure 4 An exemplary process flow 400 is depicted to support direct testing of encapsulated internal memory according to examples disclosed herein. Process flow 400 may depict a process executed by a host device (e.g., ATE) and a memory subsystem (e.g., memory subsystem 200, 300) for reading data from the non-volatile memory of the memory subsystem when the memory subsystem is operating in test mode. Additionally or alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 and / or non-volatile memory 125). For example, these instructions, when executed by a controller (e.g., interface controller 115), may cause the controller to perform the operation of process flow 400.

[0097] At 405, the memory subsystem can set register values. For example, the memory subsystem can write a value indicating the operation of the memory subsystem in test mode to a mode register (e.g., one of registers 334). In some instances, the memory subsystem can set register values ​​in response to receiving a command (e.g., an MRW command) from the test device.

[0098] At 410, the host device (e.g., ATE) can issue commands to the memory subsystem, such as a read command. The memory subsystem can receive commands using a host interface, such as host interface 304, and provide the commands to a decoder, such as decoder 332.

[0099] At 415, the decoder of the memory subsystem can forward commands to the memory interface circuitry (e.g., memory interface circuitry 326). In some instances, the decoder can use conductive paths that bypass the cache memory circuitry of the memory subsystem to forward commands to the memory interface circuitry, such as conductive path 344 or conductive path 348, and other instances. In some instances, the decoder can forward commands to the memory interface circuitry based on register values ​​that indicate the memory subsystem is operating in test mode.

[0100] At 420, the memory subsystem can read data from non-volatile memory based on a command, and the memory interface can return the data to a read response buffer (e.g., read response buffer 342) instead of an OPD buffer.

[0101] At 425, the read response buffer can return data to the host device after the read latency (tRL) has elapsed. In some instances, the read response buffer can return data to the host device via the host interface, for example, host interface 304.

[0102] Figure 5 A block diagram 500 illustrates a memory device 505 that supports direct testing of in-package memory according to examples disclosed herein. The memory device 505 may be as described in the references... Figures 1 to 4 Examples of aspects of the described memory subsystem. Memory device 505 may include a mode determination component 510, a cache memory control component 515, a command component 520, an address generation component 525, a memory access component 530, a command queue component 535, a clock synchronization component 540, a data transmission component 545, and a buffer component 550. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0103] The mode determination component 510 can determine whether to enable a first mode of the memory device.

[0104] The cache memory control component 515 can disable the cache memory of the memory device based on determining that the first mode is enabled.

[0105] After the cache memory is disabled, the command component 520 can receive one or more commands from the host device, each containing a first address with a first bit number.

[0106] In some instances, one or more commands may include a first command that includes an indication of clock synchronization operation for synchronizing a first clock with a second clock.

[0107] In some instances, command component 520 may receive a second command associated with updating the value of the mode register from the host device before reading the value of the mode register. In some instances, command component 520 may update the value of the mode register based on the receipt of the second command.

[0108] Address generation component 525 can generate a second address with a second number of bits based on the first address, the second number of bits being greater than the first number of bits. In some instances, address generation component 525 can read the value of the mode register. In some instances, address generation component 525 can append the value of the mode register to the first address.

[0109] In some instances, address generation component 525 may detect a clock edge at a first pin of the memory device. In some instances, address generation component 525 may determine the value of a group of memory devices based on the detected clock edge. In some instances, address generation component 525 may append the value of a group of memory devices to a first address.

[0110] The memory access component 530 can perform access operations on the memory array of the memory device based on a generated second address. In some instances, performing an access operation on the memory array includes activating a row of the memory array at least partially based on the second address. In some instances, performing an access operation on the memory array includes reading data from the memory array at least partially based on the second address. In some instances, performing an access operation on the memory array includes writing data to the memory array at least partially based on the second address.

[0111] Command queue component 535 may store a second indication of clock synchronization operation in the command queue of the memory device. In some instances, after storing the second indication of clock synchronization operation, command queue component 535 may read the second indication of clock synchronization operation from the command queue.

[0112] The clock synchronization component 540 can perform clock synchronization operations based on reading a second instruction from the command queue.

[0113] The data transmission component 545 can transmit data to the host device.

[0114] Before writing data at the second address of the array, buffer component 550 can retrieve data from the write buffer of the memory device.

[0115] Figure 6 A flowchart illustrating one or more methods 600 according to aspects of the present invention for testing in-package memory is shown. Operation of method 600 may be implemented by a memory device or a component thereof as described herein. For example, operation of method 600 may be performed by, as described in reference... Figure 5 The described memory device is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described function.

[0116] At 605, the memory device may determine whether to enable a first mode of the memory device. Operation 605 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 5 The described pattern determines the aspects of the component that perform operation 605.

[0117] At 610, the memory device may disable its cache memory based on determining that a first mode is enabled. Operation 610 may be performed according to the method described herein. In some instances, aspects of operation 610 may be provided by reference to [reference needed]. Figure 5 The described cache memory control component is used to perform this.

[0118] At 615, after disabling the cache memory, the memory device may receive one or more commands from the host device containing a first address having a first bit number. Operation 615 may be performed according to the method described herein. In some instances, aspects of operation 615 may be derived from, as referenced... Figure 5 The command component described is used to execute it.

[0119] At 620, the memory device can generate a second address with a second number of bits based on the first address, the second number of bits being greater than the first number of bits. Operation 620 can be performed according to the method described herein. In some instances, aspects of operation 620 can be derived from, as referenced... Figure 5 The described address generates the component for execution.

[0120] At 625, the memory device can perform an access operation on the memory array of the memory device based on the generated second address. Operation 625 can be performed according to the method described herein. In some instances, aspects of operation 625 can be derived from, as referenced... Figure 5 Figure 5 The memory access component described is used to perform this.

[0121] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for determining whether to enable a first mode of the memory device, disabling a cache memory of the memory device based on determining that the first mode is enabled, receiving one or more commands from a host device after disabling the cache memory, including a first address having a first bit quantity, generating a second address having a second bit quantity based on the first address, the second bit quantity being greater than the first bit quantity, and performing an access operation on the memory array of the memory device based on generating the second address.

[0122] In some instances of the method 600 and apparatus described herein, a first command of one or more commands includes an indication for a clock synchronization operation to synchronize a first clock with a second clock, and may include operations, features, means, or instructions for storing a second indication of the clock synchronization operation in a command queue of a memory device, reading a second indication of the clock synchronization operation from the command queue after storing the second indication of the clock synchronization operation, and performing the clock synchronization operation based on reading the second indication from the command queue.

[0123] In some instances of the method 600 and apparatus described herein, performing an access operation on a memory array may include operations, features, means, or instructions for activating a row of the memory array at least in part based on a second address.

[0124] In some instances of the method 600 and apparatus described herein, performing an access operation on a memory array may include operations, features, means, or instructions for reading data from the memory array at least in part based on a second address.

[0125] In some instances of the method 600 and apparatus described herein, performing an access operation on a memory array may include operations, features, means, or instructions for writing data into the memory array, at least in part, based on a second address.

[0126] In some instances of the method 600 and apparatus described herein, performing an access operation on a memory array may include operations, features, means, or instructions for transmitting data to a host device.

[0127] In some instances of the method 600 and apparatus described herein, performing an access operation on a memory array may include operations, features, means, or instructions for retrieving data from a write buffer of the memory device before writing data at a second address of the array.

[0128] In some instances of the method 600 and device described herein, generating a second address may include operations, features, means, or instructions for reading the value of a mode register and appending the value of the mode register to a first address.

[0129] Some instances of the method 600 and device described herein may further include operations, features, means, or instructions for receiving a second command associated with updating the value of the mode register from a host device before reading the value of the mode register, and updating the value of the mode register based on receiving the second command.

[0130] In some instances of the method 600 and apparatus described herein, generating a second address may include operations, features, means, or instructions for detecting a clock edge at a first pin of the memory device, determining a group value of the memory device based on the detected clock edge, and appending the group value to the first address.

[0131] It should be noted that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0132] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0133] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0134] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via conductive paths, while in a closed-circuit relationship, signals can be transmitted between components via conductive paths. When a component, such as a controller, couples other components together, the component initially allows signals to flow between the other components via conductive paths that were previously not permitted.

[0135] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then those components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller prevents signals from flowing between the components using previously permitted conductive paths.

[0136] As used herein, a protocol can refer to a definition or standard for supporting one or more communication procedures and one or more communication parameters used by a device or component. For example, a protocol may define various operations, timing and frequencies for those operations, means of various commands or signals, or both, one or more addressing schemes for one or more memories, the type of communication in which pins are reserved, the size of data processed at various components of an interface, the data rate supported by, for example, various components of an interface, or the bandwidth supported by, for example, various components of an interface, and other parameters and measures, or any combination thereof. The use of a shared protocol enables interaction between devices because each device can operate in a manner expected and recognized by another device. For example, two devices supporting the same protocol can interact according to the policies, procedures, and parameters defined by the protocol; however, two devices supporting different protocols may be incompatible. To illustrate, two devices supporting different protocols may be incompatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another point of view, two devices supporting different protocols can be incompatible because the protocols define different transmission procedures for responding to a single command (e.g., the burst length or number of bytes allowed in response to a command may be different). Simply translating a command into an action should not be interpreted as the use of two different protocols. In fact, if the corresponding procedures or parameters defined by the two protocols change, then the protocols can be considered different. For example, if a device supports different addressing schemes or different transmission procedures for responding to commands, then the device can be said to support two different protocols.

[0137] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0138] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET accordingly can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "disconnected" or "deactivated".

[0139] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0140] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by a second reference numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0141] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description.

[0142] The various illustrative blocks and modules described herein can be implemented or performed using general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but alternatively, the processor can be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0143] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this invention and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located at various points, including distributed features such that portions of the functionality are implemented at different physical locations. And, as used herein, the word "or" included in the claims, as in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of"), indicates a list of inclusion, such that, for example, a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). And, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the invention, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0144] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any usable media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0145] The description herein is provided to enable those skilled in the art to make or use the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory array; An interface controller, coupled to the memory array and configured to enable the device to: Determine whether to enable the first mode of the device; The device's cache memory circuitry is disabled, at least in part, based on the determination that the first mode is enabled. After the cache memory circuitry is deactivated, one or more commands associated with a first address having a first bit number are received from the host device. A second address with a second number of bits is generated, at least in part, based on the first address, wherein the second number of bits is greater than the first number of bits; as well as Access operations are performed on the memory array based at least in part on the generation of the second address.

2. The device of claim 1, wherein performing the access operation on the memory array includes activating a row of the memory array at least partially based on the second address.

3. The device of claim 1, wherein performing the access operation on the memory array includes reading data from the memory array at least partially based on the second address, and the interface controller is further configured such that the device: The data is transmitted to the host device.

4. The device of claim 1, wherein performing the access operation on the memory array includes writing data to the memory array at least partially based on the second address, and the interface controller is further configured such that the device: The data is retrieved from the write buffer of the memory subsystem before being written to the memory array.

5. The device of claim 1, wherein the first command of the one or more commands includes an indication for clock synchronization operation for synchronizing a first clock with a second clock, wherein the interface controller is further configured such that the device: A second instruction for the clock synchronization operation is stored in the command queue of the device; After saving the second indication of the clock synchronization operation, the second indication of the clock synchronization operation is read from the command queue; as well as The clock synchronization operation is performed at least in part based on reading the second instruction from the command queue.

6. The device of claim 1, wherein the first address includes a first row address and the second address includes a second row address.

7. The device of claim 1, wherein generating the second address comprises: Read the value of the mode register; as well as The value of the mode register is appended to the first address.

8. The device of claim 7, wherein the interface controller is further configured to cause the device to: Receive a second command associated with updating the value of the mode register from the host device before reading the value of the mode register; and The value of the mode register is updated at least in part based on the receipt of the second command.

9. The device of claim 1, wherein generating the second address comprises: The clock edge is detected at the first pin of the device; The value of the cluster of the memory array is determined at least in part based on the detection of the clock edge; as well as The value of the group of the memory array is appended to the first address.

10. An apparatus comprising: Memory cell array; as well as An interface controller coupled to the memory cell array, the interface controller comprising: The host interface, configured to receive commands from the host device, The cache memory management circuitry system, coupled to the decoder, and A memory interface circuitry, coupled to the cache memory management circuitry and the decoder, is configured to access the memory cell array based on commands received from the host device. The interface controller is configured to enable the device to: Receive commands from the host device Determine whether to enable the first operating mode of the device, and The command is provided directly to the memory interface circuitry via a bypass path, at least in part based on the determination that the first operating mode is enabled.

11. The device according to claim 10, further comprising: A first register is configured to store an indication of an operating mode of the device, wherein the interface controller is configured to determine whether to enable the first operating mode based at least in part on the indication of the operating mode in the first register.

12. The device according to claim 10, further comprising: A second register, configured to store a value indicating a higher row address of the memory cell array, wherein the interface controller is further configured to cause the device to: Identify the first address associated with the command. A second address is generated at least in part based on the first address and based on determining that the first operating mode is enabled, wherein generating the second address includes appending the value indicating the higher row address to the first address, and The second address is provided to the memory interface circuitry, wherein the memory interface circuitry is configured to access the memory cell array at least in part based on the second address.

13. The device of claim 12, wherein the host interface includes a first pin and the interface controller is further configured such that the device: Detect the clock edge at the first pin; and The value of the group of the memory cell array is determined at least in part based on detecting the clock edge and based on determining that the first operating mode is enabled, wherein generating the second address includes appending the value of the group to the first address.

14. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Determine whether to enable the device's first mode; The device's cache memory circuitry is disabled, at least in part, based on the determination that the first mode is enabled. After the cache memory circuitry is deactivated, one or more commands associated with a first address having a first bit number are received from the host device. A second address with a second number of bits is generated, at least in part, based on the first address, wherein the second number of bits is greater than the first number of bits; as well as At least in part, an access operation is performed on the memory array of the electronic device based on the generation of the second address.

15. The non-transitory computer-readable medium of claim 14, wherein performing the access operation on the memory array includes activating a row of the memory array at least in part based on the second address.

16. The non-transitory computer-readable medium of claim 14, wherein performing the access operation on the memory array includes reading data from the memory array at least in part based on the second address, and wherein the instruction, when executed by the processor of the electronic device, further causes the electronic device to: transmit the data to the host device.

17. The non-transitory computer-readable medium of claim 14, wherein performing the access operation on the memory array includes writing data to the memory array at least in part based on the second address, and wherein the instruction, when executed by the processor of the electronic device, further causes the electronic device to: retrieve the data from a write buffer of the memory subsystem before writing the data to the memory array.

18. The non-transitory computer-readable medium of claim 14, wherein the first of the one or more commands includes an instruction for clock synchronization operation for synchronizing a first clock with a second clock, and wherein the instruction, when executed by the processor of the electronic device, further causes the electronic device to: A second instruction for the clock synchronization operation is stored in the command queue of the non-transitory computer-readable medium; After saving the second indication of the clock synchronization operation, read the second indication of the clock synchronization operation from the command queue; and The clock synchronization operation is performed at least in part based on reading the second instruction from the command queue.

19. The non-transitory computer-readable medium of claim 14, wherein the first address includes a first line address and the second address includes a second line address.

20. The non-transitory computer-readable medium of claim 14, wherein generating the second address comprises: Read the value of the mode register; as well as The value of the mode register is appended to the first address.

21. The non-transitory computer-readable medium of claim 20, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Receive a second command associated with updating the value of the mode register from the host device before reading the value of the mode register; and The value of the mode register is updated at least in part based on the receipt of the second command.

22. The non-transitory computer-readable medium of claim 14, wherein generating the second address comprises: The clock edge is detected at the first pin of the device; The value of the cluster of the memory array is determined at least in part based on the detection of the clock edge; as well as The value of the group of the memory array is appended to the first address.

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