Semiconductor device and method for manufacturing semiconductor device

Abstract

This case relates to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device of this embodiment includes a semiconductor chip having a first surface and a second surface opposite the first surface, with a semiconductor element disposed on the first surface. A columnar electrode is disposed above the first surface and electrically connected to one of the semiconductor elements. A first component is disposed above the first surface and around the columnar electrode. An insulating material covers the columnar electrode and the first component. The first component is harder than the columnar electrode and the insulating material. The first component and the columnar electrode are exposed from the surface of the insulating material.

Description

[0001] Citations of Related Applications

[0002] This application claims the benefit of priority based on the prior Japanese Patent Application No. 2020-117274, filed on July 7, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] The industry has developed a technology that seals multiple semiconductor chips and a controller chip into a single semiconductor package (CSP (Chip Scale Package)) using resin.

[0005] However, when adjusting the thickness of a semiconductor package by polishing the resin, uneven thickness can occur. If the semiconductor package is too thin, it can warp. Furthermore, polishing the resin while measuring its thickness can reduce production yields. Summary of the Invention

[0006] One embodiment provides a semiconductor device and a method for manufacturing the semiconductor device, which can suppress a decrease in yield and suppress uneven thickness of a semiconductor package or warping of the semiconductor package.

[0007] A semiconductor device according to an embodiment comprises a semiconductor device including: a semiconductor chip (10) having a first surface and a second surface opposite to the first surface, wherein a semiconductor element is provided on the first surface side; a columnar electrode (60) provided above the first surface when the direction from the second surface toward the first surface is set as an upward direction, and electrically connected to any one of the semiconductor elements; a first component (80) provided above the first surface and around the columnar electrode; and a first insulating material (90, 122) provided around the columnar electrode and the first component; the first component being harder than the columnar electrode and the insulating material, and the first component and the columnar electrode being exposed from the surface on the upper side of the insulating material.

[0008] According to the above configuration, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress a decrease in yield and suppress thickness variations or warping of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a cross-sectional view showing an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0011] Figure 3 It means connected to Figure 2 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0012] Figure 4 It means connected to Figure 3 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0013] Figure 5 It means connected to Figure 4 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0014] Figure 6 It means connected to Figure 5 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0015] Figure 7 It means connected to Figure 6 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0016] Figure 8 It means connected to Figure 7 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0017] Figure 9 It means connected to Figure 8 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0018] Figure 10 It means connected to Figure 9 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0019] Figure 11 It means connected to Figure 10 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0020] Figure 12 It means connected to Figure 11 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0021] Figure 13 This is a cross-sectional view showing an example of a manufacturing method and a structure of a semiconductor device according to the second embodiment.

[0022] Figure 14 This is a cross-sectional view showing an example of a manufacturing method and a structure of a semiconductor device according to the second embodiment.

[0023] Figure 15 This is a cross-sectional view showing an example of a manufacturing method and a structure of a semiconductor device according to a third embodiment.

[0024] Figure 16 This is a cross-sectional view showing an example of a manufacturing method and a structure of a semiconductor device according to a third embodiment.

[0025] Figure 17 This is a cross-sectional view showing an example of a manufacturing method and a structure of a semiconductor device according to a fourth embodiment.

[0026] Figure 18 This is a cross-sectional view showing an example of a manufacturing method and a structure of a semiconductor device according to a fourth embodiment.

[0027] Figure 19 This is a cross-sectional view showing an example of a manufacturing method and structure of a semiconductor device according to a fifth embodiment.

[0028] Figure 20 This is a cross-sectional view showing an example of a manufacturing method and structure of a semiconductor device according to a fifth embodiment.

[0029] Figure 21 It is a cross-sectional view showing an example of the structure of a semiconductor device according to the sixth embodiment.

[0030] Figure 22 This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the seventh embodiment.

[0031] Figure 23 It means connected to Figure 22 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0032] Figure 24 It is a cross-sectional view showing a configuration example of a semiconductor device according to a seventh embodiment.

[0033] Figure 25 It is a cross-sectional view showing an example of the structure of a semiconductor device according to the eighth embodiment.

[0034] Figure 26 It is a cross-sectional view showing an example of the structure of a semiconductor device according to the ninth embodiment.

[0035] Figure 27 It is a cross-sectional view showing an example of the structure of a semiconductor device according to a tenth embodiment.

[0036] Figure 28 It is a cross-sectional view showing an example of the structure of a semiconductor device according to the eleventh embodiment.

[0037] Figure 29 It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the eleventh embodiment.

[0038] Figure 30 It means connected to Figure 29 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0039] Figure 31 It means connected to Figure 31 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0040] Figure 32 This is a cross-sectional view showing a state where the semiconductor device according to the eleventh embodiment is mounted on a wiring substrate.

[0041] Figure 33 It is a cross-sectional view showing an example of the structure of a semiconductor device according to the twelfth embodiment.

[0042] Figure 34 It is a cross-sectional view showing an example of the structure of a semiconductor device according to the thirteenth embodiment.

[0043] Figure 35 It is a diagram showing the state of the resin sealing step of Modification 1.

[0044] Figure 36 It is a diagram showing the state of the resin sealing step of Modification Example 2.

[0045] Figure 37 It is a cross-sectional view showing a configuration example of a semiconductor device according to a fourteenth embodiment.

[0046] Figure 38 This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the fourteenth embodiment.

[0047] Figure 39 It means connected to Figure 38 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0048] Figure 40 It means connected to Figure 39 A cross-sectional view illustrating an example of a subsequent method for manufacturing a semiconductor device.

[0049] Figure 41 It is a cross-sectional view showing a configuration example of a semiconductor device according to a fifteenth embodiment.

[0050] Figure 42 It is a cross-sectional view showing a configuration example of a semiconductor device according to a sixteenth embodiment.

[0051] Figure 43 It is a cross-sectional view showing a configuration example of a semiconductor device according to the seventeenth embodiment.

[0052] Figure 44It is a plan view showing a configuration example of a semiconductor device according to the seventeenth embodiment.

[0053] Figure 45 It is a cross-sectional view showing a configuration example of a semiconductor device according to the eighteenth embodiment.

[0054] Figure 46 It is a cross-sectional view showing a configuration example of a semiconductor device according to the nineteenth embodiment.

[0055] Figure 47 It is a cross-sectional view showing a configuration example of a semiconductor device according to the 20th embodiment.

[0056] Figure 48 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-first embodiment.

[0057] Figure 49 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-second embodiment.

[0058] Figure 50 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-second embodiment.

[0059] Figure 51 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-second embodiment.

[0060] Figure 52 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-second embodiment.

[0061] Figure 53 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-third embodiment.

[0062] Figure 54 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-fourth embodiment.

[0063] Figure 55 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-fifth embodiment.

[0064] Figure 56 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-sixth embodiment.

[0065] Figure 57 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-seventh embodiment.

[0066] Figure 58 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-eighth embodiment.

[0067] Figure 59 It is a cross-sectional view showing a configuration example of a semiconductor device according to the twenty-ninth embodiment.

[0068] Figure 60A It is a diagram showing an example of the configuration of a polishing device in the 30th embodiment.

[0069] Figure 60B It is a diagram showing an example of the configuration of a polishing device in the 30th embodiment.

[0070] Figure 60C This is a conceptual diagram showing the schematic structure of an eddy current sensor.

[0071] Figure 60D It is a diagram showing an example of the configuration of a polishing device in the 30th embodiment. DETAILED DESCRIPTION

[0072] Embodiments will now be described with reference to the accompanying drawings. The present invention is not limited to these embodiments. In the embodiments, "upper direction" or "lower direction" refers to a relative direction when the direction perpendicular to the surface of the semiconductor substrate on which the semiconductor element or semiconductor chip is provided is assumed to be the "upper direction." Therefore, the terms "upper direction" or "lower direction" are sometimes different from the upper direction or lower direction based on the direction of gravitational acceleration. In this specification and the drawings, the same elements as those described in the preceding drawings are denoted by the same reference numerals, and their detailed description is appropriately omitted.

[0073] The semiconductor device of this embodiment includes a semiconductor chip having a first surface and a second surface opposite to the first surface, and a semiconductor element is provided on the first surface. A columnar electrode is provided above the first surface and is electrically connected to any one of the semiconductor elements. A first component is provided above the first surface around the columnar electrode. An insulating material covers the columnar electrode and the first component. The first component is harder than the columnar electrode and the insulating material. The first component and the columnar electrode are exposed from the surface of the insulating material. Hereinafter, the so-called "hard" in each embodiment may also refer to hardness in tests such as the so-called Brinell hardness and Vickers hardness.

[0074] (First embodiment)

[0075] Figure 1 This is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a semiconductor chip 10, a first insulating film 20, an electrode pad 30, a second insulating film 40, a barrier metal 50, a pillar electrode 60, a resin layer 70, a dummy component 80 as a first component, a third insulating film 90 as an insulating material, and a metal bump 100. The semiconductor device 1 may be, for example, a NAND (Not And) type flash memory, an LSI (Large Scale Integration) or other semiconductor package.

[0076] The semiconductor chip 10 has a first surface F10a and a second surface F10b opposite to the first surface. Semiconductor elements (not shown) such as transistors and capacitors are formed on the first surface F10a of the semiconductor chip 10. The semiconductor chip 10 may be, for example, a NAND flash memory chip or a semiconductor chip equipped with any LSI.

[0077] The first insulating film 20 is provided on the first surface F10a of the semiconductor chip 10 to cover and protect the semiconductor element. For example, an inorganic insulating material such as a silicon oxide film or a silicon nitride film is used for the first insulating film 20.

[0078] Electrode pads 30 are provided on the first surface F10a of the semiconductor chip 10 and are electrically connected to any of the semiconductor elements. Electrode pads 30 are made of a low-resistance metal such as Al, Cu, Au, Ni, Pd, or W, a composite film of two or more of these, or an alloy of two or more of these. The first insulating film 20 is partially removed to expose a portion of the electrode pads 30.

[0079] The second insulating film 40 is provided on the first insulating film 20 and is interposed between the first insulating film 20 and the third insulating film 90. The second insulating film 40 is made of an organic insulating material such as a phenolic, polyimide, polyamide, acrylic, epoxy, PBO (p-phenylenebenzobisoxazole), silicone, or benzocyclobutene resin, or a mixed or composite material of these resins.

[0080] The barrier metal 50, which is a metal film, is provided between the columnar electrode 60 and the electrode pad 30 or the second insulating film 40. The barrier metal 50 serves as a plating electrode when forming the columnar electrode 60. The barrier metal 50 is made of, for example, a single material such as Ti, TiN, Cr, CrN, Cu, Ni, Au, Pd, or W, a composite film of two or more of these, or an alloy of two or more of these.

[0081] The columnar electrode 60 is provided on the barrier metal 50 above the first surface F10a of the semiconductor chip 10. The columnar electrode 60 extends from the barrier metal 50 in a direction substantially perpendicular to the first surface F10a. The lower end of the columnar electrode 60 is electrically connected to any semiconductor element of the semiconductor chip 10 via the barrier metal 50 and the electrode pad 30. The upper end of the columnar electrode 60 is connected to the metal bump 100. The columnar electrode 60 is formed using a conductive metal such as Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, or Al, a composite film of two or more of these, or an alloy of two or more of these.

[0082] Since the columnar electrode 60 is formed by plating or wire bonding, it is formed on the barrier metal 50 exposed during the formation process of the columnar electrode 60. In the case of wire bonding, it can also be formed directly on the wire 30.

[0083] The resin layer 70 is provided between the dummy component 80 and the second insulating film 40, and adheres the dummy component 80 to the second insulating film 40 on the first surface F10a. The resin layer 70 is made of, for example, a DAF (die attach film) or DAP (die attach paste) containing a phenolic, polyimide, polyamide, acrylic, epoxy, PBO (p-phenylenebenzobisoxazole), silicone, or benzocyclobutene resin, or a mixed or composite material of these resins.

[0084] Dummy components 80, serving as the first components, are provided above first surface F10a and around pillar electrodes 60. Dummy components 80 and pillar electrodes 60 are formed at approximately the same height from first surface F10a, with their upper surfaces exposed from the surface of third insulating film 90 at approximately the same level. To function as a polishing stopper during the polishing process of third insulating film 90, dummy components 80 are formed from a material harder than both pillar electrodes 60 and third insulating film 90. Third insulating film 90 may be formed using, for example, epoxy, phenolic, polyimide, polyamide, acrylic, PBO, silicone, or benzocyclobutene resins, or blends or composite materials thereof. Dummy components 80 may be formed using, for example, silicon, glass, alumina, SiC, AlN, ceramics, or metal.

[0085] The third insulating film 90 covers and fills the peripheries of the columnar electrodes 60 and the dummy components 80 above the first surface F10a. The surface of the third insulating film 90 is substantially flush with the surfaces of the columnar electrodes 60 and the dummy components 80, and the surfaces of the columnar electrodes 60 and the dummy components 80 are exposed.

[0086] The metal bump 100 is provided on the columnar electrode 60. The metal bump 100 is made of, for example, a conductive metal such as solder.

[0087] As described above, in the semiconductor device 1 of this embodiment, the dummy components 80 are provided around the pillar electrodes 60 and are embedded within the third insulating film 90 together with the pillar electrodes 60. The dummy components 80 are made of a material harder than the pillar electrodes 60 and the third insulating film 90 and function as a stopper during the polishing process of the third insulating film 90. This prevents the polishing process when the dummy components 80 are exposed from the third insulating film 90. As a result, the thickness of the third insulating film 90 does not vary, and the package thickness of the semiconductor device 1 is stable.

[0088] Furthermore, the thickness of the third insulating film 90 can be controlled according to the thickness of the dummy member 80. Therefore, it is not necessary to measure the thickness of the third insulating film 90 during polishing, and throughput can be improved.

[0089] Furthermore, since the dummy component 80 is made of a harder material than the pillar electrodes 60 and the third insulating film 90, the semiconductor device 1 is reinforced and less susceptible to warping. This contributes to improved reliability of the semiconductor device 1. Furthermore, by varying the volume of the dummy component 80 within the semiconductor device, warping can be adjusted, further improving reliability.

[0090] Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described.

[0091] Figures 2 to 12 1 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment. In the figure, a semiconductor chip is shown, but this semiconductor chip is a part of a wafer state before dicing.

[0092] First, a semiconductor element (not shown) is formed on the first surface F10a of the semiconductor wafer W. The semiconductor wafer W can be, for example, a semiconductor substrate such as a silicon substrate. Next, an electrode pad 30 electrically connected to the semiconductor element is formed on the first surface F10a. The electrode pad 30 is made of, for example, a monomer such as Al, Cu, Au, Ni, Pd, W, a composite film of two or more of them, or an alloy of two or more of them. Next, a first insulating film 20 is formed on the first surface F10a in such a manner as to cover the semiconductor element. The first insulating film 20 is processed using photolithography and etching techniques to expose a portion of the electrode pad 30. The first insulating film 20 is made of, for example, an inorganic insulating material such as a silicon oxide film or a silicon nitride film. Next, a second insulating film 40 is formed on the first insulating film 20. The second insulating film 40 is also processed to expose a portion of the electrode pad 30. The second insulating film 40 is made of, for example, phenolic, polyimide, polyamide, acrylic, epoxy, PBO (p-phenylenebenzobisoxazole), silicone, benzocyclobutene resins, or organic insulating materials such as mixed materials or composite materials of these resins. Figure 2 The structure shown.

[0093] Next, if Figure 3As shown, a barrier metal 50 is formed on the electrode pad 30 and the second insulating film 40 by sputtering, vapor deposition, or electroless plating. The barrier metal 50 is made of, for example, a single material such as Ti, TiN, Cr, CrN, Cu, Ni, Au, Pd, or W, a composite film of two or more of these, or an alloy of two or more of these. For example, the barrier metal 50 is a laminated film of a 0.1 μm thick Ti film and a 0.3 μm thick Cu film formed by sputtering.

[0094] Next, if Figure 4 As shown, a photoresist PR is applied to the barrier metal 50. Using photolithography technology, the photoresist PR is processed into a pattern of the columnar electrode 60. For example, the thickness of the photoresist PR is about 40 μm, and an opening of about 100 μm square is formed on the electrode pad 30. The spacing between adjacent openings is about 300 μm. In order to remove residue at the bottom of the opening, O2 ashing treatment can also be performed. As a result, the barrier metal 50 at the position where the columnar electrode 60 is formed is reliably exposed.

[0095] Next, a single material such as Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, or Al, a composite film of two or more of these materials, or an alloy of two or more of these materials is deposited on the exposed barrier metal 50 by electroplating. Figure 5 As shown, metal is selectively plated in the region where the columnar electrode 60 is to be formed, thereby forming the columnar electrode 60. For example, the columnar electrode 60 is formed by plating Cu to a thickness of approximately 35 μm.

[0096] Next, if Figure 6 As shown in FIG. 1 , the photoresist PR is stripped. After the stripping, an O2 ashing process may be performed to remove residue.

[0097] Next, if Figure 7 As shown, the barrier metal 50 is etched using the pillar-shaped electrode 60 as a mask. For example, when the barrier metal 50 is Cu, wet etching can be performed using a mixed solution of citric acid and hydrogen peroxide. When the barrier metal 50 is Ti, etching can be performed using hydrofluoric acid or hydrogen peroxide solution.

[0098] Next, if Figure 8As shown, a chip-shaped dummy component 80 is attached to the first surface F10a via a resin layer 70. The resin layer 70 is made of, for example, a single DAF (Die Attach Film) or DAP (Die Attach Paste) containing a phenolic, polyimide, polyamide, acrylic, epoxy, PBO (p-phenylenebenzobisoxazole), silicone, or benzocyclobutene resin, a mixed material of two or more of these, or a laminated material of two or more of these. The dummy component 80 is thinner than the columnar electrode 60 and the Figure 9 The third insulating film 90 shown is made of a hard material. The dummy component 80 uses, for example, a single material such as silicon, glass, aluminum oxide, SiC, AlN, ceramic, or metal, a mixed material of two or more of these, or a laminated material of two or more of these. The Vickers hardness of the dummy component 80 is ideally not less than 0.85 GPa and not more than 30 GPa. If it is less than 0.85 GPa, then it is close to the Vickers hardness of the third insulating film and the columnar electrode, making it difficult to prevent grinding. On the other hand, if it exceeds 30 GPa, then the material is expensive and special, making it difficult to use. It is more ideal to make the Vickers hardness not less than 5 GPa and not more than 25 GPa. The dummy component 80 is designed so that it has a predetermined height in advance. The upper surface of the dummy component 80 is positioned at a position lower than the upper surface of the columnar electrode 60. As a result, when grinding the third insulating film 90, the grinding can be stopped after the columnar electrode 60 is exposed. For example, if the thickness of columnar electrode 60 is approximately 35 μm, the thickness of resin layer 70 can be set to approximately 5 μm, and the thickness of dummy component 80 can be set to approximately 25 μm, for a total thickness of approximately 30 μm. Furthermore, when using metal as dummy component 80, plating can also be used. For example, after forming columnar electrode 60, plating can be used to form dummy component 80 using a different metal than columnar electrode 60. In this case, the resin layer 70 to which dummy component 80 is attached can be omitted.

[0099] Next, if Figure 9As shown, a third insulating film 90 is formed on the first surface F10a by a molding method or the like. The third insulating film 90 can be formed by applying a liquid resin or by a sheet molding method using a sheet film. The third insulating film 90 is made of a resin such as an epoxy-based, phenol-based, polyimide-based, polyamide-based, acrylic-based, PBO-based, silicone-based, or benzocyclobutene-based resin, or a blend or composite material of these resins. Examples of epoxy resins are not particularly limited. For example, bisphenol-type epoxy resins such as bisphenol A, bisphenol F, bisphenol AD, and bisphenol S, phenolic novolac-type epoxy resins such as cresol novolac, resorcinol-type epoxy resins, aromatic epoxy resins such as trisphenol triglycidyl ether, naphthalene-type epoxy resins, fluorene-type epoxy resins, dicyclopentadiene-type epoxy resins, polyether-modified epoxy resins, benzophenone-type epoxy resins, aniline-type epoxy resins, NBR-modified epoxy resins, CTBN-modified epoxy resins, and hydrides of these resins can be cited. Among them, naphthalene-type epoxy resins and dicyclopentadiene-type epoxy resins are preferred from the perspective of good adhesion to Si. In addition, benzophenone-type epoxy resins are also preferred from the perspective of easy acquisition of rapid curing properties. These epoxy resins can be used alone, or two or more types can be used together. In addition, fillers such as silica can also be included in the third insulating film 90. The third insulating film 90 is formed to fill the columnar electrodes 60 and the dummy members 80. When the third insulating film 90 is a UV (ultraviolet) curing type resin, it is cured by heating in an oven or the like, or by curing with ultraviolet rays or the like.

[0100] Next, if Figure 10 As shown, the third insulating film 90 and the columnar electrodes 60 are polished using mechanical polishing, CMP (Chemical Mechanical Polishing), or the like, to expose the dummy components 80. Since the dummy components 80 are made of a harder material than the cured third insulating film 90 and columnar electrodes 60, polishing of the third insulating film 90 and columnar electrodes 60 can be stopped when the dummy components 80 are exposed. For example, if the thickness of the dummy components 80 and the resin layer 70 beneath them is approximately 30 μm, the thickness of the third insulating film 90 can also be approximately 30 μm. Since the upper surface of the dummy components 80 is lower than the upper surface of the columnar electrodes 60, polishing of the dummy components 80 can be stopped after the columnar electrodes 60 are exposed.

[0101] Next, if Figure 11As shown, flux is applied to columnar electrode 60 to form metal bump 100. Metal bump 100 uses a metal such as solder with Sn as its primary component. For example, Sn, Ag, Cu, Au, Pd, Bi, or Zn can be used alone, or as a composite film of two or more of these, or as an alloy. Next, metal bump 100 is connected to columnar electrode 60 by reflow soldering.

[0102] Next, the semiconductor wafer W is cut into individual semiconductor chips 10 using a blade dicing method or a laser dicing method. Figure 11 The semiconductor device 1 shown in FIG. Then, as Figure 12 As shown, semiconductor device 1 is mounted on wiring substrate 200, and metal bumps 100 are connected to electrode pads on wiring substrate 200. Other semiconductor devices can also be mounted on wiring substrate 200 and modularized. Alternatively, semiconductor wafer W can be mounted on wiring substrate 200, and then the semiconductor wafer W and wiring substrate 200 can be cut together. Metal bumps 100 can also be formed on wiring substrate 200. In this case, the exposed surface of columnar electrode 60 is connected to metal bumps 100 formed on wiring substrate 200.

[0103] As described above, according to this embodiment, dummy members 80 are provided on first surface F10a along with pillar electrodes 60. Dummy members 80 are made of a material harder than pillar electrodes 60 and third insulating film 90, and function as a stopper during the polishing process of third insulating film 90. This prevents uneven thickness of third insulating film 90, and stabilizes the thickness of the semiconductor device 1 package.

[0104] Furthermore, the thickness of the third insulating film 90 can be controlled according to the thickness of the dummy member 80. Therefore, it is not necessary to measure the thickness of the third insulating film 90 during polishing, and throughput can be improved.

[0105] Furthermore, since the dummy member 80 is made of a harder material than the columnar electrode 60 and the third insulating film 90 , the semiconductor device 1 is reinforced and is less likely to warp, thereby contributing to improved reliability of the semiconductor device 1 .

[0106] For example, a thermal cycle test was performed on the semiconductor device 1 of this embodiment to investigate its reliability. The thermal cycle test consisted of a cycle consisting of -55°C (30 minutes), 25°C (5 minutes), and 125°C (30 minutes). The results showed that even after 3,000 cycles, the semiconductor device 1 showed no problems.

[0107] (Second embodiment)

[0108] Figure 13 and Figure 14 It is a cross-sectional view showing an example of a manufacturing method and a structure of the semiconductor device 1 according to the second embodiment. Figure 13 The structure of the semiconductor device 1 during manufacturing is shown, and the structure of the semiconductor device 1 during manufacturing is shown. Figure 9 The corresponding status. Figure 14 The structure of the completed semiconductor device 1 is shown.

[0109] In the second embodiment, the dummy component 80 is divided into components 80a to 80c as a plurality of second components having different areas when viewed from above the first surface F10a, forming a laminated body formed by stacking the components 80a to 80c. By making the areas of the components 80a to 80c different, the grinding area of ​​the dummy component 80 changes. Since the grinding resistance changes based on the change in the grinding area of ​​the dummy component 80, the grinding device (not shown) can identify the component 80a to 80c being ground. The grinding device stops the grinding process when the grinding area (or grinding resistance) of the dummy component 80 reaches a specified value. As long as the thickness of the components 80a to 80c and the resin layer 70a to 70c corresponding to the grinding area (or grinding resistance) of the dummy component 80 is pre-set, the residual film thickness of the dummy component 80 during grinding (the residual film thickness of the third insulating film 90) can be controlled.

[0110] The manufacturing method of the second embodiment will be described in more detail.

[0111] go through Figures 2 to 7 After the process shown, component 80a is bonded to the second insulating film 40 using the resin layer 70a, component 80b is bonded to component 80a using the resin layer 70b, and component 80c is bonded to component 80b using the resin layer 70c. For example, the thickness of components 80a to 80c is set to approximately 10 μm, and the thickness of resin layers 70a to 70c is set to approximately 5 μm. In this case, the height of the dummy component 80 becomes approximately 45 μm. In addition, when viewed from above the first surface F10a, the area of ​​component 80a among components 80a to 80c is the largest, and becomes smaller in the order of components 80b and 80c. Thus, as Figure 13 As shown, the side surfaces of components 80a to 80c are configured to have step-like steps. The material of components 80a to 80c can be the same as that of dummy component 80 in the first embodiment. In addition, the material of resin layers 70a to 70c can be the same as that of resin layer 70 in the first embodiment.

[0112] Next, like reference Figure 9 As described above, the third insulating film 90 is formed so as to fill the members 80a to 80c and the columnar electrodes 60. Figure 13 The structure shown.

[0113] Next, the third insulating film 90 and the columnar electrode 60 are ground to expose the dummy component 80. At this time, the dummy components 80 are ground in sequence starting from component 80c. Therefore, the grinding area of ​​the dummy component 80 is initially small, but gradually becomes larger. Since the grinding resistance changes according to the grinding area of ​​the dummy component 80, the grinding device can detect which of the components 80a to 80c is exposed. In this way, the thickness of the third insulating film 90 can be controlled. For example, when the grinding is stopped at the time when component 80b is exposed, after component 80c and the resin layer 70c are ground, the grinding device stops grinding at the time when component 80b is exposed. In this way, as Figure 14 As shown, the thickness of the third insulating film 90 can be controlled to be substantially equal to the total thickness of the members 80a, 80b and the resin layers 70a, 70b (for example, 30 μm in the case of the example described).

[0114] Next, flux is applied on the columnar electrodes 60 to form metal bumps 100. Next, the semiconductor wafer W is cut and singulated into semiconductor chips 10. Thus, the process is completed. Figure 14 The semiconductor device 1 is shown.

[0115] Grinding can also be stopped when component 80a is exposed. In addition, dummy component 80 can also be a laminate of two layers of components, or a laminate of four or more layers of components. The thickness of each component 80a to 80c can also be different as long as it is determined in advance.

[0116] According to the second embodiment, the dummy component 80 is formed as a laminate of multiple components 80a-80c having different areas when viewed from above. Furthermore, the thicknesses of the components 80a-80c and the resin layers 70a-70c are predetermined. This facilitates control of the thickness of the third insulating film 90. The remaining configuration of the second embodiment can be the same as that of the first embodiment. Therefore, the second embodiment can also achieve the same effects as the first embodiment.

[0117] (Third embodiment)

[0118] Figure 15 and Figure 16 It is a cross-sectional view showing an example of a manufacturing method and a structure of the semiconductor device 1 according to the third embodiment. Figure 15 The structure of the semiconductor device 1 during manufacturing is shown, and the structure of the semiconductor device 1 during manufacturing is shown. Figure 9 The corresponding status. Figure 16 The structure of the completed semiconductor device 1 is shown.

[0119] In the third embodiment, the dummy component 80 has a stepped step ST on its side surface F80c. Due to the step ST of the side surface F80c of the dummy component 80, the area of ​​each step ST when viewed from the first surface F10a varies, thereby varying the polishing area of ​​the dummy component 80. Since the polishing resistance of the polishing device changes based on the change in the polishing area of ​​the dummy component 80, the height of the step ST of the dummy component 80 being polished can be specified. By presetting the thickness (height) of each step ST of the dummy component 80, the remaining film thickness of the dummy component 80 during polishing (the remaining film thickness of the third insulating film 90) can be controlled.

[0120] The manufacturing method of the third embodiment will be described in more detail.

[0121] In passing Figures 2 to 7 After the illustrated steps, the dummy component 80 is bonded to the second insulating film 40 using the resin layer 70a. The dummy component 80 has a top surface F80a, a back surface F80b, and a side surface F80c. A step ST is formed on the side surface F80c of the dummy component 80. The step ST can also be formed using photolithography and etching techniques. Alternatively, the step ST can be formed using machining techniques or a dicing blade. The step ST can be formed after the dummy component 80 is attached to the second insulating film 40, or before the dummy component 80 is attached to the second insulating film 40. For example, the thickness of each step ST is set to approximately 10 μm, and the number of step ST stages is set to five. In this case, the height Hst from the lowest to the highest stage of the step ST of the dummy component 80 is approximately 40 μm. Furthermore, when viewed from above the first surface F10a, the polishing area of ​​the dummy component 80 is smallest at the top stage of the dummy component 80 and increases as it moves downward. The material of the dummy member 80 may be the same as that of the dummy member 80 in the first embodiment.

[0122] Next, like reference Figure 9 As described above, the third insulating film 90 is formed so as to fill the dummy member 80 and the columnar electrode 60. Figure 15 The structure shown.

[0123] Next, the third insulating film 90 and the columnar electrode 60 are ground to expose the dummy component 80. At this time, the dummy component 80 is ground in sequence from the upper section to the lower section. Therefore, the grinding area of ​​the dummy component 80 is initially small, but gradually becomes larger. Since the grinding resistance changes according to the grinding area of ​​the dummy component 80, the grinding device can detect which height step difference portion is exposed. Thus, the thickness of the third insulating film 90 can be controlled. For example, when grinding is stopped at the time point when the upper surface of the fourth section from the uppermost section of the dummy component 80 is exposed, after the third section from the uppermost section of the dummy component 80 is ground, the grinding device stops grinding at the time point when the upper surface of the fourth section is exposed. Thus, as Figure 16 As shown, the thickness of the third insulating film 90 can be controlled to be substantially equal to the total thickness of the dummy members 80 in the fourth and subsequent stages and the resin layer 70. In this case, Hst is, for example, 10 μm.

[0124] Next, flux is applied on the columnar electrodes 60 to form metal bumps 100. Next, the semiconductor wafer W is cut and singulated into semiconductor chips 10. Thus, the process is completed. Figure 16 The semiconductor device 1 is shown.

[0125] The step at which the grinding stops is not particularly limited. The grinding may also be stopped at the time when the third segment from the top of the dummy component 80 is exposed. The number of steps ST is also not particularly limited. In addition, the heights of the steps ST may be different from each other as long as they are determined in advance.

[0126] Thus, according to the third embodiment, the dummy component 80 includes a third surface (ground surface) F80a_1 exposed from the third insulating film 90, a fourth surface F80b corresponding to the first surface F10a of the semiconductor chip, and a side surface F80c located between the third surface F80a_1 and the fourth surface F80b. The side surface F80c has a stepped shape with a step ST. Furthermore, the height (thickness) of the step ST is predetermined. This facilitates control of the thickness of the third insulating film 90. The remaining configuration of the third embodiment can be the same as that of the first embodiment. Therefore, the third embodiment can also achieve the same effects as the first embodiment.

[0127] (Fourth embodiment)

[0128] Figure 17 and Figure 18 It is a cross-sectional view showing an example of a manufacturing method and a structure of the semiconductor device 1 according to the fourth embodiment. Figure 17 The structure of the semiconductor device 1 during manufacturing is shown, and the structure of the semiconductor device 1 during manufacturing is shown. Figure 9 The corresponding status. Figure 18 The structure of the completed semiconductor device 1 is shown.

[0129] In the fourth embodiment, the dummy component 80 has a recessed portion at the center of its upper surface F80a, and has stepped steps ST on both sides of the recessed portion. The area of ​​the dummy component 80 in each step ST when viewed from above the first surface F10a varies according to the step ST, thereby changing the grinding area of ​​the dummy component 80. The grinding resistance of the grinding device changes based on the change in the grinding area of ​​the dummy component 80, so the height of the step ST of the dummy component 80 being ground can be specified. By presetting the thickness (height) of each step ST of the dummy component 80, the remaining film thickness of the dummy component 80 during grinding (the remaining film thickness of the third insulating film 90) can be controlled in the same manner as in the third embodiment.

[0130] According to the fourth embodiment, steps ST are provided on both sides of the recessed portion at the center of upper surface F80a. The remaining configuration and manufacturing method of the fourth embodiment, including the number of steps ST, height, and formation method, can be the same as those of the third embodiment. Therefore, the fourth embodiment can achieve the same effects as the third embodiment.

[0131] (Fifth embodiment)

[0132] Figure 19 and Figure 20 It is a cross-sectional view showing an example of a manufacturing method and a structure of the semiconductor device 1 according to the fifth embodiment. Figure 19 The structure of the semiconductor device 1 during manufacturing is shown, and the structure of the semiconductor device 1 during manufacturing is shown. Figure 9 The corresponding status. Figure 20 The structure of the completed semiconductor device 1 is shown.

[0133] In the fifth embodiment, the dummy component 80 has an inclination on its side F80c. The side F80c is inclined from a direction perpendicular to the first surface F10a. By utilizing the inclination of the side F80c of the dummy component 80, the area when observed from the top of the first surface F10a is different according to the height position of the grinding surface of the dummy component 80, thereby changing the grinding area of ​​the dummy component 80. Since the grinding resistance changes based on the change in the grinding area of ​​the dummy component 80, the grinding device can specify the height of the grinding surface of the dummy component 80 being ground. If the area of ​​the upper surface F80a of the dummy component 80 and the inclination of the side F80c are pre-set, the residual film thickness (residual film thickness of the third insulating film 90) of the dummy component 80 during grinding can be controlled.

[0134] In the fifth embodiment, since the side surface F80c of the dummy member 80 is a continuous inclined surface, the thickness of the third insulating film 90 can be more finely controlled. The remaining configuration and manufacturing method of the fifth embodiment can be the same as those of the third or fourth embodiment. Therefore, the fifth embodiment can achieve the same effects as those of the third or fourth embodiment.

[0135] The dummy member 80 may be a triangular pyramid, a square hammer, a polygonal hammer, a cone, etc. with the upper portion thereof being flat. The dummy member 80 can be formed by, for example, cutting a semiconductor wafer in a direction oblique to its surface.

[0136] (Sixth embodiment)

[0137] Figure 21 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the sixth embodiment. In the sixth embodiment, a redistribution layer (RDL) 120 is provided on the third insulating film 90. The redistribution layer 120 is provided on the third insulating film 90, the columnar electrode 60, and the dummy component 80, and has a multilayer wiring structure formed by stacking a wiring layer 121 and an insulating layer 122. The wiring layer 121 is made of, for example, a monomer such as Ti, TiN, Cr, CrN, Cu, Ni, Au, Pd, W, Al, or Ag, a composite film of two or more of these, or an alloy of two or more of these. The insulating layer 122 is made of, for example, a phenolic, polyimide, polyamide, acrylic, epoxy, PBO, silicone, or benzocyclobutene resin, a composite film of two or more of these, or a compound of two or more of these. The columnar electrode 60 is electrically connected to a portion of the wiring layer 121. The metal bump 100 is provided on the electrode pad of the wiring layer 121 and is electrically connected to a portion of the wiring layer 121. Thus, the electrode bump 100 is electrically connected to either the columnar electrode 60 or the semiconductor element via the redistribution layer 120. By using the redistribution layer 120, the degree of freedom in the arrangement of the columnar electrode 60 can be increased. Figure 12 Similarly to the structure shown, the semiconductor device 1 according to the sixth embodiment can also be mounted on the wiring substrate 200 .

[0138] The other configurations of the sixth embodiment can be the same as the corresponding configurations of the first embodiment. Thus, the sixth embodiment can achieve the same effects as the first embodiment. The sixth embodiment can also be combined with any of the second to fifth embodiments.

[0139] (Seventh embodiment)

[0140] Figures 22 to 24 It is a cross-sectional view showing an example of a manufacturing method and a structure of the semiconductor device 1 according to the seventh embodiment. Figure 22 and Figure 23 The structure of the semiconductor device 1 during manufacture is shown. Figure 24 The structure of the completed semiconductor device 1 is shown.

[0141] In the sixth embodiment, the redistribution layer 120 is provided on the columnar electrodes 60 and the dummy members 80 . In contrast, in the seventh embodiment, the redistribution layer 120 is provided below the columnar electrodes 60 and the dummy members 80 .

[0142] The manufacturing method of the seventh embodiment will be described in more detail.

[0143] In passing Figures 2 to 7 After the steps shown in FIG. 8 , the electrode 55 and the second insulating film 40 are covered with the insulating film 85. In the seventh embodiment, since the barrier metal 50 and the columnar electrode 60 are formed on the redistribution layer 120, Figure 7 The barrier metal 50 and the columnar electrode 60 are referred to herein as the barrier metal 45 and the electrode 55, respectively. Note that the dummy component 80 is not formed at this stage. The insulating film 85 is a third insulating film 90 made of a resin such as a phenolic, polyimide, polyamide, acrylic, epoxy, PBO (p-phenylenebenzobisoxazole), silicone, or benzocyclobutene resin, or a mixed or composite material of these resins. The materials of the barrier metal 45 and the electrode 55 can be the same as those of the barrier metal 50 and the columnar electrode 60, respectively.

[0144] After the electrode 55 and the second insulating film 40 are covered with the insulating film 85, the electrode 55 is exposed by photolithography such as exposure and development. Figure 22 structure.

[0145] Next, if Figure 23 As shown, a redistribution layer 120 is formed on the electrode 55 and the insulating film 85 .

[0146] Then, as described in the first embodiment, the barrier metal 50 and the columnar electrode 60 are formed on the wiring layer 121, and the dummy component 80 is bonded to the insulating layer 122 using the resin layer 70. The columnar electrode 60 and the dummy component 80 are buried with the third insulating film 90, and the third insulating film 90 is polished until the dummy component 80 is exposed. The metal bump 100 is formed on the columnar electrode 60. Thus, the Figure 24 The semiconductor device 1 is shown.

[0147] In this manner, the redistribution layer 120 can also be provided below the columnar electrodes 60 and the dummy components 80. The metal bumps 100 and the columnar electrodes 60 are electrically connected to any semiconductor element of the semiconductor chip 10 via the redistribution layer 120. In this case, the layout of the columnar electrodes 60, the dummy components 80, and the metal bumps 100 can be more flexible.

[0148] The remaining configurations and manufacturing methods of the seventh embodiment can be the same as those of the sixth embodiment. Thus, the seventh embodiment can also achieve the effects of the sixth embodiment. Furthermore, the seventh embodiment can be combined with any of the second to fifth embodiments.

[0149] (Eighth embodiment)

[0150] Figure 25 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 of the eighth embodiment. In the eighth embodiment, the columnar electrode 60 is different from the first embodiment in that it is formed using a metal wire by a wire bonding method. Hereinafter, the columnar electrode 60 will also be referred to as a metal wire 60. When the columnar electrode 60 is formed by a metal wire, the metal wire 60 is bonded to the electrode pad 30 by a wire bonding method. In this case, the diameter (width) Φ3 of the metal wire 60 is smaller than the opening diameter Φ1 of the electrode pad 30 exposed from the first insulating film 20, 40. In addition, the area of ​​the metal wire 60 exposed from the third insulating film 90 is smaller than the contact area (bonding area) of the metal wire 60 with respect to the semiconductor chip 10. Furthermore, since the metal wire 60 can be formed by a wire bonding method, the manufacturing cost is low compared to electrodes formed by a plating method. Such characteristics are obtained when a metal wire is used for the columnar electrode 60. The metal wire 60 is made of a low-resistance metal such as Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, or Al, a composite film of two or more of these, or an alloy of two or more of these. For example, a material formed by coating Cu with Pd may also be used. To prevent the metal wire 60 from collapsing during formation of the third insulating film 90, it is preferable to use relatively hard Cu, a CuPd alloy, or a CuPd-coated Cu material for the metal wire 60.

[0151] The manufacturing method of the eighth embodiment will be described.

[0152] In passing Figure 2After the process shown, one end of the metal wire 60 is bonded to the electrode pad 30 using a wire bonding machine. Next, the metal wire 60 is pulled out in a direction approximately perpendicular to the upper direction of the first surface F10a and cut. Thus, the metal wire 60 is formed into a columnar electrode that stands upright in a direction approximately perpendicular to the first surface F10a. Then, similarly to the first embodiment, a dummy component 80, a third insulating film 90 and a metal bump 100 are formed. Alternatively, the metal bump 100 may be formed after the metal wire 60 is exposed and after an electrode pad larger than the exposed surface is formed. Thus, the process is completed. Figure 25 The semiconductor device 1 is shown.

[0153] In the eighth embodiment, the columnar electrodes 60 are formed using wire bonding using metal wires, making them cheaper and simpler to form than plating. The remaining configuration and manufacturing method of the eighth embodiment are the same as those of the first embodiment. Therefore, the eighth embodiment can also achieve the same effects as the first embodiment. The eighth embodiment can also be combined with any of the first to seventh embodiments.

[0154] (Ninth embodiment)

[0155] Figure 26 This is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a ninth embodiment. The ninth embodiment differs from the first embodiment in that the columnar electrodes 60 include both columnar electrodes 60a formed by plating and columnar electrodes (metal wires) 60b formed by wire bonding. Specifically, the columnar electrodes 60 include a mixture of the columnar electrodes 60a formed by plating and the columnar electrodes 60b formed by wire bonding.

[0156] The area of ​​the columnar electrode 60a exposed from the third insulating film 90 may be larger than the contact area of ​​the columnar electrode 60a with the semiconductor chip 10. On the other hand, the area of ​​the columnar electrode 60b exposed from the third insulating film 90 may be smaller than the contact area of ​​the columnar electrode 60b with the semiconductor chip 10.

[0157] In other words, the diameter Φ2 of the columnar electrode 60a formed by plating can be larger than the opening diameter Φ1 of the electrode pad 30 exposed from the first insulating films 20 and 40. The diameter Φ3 of the metal wire 60b formed by bonding can be smaller than the opening diameter Φ1 of the electrode pad 30 exposed from the first insulating films 20 and 40.

[0158] The remaining configurations and manufacturing methods of the ninth embodiment are the same as those of the first embodiment. Therefore, the ninth embodiment can also achieve the same effects as the first embodiment. The ninth embodiment can also be combined with any of the first to seventh embodiments.

[0159] (10th embodiment)

[0160] Figure 27 This is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the tenth embodiment. In the tenth embodiment, the dummy component 80 is a conductor, and the electrode pad 30 and the barrier metal 50 are provided below the dummy component 80. The dummy component 80 is in contact with the barrier metal 50 and is electrically connected to either the electrode pad 30 or the semiconductor element of the semiconductor chip 10 via the barrier metal 50.

[0161] In the tenth embodiment, the dummy component 80 functions as both a polishing stopper and an electrode. The dummy component 80 can also function as a power supply electrode to supply power to the semiconductor chip 10. For example, the dummy component 80 can be connected using solder or conductive paste. Alternatively, the dummy component 80 can function as a ground electrode to supply a ground voltage to the semiconductor chip 10. Furthermore, the dummy component 80 can also function as a heat sink that absorbs and releases heat from the semiconductor chip 10.

[0162] The remaining configurations and manufacturing methods of the tenth embodiment are the same as those of the first embodiment. Therefore, the tenth embodiment can also achieve the same effects as the first embodiment. The tenth embodiment can also be combined with any of the first to ninth embodiments.

[0163] Hereinafter, an embodiment of packaging the laminate of the semiconductor chip 10 will be described.

[0164] (11th embodiment)

[0165] Figure 28 This is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the eleventh embodiment. In the eleventh embodiment, a plurality of semiconductor chips 10 are stacked, and pillar-shaped electrodes 60 extend from each semiconductor chip 10 in a direction substantially perpendicular to the surface of the semiconductor chip 10. Dummy components 80 are arranged on the stack of semiconductor chips 10, with the upper surface of dummy components 80 positioned higher than the surface of the topmost semiconductor chip 10. Therefore, the surface of the topmost semiconductor chip 10 is not exposed from the third insulating film 90 but is covered by the third insulating film 90.

[0166] The plurality of semiconductor chips 10 may be, for example, memory chips of NAND-type flash memories or semiconductor chips equipped with any LSI. The plurality of semiconductor chips 10 may be semiconductor chips having the same structure or semiconductor chips having different structures. For example, the topmost semiconductor chip 10 among the plurality of semiconductor chips 10 may be a controller chip that controls the memory chip, and the other semiconductor chips 10 may be memory chips. The semiconductor chips 10 are bonded to each other using an adhesive layer 12. In the semiconductor chip 10, the surface F10a serves as the element forming surface on which the semiconductor element is formed. The back surface F10b on the opposite side of the surface F10a is bonded to other semiconductor chips 10 using an adhesive layer 12.

[0167] The adhesive layer 12 is provided between the semiconductor chips 10 in order to stack the plurality of semiconductor chips 10. The adhesive layer 12 may be made of, for example, DAF (Die Attach Film) or DAP (Die Attach Paste) containing a phenolic, polyimide, polyamide, acrylic, epoxy, PBO (p-phenylenebenzobisoxazole), silicone, or benzocyclobutene resin, or a mixed or composite material of these resins.

[0168] The columnar electrodes 60 extend in a direction approximately perpendicular to the surface F10a of the semiconductor chip 10 and are connected to each semiconductor chip 10. One end of the columnar electrodes 60 is connected to the electrode pad P10 of the semiconductor chip 10, and the other end is connected to the metal bump 100. For example, the semiconductor chips 10 are stacked in a staggered manner, and the columnar electrodes 60 extend from each electrode pad P10 provided at the step portion at the end of the plurality of semiconductor chips 10. Thus, each semiconductor chip 10 can be connected to the metal bump 100 via the columnar electrodes 60 and can directly exchange signals with the redistribution layer or external devices without passing through other semiconductor chips 10. As a result, the amount of communication data and the communication speed between the semiconductor chip 10 and a controller, etc. can be increased. The columnar electrodes 60 can be, for example, metal wires used for bonding wires or columnar electrodes formed by plating. For example, as described below, the columnar electrodes 60 of the topmost semiconductor chip 10 can be columnar electrodes formed by plating, while the columnar electrodes 60 of the semiconductor chips 10 below it can be formed by metal wires used for bonding wires. The columnar electrodes 60 are made of low-resistance metals such as Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, and Al, single metals, composite films of two or more of these, or alloys of two or more of these.

[0169] The dummy component 80 is attached to the laminate of multiple semiconductor chips 10 using a resin layer 70 and is positioned next to the topmost semiconductor chip 10. The top surface of the dummy component 80 is located higher than the top surface of the topmost semiconductor chip 10 and functions as a polishing stopper for the third insulating film 90.

[0170] The third insulating film 90 covers and protects the semiconductor chip 10 and the columnar electrodes 60. The third insulating film 90 covers the surface of the uppermost semiconductor chip 10 so that it is not exposed.

[0171] Metal bumps 100 are provided on columnar electrodes 60 to establish electrical connections with other components. Metal bumps 100 are made of a low-resistance metal such as solder primarily composed of Sn. Alternatively, metal bumps 100 may be formed after exposing metal wires 60 and forming electrode pads larger than the exposed surface.

[0172] Next, a method for manufacturing the semiconductor device 1 according to the eleventh embodiment will be described.

[0173] Figures 29 to 31 It is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 according to the eleventh embodiment.

[0174] First, if Figure 29 As shown, a plurality of semiconductor chips 10 are stacked on a supporting substrate 5. At this time, the semiconductor chips 10 are bonded to other semiconductor chips 10 using adhesive layers 12.

[0175] Next, the dummy component 80 is bonded to the laminate of the semiconductor chips 10 using the resin layer 70. At this time, the upper surface of the dummy component 80 is positioned higher than the upper surface of the semiconductor chip 10 on the uppermost layer.

[0176] Next, if Figure 30 As shown, metal wires are bonded to electrode pads P10 of semiconductor chip 10 by wire bonding and extended in a direction substantially perpendicular to first surface F10a to form columnar electrodes 60. Alternatively, the material of several metal wire columnar electrodes 60 may be changed to replace dummy components 80.

[0177] Next, if Figure 31 As shown, the laminated body of the semiconductor chip 10, the dummy components 80, and the columnar electrodes 60 are covered with a third insulating film 90. For example, the third insulating film 90 is a molding resin, and the laminated body of the semiconductor chip 10, the dummy components 80, and the columnar electrodes 60 are sealed with this resin. Next, the third insulating film 90 is cured.

[0178] Next, the third insulating film 90 is polished by mechanical polishing, CMP, etc. until the dummy component 80 is exposed. Next, after removing the supporting substrate 5, the metal bump 100 is formed on the columnar electrode 60. The metal bump 100 can be formed by, for example, ball mounting, plating, or printing. Thus, the process is completed. Figure 28 The semiconductor device 1 is shown. Alternatively, the supporting substrate 5 may be removed after the metal bumps 100 are formed.

[0179] Furthermore, as described below, the columnar electrode 60 can also be formed using a plating method. In this case, after forming the third insulating film 90, a hole that reaches the electrode pad 30 is formed in the third insulating film 90 using photolithography and etching techniques. Furthermore, the hole is filled with metal using a plating method. In this way, the columnar electrode 60 can also be formed. Alternatively, the columnar electrode 60 can be formed in advance on the semiconductor chip 10 using a plating method or the like, and the semiconductor chip 10 can be mounted thereon. Alternatively, the supporting substrate 5 can be removed from the semiconductor device 1, or it can remain in the semiconductor device 1 as a heat sink.

[0180] Alternatively, the semiconductor device 1 may be mounted on the wiring substrate 200 . Figure 32 This is a cross-sectional view showing a semiconductor device 1 according to the eleventh embodiment mounted on a wiring substrate 200. The semiconductor device 1 is mounted with the metal bumps 100 facing the wiring substrate 200, and is electrically connected to a portion of the wiring on the wiring substrate 200 via the metal bumps 100. This allows the semiconductor device 1 to be modularized with other semiconductor devices. Alternatively, the metal bumps 100 may be formed on the wiring substrate 200. In this case, the exposed surface of the columnar electrode 60 is connected to the metal bumps 100 formed on the wiring substrate 200.

[0181] (12th embodiment)

[0182] Figure 33 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the twelfth embodiment. In the twelfth embodiment, the dummy component 80 is a conductor, and a metal bump 100 is provided on the dummy component 80. The dummy component 80 is electrically connected to a portion of the wiring of the wiring substrate 200 via the metal bump 100. The dummy component 80 has both the function of a polishing stopper and the function of an electrode. The dummy component 80 can also serve as a power supply electrode to supply power to the semiconductor chip 10. Alternatively, the dummy component 80 can also serve as a ground electrode to supply a ground voltage to the semiconductor chip 10. Furthermore, the dummy component 80 also has the function of a heat sink that absorbs and releases heat from the semiconductor chip 10.

[0183] Furthermore, in the stack of semiconductor chips 10, the bottom semiconductor chip 10 ( Figure 33A supporting substrate 5 remains on the back surface F10b of the semiconductor chip 10 (shown at the top). The supporting substrate 5 contacts the back surface F10b of the bottommost semiconductor chip 10, functioning as a heat sink. Furthermore, the supporting substrate 5 can also serve as a ground electrode to supply a ground voltage to the semiconductor chip 10. The supporting substrate 5 can also be a conductive material such as metal, or a lead frame made of a thermally conductive material.

[0184] The other configurations and manufacturing methods of the twelfth embodiment can be the same as the corresponding configurations and manufacturing methods of the eleventh embodiment. Therefore, the twelfth embodiment can also obtain the same effects as the eleventh embodiment.

[0185] (Thirteenth embodiment)

[0186] Figure 34 This is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the thirteenth embodiment. The thirteenth embodiment differs from the eleventh embodiment in that a dummy component 81 is further provided. The dummy component 81 penetrates the third insulating film 90 and is provided in the stacking direction of the semiconductor chip 10, adjacent to the stacked structure of the semiconductor chip 10. The dummy component 81 is made of the same material as the dummy component 80 and is harder than the third insulating film 90 and the columnar electrode 60. The addition of the dummy component 81 further reduces warping of the semiconductor device 1 package.

[0187] The dummy member 81 is formed before the third insulating film 90 is formed. Figure 29 or Figure 30 In the process, the dummy component 81 is arranged in a manner that stands upright on the supporting substrate 5. The heights of the dummy components 80 and 81 are preferably approximately equal. Then, as described in the eleventh embodiment, the semiconductor chip 10 is buried with the third insulating film 90, and the third insulating film 90 is polished. At this time, the dummy components 80 and 81 serve as a polishing stopper. The other structures and manufacturing methods of the thirteenth embodiment can be the same as the corresponding structures and manufacturing methods of the eleventh embodiment. The thirteenth embodiment can also be combined with any of the first to twelfth embodiments.

[0188] (Variation 1)

[0189] When the third insulating film 90 is formed by pouring molten resin into a mold, the resin is preferably Figure 31 The resin flows in the direction indicated by arrow A1. The direction of arrow A1 indicates the direction in which columnar electrodes 60 are located when viewed from the laminate of semiconductor chip 10. The laminate of semiconductor chip 10 mitigates the flow of resin, preventing direct impact on columnar electrodes 60. Thus, the flow of resin can prevent columnar electrodes 60 from collapsing or warping.

[0190] Figure 35This diagram illustrates the resin sealing step of Modification 1. Molten resin is introduced from insertion port 410 in the direction of arrow A1 and sealed within molds 400 and 401. At this point, the sealed laminate of semiconductor chips 10 is positioned upstream of columnar electrodes 60 to protect them, preventing them from collapsing or warping.

[0191] (Variation 2)

[0192] Figure 36 This diagram illustrates the resin sealing step of Modification 2. When molten resin is poured into molds 400 and 401 to form third insulating film 90, a release film 420 is provided on the inner surfaces of molds 400 and 401. Release film 420 is provided to remove the resin-sealed semiconductor chip 10 from the mold and is made of resin or the like.

[0193] Variation 2 shows an example of resin sealing using compression molding. A release film 420 is placed inside molds 400 and 401, and resin is applied thereto. Then, the semiconductor chip 10, with columnar electrodes 60 formed thereon, is inverted and placed into the resin for compression molding. The columnar electrodes 60 physically penetrate the release film 420 inside the molds 400 and 401. The columnar electrodes 60 can be pressed into the release film 420 or penetrate it. This allows the ends of the columnar electrodes 60 to be fixed during the resin sealing process, preventing them from collapsing or bending due to the flow of resin.

[0194] The tensile strength of the release film 420 is preferably, for example, 1 MPa to 100 MPa. If the tensile strength of the release film 420 is less than 1 MPa, it is difficult for the release film 420 to secure the columnar electrodes 60. If the tensile strength of the release film 420 is greater than 100 MPa, it is difficult for the columnar electrodes 60 to penetrate the release film 420. Therefore, by setting the tensile strength of the release film 420 to 100 MPa, the release film 420 can prevent the columnar electrodes 60 from collapsing or bending during the resin sealing process.

[0195] (14th embodiment)

[0196] Figure 37 This is a cross-sectional view showing an example configuration of a semiconductor device 1 according to the fourteenth embodiment. In the fourteenth embodiment, the pillar electrodes 60 include both pillar electrodes 60a formed using bonding wires and pillar electrodes 60b formed using plating. For example, the pillar electrodes 60b are formed using plating on the topmost semiconductor chip 10b. The pillar electrodes 60a are formed using wire bonding on other semiconductor chips 10a. The semiconductor chip 10a is, for example, a memory chip, and the semiconductor chip 10b is, for example, a controller chip.

[0197] Figures 38 to 40 14 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 according to the fourteenth embodiment. Figures 29 to 31 Thus, we obtain Figure 38 Then, as Figure 39 As shown, the portion where the columnar electrode 60b is formed is scraped off the third insulating film 90 using laser processing technology or the like. This forms a hole H60b in the third insulating film 90. The hole H60b is formed from the upper surface of the third insulating film 90 to the electrode pad P10 of the semiconductor chip 10b.

[0198] Next, after forming a barrier metal on the electrode pad P10 of the semiconductor chip 10b, as shown in FIG. Figure 40 As shown, the metal material of the columnar electrode 60b is buried in the hole H60b using a plating method. In this way, the columnar electrode 60b is formed. Alternatively, the semiconductor chip 10 may be mounted after the columnar electrode 60 is formed in advance using a plating method or the like.

[0199] Then, the third insulating film 90 and the columnar electrodes 60a and 60b are polished by mechanical polishing or CMP until the dummy member 80 is exposed. Furthermore, the metal bumps 100 are formed on the columnar electrodes 60a and 60b to complete the process. Figure 37 The semiconductor device 1 is shown.

[0200] (15th embodiment)

[0201] Figure 41 This is a cross-sectional view showing an example configuration of a semiconductor device 1 according to a fifteenth embodiment. In Modification 3, columnar electrodes 60a and 60b protrude from the surface of the third insulating film 90 toward the metal bump 100. By having columnar electrodes 60a and 60b penetrate the metal bump 100, the semiconductor device 1 is stably connected to the wiring substrate 200 when flip-chip connection is made to the wiring substrate 200, helping to prevent defects.

[0202] The protruding shapes of the columnar electrodes 60a and 60b can be formed by polishing the third insulating film 90 and then etching only the third insulating film 90 using plasma or the like. The dummy member 80 also has a protruding shape.

[0203] The other configurations of the fifteenth embodiment may be the same as the corresponding configurations of the fourteenth embodiment. The fifteenth embodiment may be combined with any one of the twelfth and thirteenth embodiments.

[0204] (16th embodiment)

[0205] Figure 42This is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the sixteenth embodiment. The semiconductor device 1 according to the sixteenth embodiment further includes dummy columnar electrodes 60c and 60d. One end of the dummy columnar electrode 60c is bonded to the supporting substrate 5, and the other end is provided to the surface of the third insulating film 90. One end of the dummy columnar electrode 60d is bonded to any one of the semiconductor chips 10, and the other end is provided to the surface of the third insulating film 90. Metal bumps 100 are provided at the other ends of the dummy columnar electrodes 60c and 60d and are connected to the wiring substrate 200. When the columnar electrodes 60 are offset toward one side of the semiconductor device 1, the dummy columnar electrodes 60c and 60d are provided on the other side of the semiconductor device 1. This makes the arrangement of the metal bumps 100 between the semiconductor device 1 and the wiring substrate 200 relatively uniform, and the stress during the temperature cycle test is alleviated. As a result, reliability is improved. Furthermore, the dummy columnar electrodes 60 c and 60 d may be electrically connected to the semiconductor chip 10 and the wiring substrate 200 , or may not be electrically connected to the semiconductor chip 10 and the wiring substrate 200 .

[0206] The layout and number of dummy columnar electrodes 60c and 60d are set so that the positions of metal bumps 100 between semiconductor device 1 and wiring substrate 200 are relatively uniform. Furthermore, the diameter and material of dummy columnar electrodes 60c and 60d may be the same as or different from those of columnar electrodes 60a and 60b. For example, the material of dummy columnar electrodes 60c and 60d may be replaced with that of columnar electrodes 60a and 60b, allowing them to function as dummy components 80. The remaining configuration of the sixteenth embodiment may be the same as the corresponding configuration of the fifteenth embodiment. The sixteenth embodiment may also be combined with any of the twelfth and thirteenth embodiments.

[0207] (Seventeenth embodiment)

[0208] Figure 43 It is a cross-sectional view showing a configuration example of a semiconductor device 1 according to the seventeenth embodiment. Figure 44 This is a top view showing an example of the configuration of a semiconductor device 1 according to the seventeenth embodiment. According to the seventeenth embodiment, a plurality of dummy columnar electrodes 60c are provided on both sides or at the corners of the semiconductor device 1. The configuration of the dummy columnar electrodes 60c can be the same as that of the sixteenth embodiment. As a result, as in the sixteenth embodiment, the arrangement positions of the metal bumps 100 between the semiconductor device 1 and the wiring substrate 200 are relatively uniform, and stress during the temperature cycle test is alleviated. As a result, reliability is improved. In addition, the dummy columnar electrodes 60c can serve as alignment marks when flip-chip connecting the semiconductor device 1 to the wiring substrate 200.

[0209] The layout and number of dummy columnar electrodes 60c are not limited to these. They can be set so that the positions of metal bumps 100 between semiconductor device 1 and wiring substrate 200 are relatively uniform. Furthermore, the diameters and materials of the multiple dummy columnar electrodes 60c may be the same or different. The remaining configurations of the seventeenth embodiment may be the same as the corresponding configurations of the fourteenth embodiment. The seventeenth embodiment may also be combined with any of the twelfth and thirteenth embodiments.

[0210] (Eighteenth embodiment)

[0211] Figure 45 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the eighteenth embodiment. According to the eighteenth embodiment, a recess 130 is provided on the surface of the third insulating film 90, and a metal bump 100 is provided in the recess 130. By forming the metal bump 100 in the recess 130, even if the metal bump 100 is melted due to reflow soldering, the metal bump 100 can be retained in the recess 130. Therefore, the metal bump 100 can reliably connect the columnar electrode 60 and the wiring substrate 200. The other structures of the eighteenth embodiment may be the same as the corresponding structures of the fourteenth embodiment. In addition, as long as the recess 130 is formed after Figure 31 After the step of polishing, the third insulating film 90 is polished and the third insulating film 90 around the columnar electrode 60 is removed using photolithography, etching, or laser processing. The eighteenth embodiment can be combined with any of the twelfth to seventeenth embodiments.

[0212] (19th embodiment)

[0213] Figure 46 This is a cross-sectional view showing an example configuration of a semiconductor device 1 according to the nineteenth embodiment. According to the nineteenth embodiment, columnar electrodes 60 are provided within the third insulating film 90 at an angle perpendicular to the first surface F10a. As the columnar electrodes 60 approach the surface of the third insulating film 90 from the connection portion to the semiconductor chip 10, they spread outward from the center of the semiconductor device 1, and the spacing between the columnar electrodes 60 also increases. This increases the spacing between the wiring in the wiring substrate 200, increasing the degree of freedom in the wiring design of the wiring substrate 200. The remaining configurations of the nineteenth embodiment may be the same as those of the fourteenth embodiment. The nineteenth embodiment may also be combined with any of the twelfth to eighteenth embodiments.

[0214] (20th embodiment)

[0215] Figure 47This is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to the twentieth embodiment. According to the twentieth embodiment, the columnar electrodes 60 are arranged in a manner inclined perpendicular to the first surface F10a within the third insulating film 90, similar to the nineteenth embodiment. However, in the twentieth embodiment, the columnar electrodes 60 narrow inward from the center of the semiconductor device 1 as they approach the surface of the third insulating film 90 from the connection portion with the semiconductor chip 10, and the spacing between the columnar electrodes 60 also narrows. This shortens the wiring distance between, for example, a controller semiconductor chip 10b and another memory chip 10a, thereby improving the electrical characteristics of the semiconductor device 1. The remaining structures of the twentieth embodiment may be the same as those of the fourteenth embodiment. The twentieth embodiment may also be combined with any of the twelfth to eighteenth embodiments.

[0216] (21st embodiment)

[0217] Figure 48 2 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the 21st embodiment. According to the 21st embodiment, the columnar electrode 60 is different from the 19th embodiment in that it is provided in a manner that is inclined and curved from a direction perpendicular to the first surface F10a within the third insulating film 90. The columnar electrode 60 is preferably curved in a shape that can enhance the columnar electrode 60 so that the columnar electrode 60 is not affected when the third insulating film 90 is introduced. For example, the columnar electrode 60 may be bent in a direction that is perpendicular to the first surface F10a. Figure 31 The columnar electrode 60 is folded back in a direction substantially parallel to the A1 direction to form a Z-shape. This forms a spring-like shape, providing mechanical resistance to the flow of the third insulating film 90. The remaining configuration of the 21st embodiment is the same as the corresponding configuration of the 19th embodiment. The 21st embodiment can also be combined with any of the 12th to 18th embodiments.

[0218] (22nd embodiment)

[0219] Figures 49 to 52 2 is a cross-sectional view showing a configuration example of a semiconductor device 1 according to the twenty-second embodiment. Figure 49 and Figure 50In the 22nd embodiment, the semiconductor device 1 is covered with an underfill 510 and an insulating material 500 on the wiring substrate 200. The underfill 510 is filled between the semiconductor device 1 and the wiring substrate 200, covering and protecting the periphery of the metal bump 100. As a result, the reliability of the connection portion between the semiconductor device 1 and the wiring substrate 200 is improved. The underfill 510 is made of, for example, a resin. The insulating material 500 is provided so as to cover the entirety of the semiconductor device 1 and the underfill 510. The insulating material 500 is made of, for example, a resin, similar to the third insulating film 90. As a result, the reliability of the semiconductor device 1 is further improved. The other configurations of the 22nd embodiment may be the same as the corresponding configurations of the 14th embodiment.

[0220] Alternatively, the insulating material 500 may be formed as Figure 49 As described above, the support substrate 5 is provided to cover the support substrate 5, but it can also be provided as Figure 50 In this way, the upper surface of the supporting substrate 5 is exposed. In this case, the heat dissipation performance of the supporting substrate 5 can be improved.

[0221] The insulating material 500 and the bottom filling glue 510 may also be provided with only one. Figure 51 and Figure 52 In this manner, underfill 510 is omitted, and insulating material 500 covers semiconductor device 1. In this case, insulating material 500 is embedded between semiconductor device 1 and wiring substrate 200 instead of underfill, covering and protecting metal bumps 100. The twenty-second embodiment can also be combined with any of the above embodiments.

[0222] Figures 28 to 52 shows an example of using wires as columnar electrodes 60. Of course, as in products using conventional wire bonding, wires directly connecting between chips and columnar electrodes 60 using wires may be mixed. Furthermore, wires directly connecting between chips, columnar electrodes 60 using wires, and columnar electrodes 60 using plating or the like may also be mixed.

[0223] (23rd embodiment)

[0224] Figure 53 This is a cross-sectional view showing an example configuration of a semiconductor device 1 in a twenty-third embodiment. The twenty-third embodiment differs from the first embodiment in that multiple dummy components 80 are arranged within a single semiconductor chip 10. The remaining configurations of the twenty-third embodiment are the same as those of the first embodiment. The arrangement of multiple dummy components 80 allows them to function more effectively as stoppers and also helps to mitigate warpage of the semiconductor device 1. Consequently, reliability can be improved.

[0225] (Implementation 24)

[0226] Figure 54 This is a cross-sectional view showing an example configuration of a semiconductor device 1 in the 24th embodiment. The 24th embodiment differs from the 6th embodiment in that it further includes a dummy component 80 disposed within the redistribution layer 120. The remaining configurations of the 24th embodiment may be the same as the corresponding configurations of the 6th embodiment. By disposing a dummy component 80 within the redistribution layer 120 in addition to the dummy component 80, the warpage of the semiconductor device 1 can be adjusted. As a result, reliability can be improved. Alternatively, multiple dummy components 80 may be disposed between multiple wiring layers within the redistribution layer 120. This further enables the warpage of the semiconductor device 1 to be adjusted.

[0227] (Implementation 25)

[0228] Figure 55 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 in the 25th embodiment. The 25th embodiment differs from the 11th embodiment in that a redistribution layer 120 is provided on the columnar electrode 60 of the semiconductor device 1. The redistribution layer 120 is formed on the third insulating film 90 and the columnar electrode 60 after the third insulating film 90 is polished. The metal bumps 100 are formed on the redistribution layer 120. By providing the redistribution layer 120, the spacing between the metal bumps 100 can be increased even when the spacing between the columnar electrodes 60 is narrow. Furthermore, the redistribution layer 120 can electrically connect the semiconductor chips 10 via the wiring within the redistribution layer 120. Dummy components 80 can also be formed within the redistribution layer 120. In addition, a plurality of redistribution layers 120 can be provided, and dummy components 80 can be formed within the plurality of redistribution layers 120.

[0229] (Implementation 26)

[0230] Figure 56It is a cross-sectional view showing an example of the structure of the semiconductor device 1 in the 26th embodiment. This embodiment is an example of applying the semiconductor device 1 to the so-called fan-out chip-level CSP (Chip Size Package). The process of the fan-out chip-level CSP is roughly divided into RDL Last and RDL First. RDL Last is a method of forming the redistribution layer 120 after the semiconductor chip is covered with the fourth insulating film (insulating material) 150, and RDL First is a method of forming the redistribution layer 120 before the semiconductor chip is covered with the fourth insulating film 150. The fourth insulating film 150 uses epoxy-based, phenol-based, polyimide-based, polyamide-based, acrylic-based, PBO-based, silicone-based, benzocyclobutene-based resins, mixed materials of these resins, and composite materials. Examples of epoxy resins are not particularly limited. Examples include bisphenol-type epoxy resins such as bisphenol A, bisphenol F, bisphenol AD, and bisphenol S; novolac-type epoxy resins such as phenolic novolacs and cresol novolacs; resorcinol-type epoxy resins; aromatic epoxy resins such as trisphenol triglycidyl ether; naphthalene-type epoxy resins, fluorene-type epoxy resins, dicyclopentadiene-type epoxy resins, polyether-modified epoxy resins, benzophenone-type epoxy resins, aniline-type epoxy resins, NBR-modified epoxy resins, CTBN-modified epoxy resins, and hydrides of these resins. Of these, naphthalene-type epoxy resins and dicyclopentadiene-type epoxy resins are preferred due to their good adhesion to Si. Furthermore, benzophenone-type epoxy resins are preferred due to their ease of rapid curing. These epoxy resins may be used alone or in combination of two or more. Alternatively, the third insulating film 90 may contain a filler such as silicon dioxide.

[0231] Figure 56This figure shows an example of forming dummy components 80 on the redistribution layer 120 in RDL Last. In the RDL Last method, a peeling layer is formed on a supporting substrate, and then a semiconductor chip 10 is mounted and covered with a fourth insulating film 150. The supporting substrate is then peeled off, and the redistribution layer 120 is formed on the component surface of the semiconductor chip 10. After the columnar electrodes 60 are formed, the third insulating film 90 is formed and planarized using mechanical polishing, CMP, or the like. In this case, the third insulating film 90 is polished until the columnar electrodes 60 are exposed, and at this time, the dummy components 80 function as a stopper layer. The fourth insulating film 150 exists around the semiconductor chip 10, and the redistribution layer 120 is formed on the component surface of the semiconductor chip 10. The redistribution layer 120 is provided on the first surface F10a of the semiconductor chip 10 and on the fourth insulating film 150, which is flush with the first surface F10a. Dummy components 80 are formed within the redistribution layer 120, and metal bumps 100 are formed on the redistribution layer 120. The metal bumps 100 are electrically connected to the wiring substrate 200. Providing dummy components 80 within the redistribution layer 120, which includes the third insulating film of the fan-out wafer-level CSP, allows for correction of warpage of the semiconductor device 1, thereby improving reliability.

[0232] (Implementation 27)

[0233] Figure 57 27 is a cross-sectional view showing a configuration example of the semiconductor device 1 in the twenty-seventh embodiment. Figure 56 In this embodiment, multiple dummy components 80 are provided within the third insulating film 90. The remaining configuration of the twenty-seventh embodiment can be the same as the corresponding configuration of the twenty-sixth embodiment. By adding the dummy components 80, the warpage of the semiconductor device 1 can be adjusted, thereby improving reliability. Alternatively, dummy components 80 may be formed within multiple redistribution layers 120. The twenty-seventh embodiment can also be combined with other embodiments.

[0234] (Implementation 28)

[0235] Figure 58 28. This is a cross-sectional view showing a configuration example of a semiconductor device 1 in accordance with the twenty-eighth embodiment. This embodiment is an example in which the semiconductor device 1 is applied to a so-called fan-out wafer-level CSP. Figure 56The following shows an example of forming a dummy component 80 on the third insulating film 90 in RDL First. In the RDL First method, a peeling layer is formed on a supporting substrate to form a columnar electrode 60. After the dummy component 80 is mounted on the peeling layer, the third insulating film 90 is formed to cover the columnar electrode 60 and the dummy component 80, and is flattened using mechanical polishing, CMP, or the like. In this case, the third insulating layer 90 is polished until the columnar electrode 60 is exposed, and at this time, the dummy component 80 functions as a stopper layer. A redistribution layer 120 is further provided on the dummy component 80, and a fourth insulating film 150 is provided around the semiconductor chip 10. The semiconductor chip 10 has a metal bump 100A and is flip-chip mounted on the redistribution layer 120. The dummy component 80 is formed on the third insulating film 90, and a metal bump 100B is formed. The metal bump 100B is electrically connected to the wiring substrate 200. By providing dummy components 80 within the redistribution layer 120, which includes the third insulating film 90 of a fan-out wafer-level CSP, warpage of the semiconductor device 1 can be corrected, thereby improving reliability. Furthermore, after the redistribution layer is peeled from the supporting substrate, the third insulating film 90 is polished to expose the columnar electrodes 60. Since the dummy components 80 are polished from both above and below, they act as a stopper for polishing from both directions.

[0236] (Implementation 29)

[0237] Figure 59 This is a cross-sectional view showing an example configuration of a semiconductor device 1 in the 29th embodiment. The 29th embodiment differs from the 28th embodiment in that an underfill 510 is provided between the semiconductor chip 10 and the redistribution layer 120. The underfill 510 covers and protects the periphery of the metal bumps 100A between the semiconductor chip 10 and the redistribution layer 120. This improves the reliability of the connection between the semiconductor chip 10 and the redistribution layer 120.

[0238] (Implementation 30)

[0239] Figure 60A 、 Figure 60B 、 Figure 60D It is a diagram showing an example of the configuration of a polishing device in the 30th embodiment.

[0240] Figure 60A The polishing apparatus shown includes a turntable 300 , a polishing pad 310 , a rotating shaft 320 , a motor 330 , a current sensor 340 , a signal converter 350 , and a computing unit 360 .

[0241] The turntable 300 is rotatably provided, and a polishing pad 310 is mounted on the surface.

[0242] The polishing pad 310 is placed on the turntable 300 to polish the semiconductor substrate W.

[0243] The rotating shaft 320 is fixed to the turntable 300 and transmits power from the motor 330 to the turntable 300 to rotate the turntable 300 .

[0244] The motor 330 receives power from a power source (not shown) and rotates the rotating shaft 320 as indicated by arrow A.

[0245] The current sensor 340 measures the current consumed by the motor 330 .

[0246] The signal converter 350 converts the current consumption value of the motor 330 measured by the current sensor 340 and transmits the converted value to the calculation unit 360 .

[0247] The computing unit 360, for example, is a personal computer (PC), and detects the endpoint of the polishing process of the semiconductor substrate W based on the current consumption of the motor 330. More specifically, the current consumption of the motor 330 varies depending on the friction between the semiconductor substrate W and the polishing pad 310. The friction between the semiconductor substrate W and the polishing pad 310 varies depending on changes in the contact area before and after planarization of the semiconductor substrate W or changes in the type of film being polished. This friction change can be detected using the power consumption of the motor 330. This polishing endpoint detection method is also known as a TCM (Torque Current Monitor).

[0248] Figure 60B The grinding device shown is Figure 60A The difference in form is that an eddy current sensor 370 is further provided. Figure 60B Other components of the grinding device can be Figure 60A The corresponding structure of the grinding device is the same. In addition, it can also be omitted Figure 60A The current monitor 340 is provided.

[0249] like Figure 60C As shown, the eddy current sensor 370 is composed of a coil and detects an induced current (eddy current) generated in the semiconductor substrate W. The calculation unit 360 calculates the end point of the polishing process based on changes in impedance frequency or voltage caused by the eddy current. Figure 60C This is a conceptual diagram showing a schematic configuration of the eddy current sensor 370 .

[0250] This grinding endpoint detection method is also called ECM (Eddy Current Monitor).

[0251] Figure 60D The grinding device shown is Figure 60AThe difference in form is that a reflected light sensor 370 is further provided. Figure 60D Other components of the grinding device can be Figure 60A The corresponding structure of the grinding device is the same. In addition, it can also be omitted Figure 60A The current monitor 340 is provided.

[0252] like Figure 60D As shown, the reflected light sensor 380 irradiates light onto the semiconductor substrate W, detects the reflected light from the semiconductor substrate W, and calculates the reflectivity. The calculation unit 360 detects the end point of the polishing process based on the change in the reflectivity.

[0253] This polishing endpoint detection method is also called OTM (Optical Thickness Monitor).

[0254] Figure 60A The endpoint detection method based on the change in polishing resistance described in corresponds to the CMP detection method used in the above-described embodiment.

[0255] In use Figure 60D In the case of the optical endpoint detection method based on a change in reflectivity as described in , the reflectivity or transmittance of the dummy components 80 and 81 only needs to be different from that of the third insulating film 90. Generally speaking, since the third insulating film 90 is often dark in color, the reflectivity of the dummy components 80 and 81 may also be higher relative to the measurement wavelength.

[0256] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.

Claims

1. A semiconductor device comprising: A semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a semiconductor element is provided on the first surface side; a columnar electrode provided above the first surface when the direction from the second surface toward the first surface is defined as an upward direction, and electrically connected to any one of the semiconductor elements; a first component disposed above the first surface and around the columnar electrode; as well as a first insulating material provided around the columnar electrode and the first component; The first member is harder than the columnar electrode and the insulating material. The first member and the columnar electrode are exposed from the upper surface of the insulating material.

2. The semiconductor device according to claim 1 , wherein the first member comprises a third surface exposed from the first insulating material, a fourth surface facing the first surface of the semiconductor chip, and a side surface between the third surface and the fourth surface. The side surface is inclined from a direction perpendicular to the first surface or has a step. 3 . The semiconductor device according to claim 1 , wherein the first member is a laminated body formed by laminating a plurality of second members having different areas when viewed from the first surface. 4 . The semiconductor device according to claim 1 , wherein the first member is made of any one of silicon, glass, alumina, SiC, AlN, ceramics, and metal. 5 . The semiconductor device according to claim 1 , further comprising a metal bump provided on the columnar electrode. 6 . The semiconductor device according to claim 1 , further comprising a first wiring layer provided on the columnar electrode.

7. The semiconductor device according to claim 1, further comprising a metal film provided between the electrode pad of the semiconductor chip and the columnar electrode. An area of ​​the columnar electrode exposed from the insulating material is larger than a contact area of ​​the columnar electrode with respect to the electrode pad of the semiconductor chip. 8 . The semiconductor device according to claim 1 , wherein an area of ​​the pillar-shaped electrode exposed from the first insulating material is smaller than a contact area of ​​the pillar-shaped electrode with respect to the semiconductor chip.

9. The semiconductor device according to claim 1, wherein the columnar electrode comprises: a first columnar electrode, an area exposed from the first insulating material being larger than a contact area of ​​the columnar electrode with respect to the semiconductor chip; and a second columnar electrode, an area exposed from the insulating material being smaller than a contact area of ​​the columnar electrode with respect to the semiconductor chip. 10 . The semiconductor device according to claim 5 , wherein the first member is a conductor and is electrically connected to any one of the semiconductor elements.

11. The semiconductor device according to claim 1 , wherein the insulating material fills the stacked plurality of semiconductor chips. The first component is arranged on any one of the semiconductor chips.

12. The semiconductor device according to claim 11, wherein the plurality of semiconductor chips are a plurality of memory chips and controller chips of the memory chips, The first component and the controller chip are provided on a laminate of the plurality of memory chips.

13. The semiconductor device according to claim 1, wherein the columnar electrode uses at least one of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, and Al monomers, or a composite film of two or more of them, or any one of alloys of two or more of them. 14 . The semiconductor device according to claim 1 , further comprising a support portion provided on the second surface of the semiconductor element.

15. The semiconductor device according to claim 1, further comprising a first wiring layer provided on the first surface of the semiconductor chip, The columnar electrodes and the first member are provided on the upper side of the wiring layer.

16. The semiconductor device according to claim 1, further comprising: a second insulating material covering the semiconductor chip; and a first wiring layer provided on the first surface of the semiconductor chip and on the surface of the second insulating material which is coplanar with the first surface; The columnar electrodes and the first member are provided in the wiring layer.

17. A method for manufacturing a semiconductor device, comprising: A columnar electrode is formed above a first surface of a semiconductor chip, wherein the semiconductor chip has a first surface and a second surface opposite to the first surface, and has a semiconductor element on the first surface; A first member having an upper surface lower than that of the columnar electrode is provided above the first surface of the semiconductor chip; forming a first insulating material on the first surface so as to fill the columnar electrode and the first member; and The first insulating material and the columnar electrodes are polished until the first member, which is harder than the columnar electrodes and the first insulating material, is exposed.

18. The method according to claim 17, wherein the first component comprises a third surface exposed from the first insulating material, a fourth surface corresponding to the first surface of the semiconductor chip, and a side surface between the third surface and the fourth surface. The side surface is inclined from a direction perpendicular to the first surface, or has a step difference, The polishing of the first insulating material and the columnar electrodes is stopped based on the change in the polishing area of ​​the first member.

19. The method according to claim 17, wherein the first member is formed by laminating a plurality of second members having different surface areas.

20. The method according to claim 17, further comprising forming metal bumps on the pillar-shaped electrodes.

21. The method according to claim 17, further comprising forming a first wiring layer on the columnar electrode.

22. The method according to claim 17, wherein a metal film is formed on an electrode pad of the semiconductor chip, The columnar electrodes are formed on the metal film by plating.

23. The method according to claim 17, wherein the columnar electrodes are formed by bonding metal wires to electrode pads of the semiconductor chip and extending the metal wires in a direction substantially perpendicular to the first surface.

24. The method according to claim 17, further comprising stacking a plurality of the semiconductor chips. The columnar electrodes are formed on the first surface of each of the plurality of semiconductor chips. The first component is arranged on any one of the plurality of semiconductor chips. The first insulating material fills the laminate of the semiconductor chip, the columnar electrodes, and the first member.

25. The method according to claim 17, further comprising stacking a plurality of the semiconductor chips. The plurality of semiconductor chips are a plurality of memory chips and controller chips of the memory chips, The first component and the controller chip are provided on a laminate of the plurality of memory chips.

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