Bipolar semiconductor controllable rectifier

Abstract

Embodiments of the present application relate to bipolar semiconductor controllable rectifiers. In the described example, a high voltage bipolar semiconductor controllable rectifier SCR (100) includes an emitter region (102) having a first polarity overlying a base region (104) having a second polarity different from the first polarity, a collector region (106, 108) having the first polarity underlying the base region (104), an anode region (114, 116, 120) having the second polarity, a first sinker region (118) having the first polarity and contacting the collector region (106, 108), wherein the anode region (114, 116, 120) is between the first sinker region (118) and the base region (104), and a second sinker region (112) having the first polarity and contacting the collector region (106, 108, 110), the second sinker region (112) being between the anode region (114, 116, 120) and the base region (104), wherein an extension (120) of the anode region (114, 116, 120) extends under a portion of the second sinker region (112).

Description

[0001] Related information of divisional application

[0002] This application is a divisional application of the patent application entitled "Bipolar Semiconductor Controllable Rectifier", application number 201780028526.2, filed on April 3, 2017. TECHNICAL FIELD

[0003] This relates generally to integrated circuit design, and more specifically to implementing a bipolar-based semiconductor controllable rectifier for electrostatic discharge protection circuitry. BACKGROUND

[0004] Integrated circuits are susceptible to damage from electrostatic discharge from common environmental sources, and can be destroyed when subjected to voltages higher than their intended voltage supply. Electrostatic discharge (ESD) protection circuitry is used to harmlessly discharge current from ESD events, and silicon controlled rectifiers (SCRs) provide an effective solution in small area. However, there are still problems with the design of SCRs for high voltage pins. There is a lack of solution for low leakage, low capacitance bipolar-based SCRs for high voltage pins. Non-SCR based solutions are inefficient, and existing SCR designs suffer from high leakage due to punchthrough problems. SUMMARY

[0005] In described examples of a high voltage bipolar semiconductor controllable rectifier (SCR), the SCR includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity, a collector region having the first polarity and underlying the base region, an anode region having the second polarity, a first sinker region having the first polarity and contacting the collector region, with the anode region between the first sinker region and the base region, and a second sinker region having the first polarity and contacting the collector region, the second sinker region being between the anode region and the base region, with an extension of the anode region extending under a portion of the second sinker region. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A cross-sectional view of an SCR according to an embodiment is depicted.

[0007] Figure 2 A current-voltage plot of an SCR of Figure 1 is depicted.

[0008] Figure 3 A cross-sectional view of an SCR according to an embodiment is depicted.

[0009] Figure 4 A cross-sectional view of an SCR according to an embodiment is depicted.

[0010] Figure 5 A cross-sectional view of an SCR according to an embodiment is depicted.Figure 1 a plan view of the SCR of

[0011] Figure 6 depicts a plan view of the SCR of Figure 1 a plan view of the SCR of

[0012] Figure 7 depicts a plan view of the SCR of Figure 1 a plan view of the SCR of

[0013] Figure 8 depicts a plan view of the SCR of Figure 1 a plan view of the SCR of

[0014] FIG. 9 depicts an example embodiment of a conventional bipolar SCR. DETAILED DESCRIPTION

[0015] In the drawings, like reference numerals indicate like elements. References in this description to "an" or "one" embodiment of the present disclosure do not necessarily refer to the same embodiment, and such references can mean at least one. In addition, if a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the purview of those skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicit

[0016] The described examples include SCRs that contain barrier junctions to prevent shoot through. The barrier junctions are constructed by modifying the collector sinker region and introducing an anode junction under the modified sinker to enable SCR action. The modified sinker can be used to change the trigger / sustain current of the SCR and the construction allows independent modification of the trigger current while maintaining PNP injection from the substrate to noise immunity.

[0017] Figure 9 shows a cross-sectional view of a conventional SCR 900. SCR 900 is built on a bipolar transistor, i.e., an NPN transistor, formed from an n-type region N emitter 902 formed over a p-type region P base 904 and a bottom layer n-type collector formed from region 906, n-type buried layer extension (NBLX) 908, and n-type buried layer (NBL) 910. The collector is contacted by an n-type sinker 918 formed from three different implants, referred to herein as n-type source / drain (NSD), n-type deep well (DEEPN), and NBLX. The cross-hatched regions represent shallow trench isolation 920 or other dielectric layers. Since this example is an NPN transistor, a heavily doped p-type layer (p-type source / drain (PSD) 914) is inserted into the NPN transistor to create a PNPN structure that acts as an SCR. SCR 900 functions properly at voltages in the range of 3 to 5 volts, but multiple problems arise when higher voltages are used. One problem is punchthrough; for example, whenever a reverse bias is applied from P base 904 to region 906, the field can all divert to the anode, PSD 914, as shown by the arrows in Figure 9. This condition shorts one of the internal bipolar transistors, creating a leaky SCR at extremely low voltages, such that SCR 900 cannot hold a high voltage at low current. Other problems can also arise, such as a parasitic MOS transistor or charge on the shallow trench isolation can but essentially at extremely low voltages cause a short, anode PSD 914 of SCR 900 to soft short to the portion P base 904 that is the cathode, causing a large amount of leakage.

[0018] One way to avoid the leakage shown in Figure 9 is to place PSD 914 on the outside of N sinker region 918. However, in this configuration, the gain on the PNP portion of the SCR becomes extremely low, not allowing proper SCR action.

[0019] Figure 1 A cross-sectional view of a first embodiment of a semiconductor controlled rectifier (SCR) 100 that has increased immunity to the shorting effects described above is shown. Here and in the following description, SCR refers to a semiconductor controlled rectifier and not a silicon controlled rectifier, which is a special case of a semiconductor controlled rectifier. In general, reference to a semiconductor region as "heavily doped" means having a concentration of 10 18 / cm 3 or more. Likewise, "lightly doped" means a semiconductor region having a concentration of less than 10 18 / cm 3 . In both cases, the doped region can be formed by ion implantation or other known methods. Furthermore, the drawings are not drawn to scale. In the following description, the term "electrically connected" means that there is a resistive current path between two or more listed elements and does not exclude the presence of resistors, parasitic elements, or other circuit elements within the current path.

[0020] The SCR 100 includes a p-type substrate (not specifically shown) and an n-type collector region, which includes a heavily doped n-type buried layer (NBL) 110, a lightly doped n-type epitaxial layer (NEPI) 108, and a lightly doped region 106. The n-type buried layer (NBL) 110 is again contacted by an n-type deposit 118, which receives highly doped implants NSD, DEEPN, and NBLX. The heavily doped p-type region P-base 104 is overlaid on the N-type region 106, and the heavily doped n-type region N-emitter 102 is overlaid on the P-base 104.

[0021] The heavily doped p-type region PSD 114 is now isolated from the n-type region 106 by an auxiliary heavily doped n-type deposit 112 placed between PSD 114 and the P-base 104 and receiving the implants NSD and DEEPN (but no NBLX implant). Deposit 112 acts as a barrier junction against leakage in the SCR of FIG9. The heavily doped p-type region PSD 114 thus blocks leakage through deposit 112. To enable SCR operation, two heavily doped p-type regions, namely, the p-type deep well (DEEPP) 116 and the p-type buried layer extension (PBLX) 120, provide an anodic junction that extends below deposit 112 to contact the epitaxial layer NEPI 108. The presence of the modified deposit 112 and the anodic junction PBLX 120 repositions the current for deeper SCR events in the device. Leakage between the P-base 104 and PBLX 120 may occur in the current configuration, but such leakage will occur at voltages higher than the inherent transistor's rated voltage, so it is not a major issue. The sink region 118 serves two purposes: it allows the SCR to be isolated from the substrate without requiring deep trench isolation; and by having different resistors in series with sinks 118 and 112, the SCR's trigger voltage decouples from the SCR's tendency to inject current into the substrate.

[0022] In the example implementation, Figure 1 Common doping for each implant or layer in the process can be as follows: N emitter at 5x10 19 / cm 3 With 10 20 / cm 3 Doping between; P-base at 5x10 17 / cm 3 With 10 19 / cm 3 Doping between; NEPI at 5x10 15 / cm 3 With 10 17 / cm 3 Inter-doping; NBL with approximately 10 19 / cm 3 Doping; NSD with approximately 1020 / cm 3 Doping; DEEPN at 5x10 18 / cm 3 With 10 19 / cm 3 Inter-doping; NBLX with approximately 10 18 / cm 3 Or even higher doping; PSD with approximately 10 20 / cm 3 Doping; DEEPP at 10 18 / cm 3 With 10 19 / cm 3 Doping between; PBLX at 10 18 / cm 3 With 10 19 / cm 3 Doping between; and region 106 with approximately 10 15 / cm 3 Doping. However, DEEPN implants used in deposition 112 do not require as heavy doping as mentioned to function as barrier junctions; in the range of 10 16 / cm 3 With 10 18 / cm 3 Implants within this range will also be effective.

[0023] SCR is usually like Figure 1 The connection shown includes a metallization layer forming a connection line 122 that connects a sink 118 (which forms the base of the intrinsic PNP transistor) to a PSD 114 (which forms the anode of the SCR). Sink 118 and PSD 114 can be directly connected as illustrated, or connected via a resistor (not specifically shown). The presence or absence of a resistor determines the degree to which the intrinsic PNP transistor is turned on. The connection line 124 to sink 112 is generally kept floating so that any current originates from the p-type region. When the SCR 100 is turned on, i.e., during an ESD event, current flows from the PSD region 114 through the NEPI 108 and the N-type region 106 to the P-base 104 and then to the N-emitter 102. The described SCR offers one or more of the following benefits: isolated SCR; design that allows for independent control of the trigger current and the amount of PNP injection from the substrate (as described below); SCR fabrication without the need for any additional masks; avoidance of leakage issues; and bipolarity based on which the SCR is built, thus allowing for the same breakdown voltage.

[0024] Figure 2 Depicting Figure 1The current-voltage graph 200 of the SCR of FIG. 2, the horizontal axis shows voltage and the vertical axis identifies current across the SCR. A 100 nanosecond transmission line pulse (TLP) is provided to the SCR 100 and the I-V characteristics are measured. As shown, the voltage rises to approximately 6 to 7 volts with little current, then quickly recovers when the SCR is triggered. At this point, the SCR starts to act and takes a large amount of current from the protected circuit.

[0025] Figure 1 The SCR of FIG. 2 can also be implemented in a reverse dopant type, i.e., with the n-type dopants interchanged with the p-type dopants and vice versa, as shown in FIG. 3. Figure 3 The SCR 300 includes an n-type substrate (not specifically shown) and a p-type collector region including a heavily doped buried layer PBL 310, a lightly doped epitaxial layer PEPI 308, and a lightly doped region 306. The buried layer PBL 310 is contacted by a p-type sinker 318 that accepts high-doped implants PSD, DEEPp, and PBLX. A heavily doped n-type region Nbase 304 overlies the p-type region 306 and a heavily doped p-type region Pemitter 302 overlies the Nbase 304.

[0026] The heavily doped n-type region NSD 314 is now isolated from the p-type region 306 by an auxiliary heavily doped p-type sinker 312 placed between the NSD 314 and the Nbase 304 and accepting the implants PSD and DEEPp (but no PBLX implant). The sinker 312 acts as a barrier junction against leakage in the SCR of FIG. 9. The heavily doped n-type region NSD 314 is thus blocked from leakage by the sinker 312. To enable SCR action, a heavily doped n-type region DEEPN 316 and NBLX 320 are provided under the sinker 312 extending partially to contact the epitaxial layer PEPI 308 at an anode junction. The presence of the modified sinker 312 and the anode junction NBLX 320 repositions the current for a deeper SCR event in the device. As described above, leakage between the Nbase 304 and the NBLX 320 can occur in the present configuration, but such leakage would occur at a higher voltage than the rated voltage of the native transistor.

[0027] The connection line variations in the described embodiments are shown as Figure 4 in the SCR 400 of FIG. 4. Figure 1 In FIG. 4, the connection line 124 remains floating. However, in this embodiment, the connection line 424 is switchably connected to the connection line 422, e.g., by a MOSFET (not specifically shown). As shown in FIG. 5, the connection line 424 is connected to the connection line 422 when the MOSFET is on. Figure 2As shown, the embodiment of SCR 100 has a trigger voltage of approximately 6 to 7 volts. However, if this SCR is used in a system with a normal operating voltage of, for example, 15 volts, the SCR will trigger at an undesirably low voltage. The described switch between terminals 422 and 424 provides a way to modify the holding or trigger current, thereby allowing SCR 400 to be used in higher voltage conditions. In normal operation, an additional carrier is injected through NEPI 108 while the carrier reaching the P base 104 is injected through the anode PSD 414 and the extensions DEEPP 116 and PBLX 120. However, if the switch between terminals 422 and 424 is closed, some of the carrier is “stolen” by the sink 112 and does not contribute to SCR operation. Therefore, for example, when the switch is closed, Figure 2 The trigger voltage shown can be closer to 30 volts. The switch is designed to close during normal circuit operation but open during an ESD event. Although Figure 4 The doping is shown as corresponding to Figure 1 The doping, but the switchable connection between terminals 422 and 424 can also be used with Figure 3 The doping profile or any of the embodiments described herein may be used together.

[0028] Figures 5 to 8 public Figure 1 The plan views of the embodiments show different layouts in which this device can be implemented. These plan views are equally applicable. Figure 3 In some embodiments, the polarity of the dopant is reversed, and there are switchable connection lines that may or may not be included to assist sedimentation. Figure 5 The basic implementation plan is made public, while Figures 6 to 8 Each of these provides an improved way of penetrating the edges of deep trench isolation.

[0029] As shown in the SCR 500, the N-emitter 102 and P-base 104 are shown as laterally extending in this figure, while the P-base 104 extends beyond the N-emitter 102 in all four directions. Depositions 112, PSD 114, and 118 are laterally isolated from the P-base 104 and from each other by shallow trenches 530 that laterally surround the entire SCR. The PBLX 120, providing a new anode junction, is shown as a dashed line. Furthermore, [the remaining text is incomplete and likely refers to a different part of the diagram]. Figure 1 The deep trench isolation 532 shown in the image isolates the SCR 500 from the rest of the chip.

[0030] Figure 6 The SCR 600 is disclosed, wherein a settling 112 extends at each end such that the settling 112 contacts a deep trench isolation 532 to provide improved pass-through to near the deep trench isolation. The other components of the SCR remain unchanged. Figure 7An SCR 700 is disclosed in which two sections of the sinker 112 are joined at each end to form a ring 734. The ring 734 laterally encircles the P-base 104. Figure 8 Another modification is shown in which Figure 8 An SCR 800 is disclosed in which each of the sinker 112, PSD 114 and sinker 118 laterally extend at their ends to form respective rings 834, 836 and 838. In this configuration, no deep trench is required to isolate the SCR from the substrate.

[0031] Other modifications to the circuit are also possible. Although a single emitter "finger" 102 is shown overlying the P-base 104, multiple emitter fingers 102 can be placed within the P-base 104; the same applies when the dopant types are reversed, as in Figure 3 In one embodiment, the entire SCR structure can be repeated multiple times within a deep trench isolation.

[0032] Reference to an item in the singular is not intended to mean "one and only one" unless explicitly so stated. The term "or" is meant to mean either, both, or any combination thereof, unless otherwise indicated by context.

[0033] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A bipolar semiconductor controllable rectifier comprising: an emitter region having a first conductivity type and overlying a base region having a second conductivity type different from the first conductivity type; a collector region having the first conductivity type and underlying the base region; an anode region having the second conductivity type; a first sinker region having the first conductivity type and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first conductivity type and contacting the collector region, the second sinker region being between the anode region and the base region, wherein a depth of the anode region is greater than a depth of the second sinker region, and the anode region contacts a bottom of the second sinker region and contacts the collector region vertically below the bottom of the second sinker region.

2. The bipolar semiconductor controllable rectifier of claim 1, further comprising a first metallization connecting the anode region and the first sinker region.

3. The bipolar semiconductor controllable rectifier of claim 2, further comprising a second metallization contacting the second sinker region.

4. The bipolar semiconductor controllable rectifier of claim 3, wherein the second metallization is switchably connected to the first metallization.

5. The bipolar semiconductor controllable rectifier of claim 1, further comprising a shallow trench isolation between the anode region and each of the first sinker region and the second sinker region.

6. The bipolar semiconductor controllable rectifier of claim 5, further comprising a deep trench isolation surrounding the bipolar semiconductor controllable rectifier.

7. The bipolar semiconductor controllable rectifier of claim 6, wherein the shallow trench isolation separates the bipolar semiconductor controllable rectifier from the deep trench isolation.

8. The bipolar semiconductor controllable rectifier of claim 7, wherein the shallow trench isolation separates the first sinker region, the anode region, and the base region from the deep trench isolation, and the second sinker region contacts the deep trench isolation.

9. The bipolar semiconductor controllable rectifier of claim 6, wherein the shallow trench isolation separates the first sinker region and the anode region from the deep trench isolation, and the second sinker region laterally extends to surround a region containing the emitter region and the base region.

10. The bipolar semiconductor controllable rectifier of claim 5, wherein the second sinker region laterally extends to surround a region containing the emitter region and the base region, the anode region laterally extends to surround the second sinker region, and the first sinker region laterally extends to surround the anode region.

11. The bipolar semiconductor controllable rectifier of claim 6, wherein the bipolar semiconductor controllable rectifier is repeated multiple times within the deep trench isolation. ​ 12. The bipolar semiconductor controllable rectifier of claim 1, wherein an extension of the anode region extends under a first portion of the second sinker region until the extension of the anode region contacts a portion of the collector region under a second portion of the second sinker region.

13. The bipolar semiconductor controllable rectifier of claim 1, wherein the bipolar semiconductor controllable rectifier is a silicon controlled rectifier.

14. A bipolar semiconductor controllable rectifier comprising: an emitter region having a first conductivity type and overlying a base region having a second conductivity type different from the first conductivity type; a first region having the first conductivity type and underlying the base region; a first layer having the first conductivity type and underlying the first region; a buried layer having the first conductivity type and underlying the first layer; an anode region having the second conductivity type and including a doped region of the second conductivity type, a well region of the second conductivity type, and a first buried layer extension of the second conductivity type, the first buried layer extension contacting the first layer; a first sinker having the first conductivity type and including a first sinker region, a first well region, and a second buried layer extension, wherein the anode region is between the first sinker region and the base region; and a second sinker having the first conductivity type and including a second sinker region and a second well region, wherein a depth of the anode region is greater than a depth of the second sinker, and the anode region contacts a bottom of the second sinker and contacts the first layer at a location vertically below the bottom of the second sinker. ​ 15. The bipolar semiconductor controllable rectifier of claim 14, wherein the first sinker region and the second sinker region each have a doping concentration of about 10 20 / cm 3 .

16. The bipolar semiconductor controllable rectifier of claim 14, wherein the first well region has a doping concentration between 5 x 10 18 / cm 3 and 10 19 / cm 3 and the second well region has a doping concentration between 10 18 / cm 3 and 10 19 / cm 3 .

17. The bipolar semiconductor controllable rectifier of claim 14, wherein the second buried layer extension region has a doping concentration of 10 18 / cm 3 or more and the first buried layer extension region has a doping concentration between 10 18 / cm 3 and 10 19 / cm 3 .

18. The bipolar semiconductor controllable rectifier of claim 14, wherein the buried layer has a doping concentration of about 10 19 / cm 3 , the first layer has a doping concentration between 5 x 10 15 / cm 3 and 10 17 / cm 3 , and the first region has a doping concentration of 10 15 / cm 3 .

19. The bipolar semiconductor controllable rectifier of claim 14, wherein the emitter region has a doping concentration between 5 x 10 19 / cm 3 and 10 20 / cm 3 and the base region has a doping concentration between 5 x 10 17 / cm 3 and 10 19 / cm 3 .

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