Three-dimensional memory manufacturing methods and three-dimensional memory

Abstract

The application provides a three-dimensional memory manufacturing method and a three-dimensional memory, which comprises the following steps: providing a substrate and forming a sacrificial layer, a first material layer and an etching stop layer on the substrate; forming a stack structure on the etching stop layer, and the materials of the first material layer, the second material layer and the etching stop layer are different; forming a second structure hole penetrating through the stack structure, and the second structure hole extends to the etching stop layer; removing the part of the etching stop layer at the bottom of the second structure hole; forming a channel hole including the second structure hole and extending to the substrate; and forming a channel structure in the channel hole. By arranging the etching stop layer in the stack structure of the three-dimensional memory, the etching stop layer can be used as the stop layer for etching the second structure hole, and due to the position of the etching stop layer in the stack structure, the bottom of the channel hole can be located in the substrate, and the substrate is not broken.

Description

[0001] This application is a divisional application of application No. 202010161888.2, with the title of "Three-dimensional memory manufacturing method and three-dimensional memory", and filed on March 10, 2020. TECHNICAL FIELD

[0002] The present application relates to three-dimensional memory technology, and in particular to a three-dimensional memory manufacturing method and a three-dimensional memory. BACKGROUND

[0003] With the rapid development of big data, cloud computing, the Internet of Things and other technologies, the requirements for the integration and storage density of the memory are also increasing, and the traditional two-dimensional planar memory has been gradually replaced by three-dimensional memory.

[0004] In the related art, the three-dimensional memory includes a substrate and a stack structure stacked on the substrate, the stack structure is provided with a channel hole penetrating the substrate and a gate slit, the channel hole is provided with a channel structure, and the gate slit is provided with a common source contact; and the channel layer of the channel structure can be exposed from the side wall of the channel hole and connected with the substrate.

[0005] However, due to the large number of layers of the stack structure, the channel hole etching is difficult, and the etching depth is difficult to control. SUMMARY

[0006] The present application provides a three-dimensional memory manufacturing method and a three-dimensional memory to overcome the problem of difficult control of the etching depth of the channel hole in the related art.

[0007] The present application provides a three-dimensional memory manufacturing method and a three-dimensional memory to overcome the problem of difficult control of the etching depth of the channel hole in the related art.

[0008] In some optional embodiments, the channel structure has a protrusion matched with the recess.

[0009] In some optional embodiments, the recess includes a first recess; and the first recess is located on the conductive layer closest to the semiconductor layer.

[0010] In some optional embodiments, the stack structure further includes a common source contact; and the common source contact penetrates the stack structure and extends into the semiconductor layer.

[0011] In some optional embodiments, the channel structure comprises functional layers and channel layers stacked on each other; and the semiconductor layer is electrically connected with the channel layers.

[0012] In some optional embodiments, the functional layers are provided with openings, and part of the channel layers are exposed at the openings; and the semiconductor layer extends to the openings and is electrically connected with the channel layers.

[0013] In some optional embodiments, the functional layers comprise barrier layers, storage layers and tunnel insulating layers stacked on each other, and the storage layers are located between the barrier layers and the tunnel insulating layers.

[0014] The present application provides a three-dimensional memory manufacturing method, comprising the following steps:

[0015] A substrate is provided, and a sacrificial layer is formed on the substrate;

[0016] At least a first material layer and an etching stop layer arranged in pairs are formed on the sacrificial layer;

[0017] First material layers and second material layers are alternately formed on the etching stop layer to form a stack structure, and the materials of the first material layers, the second material layers and the etching stop layer are different;

[0018] A second structure hole penetrating through the stack structure is formed, the second structure hole extends to the etching stop layer, and the bottom of the second structure hole exposes the etching stop layer;

[0019] The part of the etching stop layer at the bottom of the second structure hole is removed to form a channel hole comprising the second structure hole and extending to the substrate;

[0020] A channel structure is formed in the channel hole;

[0021] The sacrificial layer is removed to form a sacrificial gap;

[0022] A semiconductor layer is formed in the sacrificial gap, and the semiconductor layer is electrically connected with a channel layer of the channel structure.

[0023] In some optional embodiments, during the process of forming the second structure hole penetrating through the stack structure; the etching rate of the first material layer and the second material layer is greater than the etching rate of the etching stop layer.

[0024] In some optional embodiments, the part of the etching stop layer at the bottom of the second structure hole is removed by wet etching, and a recess is formed on the side of the etching stop layer close to the second structure hole.

[0025] In some alternative embodiments, forming the channel structure in the channel hole includes: forming functional layers and a channel layer in the channel hole, stacked on top of each other.

[0026] In some alternative embodiments, forming the functional layers and the channel layer in the channel hole includes:

[0027] forming a barrier layer, a storage layer, and a tunneling insulating layer in the channel hole, stacked on top of each other;

[0028] forming the channel layer on the tunneling insulating layer.

[0029] In some alternative embodiments, after the step of "forming a channel structure in the channel hole", and before the step of "removing the sacrificial layer to form a sacrificial gap", further comprising:

[0030] forming a gate slit through the stack structure, the etch stop layer, the gate slit extending into the sacrificial layer.

[0031] In some alternative embodiments, forming a first structure hole through the stack structure, the first structure hole extending to the etch stop layer, a bottom of the first structure hole exposing the etch stop layer;

[0032] removing a portion of the etch stop layer at the bottom of the first structure hole;

[0033] removing the sacrificial layer opposite to the bottom of the first structure hole to further extend the bottom of the first structure hole into the sacrificial layer, and form the gate slit.

[0034] In some alternative embodiments, removing the sacrificial layer to form the sacrificial gap between the substrate and the etch stop layer;

[0035] removing the functional layer exposed in the sacrificial gap to further extend the sacrificial gap to a surface of the channel layer.

[0036] In some alternative embodiments, forming a common source contact in the gate slit, and the common source contact extending to the semiconductor layer.

[0037] In some alternative embodiments, further comprising: replacing the second material of the second material layer and the barrier material of the etch stop layer with a conductive material to form a conductive layer.

[0038] In some alternative embodiments, the barrier material is aluminum oxide.

[0039] The three-dimensional memory manufacturing method and the three-dimensional memory provided by the application can further divide the process steps of etching the second structure hole into multiple process steps of removing part of the stack structure on the top of the etching stop layer, removing the etching stop layer, and removing part of the stack structure on the bottom of the etching stop layer and extending the second structure hole to the substrate, and the etching depth in the last process step can be reduced due to the position of the etching stop layer in the stack structure, so that the processing error is reduced and the etching precision is accurately controlled. BRIEF DESCRIPTION OF DRAWINGS

[0040] The specific embodiments of the application are described in detail below with reference to the accompanying drawings, and it should be understood that the specific embodiments described herein are only used to illustrate and explain the application, and the application is not limited to the specific embodiments described below.

[0041] Figure 1 The whole structure of the three-dimensional memory in the embodiment of the application is shown in the schematic diagram.

[0042] Figures 2-4 The preparation flowchart of the channel hole in the embodiment of the application is shown in the schematic diagram.

[0043] Figure 5 The preparation flowchart of the channel structure in the embodiment of the application is shown in the schematic diagram.

[0044] Figures 6-8 The preparation flowchart of the first structure hole in the embodiment of the application is shown in the schematic diagram.

[0045] Figure 9 The preparation flowchart of the second substrate in the embodiment of the application is shown in the schematic diagram.

[0046] Figure 10 The preparation flowchart of the gate replacement process in the embodiment of the application is shown in the schematic diagram.

[0047] Figure 11 The preparation flowchart of the common source contact in the embodiment of the application is shown in the schematic diagram.

[0048] Figure 12 The partial enlarged view of A in the embodiment of the application is shown in the schematic diagram. Figure 3 The partial enlarged view of B in the embodiment of the application is shown in the schematic diagram.

[0049] Figure 13 The partial enlarged view of C in the embodiment of the application is shown in the schematic diagram. Figure 7 The partial enlarged view of B in the embodiment of the application is shown in the schematic diagram.

[0050] Figure 14 The partial enlarged view of C in the embodiment of the application is shown in the schematic diagram. Figure 11 The partial enlarged view of B in the embodiment of the application is shown in the schematic diagram.

[0051] Figure 15 The process flowchart of the three-dimensional memory in the embodiment of the application is shown in the schematic diagram.

[0052] Figure 16 To Figure 15 A process flow diagram of forming a semiconductor structure in a substrate.

[0053] Legend of reference signs:

[0054] 110: first substrate;

[0055] 120: second substrate;

[0056] 130: sacrificial layer;

[0057] 140: intermediate layer;

[0058] 200: stack structure;

[0059] 210: insulating layer;

[0060] 220: conductive layer;

[0061] 221: second recess;

[0062] 222: first recess;

[0063] 230: first structural hole;

[0064] 240: channel hole;

[0065] 250: transition layer;

[0066] 251: etching stop layer;

[0067] 260: second structural hole;

[0068] 300: common source contact;

[0069] 400: functional layer;

[0070] 410: notch;

[0071] 420: barrier layer;

[0072] 430: storage layer;

[0073] 440: tunneling insulating layer;

[0074] 500: channel layer;

[0075] 600: channel structure. DETAILED DESCRIPTION

[0076] The specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and should not be used to limit the scope of the present application.

[0077] In a manufacturing process of a three-dimensional memory, in order to electrically connect a channel layer in a channel hole to a common source contact in a gate slit, a sacrificial layer is usually arranged between a stack structure and a substrate first, and a gate slit etching is performed to extend the gate slit into the sacrificial layer, and then the sacrificial layer and a functional layer in the sacrificial layer are removed, and the channel layer is exposed from the sidewall of the channel hole, and then a semiconductor substrate is reformed between the stack structure and the substrate to electrically connect the channel layer sidewall to the common source contact.

[0078] However, due to the large number of layers of the stack structure, the gate slit etching is difficult, and the etching depth is difficult to control. If the depth is too large, the substrate at the bottom of the sacrificial layer will be damaged, and if the depth is too small, the sacrificial layer and the functional layer cannot be removed. In addition, due to the difficulty in controlling the etching depth, the depth of the gate slit at each position is not the same, and the etching uniformity is poor.

[0079] To solve the above problems, the embodiment of the present application provides a three-dimensional memory manufacturing method and a three-dimensional memory. By arranging an etching stop layer in the stack structure of the three-dimensional memory, the process step of the gate slit etching can be further divided into multiple process steps of removing part of the stack structure at the top of the etching stop layer, removing the etching stop layer, and removing part of the stack structure at the bottom of the etching stop layer and extending the gate slit into the sacrificial layer. Since the position of the etching stop layer in the stack structure is determined, the etching depth in the last process step can be reduced, thereby reducing the processing error, and the bottom of the gate slit can be located in the sacrificial layer without being too deep or too shallow.

[0080] Figure 1 The overall structure of the three-dimensional memory in the embodiment of the present application is shown in the figure. Figure 1 The embodiment provides a three-dimensional memory, which comprises a first substrate 110, a second substrate 120 and a stack structure 200 arranged in sequence.

[0081] The first substrate 110 can be made of a semiconductor material, such as but not limited to silicon germanium, germanium, silicon-on-insulator (SOI), etc. Alternatively, the first substrate 110 can be made of single crystal silicon, etc.

[0082] The second substrate 120 is formed on the first substrate 110, and the second substrate 120 can be made of a semiconductor material, such as but not limited to silicon germanium, germanium, silicon-on-insulator (SOI), etc. Alternatively, the second substrate 120 can be made of at least one of single crystal silicon or polycrystalline silicon.

[0083] The stack structure 200 is formed on the second substrate 120, and includes insulating layers 210 and conductive layers 220 arranged alternately; the thickness of the insulating layers 210 can be the same as or different from that of the conductive layers 220. Optionally, the conductive layers 220 are made of conductive materials, including but not limited to tungsten, cobalt, copper, aluminum, doped silicon, and / or silicide. The insulating layers 210 are made of insulating materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Of course, in some alternative embodiments, a plurality of stack structures 200 can also be stacked on the second substrate 120 in sequence, which can be set according to actual conditions.

[0084] The stack structure 200 is provided with a channel hole, and the channel hole is provided with a channel structure 600. The channel hole can penetrate the stack structure 200 and the second substrate, and the bottom of the channel hole can extend into the first substrate 110, so that the formed channel structure 600 penetrates the stack structure 200 and the second substrate 120 and extends to the first substrate 110.

[0085] Optionally, the number of the channel structures 600 can be multiple, and the multiple channel structures 600 are arranged in the stack structure 200.

[0086] Each channel structure 600 includes a functional layer 400 and a channel layer 500 arranged in sequence in the channel hole. In some embodiments, the channel layer 500 can be made of amorphous, polycrystalline, or monocrystalline silicon. The functional layer 400 includes a barrier layer 420, a storage layer 430, and a tunnel insulating layer 440 arranged in sequence in the channel hole. The barrier layer 420 can be made of silicon oxide, silicon nitride, high-insulation-constant insulating materials, or a combination thereof. The storage layer 430 can be made of silicon nitride, silicon oxynitride, silicon, or a combination thereof. The tunnel insulating layer 440 can be made of silicon oxide, silicon nitride, or a combination thereof.

[0087] In some alternative embodiments, the functional layer 400 in the second substrate 120 has a notch 410, which can be an annular structure surrounding the channel layer 500. The second substrate 120 extends into the notch 410 and is connected with the channel layer 500.

[0088] In addition, the stack structure 200 is also provided with a first structure hole penetrating the stack structure 200 and extending into the second substrate 120, and the first structure hole is provided with a common source contact 300.

[0089] Optionally, the number of the three-dimensional memory common source contacts 300 can be one or more, and the shape thereof can also be various, for example, each common source contact 300 can be in a cylindrical shape or along the direction of the stack structure 200. Figure 1The common source contact 300, extending vertically into a strip shape or in the direction perpendicular to the paper plane, can also be other patterned shapes such as a grid. In some embodiments, the common source contact 300 is made of a conductive material, including but not limited to titanium, tungsten, cobalt, copper, aluminum, and / or silicides. In an optional embodiment, the common source contact 300 may include a silicon conductor and a conductive portion covering the conductor, the conductive portion being made of titanium nitride. Further optionally, a conductive contact made of tungsten metal may be provided on the top of the conductor.

[0090] The bottom of the common source contact 300 is in contact with the second substrate 120, which is also connected to the channel layer 500. It is understood that the second substrate 120 may have doped regions, thereby electrically connecting the channel layer 500 to the common source contact 300.

[0091] This embodiment also provides a method for manufacturing a three-dimensional memory, which can produce the above-mentioned three-dimensional memory. Figures 2-4 This is a flowchart illustrating the fabrication process of the channel holes in an embodiment of the present invention. Figure 15 This is a flowchart illustrating the process flow of the three-dimensional memory in an embodiment of the present invention. Figure 16 for Figure 15 A flowchart of the process flow for forming a semiconductor structure.

[0092] refer to Figure 2 , 15 The method for manufacturing a three-dimensional memory can begin at step S10. Step S10 includes forming a semiconductor structure. The semiconductor structure may include a first substrate 110, a sacrificial layer 130, and a stack structure 200 stacked sequentially; the stack structure 200 includes alternating insulating layers 210 and transition layers 250; and at least one of the transition layers 250 near the sacrificial layer 130 is an etch stop layer 251 made of a barrier material; and the stack structure 200 has a first structural hole 230 whose bottom is located at the etch stop layer 251.

[0093] It is understood that there can be various specific ways to form a semiconductor structure. In one optional embodiment, refer to... Figure 16 Step S10 may further include:

[0094] The first substrate 110 is provided, and then step S11 is performed to form a sacrificial layer 130 on the first substrate 110; the sacrificial layer 130 can be made of a semiconductor material, for example but not limited to, silicon germanium, germanium, silicon-on-insulator (SOI). Optionally, the first substrate 110 can be made of monocrystalline silicon. The process of making the sacrificial layer 130 can use a thin film deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). After forming the sacrificial layer 130, step S12 can be performed to alternately stack insulating layers 210 and transition layers 250 on the sacrificial layer 130 to form a stack structure 200.

[0095] In the stack structure 200, the insulating layers 210 can be deposited from a first material; the plurality of transition layers 250 in the stack structure 200 can be made of a barrier material or a second material, i.e., at least one of the transition layers 250 can be made of a barrier material, which can be referred to as an etch stop layer 251, and the remaining transition layers 250 can be made of a second material different from the barrier material. The first material, the second material, and the barrier material are all different materials.

[0096] For ease of illustration, only one etch stop layer 251 is provided in the transition layers 250 as an example, and then step S12 can further include:

[0097] Step S1201 is performed to form an insulating layer 210 on the sacrificial layer 130, so that the insulating layer 210 can be in contact with the sacrificial layer 130. The insulating layer 210 can be a silicon oxide layer formed by a thin film deposition process.

[0098] After the insulating layer 210 is formed, step S1202 can be performed to form an etch stop layer 251 on the insulating layer 210, so that the etch stop layer 251 can be in direct contact with the insulating layer 210; the etch stop layer 251 can be a structure formed by a thin film deposition process using a barrier material.

[0099] After the etch stop layer 251 is formed, step S1203 can be further performed to further alternately stack the remaining insulating layers 210 and transition layers 250 on the etch stop layer 251. The remaining transition layers 250 can be silicon nitride layers formed by a thin film deposition process.

[0100] In summary, in the stack structure 200 formed by steps S1201-S1203, the transition layer 250 closest to the sacrificial layer 130 can be the etch stop layer 251 made of a barrier material, and the remaining transition layers 250 formed after the etch stop layer 251 are all made of a second material.

[0101] Of course, in the remaining embodiments of step S12, the first material and the second material can also be alternately stacked to form a first sub-stack structure, the bottom layer and the top layer of the first sub-stack structure are both the insulating layer 210, then the etching stop layer 251 can be formed on the first sub-stack structure, and then the first material and the second material are alternately stacked on the etching stop layer 251 to form the remaining insulating layers and transition layers. In the present embodiment, the etching stop layer 251 formed is not the transition layer 250 closest to the sacrificial layer 130, but can be a transition layer 250 closer to the sacrificial layer 130, for example, the etching stop layer 251 can be the second, third or fourth transition layer 250 from the bottom to the top.

[0102] Therefore, the "at least one transition layer 250 closest to the sacrificial layer 130 is an etching stop layer 251 composed of a barrier material" in the semiconductor structure should be understood broadly. Taking a stack structure 200 in which a total of N transition layers 250 are formed as an example, and the transition layers are sequentially labeled 1, 2, 3, …, N from bottom to top. The label of the transition layer 250 closest to the sacrificial layer 130 can be M, M can be greater than or equal to 1 and less than N / 2. Wherein M and N are natural numbers.

[0103] The method for forming the insulating layer 210 and the transition layer 250 in step S12 includes but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0104] The above is a description of the method for forming the stack structure 200 with only one etching stop layer 251. When the stack structure 200 is provided with multiple etching stop layers 251, the multiple etching stop layers 251 can be adjacent transition layers 250, or can be formed as a structure in which the multiple etching stop layers 251 are spaced apart by other transition layers 250, or at least part of the etching stop layers 251 are adjacent, and the other part of the etching stop layers 251 can be spaced apart by transition layers 250 composed of the second material.

[0105] In some embodiments, the semiconductor structure formed in step S10 is also provided with a channel structure 600, the channel structure 600 penetrates the stack structure 200 and extends to the first substrate 110. After the optional step S12, the channel structure 600 can be formed in the stack structure 200. In an optional embodiment, the step of forming the channel structure 600 can further include: Figures 2-4 The preparation process of forming a channel hole in the stack structure as shown in FIG. 13.

[0106] The process of forming a channel hole starts from step S13, as shown in FIG. 13. Figure 2As shown, a second structure hole 260 is formed in the stack structure 200, and the bottom of the second structure hole 260 is stopped in the etching stop layer 251. That is, the portion of the stack structure 200 above the etching stop layer 251 within the range of the second structure hole 260 is removed first. The method of forming the second structure hole 260 can be one or a combination of photolithography, dry / wet etching or mechanical processing.

[0107] Optionally, the second structure hole 260 can be formed by etching to remove the insulating layer 210 and the transition layer 250 on top of the etching stop layer 251, so that the bottom of the second structure hole 260 is stopped in the etching stop layer 251.

[0108] In one possible implementation, since the etching stop layer 251 and the remaining transition layer 250 are made of different materials, the etching products of the etching stop material are different from the etching products of the first material and the second material. When the etching products of the etching stop material are detected, the etching can be stopped, so that the bottom of the second structure hole 260 can be in contact with the upper surface of the etching stop layer 251 or etch a small amount into the etching stop layer 251.

[0109] In another possible implementation, the first material constituting the insulating layer 210 and the second material constituting the remaining transition layer 250 except the etching stop layer 251 both have high etching selectivity with respect to the etching stop material. High etching selectivity means that the etching rate of the first material and the second material is much higher than that of the etching stop material, so that the etchant can be selected to etch and remove the first material and the second material, but the etchant is difficult to etch or can only etch a small amount of the etching stop material, so that the bottom of the second structure hole 260 can be in contact with the upper surface of the etching stop layer 251 or etch a small amount into the etching stop layer 251.

[0110] In addition, step S13 can form multiple second structure holes 260 at the same time, or alternatively, multiple second structure holes 260 can be formed on the stack structure 200 by performing step S13 multiple times.

[0111] After step S13, step S14 can be performed, as shown in Figure 3 As shown, the etching stop layer 251 at the bottom of the second structure hole 260 is removed, and the insulating layer 210 at the bottom of the etching stop layer 251 is exposed. That is, the bottom of the second structure hole 260 is further extended to penetrate through the etching stop layer 251.

[0112] This step can also be processed by one or more combinations of photolithography, dry / wet etching or mechanical processing methods. It can be understood that this step can remove only the blocking material at the bottom of the second structure hole 260 by selecting an etchant or process method, and will not remove or only remove a small amount of the insulating layer 210 at the bottom of the etching stop layer 251.

[0113] Optionally, the blocking material can be aluminum oxide. Step S14 specifically removes the etching stop layer 251 at the bottom of the second structure hole 260 by wet etching. In addition, Figure 12 To Figure 3 The local enlarged view at A in FIG. 6; refer to Figure 12 Due to the process limitation of wet etching, it will not only remove the blocking material in the direction perpendicular to the first substrate 110, but also remove part of the blocking material in the direction parallel to the first substrate 110, so that the position of the hole wall of the second structure hole 260 surrounded by the etching stop layer 251 forms a first recess 222. It can be understood that in some embodiments, due to the etching of the channel hole 240, only the etching stop layer 251 is etched by wet etching, and the first recess 222 only exists at the position opposite to the sidewall of the channel hole 240 and the etching stop layer 251.

[0114] After step S14, step S15 can be performed, as shown in FIG. 6, Figure 4 The bottom of the second structure hole 260 is further extended into the first substrate 110 to form a channel hole 240. That is, this step can remove the remaining stack structure 200, the sacrificial layer 130 and part of the first substrate 110 at the bottom of the etching stop layer 251 in the second structure hole 260. The specific implementation can be one or more combinations of photolithography, dry / wet etching or mechanical processing methods.

[0115] In summary, the channel hole 240 formed by steps S13-S15 can penetrate through the stack structure 200 and the sacrificial layer 130, and extend into the first substrate 110.

[0116] In the embodiment, by setting the etching stop layer 251, the process steps of etching the channel hole 240 can be further divided into multiple process steps of removing the partial stack structure 200 on the top of the etching stop layer 251, removing the etching stop layer 251, and removing the partial stack structure 200 on the bottom of the etching stop layer 251 and extending the channel hole 240 into the first substrate 110, and since the position of the etching stop layer 251 in the stack structure is determined, the depth L1 of the lower surface of the etching stop layer 251 from the bottom of the channel hole 240 is known, and L1 is necessarily smaller than the depth L2 of the entire channel hole 240, that is, the etching depth L1 in the process step of removing the partial stack structure 200 on the bottom of the etching stop layer 251 and extending the channel hole 240 into the first substrate 110 is smaller than the etching depth L2 of the channel hole formed by one etching in the related art, so that the processing error can be reduced, and the bottom of the channel hole can be located in the first substrate 110, and the first substrate 110 will not be punched. Also, the depths of the respective channel holes 240 can be made more uniform, with good uniformity, which is beneficial to improve the uniformity of the bottom voltage.

[0117] Also, the smaller the size of L1 is when the etching stop layer 251 is closer to the sacrificial layer 130, the smaller the etching error is, and the etching depth of the channel hole 240 is better controlled.

[0118] It can be understood that the above only takes setting one etching stop layer 251 as an example to illustrate the forming method of the second structure hole, when multiple etching stop layers 251 are set, for example, 2 etching stop layers 251 are set, the hole bottom of the second structure hole 260 can be stopped in the upper first etching stop layer first, then the first etching stop layer at the hole bottom of the second structure hole 260 is removed, then the partial stack structure between the first etching stop layer and the lower second etching stop layer is removed, the hole bottom of the second structure hole 260 is stopped in the second etching stop layer, and then the second etching stop layer at the hole bottom of the second structure hole 260 is removed; finally, the hole bottom of the second structure hole 260 is extended into the first substrate 110. In addition, when the number of etching stop layers 251 is greater than 2, the method can be analogized in this way, which will not be described herein. When multiple etching stop layers 251 are set, the etching depth of the second structure hole can be controlled in segments, so that the hole bottom of the second structure hole 260 can be stopped at any desired position.

[0119] After step S15, step S16 can be performed, in which the functional layer 400 and the channel layer 500 are sequentially stacked in the channel hole 240. Figure 5 The preparation flow chart of the channel structure in the embodiment of the application is shown in FIG. 6. Figure 5The step S16 can further include sequentially stacking the blocking layer 420, the storage layer 430 and the tunnel insulating layer 440 in the channel hole 240, and then stacking the channel layer 500 on the tunnel insulating layer 440.

[0120] In some embodiments, the functional layer 400 is a combination of multiple layers, including but not limited to the blocking layer 420, the storage layer 430 and the tunnel insulating layer 440. Optionally, the tunnel insulating layer 440 can be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride or a combination of the above. Optionally, the storage layer 430 can include a material for storing charge for operating NAND. The material of the storage layer 430 includes but is not limited to silicon nitride, silicon oxynitride, or a combination of silicon oxide and silicon nitride, or a combination of the above. Optionally, the blocking layer 420 can also be an insulating material layer, such as a silicon oxide layer or a composite layer including silicon oxide / silicon nitride / silicon oxide (ONO). Further, the blocking layer 420 can include a high-K dielectric layer (e.g. aluminum oxide). In addition, the functional layer 400 and the channel layer 500 can be prepared by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable methods.

[0121] It can be understood that when the step S14 uses wet etching, the channel structure in the step S16 will fill the first recess 222 to form a protrusion due to the side wall of the channel hole 240 having the first recess 222.

[0122] Figures 6-8 The flow chart for preparing the first structure hole in the embodiments of the present application; refer to Figure 6 After forming the channel structure in the stack structure, the step S17 can be performed to form the first structure hole 230 in the stack structure 200 with the bottom of the first structure hole 230 located at the etching stop layer 251. That is, the portion of the stack structure 200 above the etching stop layer 251 in the range of the first structure hole 230 is removed. The method for forming the first structure hole 230 can be one or a combination of multiple of photolithography, dry / wet etching or mechanical processing methods.

[0123] Optionally, the first structure hole 230 can be formed by etching to remove the insulating layer 210 and the transition layer 250 on the top of the etching stop layer 251, so that the bottom of the first structure hole 230 is stopped at the etching stop layer 251.

[0124] In one possible implementation, it can be understood that, since the etching stop layer 251 and the rest of the transition layer 250 are made of different materials, the etching product produced by the etching stop layer 251 is obviously different from the etching product produced by the etching of the first material and the second material. When the etching product of the etching stop layer 251 is detected in the etching product, the etching can be stopped, so that the bottom of the first structure hole 230 can be in contact with the upper surface of the etching stop layer 251 or etched into the etching stop layer 251 by a small amount.

[0125] In another possible implementation, the first material constituting the insulating layer 210 and the second material constituting the rest of the transition layer 250 except the etching stop layer 251 have high etching selectivity with respect to the barrier material. High etching selectivity means that the etching rate of the first material and the second material is much greater than that of the etching barrier material, so that the first material and the second material layer can be etched and removed by selecting an etchant, but the etchant is difficult to etch or can only etch a small amount of the barrier material, so that the bottom of the first structure hole 230 can be in contact with the upper surface of the etching stop layer 251 or etched into the etching stop layer 251 by a small amount.

[0126] In addition, step S17 can form a plurality of first structure holes 230 at the same time, or a plurality of first structure holes 230 can be formed on the stack structure 200 by performing step S17 multiple times.

[0127] After step S17, step S20 can be performed, referring to Figure 15 , and combining Figure 7 , the etching stop layer 251 at the bottom of the first structure hole 230 is removed, and the insulating layer 210 at the bottom of the etching stop layer 251 is exposed. That is, this step further extends the bottom of the first structure hole 230 to penetrate the etching stop layer 251.

[0128] This step can also be processed by one or a combination of photolithography, dry / wet etching or mechanical processing methods. It can be understood that this step can remove only the barrier material at the bottom of the first structure hole 230 by selecting an etchant or a process, and will not remove or only remove a small amount of the insulating layer 210 at the bottom of the etching stop layer 251.

[0129] Optionally, the barrier material can be aluminum oxide, and step S20 specifically removes the etching stop layer 251 at the bottom of the first structure hole 230 by wet etching. In addition, Figure 13 is Figure 7 a partial enlarged view of B in FIG. 1C; referring to Figure 13Due to the process limitation of the wet etching, the blocking material will be removed not only in the direction perpendicular to the first substrate 110, but also in the direction parallel to the first substrate 110, so that the second recess 221 is formed at the position of the wall of the first structure hole 230 surrounded by the etching stop layer 251. It can be understood that, in some embodiments, due to the etching of the first structure hole 230, only the etching stop layer 251 is etched by the wet etching, and the second recess 221 only exists at the position of the sidewall of the channel hole 240 opposite to the etching stop layer 251.

[0130] After step S20, step S30 can be performed, as shown in the figure, to further extend the bottom of the first structure hole 230 into the sacrificial layer 130. That is, the remaining stack structure 200 at the bottom of the etching stop layer 251 in the first structure hole 230 and part of the sacrificial layer 130 can be removed in this step. The specific implementation can be one or a combination of photolithography, dry / wet etching or mechanical processing method. Figure 8

[0131] In summary, the first structure hole 230 formed through steps S17, S20 and S30 can penetrate the stack structure 200 and extend into the sacrificial layer 130.

[0132] In this embodiment, by setting the etching stop layer 251, the process steps of etching the first structure hole 230 can be further divided into multiple process steps of removing part of the stack structure 200 at the top of the etching stop layer 251, removing the etching stop layer 251, and removing part of the stack structure 200 at the bottom of the etching stop layer 251 and extending the first structure hole 230 into the sacrificial layer 130. Due to the position of the etching stop layer 251 in the stack structure, the depth H1 of the lower surface of the etching stop layer 251 from the bottom of the first structure hole 230 is known, and H1 is necessarily smaller than the depth H2 of the entire first structure hole 230, that is, the etching depth H1 in the process step of removing part of the stack structure 200 at the bottom of the etching stop layer 251 and extending the first structure hole 230 into the sacrificial layer 130 is smaller than the etching depth H2 of the gate slit formed by one etching in the related art, so that the processing error can be reduced, the bottom of the first structure hole 230 can be located in the sacrificial layer 130, and it will not be too shallow or too deep, so that the problem that the etching depth is too large to damage the first substrate 110 and the depth is too small to cause the subsequent process to be unable to remove the sacrificial layer 130 and the functional layer 400 can be avoided. Furthermore, the depth of each first structure hole 230 or the depth of different positions of the bottom of each first structure hole 230 can be more consistent, and the etching uniformity is good. At the same time, this process does not need to increase a new mask layer and is simple in process and low in cost.

[0133] ​And, the smaller the size of H1 is, the closer the etching stop layer 251 is to the sacrificial layer 130, and the smaller the etching error is, and the better the etching depth of the first structure hole 230 is controlled.

[0134] It can be understood that the above only takes the example of setting one etching stop layer 251 to illustrate the forming method of the first structure hole, and when multiple etching stop layers 251 are set, for example, two etching stop layers 251 are set, the hole bottom of the first structure hole 230 can be stopped in the upper first etching stop layer first, then the first etching stop layer at the hole bottom of the first structure hole 230 is removed, then the part of the stack structure between the first etching stop layer and the lower second etching stop layer is removed, the hole bottom of the first structure hole 230 is stopped in the second etching stop layer, and then the second etching stop layer at the hole bottom of the first structure hole 230 is removed; finally, the hole bottom of the first structure hole 230 is extended to the inside of the sacrificial layer 130. In addition, when the number of etching stop layers 251 is greater than 2, the above method can be analogized, which is not described herein. When multiple etching stop layers 251 are set, the etching depth of the first structure hole can be controlled in sections, so that the hole bottom of the first structure hole 230 is stopped at any position as required by design.

[0135] After step S30, step S40 can be performed to remove the sacrificial layer 130 to form a sacrificial gap. In some embodiments, when the semiconductor structure formed in step S10 has the channel structure 600, step S40 can specifically include: removing the sacrificial layer 130 and part of the channel structure 600 in the sacrificial layer 130 to form the sacrificial gap. Figure 9 The flow chart for preparing the second substrate in the embodiments of the present application; refer to Figures 8-9 The removed part of the channel structure 600 in step S40 can be the functional layer 400 at the position surrounded by the sacrificial layer 130. The removal method can be one or a combination of multiple processes such as photolithography, dry / wet etching or mechanical processing.

[0136] In some optional embodiments, step 40 can specifically further include:

[0137] Step S41, removing the sacrificial layer 130 to form a sacrificial gap between the first substrate 110 and the stack structure 200.

[0138] In this step, the formed sacrificial gap only exists in the area surrounded by the first substrate 110, the stack structure 200 and the outer surface of the functional layer 400.

[0139] Step S42, removing the functional layer 400 exposed in the sacrificial gap to further extend the sacrificial gap to the surface of the channel layer 500.

[0140] That is, step S42 further removes the functional layer 400 constituting the boundary of the sacrificial gap on the basis of step S41, thereby expanding the boundary of the sacrificial gap to the outer surface of the channel layer 500.

[0141] When the functional layer 400 includes the barrier layer 420, the storage layer 430 and the tunnel insulating layer 440 which are sequentially stacked, removing the functional layer 400 exposed in the sacrificial gap can further include sequentially removing the barrier layer 420, the storage layer 430 and the tunnel insulating layer 440 exposed in the sacrificial gap.

[0142] The removal method of step S41 and step S42 can be one or a combination of photolithography, dry / wet etching or mechanical processing.

[0143] It can be understood that only the sacrificial layer 130 and part of the functional layer 400 are removed in steps S30 and S40, and the first substrate 110 is not damaged, so that Figure 2 In some embodiments, in order to prevent damage to the first substrate 110, at least one intermediate layer 140 can be further provided between the first substrate 110 and the sacrificial layer 130, which serves as a thin layer to protect the first substrate 110 and is consumed in the process of removing the sacrificial layer 130 and the functional layer 400, so that the sacrificial gap finally formed in step S40 directly contacts the first substrate 110, that is, the intermediate layer 140 is removed together with the sacrificial layer 130 and the functional layer 400.

[0144] The constituent material of the intermediate layer can be silicon oxide or silicon nitride. The number of intermediate layers can be multiple, for example, a stacked structure of silicon oxide or silicon nitride, and the thickness of each layer can also be set according to actual conditions. For example, referring to Figure 8 In some optional embodiments, the intermediate layer can include a two-layer structure of a silicon oxide layer and a silicon nitride layer, the silicon oxide layer contacts the first substrate 110, and the silicon nitride layer is located above the silicon oxide layer.

[0145] After the sacrificial gap is formed, step S50 can be performed, referring to Figure 9 The second substrate 120 is formed in the sacrificial gap, and the bottom of the first structure hole 230 is located in the second substrate 120.

[0146] The second substrate 120 can be formed by an epitaxial process, which can grow silicon outward from a position with a silicon substrate. Since the sacrificial gap formed in step S40 exposes the first substrate 110 and the channel layer 500, the second substrate 120 can be formed by simultaneously growing the channel layer 500 and the first substrate 110 outward to fill the sacrificial gap.

[0147] Of course, the grown second substrate 120 can fill the space of the original sacrificial layer 130, or can overflow the space, i.e. the second substrate 120 can be partially located Figure 8 inside the first structure hole 230, at which time, the second substrate 120 inside the first structure hole 230 needs to be further removed, and the hole bottom of the first structure hole 230 is extended into the second substrate 120, forming Figure 9 a structure.

[0148] In some embodiments, the stack structure 200 formed in step S10 can be formed by alternately stacking insulating materials and conductive materials, for example, a stack of silicon and silicon oxide.

[0149] At this time, without performing a gate replacement process, step S50 is followed by step S60, Figure 11 which is a flowchart for preparing a common source contact in an embodiment of the present application; refer to Figure 11 In the first structure hole 230, a common source contact 300 is formed. This step can specifically include forming a first dielectric layer composed of a non-conductive material in the first structure hole 230, then removing the first dielectric layer at the hole bottom of the first structure hole 230 and extending the hole bottom into the second substrate 120, and then forming the common source contact 300 in the first structure hole 230.

[0150] The process of forming the first dielectric layer and the common source contact 300 can be a thin film deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The method of removing the first dielectric layer can be one or a combination of photolithography, dry / wet etching, or mechanical processing. The material constituting the first dielectric layer includes but is not limited to silicon oxide, silicon nitride, or a combination thereof.

[0151] In other embodiments, the stack structure 200 formed in step S10 can be formed by alternately stacking two dielectrics.

[0152] At this time, between performing steps S50 and S60, step S70 can also be included, i.e. a gate replacement process is needed. Figure 10 which is a flowchart for preparing a gate replacement process in an embodiment of the present application; refer to Figures 9-10The materials constituting the remaining transition layers and the barrier material are replaced by metal materials. That is, the second material and the barrier material in the transition layer 250 are all replaced by metal materials, which can specifically include removing all the transition layers 250 first to form conductive gaps between the insulating layers 210, and then forming a conductive layer 220 composed of metal materials in the conductive gaps by a thin film deposition process or an electroplating process, etc. In some alternative ways, when the initially formed stack structure 200 is a silicon oxide and silicon nitride stack, the silicon nitride can be replaced by a conductive material such as "tungsten" or the like by a gate replacement process.

[0153] In the manufacturing method of the three-dimensional memory described above, in the step of forming the semiconductor structure, the order of forming the channel hole 240 and the first structure hole 230 is to form the channel hole 240 and the channel structure 600 first, and then form the first structure hole 230. In some alternative embodiments, the first structure hole 230 can be formed first, and then the channel hole 240 and the channel structure 600 are formed, or the first structure hole 230 and the channel hole 240 are formed at the same time, and then the channel structure 600 is formed. The actual situation can be set according to the actual situation.

[0154] In some alternative embodiments, the three-dimensional memory manufactured based on the above method can also have the following characteristics.

[0155] Figure 14 For Figure 11 The local enlarged view at C in FIG. 10; refer to Figure 12 And 14 Since the etching stop layer 251 is removed by wet etching, the hole wall of the channel hole 240 has a first recess 222 at the position where the etching stop layer 251 is located. Therefore, the channel structure 600 formed in the channel hole 240 in step S16 has a protrusion filled in the first recess 222, so that the finally formed three-dimensional memory has a first recess 222 at the position of the hole wall of the channel hole 240 surrounded by the conductive layer 220. The conductive layer 220 is the conductive layer 220 replaced by the barrier material.

[0156] Therefore, when the stack structure formed in step S10 has at least one etching stop layer 251, the finally formed three-dimensional memory has a first recess 222 at the position of the hole wall of the channel hole 240 surrounded by at least one conductive layer 220, and the channel structure has a protrusion filled in the first recess 222.

[0157] In an alternative way, when the transition layer 250 closest to the first substrate 110 in the stack structure 200 formed in step S10 is made into the etching stop layer 251, the finally formed three-dimensional memory has a first recess 222 at the position of the hole wall of the channel hole 240 surrounded by the conductive layer 220 closest to the second substrate 120.

[0158] It can be understood that although the second recess 221 also appears on the hole wall of the first structure hole 230 in the process of forming the first structure hole 230, as shown in Figure 13 However, when the material constituting the remaining transition layer 250 and the barrier material are replaced by the metal material in step S70, the second recess 221 is filled with the metal material, resulting in that the finally formed common source contact 300 can not have the protrusion corresponding to the original etching stop layer 251 in the first structure hole 230.

[0159] In the description of the present application, it is to be understood that the terms "first", "second", "third" and the like in the description and in the claims, if they can be used at all, are used merely to distinguish one identical feature from another, and do not imply or create any relative importance or any specific order. Thus, a feature defined with "first", "second" or "third" can include at least one of the features. In the description of the present application, "a plurality of" means at least two, for example, two, three or the like, unless explicitly specified otherwise.

[0160] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixedly connected, can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected or can communicate with each other; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0161] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature is "above", "over" and "on" the second feature, which can be that the first feature is directly above or obliquely above the second feature, or only means that the horizontal height of the first feature is higher than that of the second feature. The first feature is "under", "below" and "under" the second feature, which can be that the first feature is directly below or obliquely below the second feature, or only means that the horizontal height of the first feature is less than that of the second feature.

[0162] In the above description, the description with reference to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples, without contradiction.

[0163] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-dimensional memory, characterized in that, include: Channel structure, stacked substrates, semiconductor layers, and stacked structure; The stack structure includes multiple alternating insulating and conductive layers; The channel structure penetrates the stack structure and the semiconductor layer, and extends to the substrate, with the semiconductor layer located between the substrate and the stack structure; At least one of the conductive layers has a recess on a side surface near the channel structure; The channel structure has protrusions that match the depression; The channel structure includes functional layers and channel layers stacked on top of each other; The semiconductor layer is electrically connected to the channel layer; The functional layer is provided with an opening, and a portion of the channel layer is exposed at the opening; The semiconductor layer extends to the opening and is electrically connected to the channel layer.

2. The three-dimensional memory of claim 1, wherein, The depression includes a first depression; The first recess is located on the conductive layer closest to the semiconductor layer.

3. The three-dimensional memory of claim 1, wherein, The stack structure also includes a common source contact; The common source contact extends through the stack structure and into the semiconductor layer.

4. The three-dimensional memory of claim 1, wherein, The functional layer includes a barrier layer, a storage layer, and a tunneling insulation layer stacked on top of each other, with the storage layer located between the barrier layer and the tunneling insulation layer.

5. A three-dimensional memory manufacturing method comprising: Includes the following steps: A substrate is provided, and a sacrificial layer is formed on the substrate; At least one pair of first material layers and an etch stop layer are formed on the sacrificial layer; A first material layer and a second material layer are alternately formed on the etch stop layer to form a stack structure, and the materials of the first material layer, the second material layer and the etch stop layer are different; A second structural hole is formed through the stack structure, the second structural hole extends to the etch stop layer, and the bottom of the second structural hole exposes the etch stop layer; Remove the portion of the etching stop layer located at the bottom of the second structural hole to form a channel hole that includes the second structural hole and extends into the substrate; A channel structure is formed in the channel hole; Remove the sacrificial layer to form a sacrificial gap; A semiconductor layer is formed in the sacrificial gap, and the semiconductor layer is electrically connected to the channel layer of the channel structure.

6. The three-dimensional memory fabrication method of claim 5, wherein, During the process of forming the second structural hole through the stack structure; The etching rates of the first material layer and the second material layer are greater than the etching rate of the etching stop layer.

7. The method for manufacturing a three-dimensional memory according to claim 5, characterized in that, The portion of the etching stop layer located at the bottom of the second structural hole is removed by wet etching, and a depression is formed on the side of the etching stop layer near the second structural hole.

8. The three-dimensional memory fabrication method of claim 5, wherein, Forming a channel structure in the channel hole includes: Functional layers and channel layers are formed stacked on top of each other within the channel holes.

9. The three-dimensional memory fabrication method of claim 8, wherein, Functional layers and channel layers are formed stacked within the channel holes, including: A barrier layer, a storage layer, and a tunneling insulation layer are formed stacked on top of each other within the channel hole; The trench layer is formed on the tunneling insulation layer.

10. The three-dimensional memory fabrication method of claim 8, wherein, After the step of "forming a channel structure in the channel hole" and before the step of "removing the sacrificial layer to form a sacrificial gap", the method further includes: A gate seam is formed that penetrates the stack structure and the etch stop layer, and the gate seam extends into the sacrificial layer.

11. The method of claim 10, wherein: a first structural hole is formed through the stack structure, the first structural hole extending to the etch stop layer, a bottom of the first structural hole exposing the etch stop layer; a portion of the etch stop layer at the bottom of the first structural hole is removed; a portion of the sacrificial layer opposite the bottom of the first structural hole is removed to further extend the bottom of the first structural hole into the sacrificial layer and form the gate slit.

12. The method of claim 11, wherein: the sacrificial layer is removed to form the sacrificial gap between the substrate and the etch stop layer; the functional layer exposed in the sacrificial gap is removed to further extend the sacrificial gap to a surface of the channel layer.

13. The method of claim 12, wherein: a common source contact is formed in the gate slit and extends to the semiconductor layer.

14. The three-dimensional memory fabrication method of any one of claims 5-13, wherein, further comprising: replacing the second material of the second material layer and the barrier material of the etch stop layer with a conductive material to form a conductive layer.

15. The three-dimensional memory fabrication method of claim 14, wherein, the barrier material is aluminum oxide.

Images