A phase-locked loop circuit with leakage compensation structure

Abstract

The present invention relates to a phase-locked loop circuit with a leakage compensation structure, which can solve the leakage problem of a loop filter capacitor in a phase-locked loop and provide a feasible solution for using a capacitor with high capacitance density but leakage in a phase-locked loop; the overall architecture includes: a frequency detector and charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module, and a frequency divider; the beneficial effects are: first, the leakage of the filter capacitor is compensated by a successive approximation leakage compensation capacitor array, which can not only track the leakage change caused by the process angle and temperature of the filter capacitor in real time, but also calibrate the potential mismatch in the leakage compensation path; second, the nonlinear problem of capacitor leakage current and VCTRL voltage is solved by frequency locking and VCTRL clamping, and the leakage compensation accuracy is further improved.

Description

Technical Field

[0001] The invention relates to a phase-locked loop circuit with a leakage compensation structure, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Phase-locked loop circuits are widely used in various chips. They are indispensable core circuits in the fields of RF microwave, mixed analog and digital, and pure digital. The function and performance of the phase-locked loop play a decisive role in the success or failure of the entire chip. In an integrated system on a chip (SOC) or a multi-channel interface circuit, multiple phase-locked loops are often required to provide distributed frequency sources for RF local oscillator spectrum shifting, system clocks, audio and video clocks, and analog-to-digital conversion sampling clocks. With the development of SOC, the clock requirements of chips have become more and more complex, leading to an increase in the number of phase-locked loops. However, the loop filter capacitors required in the phase-locked loop are related to the physical size and will not shrink with the evolution of the process. How to reduce the area of ​​the phase-locked loop has become a difficult problem in the industry.

[0003] Figure 1 The figure shows the traditional phase-locked loop structure, which includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The loop filter of the phase-locked loop based on the ring-structured voltage-controlled oscillator often occupies one-third or even one-half of the area. Although the low-voltage transistor with high capacitance density can effectively reduce the area of ​​the loop filter capacitor by using it as the loop filter capacitor, the leakage problem of the low-voltage transistor will seriously deteriorate the performance of the phase-locked loop. What is more serious is that the leakage of the loop filter capacitor changes with the plate voltage, process angle and temperature, which further increases the difficulty of handling the leakage problem. Although with the continuous development of technology, the emergence of various structure transistors has solved the leakage problem between the drain and the source when the transistor is turned off to a certain extent, the gate leakage problem faced by the loop filter capacitor has not been effectively solved. Therefore, the industry has to continue to use high-voltage tube capacitors or MOM capacitors with low capacitance density but small leakage as loop filter capacitors.

[0004] It can be seen that the leakage problem of the loop filter capacitor greatly limits the available types of capacitors, especially the low-voltage transistor capacitors with high capacitance density. Solving the leakage problem of the loop filter capacitor and improving the capacitance density of the loop filter are technical problems that need to be urgently solved by technical personnel in this field.

[0005] In the prior art Figure 2 The figure shows the leakage compensation technology proposed in the patent "Charge pump circuit and phase-locked loop circuit with capacitor leakage compensation". The main disadvantages of this solution are: a. Using only a fixed current to compensate for leakage cannot track process angle and temperature changes, and the leakage compensation effect is poor; b. When the temperature and frequency change, the node VC voltage will change, further deteriorating the leakage compensation effect.

[0006] like Figure 3 The figure shows the leakage compensation technology proposed in the patent "Phase-locked loop for dynamic compensation of V2I gate leakage in voltage-controlled oscillator". The main disadvantages of this solution are: a. When the VCTRL voltage (corresponding to Figure 3 When the gate voltage of V2I in the middle changes, the leakage compensation accuracy is difficult to guarantee (for example, when the VCTRL voltage increases, the leakage of V2I and the filter capacitor Cz will increase due to the increase of VCTRL voltage, but the compensation capacitors C1~Cn will decrease due to the increase of VCTRL voltage); b. The leakage of compensation capacitors C1~Cn is directly compensated to V2I and filter capacitor Cz at a ratio of 1:1. Cz usually has a large area, which leads to a large area of ​​C1~Cn.

[0007] The leakage compensation technology proposed in the prior art "A Fully Integrated Phase-Locked Loop with Leakage Current Compensation in 65-nm CMOS Technology" is as follows: Figure 4 As shown in the figure, the main disadvantages of this solution are: a. Dual CPs are required to achieve compensation, wasting extra area and power consumption; b. The matching problem of dual CPs and LCC affects the compensation accuracy and is difficult to control. The advantages are: the use of dual CPs can track the change of VCTRL voltage and solve the problem of VCTRL change deteriorating the compensation accuracy. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a phase-locked loop circuit with a leakage compensation structure, which utilizes a successive approximation method, combined with a matching loop control, to offset the leakage current of the loop filter capacitor by leakage current monitoring, calibration, and compensation. The method is intuitive in concept, simple in circuit, and easy to implement.

[0009] In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a phase-locked loop circuit with a leakage compensation structure, including a frequency detector and a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module, and a frequency divider;

[0010] Among them, one of the input ends of the frequency detector and charge pump module is used to access the reference clock REFCLK, the output end of the frequency detector and charge pump module is connected to the node VCTRL through the switch S1, and the node VCTRL is respectively connected to the input end of the filter module, one of the input ends of the successive approximation compensation capacitor module, and the input end of the frequency locking and VCTRL clamping module; the internal node VRES of the filter module constitutes the output end of the filter module, and the node VRES is respectively connected to the output end of the leakage monitoring compensation module and the other input end of the successive approximation compensation capacitor module; the output end of the successive approximation compensation capacitor module is connected to the input end of the leakage monitoring compensation module;

[0011] The output end of the frequency lock and VCTRL clamp module is connected to the input end of the frequency divider, and the output end of the frequency lock and VCTRL clamp module is used to provide the target circuit with adjusted frequency and phase; the output end of the frequency divider is connected to the other input end of the frequency detector and charge pump module, and the frequency divider provides the divided feedback clock FBCLK for the frequency detector and charge pump module.

[0012] As a preferred technical solution of the present invention: the successive approximation compensation capacitor module includes a comparator CMP1, a successive approximation logic SAR, and a compensation capacitor array; wherein the negative input terminal of the comparator CMP1 constitutes one of the input terminals of the successive approximation compensation capacitor module, which is used to connect to the node VCTRL; the positive input terminal of the comparator CMP1 constitutes another input terminal of the successive approximation compensation capacitor module, which is used to connect to the node VRES;

[0013] The compensation capacitor array includes a compensation capacitor Con, compensation capacitors C1 to Cn, and switches corresponding to the compensation capacitors C1 to Cn, respectively, wherein the lower plates of the compensation capacitors C1 to Cn are connected in series to the corresponding switches and then grounded, the lower plate of the compensation capacitor Con is directly grounded, the upper plate of the compensation capacitor Con is connected to the upper plates of the compensation capacitors C1 to Cn, and the connected end constitutes an output end of the successive approximation compensation capacitor module;

[0014] The output end of the comparator CMP1 is connected to the input end of the successive approximation logic SAR, and the output end of the successive approximation logic SAR is connected to the switches corresponding to the compensation capacitors C1 to Cn respectively.

[0015] As a preferred technical solution of the present invention: the leakage monitoring and compensation module includes a current monitoring P-type transistor MP2, a current compensation P-type transistor MP1, and a voltage clamping operational amplifier OP; wherein the drain of the current monitoring P-type transistor MP2 is connected to the positive input terminal of the voltage clamping operational amplifier OP, and the connected position between the two constitutes the input terminal of the leakage monitoring and compensation module; the negative input terminal of the voltage clamping operational amplifier OP is used to access the preset reference voltage VREF; the output terminal of the voltage clamping operational amplifier OP, the gate of the current monitoring P-type transistor MP2, and the gate of the current compensation P-type transistor MP1 are connected, the drain of the current compensation P-type transistor MP1 constitutes the output terminal of the leakage monitoring and compensation module, and the source of the current monitoring P-type transistor MP2 and the source of the current compensation P-type transistor MP1 are respectively connected to the preset power supply voltage.

[0016] As a preferred technical solution of the present invention: the frequency locking and VCTRL clamping module includes a clamping comparator CMP2, a digital logic DIG circuit, and a voltage-controlled oscillator VCO; wherein, the negative input end of the clamping comparator CMP2 is used to access a preset reference voltage VREF, the positive input end of the clamping comparator CMP2 is connected to the voltage control frequency end of the voltage-controlled oscillator VCO, and the connected position constitutes the input end of the frequency locking and VCTRL clamping module; the output end of the clamping comparator CMP2 is connected to the input end of the digital logic DIG circuit, and the output end of the digital logic DIG circuit is connected to the load capacitor array CAPARRAY in the voltage-controlled oscillator VCO, which is used to adjust the frequency of the voltage-controlled oscillator VCO; the output end of the voltage-controlled oscillator VCO constitutes the output end of the frequency locking and VCTRL clamping module, the power supply end of the voltage-controlled oscillator VCO is connected to the preset power supply voltage, and the ground end of the voltage-controlled oscillator VCO is grounded.

[0017] As a preferred technical solution of the present invention: the filter module includes a capacitor Cz, a capacitor Cp3, and a resistor R; wherein the upper plate of the capacitor Cp3 is connected to one end of the resistor R to form an internal node VRES, and serves as the input end of the filter module; the other end of the resistor R is connected to the upper plate of the capacitor Cz, and the relative end constitutes the output end of the filter module; the lower plate of the capacitor Cz is connected to the lower plate of the capacitor Cp3, and the connected end is grounded.

[0018] As a preferred technical solution of the present invention: the phase frequency detector and charge pump module includes a phase frequency detector PFD, a first current source A1, a second current source A2, and switches corresponding to the first current source A1 and the second current source A2 respectively; wherein one end of the first current source A1 is connected to a preset power supply voltage, the other end of the first current source A1 is connected in series with the switches corresponding to the first current source A1 and the second current source A2 respectively, and then connected to one end of the second current source A2, and the other end of the second current source A2 is grounded; the two input ends of the phase frequency detector PFD constitute the two input ends of the phase frequency detector and charge pump module, which are respectively used to access the reference clock REFCLK and the feedback clock FBCLK after the frequency division from the frequency divider; the two output ends of the phase frequency detector PFD are respectively connected to the switches corresponding to the first current source A1 and the second current source A2 in a one-to-one correspondence, for controlling each switch, and the connection position between the two switches constitutes the output end of the phase frequency detector and charge pump module.

[0019] The phase-locked loop circuit of the leakage compensation structure described in the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0020] The present invention designs a phase-locked loop circuit with a leakage compensation structure, adopts a brand-new structural design, includes a frequency detector and a charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module, and a frequency divider. The successive approximation method is used in combination with a matching loop control to offset the leakage current of the loop filter capacitor by leakage current monitoring, calibration, and compensation, thereby solving the leakage problem of the loop filter in the traditional phase-locked loop circuit. The present invention can be widely used in various phase-locked loops, provides a feasible solution for using low-voltage transistor-type capacitors with high capacitance density and leakage as loop filter capacitors, and can be used as an effective method to reduce the area and cost of the phase-locked loop. The leakage compensation method designed can overcome the changes in process angle and temperature, and calibrate the leakage mismatch. The entire circuit design is intuitive, the structure is simple, and it is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of an existing traditional phase-locked loop;

[0022] Figure 2 It is a schematic diagram of an existing leakage compensation structure;

[0023] Figure 3 It is a schematic diagram of an existing V2I leakage compensation circuit;

[0024] Figure 4 A schematic diagram of an existing dual charge pump leakage compensation;

[0025] Figure 5 This is a circuit diagram of a leakage compensation phase-locked loop according to the present invention;

[0026] Figure 6 This is a flow chart of the calibration algorithm corresponding to the phase-locked loop circuit of the present invention. DETAILED DESCRIPTION

[0027] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0028] The present invention designs a phase-locked loop circuit with a leakage compensation structure, such as Figure 5 As shown, it includes a frequency detector and charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module, and a divider.

[0029] Among them, one of the input ends of the frequency detector and charge pump module is used to access the reference clock REFCLK, the output end of the frequency detector and charge pump module is connected to the node VCTRL through the switch S1, and the node VCTRL is respectively connected to the input end of the filter module, one of the input ends of the successive approximation compensation capacitor module, and the input end of the frequency locking and VCTRL clamping module; the internal node VRES of the filter module constitutes the output end of the filter module, and the node VRES is respectively connected to the output end of the leakage monitoring compensation module and the other input end of the successive approximation compensation capacitor module; the output end of the successive approximation compensation capacitor module is connected to the input end of the leakage monitoring compensation module.

[0030] The output end of the frequency lock and VCTRL clamp module is connected to the input end of the frequency divider, and the output end of the frequency lock and VCTRL clamp module is used to provide the target circuit with adjusted frequency and phase; the output end of the frequency divider is connected to the other input end of the frequency detector and charge pump module, and the frequency divider provides the divided feedback clock FBCLK for the frequency detector and charge pump module.

[0031] like Figure 5As shown, the phase frequency detector and charge pump module includes a phase frequency detector PFD, a first current source A1, a second current source A2, and switches corresponding to the first current source A1 and the second current source A2 respectively; wherein one end of the first current source A1 is connected to a preset power supply voltage, the other end of the first current source A1 is connected in series with the switches corresponding to the first current source A1 and the second current source A2 respectively, and then connected to one end of the second current source A2, and the other end of the second current source A2 is grounded; the two input ends of the phase frequency detector PFD constitute the two input ends of the phase frequency detector and charge pump module, which are respectively used to access the reference clock REFCLK and the feedback clock FBCLK after the frequency division from the frequency divider; the two output ends of the phase frequency detector PFD are respectively connected to the switches corresponding to the first current source A1 and the second current source A2 in a one-to-one correspondence, for controlling each switch, and the connection position between the two switches constitutes the output end of the phase frequency detector and charge pump module.

[0032] like Figure 5 As shown, the filter module includes a capacitor Cz, a capacitor Cp3, and a resistor R; wherein the upper plate of the capacitor Cp3 is connected to one end of the resistor R to form an internal node VRES, and serves as the input end of the filter module; the other end of the resistor R is connected to the upper plate of the capacitor Cz, and the opposite end constitutes the output end of the filter module; the lower plate of the capacitor Cz is connected to the lower plate of the capacitor Cp3, and the connected end is grounded.

[0033] like Figure 5 As shown, the successive approximation compensation capacitor module includes a comparator CMP1, a successive approximation logic SAR, and a compensation capacitor array; wherein the negative input terminal of the comparator CMP1 constitutes one of the input terminals of the successive approximation compensation capacitor module, which is used to connect to the node VCTRL; the positive input terminal of the comparator CMP1 constitutes the other input terminal of the successive approximation compensation capacitor module, which is used to connect to the node VRES.

[0034] The compensation capacitor array includes a compensation capacitor Con, compensation capacitors C1 to Cn, and switches corresponding to the compensation capacitors C1 to Cn respectively, wherein the lower plates of the compensation capacitors C1 to Cn are respectively connected in series to the corresponding switches and then grounded, the lower plate of the compensation capacitor Con is directly grounded, the upper plate of the compensation capacitor Con is connected to the upper plates of the compensation capacitors C1 to Cn, and the connected end constitutes the output end of the successive approximation compensation capacitor module; the output end of the comparator CMP1 is connected to the input end of the successive approximation logic SAR, and the output end of the successive approximation logic SAR is respectively connected to the switches corresponding to the compensation capacitors C1 to Cn.

[0035] The ratio of the compensation capacitors C1 to Cn and the capacitor Cz in the filter module is 1:N, so that the leakage of the smaller capacitor can be amplified N times by the current mirror and then injected back into the capacitor Cz to save area. The leakage compensation capacitor array composed of the compensation capacitor Con and the compensation capacitors C1 to Cn and the capacitor Cz are composed of the same minimum unit and the layout is drawn together to save area. As a result, the leakage compensation capacitor can well track the process angle and temperature changes of the leakage of the capacitor Cz in the filter module to improve the leakage compensation accuracy.

[0036] The leakage monitoring and compensation module is as follows: Figure 5 As shown, it includes a current monitoring P-type transistor MP2, a current compensation P-type transistor MP1, and a voltage clamping operational amplifier OP; wherein, the drain of the current monitoring P-type transistor MP2 is connected to the positive input terminal of the voltage clamping operational amplifier OP, and the connection position between the two constitutes the input terminal of the leakage monitoring and compensation module; the negative input terminal of the voltage clamping operational amplifier OP is used to access the preset reference voltage VREF; the output terminal of the voltage clamping operational amplifier OP, the gate of the current monitoring P-type transistor MP2, and the gate of the current compensation P-type transistor MP1 are connected, the drain of the current compensation P-type transistor MP1 constitutes the output terminal of the leakage monitoring and compensation module, and the source of the current monitoring P-type transistor MP2 and the source of the current compensation P-type transistor MP1 are respectively connected to the preset power supply voltage.

[0037] Frequency locking and VCTRL clamping modules such as Figure 5 As shown, it includes a clamp comparator CMP2, a digital logic DIG circuit, and a voltage-controlled oscillator VCO; wherein, the negative input end of the clamp comparator CMP2 is used to access a preset reference voltage VREF, the positive input end of the clamp comparator CMP2 is connected to the voltage control frequency end of the voltage-controlled oscillator VCO, and the connected position constitutes the input end of the frequency locking and VCTRL clamping module; the output end of the clamp comparator CMP2 is connected to the input end of the digital logic DIG circuit, and the output end of the digital logic DIG circuit is connected to the load capacitor array CAP ARRAY in the voltage-controlled oscillator VCO, which is used to adjust the frequency of the voltage-controlled oscillator VCO; the output end of the voltage-controlled oscillator VCO constitutes the output end of the frequency locking and VCTRL clamping module, the power supply end of the voltage-controlled oscillator VCO is connected to the preset power supply voltage, and the ground end of the voltage-controlled oscillator VCO is grounded.

[0038] The leakage problem of loop filter capacitor seriously deteriorates the performance of the phase-locked loop. The leakage problem is difficult to handle mainly in two aspects. First, due to the limitations of chip manufacturing technology, the industry is forced to use capacitors with low capacitance density but small leakage as loop filter capacitors, which will result in low area utilization; second, after the phase-locked loop is locked, the control voltage value VCTRL of the voltage-controlled oscillator will change with process and environmental changes, and there is a nonlinear relationship between capacitor leakage and plate voltage, resulting in many variables affecting leakage, which is difficult to handle.

[0039] The main principle of the phase-locked loop circuit of the leakage compensation structure designed in the present invention is: Figure 5 As shown, firstly, the switch S1 is applied to disconnect the frequency detector and the charge pump from the node VCTRL, that is, the voltage of the node VCTRL is biased on the reference voltage VREF, the frequency lock and VCTRL clamping modules are turned on, and the frequency of the voltage-controlled oscillator VCO is adjusted by adjusting the CAP ARRAY, and the voltage drop (VCTRL-VRES) across the resistor R in the filter module is monitored at the same time. The leakage current of the loop filter capacitor Cz is directly reflected in the resistor voltage drop (VCTRL-VREF), the comparator CMP1 compares the VCTRL voltage and the VRES voltage, and adjusts the compensation capacitor array through the successive approximation logic, the leakage monitoring compensation module monitors the compensation capacitor array current and injects it back to the node VRES to compensate for the leakage of the capacitor Cz, and the capacitance of the compensation capacitor array is adjusted through the successive approximation logic. When the difference between the node VCTRL voltage and the node VRES voltage is the smallest, the optimal leakage compensation is achieved. After the capacitor array calibration is completed, close switch S1 to connect the frequency detector and the charge pump to the phase-locked loop for phase locking. At the same time, CMP2 remains on. By monitoring the voltage of the node VCTRL and dynamically adjusting the CAP ARRAY of the voltage-controlled oscillator VCO in real time, VCTRL is always kept near the reference voltage VREF, thereby avoiding the uncertainty of the capacitor Cz plate voltage in the filter changing with the process and temperature, so as to improve the accuracy of the leakage compensation current.

[0040] After the above capacitor array calibration is completed, the switch S1 is closed, and the phase detector and the charge pump are connected to the loop for phase locking. At the same time, the VCTRL clamp comparator CMP2 always monitors the VCTRL node voltage and dynamically adjusts the capacitor array CAP ARRAY of the voltage-controlled oscillator, so that the VCTRL voltage is always approximately equal to the VREF voltage after locking. By cooperating with the clamp op amp OP, not only can the matching degree between the current mirrors MP1 and MP2 be improved, but also the leakage current change of the capacitor Cz introduced by the change of the VCTRL node voltage can be reduced. In this way, the leakage current compensation accuracy is further improved, and the leakage compensation accuracy problem caused by the nonlinear relationship between the leakage and the capacitor plate voltage is solved.

[0041] The structure of the present invention realizes the compensation of the leakage current of the capacitor Cz in the filter module by replicating the leakage current of the capacitor Cz through the leakage current compensation capacitor array (C1 to Cn), and adjusting and calibrating the capacitor array by successive approximation logic, and the compensation capacitor array (C1 to Cn) and the filter capacitor are in a ratio of 1:N; the mirror ratio of MP1 and MP2 in the current monitoring compensation module is N:1, and the capacitors in the compensation capacitor array and the loop filter capacitor Cz are both composed of the same minimum capacitor unit module, and the layout is matched, so that the compensation capacitor array can maintain the same process angle offset and temperature coefficient as the loop filter capacitor, thereby improving the resistance to temperature and process angle changes of the leakage compensation, which solves the above-mentioned first aspect of the problem. By dynamically adjusting the load capacitor CAP ARRAY of the VCO in real time through the clamp comparator CMP2, the VCTRL voltage is always approximately equal to the VREF voltage, reducing the fluctuation of the capacitor leakage with the plate voltage, thereby reducing the nonlinear influence factors of the capacitor leakage current and the nonlinear influence factors of the current mirror image of the current monitoring compensation module, and improving the accuracy of the leakage current compensation, which solves the above-mentioned second aspect of the problem. The algorithm control of the three modes of specific frequency calibration, leakage calibration and phase locking is as follows Figure 6 It is noted that the capacitor Cz is the largest in the phase-locked loop filter module and occupies the main area, so the solution of the present invention performs leakage compensation for the capacitor Cz. By compensating the leakage of Cz, an effective solution is provided for the use of capacitors with high capacitance density but large leakage current in the phase-locked loop, which can reduce the area of ​​the phase-locked loop.

[0042] The phase-locked loop circuit with a leakage compensation structure designed by the above technical scheme adopts a brand-new structural design, including a frequency detector and charge pump module, a filter module, a leakage monitoring compensation module, a successive approximation compensation capacitor module, a frequency locking and VCTRL clamping module, and a divider. The successive approximation method is used in combination with the matching loop control to offset the leakage current of the loop filter capacitor through leakage current monitoring, calibration, and compensation, thereby solving the leakage problem of the loop filter in the traditional phase-locked loop circuit. The phase-locked loop circuit can be widely used in various phase-locked loops, and provides a feasible solution for low-voltage transistor-type capacitors with high capacitance density and leakage as loop filter capacitors, and can be used as an effective method to reduce the area and cost of the phase-locked loop. The leakage compensation method can overcome the changes in process angle and temperature and calibrate the leakage mismatch. The entire circuit design is intuitive, the structure is simple, and it is easy to implement.

[0043] The following describes the embodiments of the present invention in detail in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A phase-locked loop circuit with a leakage compensation structure, characterized in that: It includes frequency detector, charge pump module, filter module, leakage monitoring compensation module, successive approximation compensation capacitor module, frequency locking and VCTRL clamping module, and frequency divider; Among them, one of the input ends of the frequency detector and charge pump module is used to access the reference clock REFCLK, the output end of the frequency detector and charge pump module is connected to the node VCTRL through the switch S1, and the node VCTRL is respectively connected to the input end of the filter module, one of the input ends of the successive approximation compensation capacitor module, and the input end of the frequency locking and VCTRL clamping module; the internal node VRES of the filter module constitutes the output end of the filter module, and the node VRES is respectively connected to the output end of the leakage monitoring compensation module and the other input end of the successive approximation compensation capacitor module; the output end of the successive approximation compensation capacitor module is connected to the input end of the leakage monitoring compensation module; The output end of the frequency lock and VCTRL clamp module is connected to the input end of the frequency divider, and the output end of the frequency lock and VCTRL clamp module is used to provide the target circuit with the adjusted frequency and phase; the output end of the frequency divider is connected to the other input end of the frequency detector and charge pump module, and the frequency divider provides the divided feedback clock FBCLK for the frequency detector and charge pump module; The successive approximation compensation capacitor module includes a comparator CMP1, a successive approximation logic SAR, and a compensation capacitor array; wherein the negative input terminal of the comparator CMP1 constitutes one of the input terminals of the successive approximation compensation capacitor module, and is used to connect to the node VCTRL; the positive input terminal of the comparator CMP1 constitutes the other input terminal of the successive approximation compensation capacitor module, and is used to connect to the node VRES; the compensation capacitor array includes a compensation capacitor Con, compensation capacitors C1 to Cn, and switches corresponding to the compensation capacitors C1 to Cn, respectively, wherein the lower plates of the compensation capacitors C1 to Cn are connected in series with the corresponding switches and then grounded, the lower plate of the compensation capacitor Con is directly grounded, the upper plate of the compensation capacitor Con is connected to the upper plates of the compensation capacitors C1 to Cn, and the connected end constitutes the output terminal of the successive approximation compensation capacitor module; the output terminal of the comparator CMP1 is connected to the input terminal of the successive approximation logic SAR, and the output terminal of the successive approximation logic SAR is connected to the switches corresponding to the compensation capacitors C1 to Cn respectively; The leakage monitoring and compensation module includes a current monitoring P-type transistor MP2, a current compensation P-type transistor MP1, and a voltage clamping operational amplifier OP; wherein the drain of the current monitoring P-type transistor MP2 is connected to the positive input terminal of the voltage clamping operational amplifier OP, and the connection position between the two constitutes the input terminal of the leakage monitoring and compensation module; the negative input terminal of the voltage clamping operational amplifier OP is used to access the preset reference voltage VREF; the output terminal of the voltage clamping operational amplifier OP, the gate of the current monitoring P-type transistor MP2, and the gate of the current compensation P-type transistor MP1 are connected, the drain of the current compensation P-type transistor MP1 constitutes the output terminal of the leakage monitoring and compensation module, and the source of the current monitoring P-type transistor MP2 and the source of the current compensation P-type transistor MP1 are respectively connected to the preset power supply voltage; The frequency locking and VCTRL clamping module includes a clamping comparator CMP2, a digital logic DIG circuit, and a voltage controlled oscillator VCO; wherein, the negative input end of the clamping comparator CMP2 is used to access a preset reference voltage VREF, the positive input end of the clamping comparator CMP2 is connected to the voltage control frequency end of the voltage controlled oscillator VCO, and the connected position constitutes the input end of the frequency locking and VCTRL clamping module; the output end of the clamping comparator CMP2 is connected to the input end of the digital logic DIG circuit, and the output end of the digital logic DIG circuit is connected to the load capacitor array CAP ARRAY in the voltage controlled oscillator VCO, which is used to adjust the frequency of the voltage controlled oscillator VCO; the output end of the voltage controlled oscillator VCO constitutes the output end of the frequency locking and VCTRL clamping module, the power supply end of the voltage controlled oscillator VCO is connected to the preset power supply voltage, and the ground end of the voltage controlled oscillator VCO is grounded; The phase frequency detector and charge pump module includes a phase frequency detector PFD, a first current source A1, a second current source A2, and switches corresponding to the first current source A1 and the second current source A2 respectively; wherein one end of the first current source A1 is connected to a preset power supply voltage, the other end of the first current source A1 is connected in series with the switches corresponding to the first current source A1 and the second current source A2 respectively, and then connected to one end of the second current source A2, and the other end of the second current source A2 is grounded; the two input ends of the phase frequency detector PFD constitute the two input ends of the phase frequency detector and charge pump module, which are respectively used to access the reference clock REFCLK and the feedback clock FBCLK after the frequency division from the frequency divider; the two output ends of the phase frequency detector PFD are respectively connected to the switches corresponding to the first current source A1 and the second current source A2 in a one-to-one correspondence, for controlling each switch, and the connection position between the two switches constitutes the output end of the phase frequency detector and charge pump module.

2. A phase-locked loop circuit with a leakage compensation structure according to claim 1, characterized in that: The filter module includes a capacitor Cz, a capacitor Cp3, and a resistor R; wherein the upper plate of the capacitor Cp3 is connected to one end of the resistor R to form an internal node VRES, and serves as the input end of the filter module; the other end of the resistor R is connected to the upper plate of the capacitor Cz, and the connected end constitutes the output end of the filter module; the lower plate of the capacitor Cz is connected to the lower plate of the capacitor Cp3, and the connected end is grounded.

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