Controller for a memory component

Abstract

A controller for a memory component includes a processing unit and at least one memory unit coupled to the processing unit, the memory unit including at least a first region for storing user firmware and a second region for storing controller firmware; the processing unit configured to capture a memory address of a program instruction to be executed, compare the memory address to a reference value, and enable / restrict an action associated with the program instruction based on the comparison. A related memory component and a related method are also disclosed.

Description

Technical Field

[0001] This disclosure relates to memory devices, and more particularly, to a controller for memory components. Background Technology

[0002] Non-volatile flash memory is now a fundamental building block of modern electronic systems, especially real-time operating systems (RTOS). Generally, the operation of non-volatile flash memory is managed by a controller, including embedded firmware, which performs the necessary write / read / erase operations.

[0003] Flash memory's performance in terms of speed, power consumption, modifiability, non-volatility, and increasingly important system reconfigurability has driven its integration into system-on-a-chip (SoC) devices to date.

[0004] A System-on-a-Chip (SoC) is a semiconductor integrated circuit that integrates all the components of a computer or other electronic system. These components typically include a central processing unit (CPU), an SoC controller, a memory section, input / output ports, and secondary storage components, all of which reside on a single semiconductor substrate. Depending on the application, an SoC can contain digital, analog, mixed-signal, and commonly used radio frequency (RF) signal processing functions. Because these functions are integrated on a single electronic substrate, SoC devices consume significantly less power and occupy a much smaller area compared to multi-chip designs with equivalent functionality. SoC devices are now extremely common in mobile computing, embedded systems, and the Internet of Things (IoT).

[0005] When flash memory is coupled to the SoC, the SoC controller communicates and interacts with the flash memory controller, that is, it communicates and interacts with the controller of the flash memory.

[0006] Generally, in known solutions, such as the interaction between an external controller and a flash controller (e.g., the SoC controller) is limited to standard client commands, and access to the firmware embedded in the flash controller is not permitted. Therefore, the flash controller firmware is used only by the internal flash controller and is not accessible to users. Summary of the Invention

[0007] In one aspect, this application relates to a controller for a memory component, comprising: a processing unit; and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first region for storing user firmware and a second region for storing controller firmware; wherein the processing unit is configured to: capture a memory address of a program instruction to be executed; compare the memory address with a reference value; and enable / restrict actions associated with the program instruction based on the comparison.

[0008] In another aspect, this application relates to a memory component for a system-on-a-chip (SoC) architecture, the memory component including a flash memory array and a controller, the controller including: a processing unit; and at least one memory cell coupled to the processing unit, the memory cell including at least a first region for storing user firmware and a second region for storing controller firmware; wherein the processing unit of the controller is configured to: capture the memory address of a program instruction to be executed; compare the memory address with a reference value; and enable / restrict actions associated with the program instruction based on the comparison.

[0009] In another aspect, this application relates to a method comprising the steps of: storing user firmware in a first region of a memory cell and storing controller firmware in a second region of the memory cell; capturing the memory address of a program instruction to be executed; comparing the memory address with a reference value; and the comparison enabling / restricting actions associated with the program instruction.

[0010] In another aspect, this application relates to a method for initializing a memory controller comprising at least RAM and ROM, the ROM being divided into at least a first region and a second region, the method comprising: writing firmware into a portion of RAM using the JTAG protocol; invoking an API stored in the second region of the ROM; and moving the firmware to the first region of the ROM via the API. Attached Figure Description

[0011] Figure 1 A schematic perspective view of a system-on-a-chip device according to the prior art and including an embedded memory portion;

[0012] Figure 2 A schematic perspective view of a system-on-a-chip device according to the present disclosure, which includes an embedded memory portion that replaces a prior art device;

[0013] Figure 3 A schematic diagram of a memory component according to this disclosure;

[0014] Figure 4 The architecture of the controller for the memory component according to this disclosure is illustrated schematically;

[0015] Figure 5 Examples of instructions filtered by the controller according to this disclosure;

[0016] Figure 6A and 6B The diagram schematically illustrates access operations to a region of the ROM of the controller of this disclosure; and

[0017] Figure 7 The initialization of the user area of ​​the ROM of the controller of this disclosure is illustrated schematically.

[0018] Figure 8 A flowchart illustrating the method according to this disclosure is provided.

[0019] Figure 9 A flowchart illustrating another method according to this disclosure is provided. Detailed Implementation

[0020] Referring to those diagrams, this document discloses systems and methods relating to controllers for memory components (specifically including non-volatile memory).

[0021] More specifically, as will be described in detail below, the instance controller for the memory component includes a processing unit and at least one memory unit coupled to the processing unit. The memory unit includes at least a first region for storing user firmware and a second region for storing controller firmware. The processing unit is configured to: capture the memory address of a program instruction to be executed, the memory address being associated with the memory unit; compare the memory address with the reference value; and, based on the comparison, enable / disable (i.e., restrict) actions associated with the program instruction. Specifically, the controller for the memory component is configured to store certain information that can be shared with an external controller (e.g., a system-on-a-chip controller), while other stored information remains confidential and is not accessible to the user.

[0022] Furthermore, the example method according to this disclosure includes the following steps: storing user firmware in a first region of the memory cell and storing controller firmware in a second region of the memory cell, capturing the memory address of the program instruction to be executed, comparing the memory address with a reference value, and enabling / disabling (i.e. restricting) actions associated with the program instruction based on the comparison.

[0023] Non-volatile memory retains its contents when power is disconnected, making it a good choice for storing information that will be retrieved after a system reboot. However, non-volatile memory is generally slower than volatile memory and often has more complex write and erase procedures.

[0024] Flash memory is a type of non-volatile memory that retains stored data and is characterized by extremely fast access times. Furthermore, it can be erased in blocks, rather than one byte at a time. Each erasable memory block contains multiple non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating voltages on the access and data lines.

[0025] Currently, technologies using complex semiconductor structures known as system-on-a-chip (SoC) provide the integration of at least one embedded non-volatile memory up to 128 Mbit.

[0026] Figure 1 Examples of known solutions to a complex system-on-chip (SoC) architecture 100, including a large portion of circuitry occupied by a conventional embedded non-volatile memory portion 110, are presented.

[0027] This embedded non-volatile memory portion 110 includes Figure 1 The array of flash memory cells is indicated as e-flash array.

[0028] To read the memory cells of the array, a dedicated circuit section 130 is provided, including an optimized read finite state machine to ensure high read performance, such as branch prediction, fetch / prefetch, interrupt management, error correction, etc.

[0029] For writing to and erasing memory cells of the array, a dedicated logic circuit section 140 is provided, which includes a simplified reduced instruction set computer (RISC) controller or a modified finite state machine, the dedicated logic circuit section 140 being logic circuitry for processing programming and erasing algorithms.

[0030] like Figure 2 As shown in the diagram, according to this disclosure, the memory portion is removed from the SoC architecture (i.e., Figure 1 (Ref. 110 in the reference numerals) thus allows the corresponding semiconductor region to be used for other logic circuitry and to provide support for a structurally independent memory component 210 that partially overlaps with the SoC structure 200. This memory component 210 is scaled up to greater than 256 Mbit or even 512 Mbit. Generally, the memory component 210 has a variable size depending on the size of the memory array included therein, and is manufactured in the range of 128 Mbit to 512 Mbit or greater, depending on user requirements.

[0031] The removal of the embedded memory portion also has the significant advantage of freeing up space, thus enabling the semiconductor region 220 of the SoC structure 200 to achieve integration of additional user functions and / or a reduction in the overall SoC area.

[0032] The result of this solution is: Figure 2 The new SoC architecture is strictly associated with a new, structurally independent memory component 210, which is coupled to the SoC architecture 200, for example, through multiple coupling elements 230, such as pillars, and through through-silicon vias, ball grids, flip-chip technology, wireless interconnects (coils), etc. In one embodiment, the coupling element is a pillar, which is arranged in a space previously dedicated to... Figure 1 The embedded memory portion 110 is located in the semiconductor region 220.

[0033] In one embodiment of this disclosure, a memory component 210 for a SoC structure 200 includes at least a memory portion and a logic circuit portion for interacting with the memory portion and the SoC structure 200, wherein the memory component 210 is a structurally independent semiconductor device coupled to and partially overlapping with the system-on-a-chip structure 200. Logic circuitry 240 is integrated in the SoC structure 200 to cooperate with the logic circuitry portion of the memory component 210.

[0034] More generally, if the memory component 210 is smaller in size compared to the larger SoC structure 200, the term "partially overlapping" means that the memory component 210 only partially or not completely covers an area of ​​the SoC structure 200.

[0035] The coupling between the SoC structure 200 and the memory component 210 is achieved by interconnecting multiple corresponding pads or pin terminals facing each other in the circuit layout, and the pad alignment is maintained even if the size of the memory component 210 is modified.

[0036] In one embodiment of this disclosure, the pads of the memory component 210 are arranged on the surface of the memory component 210. More specifically, the pads are arranged above the array such that when the memory component 210 is flipped, its pads face the corresponding pads of the SoC structure 200. In the known system-on-a-chip device 100, a semiconductor region 220 occupied by the embedded non-volatile memory portion is dedicated to the housing of the interconnect pads corresponding to the pads of the memory component 210 and is also used for other circuitry.

[0037] Even larger memory components can be supported and interconnected by pads of the SoC structure 200, thereby maintaining the position and dislocation of its interconnect pads.

[0038] In the context of this disclosure, the SoC structure 200 links its top side to the inverted side of the memory component 210, with the pads of the SoC structure 200 aligned with the mating pads of the inverted memory component. Alternatively, the structurally independent memory component 210 can be wirelessly coupled to the SoC structure 200. If wireless coupling is used, stacked memory components of the same size can be overlapped to achieve a stacked structure, wherein each independent component is addressed by the logic circuitry of the SoC structure 200 via a corresponding identification address.

[0039] The semiconductor region 220, previously occupied by the embedded memory portion 110, is now used to implement additional functionality and to prepare a semiconductor device for on-pad logic technology. The term "on-pad logic" means providing a logic circuit system that overlaps with some internal connection pads to the first layer or base layer represented by the complete semiconductor product, i.e., the SoC structure 200.

[0040] Memory component 210 thus represents an upper layer coupled and interconnected to the substrate SoC structure 200. Memory component 210 partially overlaps with the SoC structure surface covering at least a semiconductor region 220 previously occupied by embedded memory portion 110. However, memory component 210 has a larger capacity capable of covering a semiconductor region larger than semiconductor region 220. In this respect, the size of the overlapping memory component 210 is larger than the size of the overlapping semiconductor region 220 dedicated to interconnecting with such overlapping memory component 210. In other words, the region of the overlapping memory component 210 is larger than the semiconductor region 220 of the SoC structure 200 dedicated to the interconnect pads of the memory component 210.

[0041] Furthermore, for better functionality of the SoC architecture 200, even Figure 1 The logic circuit section 140 (which is in) Figure 1 The SoC device 100 includes a modified finite state machine (or RISC) that can be removed and reassembled in association with the memory component 210. To support write and erase phases performed on the larger memory component 210, the modified finite state machine (or RISC) 240 has been migrated into the memory component 210.

[0042] As previously indicated, memory component 210 includes logic circuitry for interacting with the memory portion and with the SoC architecture 200.

[0043] The separation and optimization of the logic circuit section further allows for enhanced functionality of the entire SoC structure 200, thus obtaining an independent semiconductor memory component 210 coupled to the SoC structure 200.

[0044] This standalone semiconductor memory component 210 therefore includes at least a memory portion (e.g., a non-volatile memory portion) and an associated modified finite state machine 240, both incorporated into the semiconductor product coupled to the SoC architecture 200. In this case, the memory logic in the SoC architecture 200 is one that handles memory interface communication.

[0045] In other words, the non-volatile memory portion and the associated logic circuit portion are both integrated in a separate semiconductor memory component 210 coupled to and connected to the SoC structure 200.

[0046] Now, for more specific reference Figure 3 An example will be disclosed, which will reveal the main structure of the memory component 310 according to an embodiment of the present disclosure, wherein Figure 3 The number 310 and Figure 2 It corresponds to the number 210.

[0047] The memory component 310 includes at least: I / O circuitry, a microsequencer, a memory cell array 320, array peripherals, a charge pump architecture (including positive and negative pumps), an address decoder, a sense amplifier and corresponding latches, business logic connecting all parts of the memory, and a command and control user interface, such as a CUI block. The memory component communicates via multiple high-speed pads and multiple high / low-speed JTAG pads that prevent electrostatic discharge (ESD).

[0048] In one instance, the memory cell array 320 includes non-volatile flash memory cells.

[0049] In one embodiment of this disclosure, memory component 310 implements a direct memory access type of memory to replace the embedded memory array of a known SoC device.

[0050] Furthermore, the proposed idea provides a memory component 310 implemented in a "Known Good Die" (KGD) form factor or as a bare die, which allows the sense amplifier output to be directly connected to the controller of the SoC structure, except for an intermediate latch structure.

[0051] The strategy used to obtain KGD form factor has been based on testing and aging traditional packaged components using existing infrastructure. This minimizes the amount of hardware, tooling, or inserts that increase the cost of bare die products.

[0052] Furthermore, a JTAG interface is employed for testing the memory component 310, thereby allowing for the reuse of test tools. Therefore, the memory component 310 also includes JTAG logic.

[0053] The memory component 310 uses interconnect pads and logic circuit sections to allow interconnection with the SoC architecture.

[0054] The final configuration will be a face-to-face interconnect SoC / flash array, where, in a direct memory access configuration, the sense amplifier of memory component 310 will be connected to the SoC. The interconnect also includes a JTAG interface and control pins for testing and other purposes.

[0055] In this way, it is possible to keep the number of required interconnects relatively small, for example, in the range of 600 to 650 pads.

[0056] The memory array 320 of memory component 310 is constructed as a collection of subarrays. Scan chains can be connected to form unique shift registers for proper testing of interconnects.

[0057] The advantage of this architecture is its extreme scalability, where scaling up and / or reducing the density of the final device is achieved only by mirroring subarrays and generating connections.

[0058] Direct memory access allows for a reduction in the final latency that a SoC may experience when reading data.

[0059] According to this disclosure, the memory component 310 is equipped with a controller 300 (hereinafter referred to as the flash array controller) for the flash array 320, the flash array controller 300 having an architecture that allows sharing some flash array resources with the SoC controller without compromising the confidentiality of certain information stored therein (e.g., algorithms, flash array voltage, current, and more generally process information) and ensures end-customer return management.

[0060] Figure 4 This is a schematic diagram of the architecture of the controller 400 according to the present disclosure, wherein the controller 400 and Figure 3 The corresponding controller is 300.

[0061] The controller 400 includes a processing unit 410 and a memory unit 420 operatively connected to the processing unit 410.

[0062] According to embodiments of this disclosure, such as Figure 4 As shown, memory cell 420 is a read-only memory (ROM) in the form of a dedicated flash array, which is partially addressable (readable / writable) from outside the flash array controller 400, i.e. from outside the SoC controller, as will be described in detail below.

[0063] More specifically, the ROM comprises at least two distinct flash memory blocks logically mapped to a contiguous address space. In other words, the ROM is divided into a first region 420' and a second region 420' mapped to a contiguous address space, which are physically separate and independently erasable.

[0064] As in Figure 4 As shown, the processing unit 410 includes a control section 430 (also referred to as a ROM user area - RUA - watchdog) configured to allow the user to select regions of the ROM and to guide the user to access regions of the ROM, as described below.

[0065] According to embodiments of this disclosure, a user can write and store their own firmware in a first region 420' of the ROM. Therefore, the first region 420' contains the user firmware and is accessible by an external controller, such as the controller of the SoC.

[0066] On the other hand, the second region 420” is configured to store the flash array controller firmware (i.e., the internal controller firmware that manages the system's operation and is written by the manufacturer) and is not directly accessible to the user. The second region 420” can therefore only be written by the manufacturer, and the user cannot directly access it, nor can the user directly use or change the firmware embedded therein.

[0067] Due to the aforementioned separation of the first and second regions, the ROM of the controller 400 of this disclosure is therefore partially addressable (readable / writable) by the SoC controller.

[0068] In order to correctly identify which instruction of the user firmware should be retrieved for execution, the controller 400 includes a register that identifies which firmware instruction to retrieve and execute next; this register is commonly referred to as the program counter (PC).

[0069] The control section 430 of the processing unit 410 is connected to the program counter PC via the address bus, enabling it to capture the value of the program counter PC and read the memory address of the instruction to be executed, which is referred to herein as PC_addr.

[0070] Processing unit 410, specifically, control section 430, is then configured to compare the memory address received from the program counter PC with a reference value (or threshold address, hereinafter referred to as User_ADDR_limit) previously stored in processing unit 410. The reference value User_ADDR_limit may be set by the manufacturer as needed and / or as required.

[0071] According to embodiments of this disclosure, the reference value User_ADDR_limit is a ROM memory address that defines the first region 420' and the second region 420'. Preferably, the reference value User_ADDR_limit belongs to the first region 420' of the ROM and is a memory address at the separation point between the first region 420' and the second region 420' in the ROM.

[0072] Specifically, if the memory address PC_addr received from the program counter PC belongs to the first region 420' of the memory cell 420 (i.e., it is associated with the first region 420'), then the processing unit 410, specifically the control unit 430, generates a corresponding output signal that is adapted to disable the action associated with the instruction of the user firmware to be executed and corresponding to the memory address PC_addr, thus applying a restriction to the instruction of the user firmware.

[0073] In this way, controller 400 is able to recognize that the instruction to be executed is not an instruction written by the manufacturer's controller firmware, but an instruction of user firmware with a lower (or generally different) priority and therefore some restrictions, so that portions of the manufacturer's code in the second area 420” and other areas cannot be directly accessed by external users.

[0074] More specifically, the generated output signal is adapted to trigger a dedicated filter block of the controller 400, which is configured to act on instructions in the user firmware (e.g., on the destination address of such instructions) to prevent the execution of some actions associated with the instructions, thereby applying the restrictions indicated above to the instructions in the user firmware.

[0075] The output signal of the processing unit 410 is also referred to as the RUA signal below.

[0076] More specifically, in one embodiment of this disclosure, the RUA signal is generated by a state machine in processing unit 410. Such signals are assumed to be based on the different values ​​of the aforementioned comparison between memory address PC_addr and reference value User_ADDR_limit. For example, the RUA signal may be higher (e.g., equal to 1) when the memory address PC_addr associated with a user instruction is an address of a first region 420' of the ROM, and lower (i.e., equal to 0) when the memory address PC_addr is an address of a second first region 420" of the ROM.

[0077] In embodiments of this disclosure, the processing unit 410, specifically the control section 430, is configured to generate and confirm the RUA signal when the value of the program counter PC is less than or equal to the reference value User_ADDR_limit, i.e., when the program counter PC is within the ROM region shared with the external controller (i.e., within the first region 420' of the ROM). The control section 430 of the processing unit 410 is therefore configured to verify whether PC_addr ≤ User_ADDR_limit.

[0078] Therefore, the above comparison between the captured memory address PC_addr based on the program instructions and the reference value User_ADDR_limit may enable / disable actions associated with the program instructions of the user firmware, specifically thanks to the RUA signal generated by the processing unit 410.

[0079] As will be disclosed in more detail below, actions associated with program instructions in the user firmware may be, for example, access to a specific portion of the ROM, selection of a specific address in the RAM, or selection of a specific test register implemented in a memory component associated with the controller 400. Therefore, the aforementioned filter block, activated by the RUA signal (i.e., activated when PC_addr ≤ User_ADDR_limit), can identify and act on the specific target address of the instruction to prevent such actions.

[0080] According to one embodiment of this disclosure, the user firmware is able to use some subroutines of the controller firmware without having direct access to and understanding of the details of such subroutines.

[0081] Specifically, in order to interface the user firmware of the first region 420' with the controller firmware of the second region 420", the second region 420" of the memory unit 420 includes multiple application programming interfaces (APIs). According to embodiments of this disclosure, it is not possible to directly call the APIs of the second region 420" through the user firmware (i.e., directly from the first region 420'), so that some reserved information is not shared with the user. API calls are described below.

[0082] More specifically, the second region 420” of the ROM is further configured to store a plurality of call instructions that can be invoked by the user firmware, each of which is associated with a specific address of the second region 420”. The call instructions interrupt program flow by passing control to a subroutine of the controller firmware. In this way, the plurality of call instructions define a subregion 420sub within the second region 420” of the memory unit 420, which stores all necessary call instructions. The call instructions of this subregion 420sub are suitable for invoking all APIs contained in the second region 420” of the ROM, and therefore suitable for interfacing the user firmware of the first region 420’ with the subroutines of the controller firmware of the second region 420”.

[0083] The API in the second region 420” is written by the manufacturer and cannot be directly accessed or modified by the user. In this way, the user program in the first region 420’ can interact with the controller program in the second region 420” through the calling instructions of the sub-region 420sub without direct access to the latter.

[0084] Multiple call instructions in a sub-region 420sub of the second region 420" define an API lookup table in the second region 420" of the memory unit 420. This API lookup table is a set of call instructions suitable for implementing external user interfacing.

[0085] The address of the call instruction stored in the sub-region 420sub of the second region 420” of the ROM is contained between the memory address of the first region 420’ and the remaining addresses of the second region 420’, and the sub-region can be directly accessed by instructions from the user firmware.

[0086] More specifically, according to one embodiment of this disclosure, the sub-region 420sub containing the calling instruction is allocated on top of the second region 420", and the reference value User_ADDR_limit is the lowest address of the first region 420". In other words, the sub-region 420sub is the portion of the second region 420" represented by a higher address, even if other configurations are not excluded.

[0087] According to embodiments of this disclosure, the RUA signal generated by the processing unit 410 prevents the user firmware from directly calling API instructions in the second region 420” from the first region 420’. More specifically, if the API is directly called by the user firmware instructions, the control section 430 of the processing unit 410 captures the corresponding address PC_addr of the program counter PC and establishes its belonging to the first region 420’: therefore, an RUA signal is generated (e.g., the RUA signal equals 1), and the user is not allowed to directly call the API located in the second region 420”.

[0088] More specifically, according to embodiments of this disclosure, processing unit 410 is configured to implement a first filtering block 440, which acts on user program instructions based on an RUA signal. When an RUA signal is generated (e.g., the RUA signal equals 1), the first filtering block 440 is configured to mask parameters of the user firmware program instructions to prevent direct access to a second region of the memory cell, such as... Figure 5 As shown, some of these bits are forced to 0 (e.g., in...). Figure 5 (Those bits marked as "masking bits"). For example, when the RUA signal is equal to 1, instructions are filtered, thus masking the destination address of JMP and call instructions to prevent direct jumps to the internal controller flash memory area and setting valid numbers to 0. Therefore, further jumps / calls permitted by the controller architecture enter the API lookup table area, i.e., into sub-region 420sub.

[0089] On the other hand, if a user program instruction calls an API lookup table call instruction in sub-region 420sub, then control section 430 detects that PC_addr > User_ADDR_limit and no control output signal is generated (i.e., the RUA signal equals 0). Since the memory address is the address associated with the call instruction in sub-region 420sub under this condition, sub-region 420sub is a permitted region; the call instruction called by the user firmware in this way can call the API of the second region 420". Therefore, since the call instruction is called by an instruction in sub-region 420sub, it is executed without any restrictions, such as... Figure 6A and 6B As shown in the image. Figure 6A This explains the general principle, and Figure 6B This describes an instance where the first API out of multiple APIs is invoked by the corresponding caller in subregion 420sub. When a subroutine is invoked by the caller corresponding to a RUA signal equal to 0, all actions are therefore permitted. The invocation (and corresponding return) is thus a two-step process, and direct invocation is not allowed.

[0090] In this way, users can invoke the desired API of the second region 420" using the invocation instructions in the sub-region 420sub, and can perform related actions.

[0091] In summary, the API can be invoked by instructions stored in sub-region 420sub, i.e., by the internal controller flash memory region, which has a memory address between the reference value User_Addr_limit and another limit in the second region 420”, referred to herein as API_ADDR_limit. This invocation instruction is first invoked by instructions from the user firmware, i.e., by the user flash memory region. This has the advantages that the user can write their own firmware into the first region and interact with the controller's internal firmware in the second region while maintaining the confidentiality of certain information, thus providing a highly versatile and reliable controller.

[0092] Refer again Figure 4 According to embodiments of this disclosure, controller 400 further includes random access memory (RAM) 450, which includes a first RAM region 450' that can be directly accessed by user firmware (and therefore by an external controller such as a SoC controller) and a second RAM region 450" with different addresses. The first RAM region 450' is a stack pointer, where data is organized in a LIFO configuration, thereby allowing the execution of PUSH-POP instructions known in the art. Therefore, user access to this region is always allowed without any restrictions. The separate RAM address between the first RAM region 450' and the second RAM region 450" is hereinafter referred to as STACK_ADDR.

[0093] The second region 450 of RAM includes a first portion 451 that is not accessible to the user (accessible only by the manufacturer) and a second portion 452 that is accessible to the user under certain circumstances.

[0094] Specifically, when the processing unit 410 generates an output signal (i.e., when the RUA signal equals 1), the dedicated second filter block 460 (hereinafter referred to as R_Addr_filter) prevents the selection of all addresses for the second region 450” of RAM, and the second part 451 of this region is also not addressable. In this case, the user can control only the first region 450', i.e., the stack pointer region, through the PUSH / POP instructions.

[0095] In other words, if the user firmware program instruction is associated with a memory address belonging to the first region 420' of the ROM, then the processing unit 410 recognizes that the instruction does not have the required permission to access the portion 452 of RAM, and so that the second filter block 460, which receives at its input the address (indicated as ram_addr) of the portion of RAM that the user wants to access, masks the relevant parameters of the instruction to make this portion unaddressable.

[0096] However, if no output signal is generated (i.e., when the RUA signal equals 0), that is, when the API of the second region 420” is invoked by the appropriate calling instruction in the sub-region 420sub (which in turn is invoked by the user program instruction in the first region 420’), then all restrictions are removed for the specific instruction, and the user can access the second region 450” of the RAM, especially the second portion 452 of the second region of the RAM. In other words, the constraints on the RAM address are removed when the RAM is addressed by the API invoked by its appropriate caller.

[0097] Furthermore, according to embodiments of this disclosure, the controller includes an interface with multiple test registers (simply indicated as T_reg), each register being associated with a specific address (indicated as T_reg_addr) for testing the functionality of memory components associated with the controller 400, or generally for interfacing memory components with a test machine and / or an external controller.

[0098] The test mode architecture for the memory components is therefore based on these registers, which in some cases can be written / read by the SoC controller via the JTAG interface, by the test machine via the JTAG interface, and by the flash array controller 400 via the internal bus.

[0099] The test register T_reg contains instructions for testing memory components (e.g., parameters such as current / voltage).

[0100] Specifically, the test registers are organized in several libraries, each containing N registers (N = 8, 16, etc.) and associated with a specific address (hereinafter referred to as TL_addr). Each library also tends to drive one or more macro functions (analog or digital). For example, library 0 is dedicated to positive read charge pumps, and each bit of the library corresponds to a specific function (e.g., bit 0 = pump enabled, bits 5:1 = clock frequency, bits 7:6 = drive capability (maximum current)), while library 12 is dedicated to sense amplifiers.

[0101] Therefore, the testing of memory components is managed via a JTAG-based protocol using instructions in the test register T_reg. As previously observed, the testing can be controlled by the SoC controller or by an external test machine. In either case, both methods are based on a built-in self-test (BIST) performed by the internal flash array controller 400 of this disclosure. This method also keeps internal algorithms with sensitive technical parameters (such as timing voltages) confidential.

[0102] In order to allow the use of some test registers and disable access to other reserved test registers, according to an advantageous embodiment of this disclosure, controller 400 includes a third filter block 470 (also indicated as T_Addr filter).

[0103] In reality, not all test registers T_reg are accessible to external users, and the third filter block 470 is configured to disable access to some test registers T_reg based on the RUA signal generated by the processing unit 410. In this embodiment, the third filter block 470 is configured such that when the RUA signal is generated by the processing unit 410, some reserved registers are not addressable by masking a specific address, and the output of this third filter block 470 only generates the first enabled register T_reg.

[0104] The non-addressable test register T_reg is written into the configuration register by controller 400.

[0105] As previously observed, once the address captured from the program counter (PC) is within the second region 420" of the ROM (i.e., when PC_addr > User_ADDR_limit), the RUA signal equals 0 and all limits are removed. In other words, this register is not disabled and is available to external users when the test register T_reg is accessed by the appropriate caller API in subregion 420sub (however, it cannot be directly accessed by the user firmware). In this way, the user can access some registers without being able to directly write to / erase such registers, i.e., the user has indirect access to registers.

[0106] In one embodiment, some registers T_reg may never be accessed by the user firmware and may only be accessed by the manufacturer, who has the necessary permissions to perform specific test modes required by users who require such disabled registers.

[0107] According to embodiments of this disclosure, the processing unit 410 is also configured to receive at its input an additional signal that forces the control section 430 not to generate an RUA signal (i.e., its default setting is RUA = 0). For example, this additional signal, indicated herein as Force_RUA_low, is the output of one of a plurality of test registers T_reg, preferably a register that cannot be accessed by an external user (i.e., a register that can only be accessed in a higher-privilege test mode, which may be, for example, only by the manufacturer). In this case, all constraints are removed.

[0108] Figure 8 A flowchart illustrating method 800 according to this disclosure is provided. The method can be used to operate memory components, such as those referenced above. Figures 2 to 7 The memory component 210 or 310 is described.

[0109] Method 800 includes, at step 810, storing user firmware in a first region of the memory unit and controller firmware in a second region of the memory unit. For example, the user firmware may be freely stored in the first region of the memory unit, while the controller firmware may be stored in a second region of the memory unit that is inaccessible to the user, as described above.

[0110] Method 800 includes, at step 820, capturing the memory address of the program instructions to be executed. For example, this can be achieved by... (See reference...) Figure 4 The described processing unit 410 captures the memory address.

[0111] Method 800 includes comparing the memory address with a reference value at step 830.

[0112] Method 800 further includes, at step 840, enabling / restricting actions associated with program instructions based on the comparison. (See above reference) Figures 2 to 7 As described, the controller can perform the comparison and apply any enabling or limiting actions to the memory region.

[0113] Method 800 may further include the following steps: generating an output signal when the captured memory address of a program instruction is an address of a first region of a memory cell, the output signal restricting actions associated with instructions in the user firmware; triggering a filter block acting on instructions in the user firmware via the output signal to prevent actions associated with the instructions.

[0114] Method 800 may include the following steps: storing a plurality of application programming interfaces (APIs) in a second region of a memory cell; storing a plurality of invocation instructions in the second region of the memory cell, each of the invocation instructions being associated with a specific address of a sub-region defined in the second region; invoking the corresponding API in the second region via the invocation instructions and interfacing user firmware with controller firmware; and optionally masking parameters of the user program instructions to prevent the user program instructions in the first region from directly invoking the API stored in the second region.

[0115] Method 800 may further include the following steps: preventing the selection of a specific address in a second RAM region; preventing the selection of a specific test register adapted to interface a memory component with a test machine and / or an external controller; and / or identifying different users with different permissions and applying different constraints to actions associated with program instructions based on the permissions.

[0116] The steps in Method 800 do not require reporting in Figure 8 The order of execution is determined, and additional (unreported) steps can be performed.

[0117] Finally, refer to Figure 9 According to embodiments of this disclosure, an external controller (e.g., the controller of a SoC) cannot directly program the first region 420' of the ROM. The controller can then be programmed by a user via method 900, which includes: writing firmware into a portion of RAM using the JTAG protocol (step 910), specifically into a second portion 452 of the second RAM region 450", as shown below. Figure 7 As shown in the diagram. The method then includes calling an API stored in a second region 420' of the ROM (step 920), which is specifically dedicated to the user programming phase, and then moving the firmware to the first region 420' of the ROM where it is stored via this API (step 930). The API dedicated to user flash updates then erases and programs the firmware into the flash memory block. This operation is possible because the two flash memories are separated by a "well".

[0118] In summary, according to this disclosure, the disclosed controller enables users to write their own firmware into a dedicated ROM area and share some information for specific operations, while confidential information remains secret, as this confidential information is executed indirectly via an API lookup table, and some areas of the controller are inaccessible. More specifically, thanks to the RUA signal generated by the processing unit, it is possible to implement an "instruction filter" configured to filter some instructions of the user program to avoid CALL / JUMP outside the permitted area. During code execution from the user flash memory area (i.e., when RUA=1), certain constraints are thus applied to the reachable, RAM addressable, and T_REG and subsequently text-mode available code areas. Therefore, even if users are allowed to use some resources of the controller, they cannot directly access / write to the disabled areas of this controller.

[0119] This modified architecture ensures the controller of this disclosure has great versatility and allows users to use some functionality without directly accessing the disabled areas.

[0120] Furthermore, filters can be configured to apply different restrictions (e.g., different RAM regions, different constraints on T_reg, and different available APIs) to different users with different access rights. Specifically, the controller's filters can receive additional input considering a particular test pattern to be performed, each test pattern associated with a specific user with specific permissions, thus allowing the controller to apply different restrictions to different users, as indicated above. Therefore, it is possible to perform different test patterns with different permissions, and disable access to some regions of the controller based on such permissions.

[0121] In other words, filter blocks can be configured differently based on different users, who can be identified by the controller during authentication, and the controller can then configure the filters accordingly.

[0122] In the preceding detailed description, reference has been made to the accompanying drawings, which form part of the invention, and in which specific examples are illustrated by way of description. In the drawings, similar reference numerals describe generally similar components throughout several views. Other examples may be utilized, and structural, logical, and / or electrical changes may be made without departing from the scope of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the drawings are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0123] As used herein, “a (a / an)” or “several” something can refer to one or more of such things. “Several” something means two or more. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection without an intervening element (e.g., through direct physical contact), or indirect coupling and / or connection with an intervening element. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., causally related).

[0124] Although specific examples have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the above description has been made in an illustrative rather than restrictive manner. The scope of one or more examples of this disclosure should be determined by reference to the appended claims and the full scope of the equivalents conferred by such claims.

Claims

1. A controller for a memory component, comprising: - Processing unit; as well as - At least one memory unit coupled to the processing unit, the memory unit comprising at least a first region for storing user firmware and a second region for storing controller firmware; The processing unit is configured to: - The memory address that receives the program instructions to be executed; - Compare the memory address with the reference value; and - Based on the comparison, enable / restrict actions associated with the program instructions; and The memory component is coupled to the system-on-a-chip (SoC) architecture.

2. The controller of claim 1, wherein the reference value is a memory address of the memory cell that demarcates the first region and the second region, and wherein the processing unit is configured to generate an output signal when the memory address received by the program instruction is an address of the first region of the memory cell, the output signal being adapted to limit the action associated with the program instruction of the user firmware.

3. The controller of claim 2, wherein the output signal of the processing unit is adapted to trigger a filter block configured to act on the program instructions of the user firmware to prevent the action associated with the program instructions.

4. The controller according to any one of claims 1-3, wherein the memory unit is a read-only memory (ROM) physically separated into the first region and the second region, the first region and the second region being mapped to a contiguous address space.

5. The controller of claim 1, wherein the second region of the memory unit is configured to store a plurality of application programming interface (API) data.

6. The controller of claim 5, wherein the second region is further configured to store a plurality of invocation instructions, each of the invocation instructions being associated with a specific memory address of a sub-region defining the second region, and wherein each of the invocation instructions is adapted to invoke a corresponding API of the second region to interface the user firmware of the first region with the controller firmware of the second region.

7. The controller of claim 6, wherein the address of the invocation instruction stored in the sub-region of the second region is contained between the address of the first region and the remaining addresses of the second region.

8. The controller according to any one of claims 3 and 5, comprising a first filter block configured to mask parameters of the program instructions of the user firmware to prevent the program instructions of the user firmware in the first region from directly calling an API stored in the second region.

9. The controller of claim 1, further comprising random access memory (RAM), the RAM including at least a first RAM region directly accessible by the user firmware and a second RAM region having a RAM address different from the first RAM region.

10. The controller of claim 9, further comprising a second filtering block configured to prevent selection of a specific address of the second RAM region based on an output signal of the processing unit.

11. The controller of claim 1, comprising an interface having a plurality of test registers adapted to interface the memory component with a test machine and / or an external controller, each of the test registers being associated with a specific address.

12. The controller according to any one of claims 3 and 11, comprising a third filtering block configured to disable access to a specific test register.

13. The controller of claim 1, wherein the processing unit is configured to read the address of the program instruction to be executed from the program counter.

14. The controller of claim 4, wherein the processing unit is configured to receive a signal that forces the processing unit to remove all constraints on the program instructions.

15. The controller of claim 1, wherein the processing unit is configured to receive a signal that forces the processing unit to remove all constraints on the program instructions.

16. The controller of claim 3, wherein the filter block is configured to apply different restrictions to the actions associated with the program instructions for different users with different permissions.

17. A memory component, the memory component comprising: -Memory cell array; - A controller, coupled to the array and comprising: - Processing unit; and - At least one memory unit coupled to the processing unit, the memory unit comprising at least a first region for storing user firmware and a second region for storing controller firmware; The processing unit is configured to: - The memory address that receives the program instructions to be executed; - Compare the memory address with the reference value; and - Based on the comparison, enable / restrict actions associated with the program instructions; and The memory unit is a read-only memory (ROM) physically separated into a first region and a second region, and the first region and the second region are mapped to a contiguous address space.

18. A method for performing memory operations, comprising: - The user firmware is stored in a first region of the memory unit and the controller firmware is stored in a second region of the memory unit, wherein the memory unit is contained in a memory component; - The memory address that receives the program instructions to be executed; - Compare the memory address with the reference value; - Based on the comparison, enable / restrict actions associated with the program instructions, wherein restricting actions associated with the program instructions includes preventing the selection of a specific test register adapted to interface the memory component with a test machine and / or an external controller.

19. The method of claim 18, further comprising the step of: generating an output signal when the memory address of the program instruction is an address of the first region of the memory cell, the output signal limiting the action associated with the program instruction of the user firmware.

20. The method of claim 19, further comprising the step of: triggering a filter block of the program instructions acting on the user firmware via the output signal to block the action associated with the program instructions.

21. The method of claim 18, further comprising the following steps: -Storing multiple application programming interface (API) files in the second region of the memory unit; and - Storing multiple call instructions in the second region of the memory cell, each of the call instructions being associated with a specific address of a sub-region defining the second region; and - The corresponding API of the second region is invoked via the invocation instruction, and the user firmware is interfacing with the controller firmware.

22. The method of claim 21, further comprising the step of: masking parameters of the program instructions of the user firmware to prevent the program instructions of the user firmware in the first region from directly calling an API stored in the second region.

23. The method according to any one of claims 18-22, comprising the step of: preventing the selection of a specific address for the second region.

24. The method according to any one of claims 18-22, comprising identifying different users with different permissions, and applying different constraints to the actions associated with the program instructions according to the different permissions.

25. A method for initializing a memory controller comprising at least RAM and ROM, the ROM being divided into at least a first region and a second region, the method comprising: - Use the JTAG protocol to write the firmware into a portion of the RAM; - Call the API stored in the second area of ​​the ROM; - Move the firmware to the first region of the ROM via the API.

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