Image pickup element, stacked image pickup element, and solid-state image pickup device

Abstract

The imaging element disclosed herein includes a photoelectric conversion unit, which includes a stacked first electrode (21), a photoelectric conversion layer (23A) and a second electrode (22), wherein a protective layer (23B) and an inorganic oxide semiconductor material layer (23C) are formed directly below the photoelectric conversion layer (23A) from the photoelectric conversion layer side, and the protective layer (23B) includes an inorganic oxide.

Description

Technical Field

[0001] The present disclosure relates to an imaging element, a stacked imaging element, and a solid-state imaging device. Background Art

[0002] In recent years, stacked imaging elements have attracted considerable attention as imaging elements in image sensors and other applications. These elements have a structure in which a photoelectric conversion layer (light-receiving layer) is sandwiched between two electrodes. Furthermore, stacked imaging elements require a structure for accumulating and transmitting the signal charge generated in the photoelectric conversion layer based on photoelectric conversion. Among currently available structures, a mechanism for accumulating and transmitting the signal charge to an FD (Floating Drain) electrode is required, and high-speed transmission is required to avoid signal charge delays.

[0003] For example, Japanese Unexamined Patent Application Publication No. 2016-063165 discloses an imaging element (photoelectric conversion element) for solving such a problem.

[0004] The imaging element comprises:

[0005] an accumulation electrode formed on the first insulating layer;

[0006] a second insulating layer formed on the accumulation electrode;

[0007] a semiconductor layer formed so as to cover the accumulation electrode and the second insulating layer;

[0008] a collecting electrode formed in contact with the semiconductor layer and separated from the accumulating electrode;

[0009] a photoelectric conversion layer formed on the semiconductor layer; and

[0010] An upper electrode is formed on the photoelectric conversion layer.

[0011] An imaging element using an organic semiconductor material for its photoelectric conversion layer is capable of photoelectric conversion for specific colors (wavelength bands). This characteristic allows it to be used in solid-state imaging devices, resulting in a structure comprising stacked sub-pixels (a stacked imaging element), which is difficult to achieve with existing solid-state imaging devices. In this structure, the sub-pixels are formed by a combination of an on-chip color filter layer (OCCF) and the imaging element, and are arranged in a two-dimensional pattern (see, for example, Japanese Unexamined Patent Application Publication No. 2011-138927). Furthermore, since demosaicing is not required, this imaging element has the advantage of not generating false colors. In the following description, in some cases, for convenience, an imaging element including a photoelectric conversion unit arranged on or above a semiconductor substrate is referred to as a "first type imaging element"; for convenience, the photoelectric conversion unit included in the first type imaging element is referred to as a "first type photoelectric conversion unit"; for convenience, an imaging element arranged in a semiconductor substrate is referred to as a "second type imaging element"; for convenience, the photoelectric conversion unit included in the second type imaging element is referred to as a "second type photoelectric conversion unit".

[0012] Figure 72 An example of the structure of a conventional stacked image pickup element (stacked solid-state image pickup device) is shown. Figure 72 In the illustrated example, a third photoelectric converter 343A and a second photoelectric converter 341A are stacked and formed on a semiconductor substrate 370. The third photoelectric converter 343A and the second photoelectric converter 341A are second-type photoelectric converters and are included in the third imaging element 343 and the second imaging element 341, which are second-type imaging elements. Furthermore, a first photoelectric converter 310A, which is a first-type photoelectric converter, is arranged above the semiconductor substrate 370 (specifically, above the second imaging element 341). The first photoelectric converter 310A includes a first electrode 321, a photoelectric conversion layer 323 containing an organic material, and a second electrode 322. The first photoelectric converter 310A is included in the first imaging element 310, which is a first-type imaging element. Due to differences in absorption coefficients, the second photoelectric converter 341A and the third photoelectric converter 343A perform photoelectric conversion on, for example, blue light and red light, respectively. Furthermore, the first photoelectric converter 310A performs photoelectric conversion on, for example, green light.

[0013] Charge generated by photoelectric conversion in the second photoelectric converter 341A and the third photoelectric converter 343A is temporarily accumulated in the second photoelectric converter 341A and the third photoelectric converter 343A. A vertical transistor (gate portion 345 is shown) and a transfer transistor (gate portion 346 is shown) then transfer the charge to the second floating diffusion layer (Floating Diffusion) FD2 and the third floating diffusion layer FD3, respectively, and further output the charge to an external readout circuit (not shown). These transistors and the floating diffusion layers FD2 and FD3 are also formed in the semiconductor substrate 370.

[0014] Charge generated by photoelectric conversion in the first photoelectric conversion unit 310A is accumulated in the first floating diffusion layer FD1 formed in the semiconductor substrate 370 via the contact hole 361 and the wiring layer 362. Furthermore, the first photoelectric conversion unit 310A is also connected to the gate portion 352 of the amplifier transistor for converting charge into voltage via the contact hole 361 and the wiring layer 362. Furthermore, the first floating diffusion layer FD1 constitutes part of the reset transistor (gate portion 351 is shown). Reference numeral 371 denotes an element isolation region. Reference numeral 372 denotes an insulating material film formed on the surface of the semiconductor substrate 370. Reference numerals 376 and 381 denote interlayer insulating layers. Reference numeral 383 denotes a protective material layer. Reference numeral 314 denotes an on-chip microlens.

[0015] Citation list

[0016] Patent Literature

[0017] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2016-063165

[0018] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2011-138927

[0019] Patent Document 3: Japanese Unexamined Patent Application Publication (published Japanese translation of PCT application) No. 2016-502278 Summary of the Invention

[0020] Problems to be solved by the present invention

[0021] However, the technology disclosed in the aforementioned Japanese Unexamined Patent Application No. 2016-63165 has the following limitations: the accumulation electrode and the second insulating layer formed on the accumulation electrode must be formed to the same length, and the gap between the accumulation electrode and the collection electrode must be precisely specified, which may complicate the manufacturing process and may lead to a decrease in manufacturing yield. In addition, some materials constituting the semiconductor layer are mentioned, but the specific composition and structure of these materials are not described. In addition, the correlation expression between the carrier mobility of the semiconductor layer and the accumulated charge is mentioned, but there is no mention of matters related to improving the transport of charge, such as the relationship between the energy level of the region adjacent to the photoelectric conversion layer, which is important for the transport of the generated charge. In addition, regarding energy levels, in the thin film transistor disclosed in Japanese Unexamined Patent Application Publication (published Japanese translation of PCT application) No. 2016-502278, it is mentioned that the energy level of the conduction band of the metal oxide semiconductor included in the channel is equal to the energy level of the conduction band of the passivation material stacked on the channel, or is only less than 0.5 eV higher, but there is no mention of matters related to improving the transport of charges.

[0022] Therefore, an object of the present disclosure is to provide an image pickup element, a stacked image pickup element, and a solid-state image pickup device that are excellent in transfer characteristics of charges accumulated in a photoelectric conversion layer despite having a simple configuration and structure.

[0023] Technical solutions to the problem

[0024] To achieve the above-mentioned object, the imaging element of the present disclosure includes a photoelectric conversion section including a first electrode, a photoelectric conversion layer, and a second electrode stacked together, wherein:

[0025] Directly below the photoelectric conversion layer, a protective layer and an inorganic oxide semiconductor material layer are formed from the photoelectric conversion unit side, the protective layer including an inorganic oxide.

[0026] To achieve the above-mentioned object, a stacked image pickup element of the present disclosure includes at least one image pickup element of the present disclosure.

[0027] A solid-state imaging device according to a first aspect of the present disclosure for achieving the above-mentioned object includes a plurality of the above-mentioned imaging elements. A solid-state imaging device according to a second aspect of the present disclosure for achieving the above-mentioned object includes a plurality of the above-mentioned stacked imaging elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic partial cross-sectional view of the image pickup element of Example 1.

[0029] Figure 2 This is an equivalent circuit diagram of the imaging element of Example 1.

[0030] Figure 3 This is an equivalent circuit diagram of the imaging element of Example 1.

[0031] Figure 4 This is a schematic layout diagram of a first electrode and a charge accumulation electrode included in the image sensor of Example 1, and a transistor included in the control section.

[0032] Figure 5 The potential states at various locations during operation of the image pickup element of Example 1 are schematically shown.

[0033] Figure 6A 、 Figure 6B and Figure 6C Is used to illustrate Figure 5 (Example 1), Figure 20 and Figure 21 (Example 4) and Figure 32 and Figure 33 (Example 6) Equivalent circuit diagram of each part of the imaging element of Example 1, Example 4 and Example 6.

[0034] Figure 7 This is a schematic layout diagram of the first electrode and the charge accumulation electrode included in the image sensor of Example 1.

[0035] Figure 8 This is a schematic perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion included in the image sensor of Example 1.

[0036] Figure 9 This is an equivalent circuit diagram of a modified example of the imaging element of Example 1.

[0037] Figure 10 yes Figure 9 Schematic layout diagram of a first electrode and a charge storage electrode included in a modification of the imaging element of Example 1, and a transistor included in a control unit.

[0038] Figure 11 This is a schematic partial cross-sectional view of the imaging element of Example 2.

[0039] Figure 12 This is a schematic partial cross-sectional view of the imaging element of Example 3.

[0040] Figure 13 This is a schematic partial cross-sectional view of a modified example of the imaging element of Example 3.

[0041] Figure 14 This is a schematic partial cross-sectional view of another modified example of the imaging element of Example 3.

[0042] Figure 15 This is a schematic partial cross-sectional view of still another modified example of the imaging element of Example 3.

[0043] Figure 16 This is a schematic partial cross-sectional view of a portion of the imaging element of Example 4.

[0044] Figure 17 This is an equivalent circuit diagram of the imaging element of Example 4.

[0045] Figure 18 This is an equivalent circuit diagram of the imaging element of Example 4.

[0046] Figure 19 This is a schematic layout diagram of a first electrode, a transfer control electrode, a charge accumulation electrode included in the image sensor of Example 4, and a transistor included in the control section.

[0047] Figure 20 The potential states at various locations during operation of the image pickup element of Example 4 are schematically shown.

[0048] Figure 21 The potential states at various locations during another operation of the image pickup element of Example 4 are schematically shown.

[0049] Figure 22 This is a schematic layout diagram of a first electrode, a transfer control electrode, and a charge accumulation electrode included in the image sensor of Example 4.

[0050] Figure 23 This is a schematic perspective view of a first electrode, a transfer control electrode, a charge storage electrode, a second electrode, and a contact hole portion included in the image sensor of Example 4.

[0051] Figure 24 This is a schematic layout diagram of a first electrode, a transfer control electrode, a charge storage electrode, and a transistor included in a control unit in a modification of the imaging element of Example 4.

[0052] Figure 25 This is a schematic partial cross-sectional view of a portion of the imaging element of Example 5.

[0053] Figure 26 This is a schematic layout diagram of a first electrode, a charge accumulation electrode, and a charge discharge electrode included in the image sensor of Example 5.

[0054] Figure 27 This is a schematic perspective view of a first electrode, a charge storage electrode, a charge discharge electrode, a second electrode, and a contact hole portion included in the image sensor of Example 5.

[0055] Figure 28 This is a schematic partial cross-sectional view of the imaging element of Example 6.

[0056] Figure 29 This is an equivalent circuit diagram of the imaging element of Example 6.

[0057] Figure 30 This is an equivalent circuit diagram of the imaging element of Example 6.

[0058] Figure 31 This is a schematic layout diagram of a first electrode and a charge accumulation electrode included in the image sensor of Example 6, and a transistor included in the control unit.

[0059] Figure 32 The potential states at various locations during operation of the image pickup element of Example 6 are schematically shown.

[0060] Figure 33 The potential states at various locations during another operation period (transfer period) of the image pickup element of Example 6 are schematically shown.

[0061] Figure 34 This is a schematic layout diagram of the first electrode and the charge accumulation electrode included in the image sensor of Example 6.

[0062] Figure 35 This is a schematic perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion included in the image sensor of Example 6.

[0063] Figure 36 This is a schematic layout diagram of the first electrode and the charge storage electrode included in a modification of the imaging element of Example 6.

[0064] Figure 37 This is a schematic cross-sectional view of a portion of the imaging element of Example 7 (two imaging elements arranged side by side).

[0065] Figure 38 This is a schematic layout diagram of the first electrode, the charge accumulation electrode, and the like included in the imaging element of Example 7, and the transistor included in the control unit.

[0066] Figure 39 This is a schematic layout diagram of the first electrode, the charge accumulation electrode, and the like included in the imaging element of Example 7.

[0067] Figure 40 This is a schematic layout diagram of a modified example of the first electrode, the charge storage electrode, and the like included in the imaging element of Example 7.

[0068] Figure 41This is a schematic layout diagram of a modified example of the first electrode, the charge storage electrode, and the like included in the imaging element of Example 7.

[0069] Figure 42A and Figure 42B This is a schematic layout diagram of a modified example of the first electrode, the charge storage electrode, and the like included in the imaging element of Example 7.

[0070] Figure 43 This is a schematic cross-sectional view of a portion of the imaging element of Example 8 (two imaging elements arranged side by side).

[0071] Figure 44 This is a schematic plan view of a portion of the imaging element of Example 8 (2×2 imaging elements arranged side by side).

[0072] Figure 45 This is a schematic plan view of a portion of a modified example of the imaging element of Example 8 (2×2 imaging elements arranged side by side).

[0073] Figure 46A and Figure 46B This is a schematic cross-sectional view of a portion of a modified example of the imaging element of Example 8 (two imaging elements arranged side by side).

[0074] Figure 47A and Figure 47B This is a schematic cross-sectional view of a portion of a modified example of the imaging element of Example 8 (two imaging elements arranged side by side).

[0075] Figure 48A and Figure 48B This is a schematic plan view of a portion of a modified example of the imaging element of Example 8.

[0076] Figure 49A and Figure 49B This is a schematic plan view of a portion of a modified example of the imaging element of Example 8.

[0077] Figure 50 1 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a solid-state imaging device according to a ninth embodiment.

[0078] Figure 51 1 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a first modification of the solid-state imaging device of Example 9.

[0079] Figure 52 1 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a second modification of the solid-state imaging device of Example 9.

[0080] Figure 531 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a third modification of the solid-state imaging device of Example 9.

[0081] Figure 54 1 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a fourth modification of the solid-state imaging device of Example 9.

[0082] Figure 55 1 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a fifth modification of the solid-state imaging device of Example 9.

[0083] Figure 56 1 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a sixth modification of the solid-state imaging device of Example 9.

[0084] Figure 57 1 is a schematic plan view of a first electrode and a charge accumulation electrode segment in a seventh modification of the solid-state imaging device of Example 9.

[0085] Figure 58A 、 Figure 58B and Figure 58C : is a diagram showing an example of readout driving in the image pickup element block of Example 9.

[0086] Figure 59 10 is a schematic plan view of a first electrode and a charge accumulation electrode segment in the solid-state imaging device of Example 10.

[0087] Figure 60 10. This is a schematic plan view of a first electrode and a charge accumulation electrode segment in a modified example of the solid-state imaging device of Example 10.

[0088] Figure 61 10. This is a schematic plan view of a first electrode and a charge accumulation electrode segment in a modified example of the solid-state imaging device of Example 10.

[0089] Figure 62 10. This is a schematic plan view of a first electrode and a charge accumulation electrode segment in a modified example of the solid-state imaging device of Example 10.

[0090] Figure 63 This is a schematic partial cross-sectional view of still another modified example of the imaging element of Example 1 and the stacked imaging element.

[0091] Figure 64 This is a schematic partial cross-sectional view of still another modified example of the imaging element of Example 1 and the stacked imaging element.

[0092] Figure 65 This is a schematic partial cross-sectional view of still another modified example of the imaging element of Example 1 and the stacked imaging element.

[0093] Figure 66 This is a schematic partial cross-sectional view of the imaging element of Example 1 and another modified example of the stacked imaging element.

[0094] Figure 67 This is a schematic partial cross-sectional view of still another modified example of the imaging element of Example 4.

[0095] Figure 68 This is a conceptual diagram of the solid-state imaging device of Example 1.

[0096] Figure 69 This is a conceptual diagram of an example in which a solid-state imaging device including an imaging element and a stacked imaging element according to the present disclosure is used in an electronic device (camera).

[0097] Figure 70 It is a conceptual diagram of the energy arrangement of the present disclosure.

[0098] Figure 71A and Figure 71B They are respectively graphs showing the operating results of a bottom-gate thin film transistor used for testing, wherein a protective layer and an inorganic oxide semiconductor material layer are stacked in Example 1 and the protective layer and the inorganic oxide semiconductor material layer are used as a channel formation region, and graphs showing the operating results of a bottom-gate thin film transistor without a protective layer used for comparative testing, wherein the inorganic oxide semiconductor material layer is used as a channel formation region.

[0099] Figure 72 This is a conceptual diagram of a conventional stacked imaging element (stacked solid-state imaging device).

[0100] Figure 73 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0101] Figure 74 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0102] Figure 75 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0103] Figure 76 : is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU: camera control unit). DETAILED DESCRIPTION

[0104] Hereinafter, with reference to the accompanying drawings, the present disclosure will be described based on embodiments. However, the present disclosure is not limited to the embodiments, and the various numerical values ​​and materials in the embodiments are illustrative. It should be noted that the description will be given in the following order.

[0105] 1. General Description of the Image Pickup Element of the Present Disclosure, the Stacked Image Pickup Element of the Present Disclosure, and the Solid-State Image Pickup Devices According to the First and Second Aspects of the Present Disclosure

[0106] 2. Example 1 (Image pickup element of the present disclosure, stacked image pickup element of the present disclosure, and solid-state image pickup device according to the second aspect of the present disclosure)

[0107] 3. Example 2 (Variation of Example 1)

[0108] 4. Embodiment 3 (Variation of Embodiments 1 and 2, Solid-State Image Capturing Device According to the First Aspect of the Present Disclosure)

[0109] 5. Example 4 (Variation of Examples 1 to 3, Imaging Element Including Transfer Control Electrodes)

[0110] 6. Example 5 (Variation of Examples 1 to 4, Imaging Element Including Charge Discharge Electrode)

[0111] 7. Example 6 (Variation of Examples 1 to 5, Imaging Element Including Multiple Charge Accumulation Electrode Segments)

[0112] 8. Example 7 (Variation of Examples 1 to 6, Imaging Element Including Charge Transfer Control Electrode)

[0113] 9. Example 8 (Variation of Example 7)

[0114] 10. Example 9 (Solid-state imaging devices of the first and second structures)

[0115] 11. Example 10 (Variation of Example 9)

[0116] 12. Others

[0117] <General Description of the Image Pickup Element of the Present Disclosure, the Stacked Image Pickup Element of the Present Disclosure, and the Solid-State Image Pickup Devices According to the First and Second Aspects of the Present Disclosure>

[0118] In the imaging element of the present disclosure, the imaging element of the present disclosure included in the stacked imaging element of the present disclosure, and the imaging element of the present disclosure included in the solid-state imaging device according to any one of the first and second aspects of the present disclosure (hereinafter collectively referred to as "the imaging element of the present disclosure, etc." in some cases), the oxygen vacancy formation energy (energy required to form oxygen vacancies) of the metal atoms included in the protective layer is preferably 5 eV or more (or, in other cases, 4.5 eV or more). In addition, in these cases, it is preferable to satisfy the following:

[0119] E OD-1 -E OD-2 ≥1eV

[0120] Among them, E OD-1 represents the oxygen vacancy formation energy of the metal atoms included in the protective layer, E OD-2 represents the oxygen vacancy formation energy of the metal atoms included in the inorganic oxide semiconductor material layer. In addition, in these cases, preferably, the oxygen vacancy formation energy E of the metal atoms included in the inorganic oxide semiconductor material layer is OD-2 It is 3 eV or more, preferably 4 eV or more. It should be noted that when the protective layer or the inorganic oxide semiconductor material layer includes multiple metal atoms, the "oxygen vacancy formation energy of the metal atom" refers to the average value of the oxygen vacancy formation energies of the multiple metal atoms. The higher the value of the oxygen vacancy formation energy, the more difficult it is for the oxygen atom to desorb and the more difficult it is to bind to oxygen atoms, oxygen molecules or other atoms or molecules, and therefore it can be said to be stable. For example, the oxygen vacancy formation energy can be determined based on first principle calculations.

[0121] In the imaging element and the like of the present disclosure including the above-mentioned preferred embodiment, when the vacuum level is used as a zero reference and the absolute value of energy (the sign of the value is negative) is defined as increasing as the distance from the vacuum level increases, it is preferable to satisfy the following:

[0122] E0≥E1,

[0123] Ideally,

[0124] E0-E1≥0.1(eV),

[0125] More ideally,

[0126] E0-E1>0.1(eV)

[0127] Wherein, E0 represents the LUMO value of the photoelectric conversion layer (see Figure 70 The energy average value of "A" in the figure, E1 represents the maximum energy value of the conduction band of the protective layer (see Figure 70 In addition, it is preferred to satisfy:

[0128] E1-E2≥0.1(eV)

[0129] Furthermore, it is more preferred that:

[0130] E1-E2>0.1(eV)

[0131] Wherein, E2 represents the maximum energy value of the conduction band of the inorganic oxide semiconductor material layer (see Figure 70The energy average value in the "C" in the protective layer and the inorganic oxide semiconductor material layer). The energy average values ​​E1 and E2 in the maximum energy values ​​of the conduction bands of the protective layer and the inorganic oxide semiconductor material layer are average values ​​in the protective layer and the inorganic oxide semiconductor material layer. In addition, the energy average value E0 in the LUMO value of the photoelectric conversion layer is the average value of the portion of the photoelectric conversion layer located near the protective layer. Here, "the portion of the photoelectric conversion layer located near the protective layer" refers to the portion of the photoelectric conversion layer located in the area corresponding to within 10% of the thickness of the photoelectric conversion layer (that is, the area extending from 0% to 10% of the thickness of the photoelectric conversion layer) based on the interface between the protective layer and the photoelectric conversion layer. In addition, "minimum energy" means that the absolute value of the energy value is the smallest, and "maximum energy" means that the absolute value of the energy value is the largest. This also applies to the following description.

[0132] The energy of the valence band and the value of HOMO (highest occupied molecular orbital) can be obtained based on, for example, ultraviolet photoelectron spectroscopy (UPS method). Alternatively, the energy of the valence band and the value of HOMO (highest occupied molecular orbital) can be obtained based on {(energy of the valence band, value of HOMO) + E b} to find the conduction band energy and LUMO value. In addition, the band gap energy E can be found based on the following expression according to the light absorption wavelength λ (light absorption edge wavelength, unit is nm): b :

[0133] E b =hν=h(c / λ)=1239.8 / λ[eV].

[0134] Furthermore, in the imaging element and the like of the present disclosure including the above-mentioned preferred embodiment, it is preferable that the protective layer includes Nb a Ti b O c (wherein a+b+c=1.00), and in this case, it is more preferred to satisfy 0.05≤a≤0.25 and 0.05≤b≤0.25. The values ​​a, b, and c are values ​​corresponding to atomic percentages. The protective layer may include metal atoms, such as aluminum (Al), silver (Ag), and copper (Cu). The composition of the protective layer and the inorganic oxide semiconductor material layer can be determined based on, for example, ICP emission spectroscopy (high-frequency inductively coupled plasma atomic emission spectroscopy, ICP-AES) or X-ray photoelectron spectroscopy (XPS). In the formation process of the protective layer and the inorganic oxide semiconductor material layer, in some cases, hydrogen or other metals, or other impurities such as metal compounds may be mixed in; however, as long as the amount of impurities mixed in is very small (for example, the molar fraction is 3% or less), the mixing of impurities is acceptable.

[0135] In addition, in the imaging element of the present disclosure including the above-mentioned preferred form, a form in which a protective layer prevents hydrogen from entering the inorganic oxide semiconductor material layer can be adopted. By preventing hydrogen from entering the inorganic oxide semiconductor material layer, oxygen atoms in the inorganic oxide semiconductor material layer can be extracted, and the formation of oxygen vacancies can be suppressed, and an inorganic oxide semiconductor material layer with stable characteristics can be obtained. It should be noted that the hydrogen that may enter the inorganic oxide semiconductor material layer exists in the photoelectric conversion layer or exists in the manufacturing process of the imaging element. For the hydrogen suppression ability of the protective layer by thermal desorption spectroscopy (TDS method, thermal desorption spectroscopy), when the intensity ratio of heated titanium detected when heated to 350°C measured using the TDS method is 1.0, the relative intensity ratio of hydrogen ions detected when heated to 350°C measured using the TDS method is preferably less than 0.1. In thermal desorption spectroscopy, the sample is heated in a vacuum, and the partial pressure of hydrogen to be desorbed is measured, so that the relationship between the desorption rate of hydrogen and the sample temperature can be determined. Specifically, a sample is placed on a stage and heated by irradiating it with infrared light from below. Temperature control is performed by a thermocouple located on the side of the stage. The temperature of the sample surface can also be measured using a thermocouple located above the sample. The gas generated by heating is positively ionized by the collision of accelerated electrons and separated according to its mass-to-charge ratio. This allows the detection of hydrogen ions.

[0136] In addition, in the imaging element of the present disclosure including the above-mentioned preferred form, the following form can be adopted: wherein the photoelectric conversion part also includes an insulating layer and a charge accumulation electrode, which is arranged separately from the first electrode and arranged to face the inorganic oxide semiconductor material layer through the insulating layer.

[0137] Alternatively, the following form can be adopted: wherein the inorganic oxide semiconductor material layer includes at least two or more elements selected from the group consisting of indium (In), tungsten (W), tin (Sn), and zinc (Zn). Here, the following form can be adopted: wherein the inorganic oxide semiconductor material layer does not include gallium atoms. Specifically, the inorganic oxide semiconductor material layer includes: indium tungsten oxide (IWO) which is a material obtained by adding tungsten (W) to indium oxide, indium-tungsten-zinc oxide (IWZO) which is a material obtained by adding tungsten (W) and zinc (Zn) to indium oxide, indium-tin-zinc oxide (ITZO) which is a material obtained by adding tin (Sn) and zinc (Zn) to indium oxide, or zinc-tin oxide (ZTO). More specifically, the inorganic oxide semiconductor material layer contains In-W oxide, or In-Sn oxide, In-Zn oxide, or W-Sn oxide, or W-Zn oxide, or Sn-Zn oxide, or In-W-Sn oxide, or In-W-Zn oxide, or In-Sn-Zn oxide, or In-W-Sn-Zn oxide. For IWO, when the total mass of indium oxide and tungsten oxide is 100% (mass), the mass ratio of tungsten oxide is preferably 10% to 30% (mass). In addition, for IWZO, when the total mass of indium oxide, tungsten oxide, and zinc oxide is 100% (mass), the mass ratio of tungsten oxide is preferably 2% to 15% (mass), and the mass ratio of zinc oxide is preferably 1% to 3% (mass). Further, for ITZO, when the total mass of indium oxide, zinc oxide, and tin oxide is 100% (mass), the mass ratio of tungsten oxide is preferably 3% to 10% (mass), and the mass ratio of tin oxide is preferably 10% to 17% (mass). However, these mass ratios are not limited to the above values.

[0138] Alternatively, the following form can be adopted: wherein the inorganic oxide semiconductor material layer includes indium (In) atoms, gallium (Ga) atoms, tin (Sn) atoms, and zinc (Zn) atoms. Specifically, the following form can be adopted: wherein, when the inorganic oxide semiconductor material layer is represented by a Ga b Sn c Zn d O e it satisfies 1.8 < (b + c) / a < 2.3 and 2.3 < d / a < 2.6, and also satisfies b > 0.

[0139] Alternatively, a form in which the metal element included in the inorganic oxide semiconductor material has a closed-shell d orbital can be adopted. Specifically, a metal atom selected from the group consisting of copper, silver, gold, zinc, gallium, germanium, indium, tin, and thallium can be adopted. That is, the following structure can be adopted: Among them, the metal atom having a closed-shell d orbital is a metal atom selected from the group consisting of copper (Cu), silver (Ag), gold (Au), zinc (Zn), gallium (Ga), germanium (Ge), indium (In), tin (Sn), thallium (Tl), cadmium (Cd), mercury (Hg), and lead (Pb). Preferably, the metal atom is a metal atom selected from the group consisting of copper (Cu), silver (Ag), gold (Au), zinc (Zn), gallium (Ga), germanium (Ge), indium (In), tin (Sn), and thallium (Tl). More preferably, the metal atom does not include indium (In), and more preferably, the metal atom is a metal atom selected from the group consisting of copper (Cu), silver (Ag), zinc (Zn), gallium (Ga), germanium (Ge), and tin (Sn). Here, more preferred combinations of metal atoms may include (In, Ga), (In, Zn), (In, Sn), (Ga, Sn), (Ga, Zn), (Zn, Sn), (Cu, Zn), (Cu, Ga), (Cu, Sn), (Ag, Zn), (Ag, Ga), and (Ag, Sn).

[0140] Alternatively, a form in which the inorganic oxide semiconductor material layer includes indium (In) atoms, gallium (Ga) atoms, and tin (Sn) atoms can be adopted. Here, when the inorganic oxide semiconductor material layer is represented by In a Ga b Sn c O d it is preferably satisfied that a > b and a > c. In addition, it is more preferably satisfied that a > b > c or a > c > b. In addition, it is more preferably satisfied that a > b > c. In addition, in the imaging element of the present disclosure including the above preferred form, etc., it is preferably satisfied that:

[0141] a + b + c + d = 1.00

[0142] 0.4 < a / (a + b + c) < 0.5

[0143] 0.3 < b / (a + b + c) < 0.4

[0144] 0.2 < c / (a + b + c) < 0.3, or

[0145] it is preferably satisfied that:

[0146] a + b + c + d = 1.00

[0147] 0.30 < a / (a + b + c) < 0.55

[0148] 0.20

[0149] 0.25 <c / (a+b+c)<0.45.

[0150] Alternatively, a configuration in which the inorganic oxide semiconductor material layer includes gallium (Ga) atoms and tin (Sn) atoms may be employed. a Sn b O c In the case of , it is preferred to satisfy a>b, specifically, it is preferred to satisfy:

[0151] a+b+c=1.00

[0152] and

[0153] 0.20

[0154] Alternatively, a configuration in which the inorganic oxide semiconductor material layer includes gallium (Ga) atoms and indium (In) atoms may be employed. d In e O f In the case of , it is preferred to satisfy d>e, specifically, it is preferred to satisfy:

[0155] d+e+f=1.00

[0156] and

[0157] 0.20 <e / (d+e)<0.40。

[0158] Alternatively, the following form may be adopted: wherein the inorganic oxide semiconductor material layer includes zinc (Zn) atoms and tin (Sn) atoms and is composed of Zn a Sn b O c In the case of expression, it can be satisfied:

[0159] a+b+c=1.00

[0160] b>a

[0161] And preferably, b>a>0.18 is satisfied. In addition, preferably, the inorganic oxide semiconductor material layer further comprises a 5d-transition metal. In addition, the inorganic oxide semiconductor material layer further comprises tungsten atoms and is composed of Zn a Sn b M d O c (wherein M refers to a tungsten atom), preferably, the following is satisfied:

[0162] ​​a+b+c+d=1.00

[0163] 0.0005 <d<0.065。

[0164] Alternatively, the inorganic oxide semiconductor material layer further includes tantalum atoms or hafnium atoms and is composed of Zn a Sn b M d O c (wherein M refers to a tantalum atom or a hafnium atom), preferably, the following is satisfied:

[0165] a+b+c+d=1.00

[0166] 0.0005 <d<0.065。

[0167] Alternatively, a method in which the inorganic oxide semiconductor material layer includes In a Ga b Sn c O d The form of , and satisfies the following expression:

[0168] 0.30≤b / (a+b+c)≤0.50

[0169] and

[0170] b≥c.

[0171] Alternatively, a form that satisfies the following expression may be employed:

[0172] 0.40≤b / (a+b+c)≤0.50.

[0173] Alternatively, a form that satisfies the following expression may be employed:

[0174] b≥1.2c.

[0175] Alternatively, a form may be adopted in which the inorganic oxide semiconductor material layer includes indium (In) atoms, tin (Sn) atoms, titanium (Ti) atoms, and zinc (Zn) atoms, and the composition of the inorganic oxide semiconductor material layer is composed of In. a Sn b Ti c Zn d O e In the case of expression, it is preferred to satisfy:

[0176] b>d>c>0.09

[0177] Where a+b+c+d=1.00, and

[0178] Preferably meet:

[0179] a<(b+c+d)≤0.6

[0180] Among them, a+b+c+d=1.00.

[0181] Alternatively, the inorganic oxide semiconductor material layer is composed of In a Sn b M f Zn d O e In the case of expression, it is preferred to satisfy:

[0182] b>d>f>0.09

[0183] Among them, a+b+f+d=1.00.

[0184] Here, M is aluminum, hafnium or zirconium. Alternatively, in the inorganic oxide semiconductor material layer, the composition is In a Sn b Ti c Zn d O e In the case of expression, it is better to meet:

[0185] a<(b+c+d)≤0.6

[0186] Among them, a+b+c+d=1.00.

[0187] In addition, it is preferred that:

[0188] 0.4≤a<(b+d)≤0.5.

[0189] Alternatively, the inorganic oxide semiconductor material layer is composed of In a Sn b M f Zn d O e In the case of expression, it is better to meet:

[0190] a<(b+f+d)≤0.6

[0191] Among them, a+b+f+d=1.00.

[0192] In addition, it is preferred that:

[0193] 0.4≤a<(b+d)≤0.5.

[0194] In a similar manner as described above, M is aluminum, hafnium, or zirconium.

[0195] Alternatively, examples of the inorganic oxide semiconductor material (hereinafter sometimes referred to as “inorganic oxide semiconductor material layer material”) that is a material included in the inorganic oxide semiconductor material layer may include indium oxide, gallium oxide, zinc oxide, tin oxide, a material including at least one selected from these oxides, and a material obtained by adding a dopant to any of these materials. Specific examples thereof may include IGZO (indium-gallium-zinc oxide obtained by adding indium and gallium as dopants to zinc oxide), ITZO, IWZO, IWO, ZTO, ITO-SiO X -based material (indium-tin oxide obtained by mixing or doping silicon oxide), GZO (gallium-zinc oxide obtained by adding gallium as a dopant to zinc oxide), IGO (indium-gallium oxide obtained by adding indium as a dopant to gallium oxide), ZnSnO3, AlZnO, GaZnO and InZnO. In addition, specific examples thereof may include materials containing CuI, InSbO4, ZnMgO, CuInO2, MgIn2O4 and CdO, etc. However, the inorganic oxide semiconductor material is not limited to these materials. Alternatively, in the case where the charge to be accumulated is an electron, the inorganic oxide semiconductor material layer material may include a material having an ionization potential greater than the ionization potential of the material included in the photoelectric conversion layer, and in the case where the charge to be accumulated is a hole, the inorganic oxide semiconductor material layer material may include a material having an electron affinity less than the electron affinity of the material included in the photoelectric conversion layer. Alternatively, the impurity concentration in the inorganic oxide semiconductor material layer material is preferably 1×10 18 cm -3 the following.

[0196] Alternatively, the inorganic oxide semiconductor material layer includes a composite oxide containing titanium oxide and zinc oxide. However, this is not restrictive, and titanium oxide can be replaced by aluminum oxide, hafnium oxide or zirconium oxide. That is, a form in which the inorganic oxide semiconductor material layer includes indium (In) atoms, tin (Sn) atoms, aluminum (Al) and zinc (Zn) atoms can be adopted. A form in which the inorganic oxide semiconductor material layer includes indium (In) atoms, tin (Sn) atoms, hafnium (Hf) and zinc (Zn) atoms can be adopted. A form in which the inorganic oxide semiconductor material layer includes indium (In) atoms, tin (Sn) atoms, zirconium (Zr) and zinc (Zn) atoms can be adopted. Alternatively, a form in which the inorganic oxide semiconductor material layer includes indium (In) atoms, tin (Sn) atoms, metal atoms and zinc (Zn) atoms can be adopted, and the metal atoms are atoms selected from at least one of the group including titanium, aluminum, hafnium and zirconium.

[0197] In addition, in the imaging element of the present disclosure including the above-mentioned preferred embodiment, a form in which the charge generated in the photoelectric conversion layer moves to the first electrode via the protective layer and the inorganic oxide semiconductor material layer can be adopted. In this case, a form in which the charge is an electron can be adopted.

[0198] In the imaging element and the like of the present disclosure including the above-mentioned various preferred embodiments, it is preferable that the carrier mobility of the inorganic oxide semiconductor material layer material is 10 cm 2 / V·s or more, which can quickly move the charges accumulated in the inorganic oxide semiconductor material layer to the first electrode. In addition, the carrier concentration (carrier density) of the inorganic oxide semiconductor material layer is preferably 1×10 16 / cm 3 Subsequently, this causes the amount of charge accumulated in the inorganic oxide semiconductor material layer to increase.

[0199] Furthermore, in the imaging element and the like of the present disclosure including the various preferred aspects described above, it is preferred that:

[0200] Light is incident from the second electrode; and

[0201] The surface roughness Ra of the inorganic oxide semiconductor material layer surface at the interface between the protective layer and the inorganic oxide semiconductor material layer is less than 1.5 nm, and the root mean square roughness Rq of the inorganic oxide semiconductor material layer surface is less than 2.5 nm. The surface roughness Ra and Rq are based on the provisions of JIS B0601:2013. This smoothness of the inorganic oxide semiconductor material layer surface at the interface between the protective layer and the inorganic oxide semiconductor material layer can suppress diffuse reflection at the surface of the inorganic oxide semiconductor material layer and improve the photocurrent characteristics in photoelectric conversion. Preferably, the surface roughness Ra of the charge accumulation electrode surface is less than 1.5 nm, and the root mean square roughness Rq of the charge accumulation electrode surface is less than 2.5 nm.

[0202] In addition, in the imaging element of the present disclosure including the various preferred forms described above, a form in which the inorganic oxide semiconductor material layer is amorphous (e.g., an amorphous state that does not partially have a crystal structure) can be adopted. Whether the inorganic oxide semiconductor material layer is amorphous can be determined based on X-ray diffraction analysis. However, the inorganic oxide semiconductor material layer is not limited to being amorphous and may have a crystal structure or a polycrystalline structure.

[0203] In the imaging element and the like of the present disclosure including the various preferred embodiments described above, it is desirable that the thickness of the inorganic oxide semiconductor material layer is 1×10 -8 m to 1.5×10 -7 m, preferably 2×10 -8m to 1.0×10 -7 m, more preferably 3×10 -8 m to 1.0×10 -7 m.

[0204] The first electrode, the second electrode, the charge accumulation electrode, and the photoelectric conversion layer will be described in detail below.

[0205] exist Figure 72 In the conventional imaging element shown, the charge generated by photoelectric conversion in the second photoelectric converter 341A and the third photoelectric converter 343A is temporarily accumulated there and then transferred to the second floating diffusion layer FD2 and the third floating diffusion layer FD3. Therefore, the second photoelectric converter 341A and the third photoelectric converter 343A can be completely depleted. However, the charge generated by photoelectric conversion in the first photoelectric converter 310A is directly accumulated in the first floating diffusion layer FD1. Therefore, it is difficult to completely deplete the first photoelectric converter 310A. As a result, kTC noise increases and random noise worsens, potentially reducing the quality of captured images.

[0206] In the imaging element and the like of the present disclosure, as described above, as long as a charge accumulation electrode is provided that is arranged separately from the first electrode and arranged to face the inorganic oxide semiconductor material layer via an insulating layer, when the photoelectric conversion portion is irradiated with light and photoelectric conversion is performed in the photoelectric conversion portion, charge can be accumulated in the inorganic oxide semiconductor material layer (in some cases, accumulated in the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer). Therefore, at the start of exposure, the charge accumulation portion can be completely depleted and the charge can be cleared. As a result, the occurrence of the following phenomenon can be suppressed: kTC noise becomes larger, random noise deteriorates, and the quality of the captured image is reduced. It should be noted that in the following description, in some cases, the inorganic oxide semiconductor material layer, or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer may be collectively referred to as "inorganic oxide semiconductor material layer, etc."

[0207] The inorganic oxide semiconductor material layer may have a single-layer structure or a multi-layer structure. Furthermore, the inorganic oxide semiconductor material layer material included in the inorganic oxide semiconductor material layer located above the charge accumulation electrode and the inorganic oxide semiconductor material layer material included in the inorganic oxide semiconductor material layer located above the first electrode may be different from each other. The protective layer may also have a single-layer structure or a multi-layer structure.

[0208] The protective layer and the inorganic oxide semiconductor material layer can be formed based on, for example, a physical vapor deposition method (PVD method), specifically a sputtering method. More specifically, examples of sputtering methods may include a sputtering method using a parallel flat plate sputtering device, a DC magnetron sputtering device, or an RF sputtering device as a sputtering device; using argon (Ar) gas as a processing gas; and using an ideal sintered body as a target. Alternatively, an example of a method for forming the protective layer may include an atomic layer deposition method (ALD method). However, the method is not limited to these film forming methods.

[0209] The energy level of the inorganic oxide semiconductor material layer can be controlled by controlling the amount of oxygen introduced (oxygen partial pressure) when the inorganic oxide semiconductor material layer is formed based on the sputtering method. Specifically, when the inorganic oxide semiconductor material layer is formed based on the sputtering method, the control is based on the oxygen partial pressure = (O2 gas pressure) / (total pressure of Ar gas and O2 gas). The oxygen partial pressure is preferably 0.005 to 0.10. In addition, in the imaging element of the present disclosure, a form in which the oxygen content in the inorganic oxide semiconductor material layer is lower than the stoichiometric oxygen content can be adopted. Here, the energy level of the inorganic oxide semiconductor material layer can be controlled based on the oxygen content, and as the oxygen content becomes lower than the stoichiometric oxygen content, that is, as the oxygen vacancies are more, the energy level can be made deeper.

[0210] Examples of the imaging element and the like of the present disclosure may include CCD elements, CMOS image sensors, CIS (Contact Image Sensor) and CMD (Charge Modulation Device) type signal amplification image sensors. The solid-state imaging devices according to the first and second aspects of the present disclosure, as well as the first and second configurations described later, can be included in, for example, digital cameras, video cameras, camcorders, surveillance cameras, in-vehicle cameras, smartphone cameras, user interface cameras for gaming, and cameras for biometric authentication.

[0211] [Example 1]

[0212] Embodiment 1 relates to an image pickup element of the present disclosure, a stacked image pickup element of the present disclosure, and a solid-state image pickup device according to the second aspect of the present disclosure. Figure 1 Schematic partial cross-sectional view of the imaging element and the stacked imaging element (hereinafter simply referred to as “imaging element”) of Example 1. Figure 2 and Figure 3 This is an equivalent circuit diagram of the imaging element of Example 1. Figure 4 This is a schematic layout diagram of a first electrode and a charge storage electrode included in a photoelectric conversion portion of the image sensor of Example 1, and a transistor included in a control portion. Figure 5The potential states at various locations during operation of the image pickup element of Example 1 are schematically shown. Figure 6A This is an equivalent circuit diagram for explaining each part of the imaging element of Example 1. Figure 7 This is a schematic layout diagram of a first electrode and a charge accumulation electrode included in the photoelectric conversion portion of the image sensor of Example 1. Figure 8 : is a schematic perspective view of the first electrode, the charge accumulation electrode, the second electrode and the contact hole portion. Figure 68 A conceptual diagram showing a solid-state imaging device according to Embodiment 1.

[0213] The imaging element of Example 1 includes a photoelectric conversion section comprising a stacked first electrode 21, a photoelectric conversion layer 23A, and a second electrode 22. A protective layer 23B and an inorganic oxide semiconductor material layer 23C are formed directly below the photoelectric conversion layer 23A from the photoelectric conversion section side. The inorganic oxide semiconductor material layer 23C is in contact with the first electrode 21. The inorganic oxide semiconductor material layer 23C and the protective layer 23B are in contact with each other. The protective layer 23B is in contact with the photoelectric conversion layer 23A.

[0214] The stacked imaging element of Example 1 includes at least one imaging element of Example 1. Furthermore, the solid-state imaging device of Example 1 includes a plurality of stacked imaging elements of Example 1. The solid-state imaging device of Example 1 is included in, for example, a digital camera, a video camera, a camcorder, a surveillance camera, an in-vehicle camera, a smartphone camera, a user interface camera for gaming, and a biometric authentication camera.

[0215] In the image pickup element of Example 1, the oxygen vacancy formation energy of the metal atoms included in the protective layer 23B is 5 eV or more. In this case, the following expression is satisfied:

[0216] E OD-1 -E OD-2 ≥1eV

[0217] Among them, E OD-1 represents the oxygen vacancy formation energy of the metal atoms included in the protective layer 23B, E OD-2 represents the oxygen vacancy formation energy of the metal atoms included in the inorganic oxide semiconductor material layer 23C. In addition, the oxygen vacancy formation energy of the metal atoms included in the inorganic oxide semiconductor material layer 23C is 3 eV or more. In addition, the following expression is satisfied:

[0218] E0≥E1

[0219] Preferably,

[0220] E0-E1≥0.1(eV)

[0221] More preferably,

[0222] E0-E1>0.1(eV)

[0223] Satisfies the following expression:

[0224] E1-E2≥0.1(eV)

[0225] In addition, the following expression is satisfied:

[0226] E1-E2>0.1(eV)

[0227] Here, E0 represents the energy average of the LUMO values ​​of the portion of the photoelectric conversion layer 23A facing the protective layer 23B, and E1 and E2 represent the energy averages of the maximum energy values ​​of the conduction bands of the protective layer 23B and the inorganic oxide semiconductor material layer 23C.

[0228] The protective layer 23B includes Nb a Ti b O c (where a+b+c=1.00), and in this case, 0.05≤a≤0.25 and 0.05≤b≤0.25 were satisfied. In Example 1, three types of protective layers 23B were evaluated. Specifically, in the protective layers 23B of Example 1A, Example 1B, and Example 1C, the specific values ​​of a, b, and c are shown in Table 1 below.

[0229]

[0230]

[0231]

[0232] Protective layer 23B prevents hydrogen from entering inorganic oxide semiconductor material layer 23C. The hydrogen barrier capacity of protective layer 23B, as determined by thermal desorption spectroscopy, is shown in Table 2 below. Note that in the thermal desorption spectroscopy test, a sample was used in which a titanium layer was formed as a base layer on a silicon semiconductor substrate, and a protective layer 23B with a thickness of 30 nm was formed on the titanium layer. The ion current value was determined while the sample was heated. Furthermore, in Comparative Example 1, protective layer 23B was not provided, and only a titanium layer was formed as a base layer on a silicon semiconductor substrate.

[0233]

[0234]

[0235] Table 2 confirms that the intensity of detected hydrogen atoms decreased by one order of magnitude or more when heated to 350°C, compared to the case where no protective layer was provided (Comparative Example 1). This indicates that the protective layer can prevent the ingress of hydrogen, which is likely to enter during the manufacture or handling of the imaging element.

[0236] The thickness of the inorganic oxide semiconductor material layer 23C is 1×10 -8 m~1.5×10 -7 m. In Example 1, the inorganic oxide semiconductor material layer 23C includes IGZO with a thickness of 50 nm. In addition, the photoelectric conversion layer 23A includes D60 with a thickness of 0.1 μm. The thickness of the protective layer 23B is 3 nm. In addition, the charges generated in the photoelectric conversion layer 23A move to the first electrode 21 through the protective layer 23B and the inorganic oxide semiconductor material layer 23C. In this case, the charges are electrons.

[0237] The oxygen vacancy formation energy of the metal atoms included in the protective layer 23B is 5 eV or more, and the oxygen vacancy formation energy of the metal atoms included in the inorganic oxide semiconductor material layer 23C is 3 eV or more.

[0238] Specifically, the following expressions hold:

[0239] E OD-1 =5.5eV (oxygen vacancy formation energy of niobium atom)

[0240] E OD-2 =3.1eV (oxygen vacancy formation energy of gallium atom)

[0241] And the following expressions are satisfied:

[0242] E OD-1 -E OD-2 ≥1eV.

[0243] In addition, the following expressions hold:

[0244] E0=-4.3eV(C60)

[0245] E2=-4.7eV(IGZO)

[0246] And the following expression holds:

[0247] E1 of Example 1A = -4.4 eV

[0248] E1 of Example 1B = -4.3 eV

[0249] Example 1C has E1 = -4.4 eV.

[0250] In addition, the following expressions hold:

[0251] E1' of Example 1A = -7.7 eV

[0252] E1' of Example 1B = -7.6 eV

[0253] Example 1C E1' = -7.8 eV

[0254] Here, E1′ represents the energy average of the minimum energy value of the valence band of the protective layer.

[0255] In addition, the carrier mobility of the inorganic oxide semiconductor material layer is 10 cm 2 / V·s or more; the carrier concentration of the inorganic oxide semiconductor material layer 23C is 1×10 16 / cm 3 The inorganic oxide semiconductor material layer 23C is amorphous. Specific examples of these values ​​are shown in Table 3 below.

[0256]

[0257] Inorganic oxide semiconductor material layer material (IGZO)

[0258] Mobility 1×10cm 2 / V·s

[0259] Carrier concentration 1×10 16 / cm 3

[0260] The photoelectric conversion portion further includes an insulating layer 82 and a charge accumulation electrode 24, which is arranged separately from the first electrode 21 and faces the inorganic oxide semiconductor material layer 23C across the insulating layer 82. Specifically, the inorganic oxide semiconductor material layer 23C includes a region in contact with the first electrode 21, a region in contact with the insulating layer 82 and without the charge accumulation electrode 24 therebelow, and a region in contact with the insulating layer 82 and with the charge accumulation electrode 24 therebelow. Light is incident from the second electrode 22. The surface roughness Ra of the inorganic oxide semiconductor material layer 23C at the interface between the protective layer 23B and the inorganic oxide semiconductor material layer 23C is 1.5 nm or less, specifically 0.65 nm, and the root mean square roughness Rq of the inorganic oxide semiconductor material layer 23C is 2.5 nm or less, specifically 1.3 nm. The surface roughness Ra of the charge storage electrode 24 is 1.5 nm or less, specifically 0.45 nm, and the root mean square roughness Rq of the charge storage electrode 24 is 2.5 nm or less, specifically 1.5 nm.

[0261] The energy level of the inorganic oxide semiconductor material layer 23C can be controlled by controlling the amount of oxygen introduced (oxygen partial pressure) when the inorganic oxide semiconductor material layer 23C is formed by sputtering. The oxygen partial pressure is preferably 0.005 (0.5%) to 0.10 (10%).

[0262] Figure 70 The conceptual diagram shows the energy level structure of the photoelectric conversion unit in the imaging element of Example 1. An inorganic oxide semiconductor material layer 23C, a protective layer 23B, and a photoelectric conversion layer 23A are stacked in this order from the first electrode side. The average energy value E1 of the maximum energy value of the conduction band of protective layer 23B is deeper than the average energy value E0 of the LUMO value of photoelectric conversion layer 23A, and the average energy value of the minimum energy value of the valence band of protective layer 23B is deeper than the average energy value of the HOMO value of photoelectric conversion layer 23A. As a result, electrons generated during the photoelectric conversion process are transmitted without any obstruction, and the escape of holes is suppressed.

[0263] in addition, Figure 71A The results of characteristic evaluation of a bottom-gate thin film transistor are shown, in which a protective layer is formed on an inorganic oxide semiconductor material layer in Example 1 (Example 1B) and both layers serve as a channel formation region. Figure 71B The results of evaluating the characteristics of a bottom-gate thin-film transistor without a protective layer, in which the inorganic oxide semiconductor material layer serves as the channel formation region, are shown. The TDS results show that the provision of a protective layer prevents hydrogen ingress and suppresses oxygen extraction from the inorganic oxide semiconductor material layer 23C, allowing the TFT to function normally. In other words, the stable characteristics of the inorganic oxide semiconductor material layer 23C enable the realization of an imaging element with stable characteristics.

[0264] As described above, in the imaging element of Example 1, by providing a protective layer between the photoelectric conversion layer and the inorganic oxide semiconductor material layer, hydrogen can be effectively prevented from entering the inorganic oxide semiconductor material layer, thereby suppressing the extraction of oxygen atoms in the inorganic oxide semiconductor material layer and suppressing the generation of oxygen vacancies caused by the entry of hydrogen. Therefore, an inorganic oxide semiconductor material layer with stable characteristics and an imaging element with stable characteristics can be achieved. In addition, the oxygen vacancy formation energy (energy required to generate oxygen vacancies) of the metal atoms included in the protective layer is defined, so the more difficult it is for oxygen atoms to desorb, and it is difficult to combine with oxygen atoms, oxygen molecules or other atoms or molecules. Therefore, the extraction of oxygen atoms and the generation of oxygen vacancies in the inorganic oxide semiconductor material layer can be more reliably suppressed. In addition, by specifying the relationship between the energy average value E0 in the LUMO value of the photoelectric conversion layer and the energy average value E1 in the maximum energy value of the conduction band of the protective layer, the energy barrier between the protective layer and the adjacent photoelectric conversion layer can be reduced, and the reliable movement of charge from the photoelectric conversion layer through the protective layer to the inorganic oxide semiconductor material layer can be achieved. In addition, the optimization of the carrier concentration of the inorganic oxide semiconductor material layer (optimization of the depletion degree of the inorganic oxide semiconductor material), the high carrier mobility of the inorganic oxide semiconductor material layer, the control of the energy average value E2 in the maximum energy value of the conduction band of the inorganic oxide semiconductor material layer, and the suppression of the generation of oxygen vacancies in the inorganic oxide semiconductor material layer can be achieved in a balanced manner. Therefore, despite the simple construction and structure, an imaging element, a stacked imaging element, and a solid-state imaging device with excellent transfer characteristics of the charges accumulated in the photoelectric conversion layer can be provided. In addition, since the photoelectric conversion portion has a stacked structure of an inorganic oxide semiconductor material layer, a protective layer, and a photoelectric conversion layer, recombination during charge accumulation can be prevented, and the transfer efficiency of the charges accumulated in the photoelectric conversion layer to the first electrode can be further improved. In addition, the charges generated in the photoelectric conversion layer can be temporarily maintained, thereby controlling the timing of the transfer, etc. The generation of dark current can also be suppressed.

[0265] The following generally describes the imaging element, stacked imaging element, and solid-state imaging device according to the second aspect of the present disclosure. The imaging element and solid-state imaging device of Example 1 are then described in detail. The following describes a case where the potential applied to the first electrode is higher than the potential applied to the second electrode. The symbols representing the potentials applied to the various electrodes described below are listed in Table 4 below.

[0266]

[0267]

[0268]

[0269] For convenience, in some cases, the imaging element and the like of the present disclosure that includes the above-mentioned preferred embodiment and includes a charge accumulation electrode will be referred to as “the imaging element and the like of the present disclosure that includes a charge accumulation electrode”.

[0270] In the imaging element of the present disclosure, the transmittance of the inorganic oxide semiconductor material layer is preferably 65% ​​or more for light with a wavelength of 400 nm to 660 nm. In addition, the transmittance of the charge accumulation electrode is also preferably 65% ​​or more for light with a wavelength of 400 nm to 660 nm. The sheet resistance of the charge accumulation electrode is preferably 3×10 Ω / □ to 1×10 3 Ω / □.

[0271] In the imaging element of the present disclosure, a configuration can be adopted in which the imaging element further includes a semiconductor substrate and a photoelectric conversion unit is provided above the semiconductor substrate. Note that the first electrode, the charge accumulation electrode, the second electrode, and the various electrodes are connected to a drive circuit described later.

[0272] The second electrode located on the light incident side can be shared by multiple imaging elements. That is, in addition to the imaging element of the present disclosure including the upper charge transfer control electrode described later, the second electrode can be a so-called solid electrode. The photoelectric conversion layer can be shared by multiple imaging elements, that is, one photoelectric conversion layer can be formed for multiple imaging elements. Alternatively, a photoelectric conversion layer can be provided for each imaging element. Preferably, an inorganic oxide semiconductor material layer and a protective layer are provided for each imaging element; however, in some cases, the inorganic oxide semiconductor material layer and the protective layer can also be shared by multiple imaging elements. In other words, by providing, for example, a charge transfer control electrode described later between the imaging elements, one inorganic oxide semiconductor material layer and one protective layer can be formed for multiple imaging elements. In the case of forming one inorganic oxide semiconductor material layer and one protective layer shared by multiple imaging elements, from the perspective of protecting the ends of the inorganic oxide semiconductor material layer and the protective layer, it is ideal that the ends of the inorganic oxide semiconductor material layer and the protective layer are at least covered by the photoelectric conversion layer.

[0273] In addition, in the imaging element of the present disclosure including the above-mentioned various preferred forms, a form in which the first electrode extends within an opening provided in the insulating layer and is connected to the inorganic oxide semiconductor material layer can be adopted. Alternatively, a form in which the inorganic oxide semiconductor material layer and the protective layer extend within an opening provided in the insulating layer and the inorganic oxide semiconductor material layer is connected to the first electrode can be adopted. In this case, the following form can be adopted: wherein,

[0274] The edge of the top surface of the first electrode is covered by the insulating layer,

[0275] The first electrode is exposed at the bottom surface of the opening, and

[0276] The side surface of the opening portion is inclined in a manner that expands the opening portion from the first surface toward the second surface, wherein the first surface is a surface of the insulating layer in contact with the top surface of the first electrode and the second surface is a surface of the insulating layer in contact with a portion of the inorganic oxide semiconductor material layer facing the charge accumulation electrode, and further, the side surface of the opening portion is inclined in a manner that expands the opening portion from the first surface toward the second surface is located on the charge accumulation electrode side.

[0277] Furthermore, in the imaging element and the like including the various preferred aspects described above, the following aspects may be adopted:

[0278] The imaging element or the like further includes a control section provided in the semiconductor substrate and including a drive circuit.

[0279] The first electrode and the charge accumulation electrode are connected to a drive circuit,

[0280] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31 , and accumulates charges in the inorganic oxide semiconductor material layer, etc., and

[0281] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode. 12 , apply a potential V to the charge accumulation electrode 32 , and the charge accumulated in the inorganic oxide semiconductor material layer, etc. is read out to the control unit via the first electrode. It should be noted that the potential of the first electrode is higher than the potential of the second electrode, and the following expression is established:

[0282] V 31 ≥V 11 and V 32 <V 12

[0283] In addition, in the imaging element and the like including the various preferred forms described above, a form can be adopted in which the charge transfer control electrode is formed in an area opposite to the area of ​​the photoelectric conversion layer located between adjacent imaging elements across an insulating layer. It should be noted that in some cases, for the sake of convenience, such a form is referred to as "the imaging element and the like disclosed herein including a lower charge transfer control electrode". Alternatively, a form can be adopted in which a charge transfer control electrode is formed on an area of ​​the photoelectric conversion layer located between adjacent imaging elements instead of a second electrode. It should be noted that in some cases, for the sake of convenience, such a form is referred to as "the imaging element and the like disclosed herein including an upper charge transfer control electrode".

[0284] In the following description, for convenience, the "region of the photoelectric conversion layer located between adjacent imaging elements" is referred to as "region A of the photoelectric conversion layer," and for convenience, the "region of the insulating layer located between adjacent imaging elements" is referred to as "region A of the insulating layer." Region A of the photoelectric conversion layer corresponds to region A of the insulating layer. Furthermore, for convenience, the "region between adjacent imaging elements" is referred to as "region a."

[0285] In the imaging element disclosed herein, etc., which includes a lower charge transfer control electrode (a lower charge transfer control electrode, a charge transfer control electrode located on the opposite side of the light incident side relative to the photoelectric conversion layer), the lower charge transfer control electrode is formed in a region opposite to region-A of the photoelectric conversion layer via an insulating layer. In other words, the lower charge transfer control electrode is formed below a portion of the insulating layer (region-A of the insulating layer) in a region (region-a) sandwiched between the charge accumulation electrode and the charge accumulation electrode included in each adjacent imaging element. The lower charge transfer control electrode is disposed separately from the charge accumulation electrode. Or, in other words, the lower charge transfer control electrode surrounds the charge accumulation electrode and is disposed separately from the charge accumulation electrode. The lower charge transfer control electrode is arranged to face region-A of the photoelectric conversion layer via the insulating layer.

[0286] In addition, the following form can be adopted:

[0287] The imaging element or the like including the lower charge transfer control electrode of the present disclosure further includes a control section provided in the semiconductor substrate and including a drive circuit.

[0288] The first electrode, the second electrode, the charge accumulation electrode and the lower charge transfer control electrode are connected to a drive circuit.

[0289] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31, apply a potential V to the lower charge movement control electrode 41 , and accumulates charges in the inorganic oxide semiconductor material layer, etc., and

[0290] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode. 12 , apply a potential V to the charge accumulation electrode 32 , apply a potential V to the lower charge movement control electrode 42 , and the charge accumulated in the inorganic oxide semiconductor material layer and the like is read out to the control unit via the first electrode. Note that the following expression holds true.

[0291] V 31 ≥V 11 , V 31 >V 41 and V 12 >V 32 >V 42

[0292] The lower charge transfer control electrode may be formed on the same level as or on a different level from that of the first electrode or the charge accumulation electrode.

[0293] In the imaging element and the like disclosed herein that include an upper charge transfer control electrode (an upper charge transfer control electrode located on the light-incident side relative to the photoelectric conversion layer), the upper charge transfer control electrode is formed in a region of the photoelectric conversion layer located between adjacent imaging elements, rather than the second electrode. The upper charge transfer control electrode is provided separately from the second electrode. In other words:

[0294] [A] The following configuration may be employed: a second electrode is provided for each imaging element; and an upper charge transfer control electrode surrounds at least a portion of the second electrode and is provided on region -A of the photoelectric conversion layer in a manner separate from the second electrode. Alternatively,

[0295] [B] The following form may be adopted: wherein a second electrode is provided for each imaging element; an upper charge transfer control electrode surrounds at least a portion of the second electrode and is provided separately from the second electrode; and a portion of the charge accumulation electrode exists below the upper charge transfer control electrode. Alternatively,

[0296] [C] A configuration may be employed in which a second electrode is provided for each imaging element; an upper charge transfer control electrode surrounds at least a portion of the second electrode and is provided separately from the second electrode; a portion of the charge accumulation electrode is provided below the upper charge transfer control electrode; and a lower charge transfer control electrode is provided below the upper charge transfer control electrode. In some cases, a potential generated by the connection between the upper charge transfer control electrode and the second electrode may be applied to a region of the photoelectric conversion layer below the region between the upper charge transfer control electrode and the second electrode.

[0297] In addition, the following form can be adopted:

[0298] The imaging element or the like including the upper charge transfer control electrode of the present disclosure further includes a control section provided in the semiconductor substrate and including a drive circuit.

[0299] The first electrode, the second electrode, the charge accumulation electrode and the upper charge transfer control electrode are connected to a drive circuit.

[0300] During the charge accumulation period, a potential V is applied from the drive circuit to the second electrode. 21 , apply a potential V to the upper charge movement control electrode 41 , and accumulates charges in the inorganic oxide semiconductor material layer, etc., and

[0301] During the charge transfer period, a potential V is applied from the driving circuit to the second electrode. 22 , apply a potential V to the upper charge movement control electrode 42 , and the charge accumulated in the inorganic oxide semiconductor material layer and the like is read out to the control unit via the first electrode. Note that the following expression holds true.

[0302] V 21 ≥V 41 and V 22 ≥V 42

[0303] The upper charge movement control electrode is formed on the same level as the second electrode.

[0304] Furthermore, in the imaging element and the like of the present disclosure including the various preferred embodiments described above, the imaging element and the like may further include a transfer control electrode (charge transfer electrode) between the first electrode and the charge accumulation electrode, the transfer control electrode being arranged separately from the first electrode and the charge accumulation electrode, and the transfer control electrode being arranged to face the inorganic oxide semiconductor material layer with an insulating layer interposed therebetween. For convenience, the imaging element and the like of the present disclosure having such an embodiment will be referred to as "the imaging element and the like of the present disclosure including the transfer control electrode."

[0305] Furthermore, in the imaging element and the like including the transfer control electrode of the present disclosure, the following embodiment may be adopted:

[0306] The imaging element further includes a control unit provided in the semiconductor substrate and including a drive circuit.

[0307] The first electrode, the charge accumulation electrode, and the transfer control electrode are connected to a drive circuit.

[0308] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31 , apply a potential V to the transmission control electrode 51 , and accumulates charges in the inorganic oxide semiconductor material layer, etc., and

[0309] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode. 12 , apply a potential V to the charge accumulation electrode 32 , apply a potential V to the transmission control electrode 52 , and the charge accumulated in the inorganic oxide semiconductor material layer etc. is read out to the control section via the first electrode. Note that the potential of the first electrode is higher than the potential of the second electrode, and the following expression holds.

[0310] V 31 >V 51 and V 32 ≤V 52 ≤V 12

[0311] In addition, in the imaging element etc. including the various preferred forms described above, the following form may be adopted: wherein the imaging element etc. further includes a charge discharge electrode, which is connected to the inorganic oxide semiconductor material layer and is arranged separately from the first electrode and the charge accumulation electrode. For the sake of convenience, the imaging element etc. of the present disclosure having such a form is referred to as "the imaging element etc. of the present disclosure including the charge discharge electrode". In addition, in the imaging element etc. of the present disclosure including the charge discharge electrode, a form may be adopted in which the charge discharge electrode is arranged to surround the first electrode and the charge accumulation electrode (i.e., in the shape of a photo frame). The charge discharge electrode may be shared (in common) by a plurality of imaging elements. In addition, in this case, the following form may be adopted: wherein,

[0312] The inorganic oxide semiconductor material layer and the like extend in the second opening provided in the insulating layer and are connected to the charge discharge electrode.

[0313] The edge of the top surface of the charge discharge electrode is covered with an insulating layer,

[0314] The charge discharge electrode is exposed at the bottom surface of the second opening, and

[0315] The side surface of the second opening portion is inclined in a manner that expands the second opening portion from the third surface toward the second surface, wherein the third surface is a surface of the insulating layer that contacts the top surface of the charge discharge electrode, and the second surface is a surface of the insulating layer that contacts a portion of the inorganic oxide semiconductor material layer that faces the charge accumulation electrode.

[0316] Furthermore, in the imaging element and the like including the charge discharge electrode of the present disclosure, the following embodiment may be adopted:

[0317] The imaging element further includes a control unit provided in the semiconductor substrate and including a drive circuit.

[0318] The first electrode, the charge accumulation electrode, and the charge discharge electrode are connected to a drive circuit.

[0319] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31 , apply a potential V to the charge discharge electrode 61 , and accumulates charges in the inorganic oxide semiconductor material layer, etc., and

[0320] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode. 12 , apply a potential V to the charge accumulation electrode 32 , apply a potential V to the charge discharge electrode 62 , and the charge accumulated in the inorganic oxide semiconductor material layer etc. is read out to the control section via the first electrode. Note that the potential of the first electrode is higher than the potential of the second electrode, and the following expression holds.

[0321] V 61 >V 11 and V 62 <V 12

[0322] In addition, among the above-mentioned various preferred forms of the imaging element etc. disclosed in the present invention, a form can be adopted in which the charge accumulation electrode includes a plurality of charge accumulation electrode segments. For the sake of convenience, the imaging element etc. disclosed in the present invention of this form is referred to as "the imaging element etc. disclosed in the present invention including a plurality of charge accumulation electrode segments". It is sufficient that the number of charge accumulation electrode segments is two or more. In the imaging element etc. disclosed in the present invention including a plurality of charge accumulation electrode segments, when different potentials are applied to N charge accumulation electrode segments, the following form can be adopted: wherein,

[0323] In the case where the potential of the first electrode is higher than the potential of the second electrode, during the charge transfer period, the potential applied to the charge accumulation electrode segment closest to the first electrode (the first photoelectric conversion portion segment) is higher than the potential applied to the charge accumulation electrode segment farthest from the first electrode (the Nth photoelectric conversion portion segment), and

[0324] When the potential of the first electrode is lower than the potential of the second electrode, during the charge transfer period, the potential applied to the charge accumulation electrode segment closest to the first electrode (the first photoelectric conversion segment) is lower than the potential applied to the charge accumulation electrode segment farthest from the first electrode (the Nth photoelectric conversion segment).

[0325] In the imaging element and the like of the present disclosure including the various preferred aspects described above, the following structure may be adopted:

[0326] In the semiconductor substrate, at least a floating diffusion layer and an amplifying transistor included in the control section are provided, and

[0327] The first electrode is connected to the floating diffusion layer and the gate portion of the amplifying transistor. In addition, in this case, the following structure can also be adopted:

[0328] In the semiconductor substrate, a reset transistor and a selection transistor included in the control unit are further provided.

[0329] The floating diffusion layer is connected to one of the source / drain regions of the reset transistor, and

[0330] One of the source / drain regions of the amplification transistor is connected to one of the source / drain regions of the selection transistor, and the other of the source / drain regions of the selection transistor is connected to the signal line.

[0331] Furthermore, in the imaging element of the present disclosure including the various preferred embodiments described above, a form in which the size of the charge accumulation electrode is larger than the size of the first electrode may be adopted. Although not limited, it is preferable to satisfy

[0332] 4≤s1' / s1,

[0333] Here, s1′ represents the area of ​​the charge accumulation electrode, and s1 represents the area of ​​the first electrode.

[0334] Alternatively, as a modified example of the imaging element of the present disclosure including the various preferred embodiments described above, the imaging element of the first to sixth configurations described below may be adopted. That is, in the imaging element of the first to sixth configurations among the imaging element of the present disclosure including the various preferred embodiments described above,

[0335] The photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit segments,

[0336] The inorganic oxide semiconductor material layer includes N photoelectric conversion layer segments,

[0337] The insulating layer includes N insulating layer segments,

[0338] In the imaging element of the first to third configurations, the charge accumulation electrode includes N charge accumulation electrode segments.

[0339] In the image pickup elements of the fourth and fifth configurations, the charge accumulation electrode includes N charge accumulation electrode segments arranged apart from each other,

[0340] The nth (where n=1, 2, 3, ..., N) photoelectric conversion portion segment includes the nth charge accumulation electrode segment, the nth insulating layer segment, and the nth photoelectric conversion layer segment, and

[0341] The larger the n value, the farther the photoelectric conversion section is from the first electrode. Here, the "photoelectric conversion layer section" refers to a section including a stacked photoelectric conversion layer, a protective layer, and an inorganic oxide semiconductor material layer.

[0342] Furthermore, in the imaging element of the first configuration, the thickness of the insulating layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. Furthermore, in the imaging element of the second configuration, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. It should be noted that within the photoelectric conversion layer section, the thickness of the photoelectric conversion layer section can be varied by maintaining the thickness of a portion of the inorganic oxide semiconductor material layer constant while varying the thickness of a portion of the photoelectric conversion layer. The thickness of the photoelectric conversion layer section can be varied by maintaining the thickness of a portion of the photoelectric conversion layer constant while varying the thickness of a portion of the inorganic oxide semiconductor material layer. The thickness of the photoelectric conversion layer section can be varied by varying the thickness of a portion of the photoelectric conversion layer and varying the thickness of a portion of the inorganic oxide semiconductor material layer. Furthermore, in the imaging element of the third configuration, the material contained in the insulating layer section differs between adjacent photoelectric conversion section sections. Furthermore, in the imaging element of the fourth configuration, the material contained in the charge accumulation electrode section differs between adjacent photoelectric conversion section sections. In the imaging element of the fifth structure, the area of ​​the charge storage electrode segment gradually decreases from the first photoelectric conversion region segment to the Nth photoelectric conversion region segment. The area may decrease continuously or in steps.

[0343] Alternatively, in the imaging element of the sixth configuration among the imaging elements of the present disclosure including the various preferred aspects described above, the cross-sectional area of ​​the stacked portion in which the charge accumulation electrode, the insulating layer, the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer are stacked, taken along the YZ imaginary plane, varies depending on the distance from the first electrode, where the Z direction is the stacking direction of the charge accumulation electrode, the insulating layer, the inorganic oxide semiconductor material layer, and the photoelectric conversion layer, and the X direction is the direction away from the first electrode. This change in cross-sectional area may be a continuous change or a step-like change.

[0344] In the imaging elements of the first and second structures, N photoelectric conversion layer segments are arranged continuously, N insulating layer segments are also arranged continuously, and N charge accumulation electrode segments are also arranged continuously. In the imaging elements of the third to fifth structures, N photoelectric conversion layer segments are arranged continuously. In addition, in the imaging elements of the fourth and fifth structures, N insulating layer segments are arranged continuously, while in the imaging element of the third structure, N insulating layer segments are arranged to correspond to each photoelectric conversion section. In addition, in the imaging elements of the fourth and fifth structures, and as the case may be, in the imaging element of the third structure, N charge accumulation electrode segments are arranged to correspond to each photoelectric conversion section. In addition, in the imaging elements of the first to sixth structures, the same potential is applied to all the charge accumulation electrode segments. Alternatively, in the imaging elements of the fourth and fifth structures, and as the case may be, in the imaging element of the third structure, different potentials may be applied to the N charge accumulation electrode segments.

[0345] In the imaging element of the present disclosure including any one of the imaging elements of the first to sixth structures, etc., the thickness of the insulating layer segment is specified. Alternatively, the thickness of the photoelectric conversion layer segment is specified. Alternatively, the materials contained in the insulating layer segment are different. Alternatively, the materials contained in the charge accumulation electrode segment are different. Alternatively, the area of ​​the charge accumulation electrode segment is specified. Alternatively, the cross-sectional area of ​​the stacked portion is specified. Therefore, a charge transfer gradient is formed, and the charge generated by the photoelectric conversion can be more easily and reliably transferred to the first electrode. In addition, as a result, the generation of a residual image can be prevented or some charges can be prevented from remaining untransmitted.

[0346] In the imaging elements of the first to fifth structures, the larger the n value, the farther the photoelectric conversion section is from the first electrode. Whether the photoelectric conversion section is far away from the first electrode is judged based on the X direction. In addition, in the imaging element of the sixth structure, when the direction away from the first electrode is the X direction, the "X direction" is defined as follows. That is, the pixel area in which a plurality of imaging elements or a plurality of stacked imaging elements are arranged includes a plurality of pixels arranged in a two-dimensional array, that is, a plurality of pixels regularly arranged in the X direction and the Y direction. In the case where the planar shape of the pixel is a rectangle, the extension direction of the side closest to the first electrode is the Y direction, and the direction orthogonal to the Y direction is the X direction. Alternatively, in the case where the pixel has an arbitrary planar shape, the overall direction including the line segment or curve closest to the first electrode is the Y direction, and the direction orthogonal to the Y direction is the X direction.

[0347] Regarding the imaging elements of the first to sixth structures, the case where the potential of the first electrode is higher than the potential of the second electrode will be described below.

[0348] In the imaging element of the first configuration, the thickness of the insulating layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. The thickness of the insulating layer section preferably gradually increases. Thus, a charge transfer gradient is formed. Then, V is established during the charge accumulation period. 31 ≥V 11 In the case of the state of , the nth photoelectric conversion section can accumulate more charge and is applied with a stronger electric field than the (n+1)th photoelectric conversion section. Therefore, it is possible to reliably prevent the charge from flowing from the first photoelectric conversion section to the first electrode. In addition, V is established during the charge transfer period. 32 <V 12 In the case of the state of , it can be reliably ensured that charges flow from the first photoelectric conversion region to the first electrode and that charges flow from the (n+1)th photoelectric conversion region to the nth photoelectric conversion region.

[0349] In the second configuration of the imaging element, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. The thickness of the photoelectric conversion layer section preferably gradually increases. Thus, a charge transfer gradient is formed. Then, V is established during the charge accumulation period. 31 ≥V 11 In the case of the state of , a stronger electric field is applied to the nth photoelectric conversion section than to the (n+1)th photoelectric conversion section. Therefore, it is possible to reliably prevent the flow of charge from the first photoelectric conversion section to the first electrode. In addition, V is established during the charge transfer period. 32 <V 12In the case of the state of , it can be reliably ensured that charges flow from the first photoelectric conversion region to the first electrode and that charges flow from the (n+1)th photoelectric conversion region to the nth photoelectric conversion region.

[0350] In the imaging element of the third configuration, the materials contained in the insulating layer sections are different between adjacent photoelectric converter sections, thereby forming a charge transfer gradient. Preferably, the dielectric constant of the material contained in the insulating layer sections gradually decreases from the first photoelectric converter section to the Nth photoelectric converter section. By adopting this configuration, V is established during the charge accumulation period. 31 ≥V 11 In the case of the state of n, the nth photoelectric conversion section can accumulate more charge than the (n+1)th photoelectric conversion section. In addition, V is established during the charge transfer period. 32 <V 12 In the case of the state of , it can be reliably ensured that charges flow from the first photoelectric conversion region to the first electrode and that charges flow from the (n+1)th photoelectric conversion region to the nth photoelectric conversion region.

[0351] In the imaging element of the fourth configuration, the materials contained in the charge accumulation electrode segments differ between adjacent photoelectric converter segments, thereby forming a charge transfer gradient. Preferably, the work function value of the material contained in the insulating layer segments gradually increases from the first photoelectric converter segment to the Nth photoelectric converter segment. This configuration creates a potential gradient that facilitates signal charge transfer, regardless of whether the voltage (potential) is positive or negative.

[0352] In the imaging element of the fifth configuration, the area of ​​the charge accumulation electrode section gradually decreases from the first photoelectric conversion section to the Nth photoelectric conversion section, thereby forming a charge transfer gradient. Therefore, V is established during the charge accumulation period. 31 ≥V 11 In the case of the state of n, the nth photoelectric conversion section can accumulate more charge than the (n+1)th photoelectric conversion section. In addition, V is established during the charge transfer period. 32 <V 12 In the case of the state of , it can be reliably ensured that charges flow from the first photoelectric conversion region to the first electrode and that charges flow from the (n+1)th photoelectric conversion region to the nth photoelectric conversion region.

[0353] In the imaging element of the sixth configuration, the cross-sectional area of ​​the stacked portion changes according to the distance from the first electrode, thereby forming a charge transfer gradient. Specifically, by adopting a configuration in which the cross-sectional thickness of the stacked portion is constant and the cross-sectional width of the stacked portion decreases as the distance from the first electrode increases, similar to the description of the imaging element of the fifth configuration, a V is established during the charge accumulation period. 31 ≥V 11 In the case of the state of , the area close to the first electrode can accumulate more charges than the area far from the first electrode. Therefore, V is established during the charge transfer period. 32 <V 12 In the case of a state of , it can be reliably ensured that charges flow from the area close to the first electrode to the first electrode and that charges flow from the farther area to the closer area. On the contrary, by adopting a structure in which the cross-sectional width of the stacked portion is constant and the cross-sectional thickness of the stacked portion gradually increases, specifically, the thickness of the insulating layer section gradually increases, then similar to the description of the imaging element of the first structure, V is established during the charge accumulation period. 31 ≥V 11 In the case of a state where V is established during the charge transfer period, the region close to the first electrode can accumulate more charge and be subjected to a stronger electric field than the region far from the first electrode, thereby reliably preventing the charge from flowing from the region close to the first electrode to the first electrode. 32 <V 12 In the case of a state of , it is possible to reliably ensure that charges flow from a region close to the first electrode to the first electrode and that charges flow from a farther region to a closer region. In addition, by adopting a configuration in which the thickness of the photoelectric conversion layer segment gradually increases, similar to the description of the imaging element of the second configuration, V is established during the charge accumulation period. 31 ≥V 11 In the case of a state where V is applied to a region close to the first electrode, a stronger electric field is applied to a region far from the first electrode than to a region close to the first electrode, thereby reliably preventing charge from flowing from a region close to the first electrode to the first electrode. In addition, V is established during the charge transfer period. 32 <V 12 In the case of a state, it can be reliably ensured that charges flow from an area close to the first electrode to the first electrode and that charges flow from a farther area to a closer area.

[0354] If necessary, two or more types of imaging elements including the first to sixth structures of the above-described preferred aspects may be appropriately combined.

[0355] As a modification example of the solid-state imaging device according to the first and second aspects of the present disclosure, the solid-state imaging device may have a configuration in which:

[0356] The solid-state imaging device includes any one of a plurality of imaging elements of the first to sixth configurations.

[0357] A plurality of imaging elements constitute an imaging element block, and

[0358] The first electrode is shared by a plurality of imaging elements constituting the imaging element block. For convenience, a solid-state imaging device having such a structure is referred to as a "solid-state imaging device of the first structure". Alternatively, as a modified example of the solid-state imaging device according to the first aspect and the second aspect of the present disclosure, the solid-state imaging device may have the following structure: wherein,

[0359] The solid-state imaging device includes any one of a plurality of imaging elements of the first to sixth configurations, or includes a plurality of stacked imaging elements including at least one of the imaging elements of the first to sixth configurations.

[0360] A plurality of imaging elements or a plurality of stacked imaging elements constitute an imaging element block, and

[0361] The first electrode is shared by multiple imaging elements or multiple stacked imaging elements that make up the imaging element block. For convenience, a solid-state imaging device having this configuration will be referred to as a "solid-state imaging device having the second configuration." Furthermore, by sharing the first electrode by multiple imaging elements that make up the imaging element block as described above, the configuration and structure of the pixel region where the multiple imaging elements are arranged can be simplified and miniaturized.

[0362] In the solid-state imaging devices of the first and second structures, a floating diffusion layer is provided for a plurality of imaging elements (an imaging element block). Here, the plurality of imaging elements provided for a floating diffusion layer may include a plurality of first-type imaging elements to be described later, or may include at least one first-type imaging element and one or more second-type imaging elements to be described later. In addition, by appropriately controlling the timing of the charge transfer period, a plurality of imaging elements are allowed to share a floating diffusion layer. The plurality of imaging elements operate in cooperation and are connected to a drive circuit to be described later as an imaging element block. That is, the plurality of imaging elements constituting the imaging element block are connected to a drive circuit. However, control of the charge accumulation electrode is performed for each imaging element. In addition, the plurality of imaging elements may share a contact hole portion. The arrangement relationship between the first electrode shared by the plurality of imaging elements and the charge accumulation electrode of each imaging element may be such that, in some cases, the first electrode is arranged adjacent to the charge accumulation electrode of each imaging element. Alternatively, the first electrode may be arranged adjacent to the charge accumulation electrodes of some of the plurality of imaging elements, and not adjacent to the charge accumulation electrodes of the remaining imaging elements of the plurality of imaging elements. In this case, the movement of charge from the remaining imaging elements of the plurality of imaging elements to the first electrode is via the movement of some of the plurality of imaging elements. In order to ensure that the charge moves from each imaging element to the first electrode, preferably, the distance between the charge accumulation electrode included in the imaging element and the charge accumulation electrode included in the imaging element (for convenience, referred to as "distance A") is longer than the distance between the first electrode and the charge accumulation electrode in the imaging element adjacent to the first electrode (for convenience, referred to as "distance B"). In addition, preferably, the value of distance A increases as the imaging element is farther away from the first electrode. It should be noted that the above description applies not only to the solid-state imaging devices of the first construction and the second construction, but also to the solid-state imaging devices of the first aspect and the second aspect of the present disclosure.

[0363] In addition, in the imaging element of the present disclosure including the various preferred forms described above, a form can be adopted in which light is incident from the second electrode side and a light-shielding layer is formed on the light-incident side closer to the second electrode. Alternatively, a form can be adopted in which light is incident from the second electrode side and the light is not incident on the first electrode (as the case may be, the light is not incident on the first electrode and the transmission control electrode). In addition, in this case, a structure can be adopted in which a light-shielding layer is formed on the light-incident side closer to the second electrode and above the first electrode (as the case may be, the first electrode and the transmission control electrode). Alternatively, a structure can be adopted in which an on-chip microlens is provided above the charge accumulation electrode and the second electrode, and the light incident on the on-chip microlens is converged on the charge accumulation electrode. Here, the light-shielding layer can be arranged above the surface of the light-incident side of the second electrode, or can be arranged on the surface of the light-incident side of the second electrode. As the case may be, the light-shielding layer can be formed in the second electrode. Examples of the material contained in the light shielding layer include chromium (Cr), copper (Cu), aluminum (Al), tungsten (W), and a light-impermeable resin (eg, polyimide resin).

[0364] Specific examples of the imaging element and the like disclosed herein include: an imaging element including a photoelectric conversion layer or a photoelectric conversion portion (for convenience, referred to as a “first type blue light photoelectric conversion layer” or a “first type blue light photoelectric conversion portion”) that absorbs blue light (light of 425 nm to 495 nm) and is sensitive to blue light (for convenience, referred to as a “first type blue light imaging element”); an imaging element including a photoelectric conversion layer or a photoelectric conversion portion (for convenience, referred to as a “first type blue light imaging element”) that absorbs green light (light of 495 nm to 570 nm); The invention relates to an imaging element that includes a photoelectric conversion layer or a photoelectric conversion portion that absorbs red light (light of 620nm to 750nm) and is sensitive to red light (for the sake of convenience, it is referred to as a "first type photoelectric conversion layer for red light" or a "first type photoelectric conversion portion for red light") and is sensitive to green light (for the sake of convenience, it is referred to as a "first type imaging element for red light"). In addition, for the sake of convenience, the existing imaging element that does not include a charge accumulation electrode and is sensitive to blue light is referred to as a "second type imaging element for blue light". For the sake of convenience, the existing imaging element that does not include a charge accumulation electrode and is sensitive to green light is referred to as a "second type imaging element for green light". For the sake of convenience, the existing imaging element that does not include a charge accumulation electrode and is sensitive to red light is referred to as a "second type imaging element for red light". For convenience, the photoelectric conversion layer or photoelectric conversion section included in the second-type blue light imaging element is referred to as the "second-type blue light photoelectric conversion layer" or "second-type blue light photoelectric conversion section." For convenience, the photoelectric conversion layer or photoelectric conversion section included in the second-type green light imaging element is referred to as the "second-type green light photoelectric conversion layer" or "second-type green light photoelectric conversion section." For convenience, the photoelectric conversion layer or photoelectric conversion section included in the second-type red light imaging element is referred to as the "second-type red light photoelectric conversion layer" or "second-type red light photoelectric conversion section."

[0365] The stacked image pickup element of the present disclosure includes at least one image pickup element or the like (photoelectric conversion element) of the present disclosure, and specific examples of the configuration and structure of the stacked image pickup element include the following configurations and structures:

[0366] [A] a first-type blue light photoelectric conversion portion, a first-type green light photoelectric conversion portion, and a first-type red light photoelectric conversion portion are stacked in a vertical direction, and

[0367] A control unit for the first type blue light imaging element, a control unit for the first type green light imaging element, and a control unit for the first type red light imaging element are respectively provided in the semiconductor substrate;

[0368] [B] The first type blue light photoelectric conversion portion and the first type green light photoelectric conversion portion are stacked in a vertical direction,

[0369] Below the two layers of the first type photoelectric conversion unit, a second type photoelectric conversion unit for red light is arranged, and

[0370] A control unit for the first type blue light imaging element, a control unit for the first type green light imaging element, and a control unit for the second type red light imaging element are respectively provided in the semiconductor substrate;

[0371] [C] the second type photoelectric conversion portion for blue light and the second type photoelectric conversion portion for red light are arranged below the first type photoelectric conversion portion for green light, and

[0372] A control unit for the first type green light imaging element, a control unit for the second type blue light imaging element, and a control unit for the second type red light imaging element are each provided in the semiconductor substrate; and

[0373] [D] the second type photoelectric conversion portion for green light and the second type photoelectric conversion portion for red light are arranged below the first type photoelectric conversion portion for blue light, and

[0374] The control unit of the first-type blue light imaging element, the control unit of the second-type green light imaging element, and the control unit of the second-type red light imaging element are respectively provided in the semiconductor substrate.

[0375] Preferably, the order of arrangement of the photoelectric conversion units of these imaging elements in the vertical direction is the order of blue light photoelectric conversion unit, green light photoelectric conversion unit and red light photoelectric conversion unit from the light incident direction, or the order of green light photoelectric conversion unit, blue light photoelectric conversion unit and red light photoelectric conversion unit from the light incident direction. One of the reasons is that light with shorter wavelengths is efficiently absorbed on the incident surface side. Since red has the longest wavelength among the three colors, the red light photoelectric conversion unit is preferably located at the bottom layer when observed from the light incident surface. The stacked structure of these imaging elements constitutes one pixel. In addition, a first type near-infrared photoelectric conversion unit (alternatively, an infrared photoelectric conversion unit) can be provided. Here, preferably, the photoelectric conversion layer of the first type infrared photoelectric conversion unit contains, for example, an organic material, and is arranged in the bottom layer of the stacked structure of the first type imaging element and above the second type imaging element. Alternatively, a second type near-infrared photoelectric conversion unit (alternatively, an infrared photoelectric conversion unit) can be provided below the first type photoelectric conversion unit.

[0376] In the first type imaging element, for example, the first electrode is formed on an interlayer insulating layer provided on a semiconductor substrate. The imaging element formed on the semiconductor substrate may be a back-illuminated type or a front-illuminated type.

[0377] In the case where the photoelectric conversion layer includes an organic material, the photoelectric conversion layer can adopt any one of the following four aspects.

[0378] (1) The photoelectric conversion layer includes a p-type organic semiconductor.

[0379] (2) The photoelectric conversion layer includes an n-type organic semiconductor.

[0380] (3) The photoelectric conversion layer comprises a stacked structure of a p-type organic semiconductor layer / an n-type organic semiconductor layer. The photoelectric conversion layer comprises a stacked structure of a p-type organic semiconductor layer / a mixed layer of a p-type organic semiconductor and an n-type organic semiconductor (bulk heterostructure) / an n-type organic semiconductor layer. The photoelectric conversion layer comprises a stacked structure of a p-type organic semiconductor layer / a mixed layer of a p-type organic semiconductor and an n-type organic semiconductor (bulk heterostructure). The photoelectric conversion layer comprises an n-type organic semiconductor layer / a mixed layer of a p-type organic semiconductor and an n-type organic semiconductor (bulk heterostructure).

[0381] (4) The photoelectric conversion layer includes a mixture of a p-type organic semiconductor and an n-type organic semiconductor (bulk heterostructure). Note that the order of stacking can be arbitrarily changed.

[0382] Examples of p-type organic semiconductors include naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, tetracene derivatives, pentacene derivatives, quinacridone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzothiophene-benzothiophene derivatives, triallylamine derivatives, carbazole derivatives, perylene derivatives, chrysene derivatives, Derivatives, fluoranthene derivatives, phthalocyanine derivatives, subphthalocyanine derivatives, subporphyrazine derivatives, metal complexes containing heterocyclic compounds as ligands, polythiophene derivatives, polybenzothiadiazole derivatives, and polyfluorene derivatives. Examples of n-type organic semiconductors include fullerenes and fullerene derivatives (e.g., fullerenes such as C60, C70, and C74 (higher fullerenes) or endohedral fullerenes, or fullerene derivatives (e.g., fullerene fluorides, PCBM fullerene compounds, or fullerene multimers), organic semiconductors having larger (deeper) HOMO and LUMO than p-type organic semiconductors, and transparent inorganic metal oxides. Specific examples of n-type organic semiconductors include: organic molecules including, as part of a molecular skeleton, a heterocyclic compound containing a nitrogen atom, an oxygen atom, and a sulfur atom, such as a pyridine derivative, a pyrazine derivative, a pyrimidine derivative, a triazine derivative, a quinoline derivative, a quinoxaline derivative, an isoquinoline derivative, an acridine derivative, a phenazine derivative, a phenanthroline derivative, a tetrazole derivative, a pyrazole derivative, an imidazole derivative, a thiazole derivative, an oxazole derivative, an imidazole derivative, a benzimidazole derivative, a benzotriazole derivative, a benzoxazole derivative, a benzoxazole derivative, a carbazole derivative, a benzofuran derivative, a dibenzofuran derivative, a porphyrin derivative, a polyphenylenevinylene derivative, a polybenzothiadiazole derivative, and a polyfluorene derivative; organometallic complexes; and subphthalocyanine derivatives. Examples of the groups and the like included in the fullerene derivative include: a halogen atom; a linear, branched, or cyclic alkyl group or phenyl group; a group including a linear or condensed aromatic compound; a group including a halide; a partially fluorinated alkyl group; a perfluoroalkyl group; a silylalkyl group; a silylalkoxy group; an arylsilyl group; an arylsulfanyl group; an alkylsulfanyl group; an arylsulfonyl group; an alkylsulfonyl group; an arylthio group; an alkylthio group; an amino group; an alkylamino group; an arylamino group; a hydroxyl group; an alkoxy group; an acylamino group; an acyloxy group; a carbonyl group; a carboxyl group; a carboxamide group; a carboxyalkyloxy group; an acyl group; a sulfonyl group; a cyano group; a nitro group; a group including a chalcogenide compound; a phosphino group; a phosphonic acid group; and derivatives of the above groups. The thickness of the photoelectric conversion layer including an organic material (in some cases, referred to as an "organic photoelectric conversion layer") is not limited, and the thickness may be, for example, 1×10 -8 m to 5×10 -7 m, preferably 2.5×10 -8 m to 3×10 -7 m, more preferably 2.5×10 -8 m to 2×10-7 m, and more preferably 1×10 -7 m to 1.8×10 -7 m. It should be noted that organic semiconductors are generally classified as p-type or n-type. P-type means that holes are easily transported, and n-type means that electrons are easily transported. As with inorganic semiconductors, organic semiconductors are not limited to being interpreted as having either holes or electrons as thermally excited majority carriers.

[0383] Alternatively, examples of materials included in the organic photoelectric conversion layer that performs photoelectric conversion on green light include rhodamine-based dyes, merocyanine-based dyes, quinacridone derivatives, and subphthalocyanine-based dyes (subphthalocyanine derivatives). Examples of materials included in the organic photoelectric conversion layer that performs photoelectric conversion on blue light include coumaric acid dyes, tris-8-hydroxyquinoline aluminum (Alq3), and merocyanine-based dyes. Examples of materials included in the organic photoelectric conversion layer that performs photoelectric conversion on red light include phthalocyanine-based dyes and subphthalocyanine-based dyes (subphthalocyanine derivatives).

[0384] Alternatively, examples of inorganic materials included in the photoelectric conversion layer include: crystalline silicon; amorphous silicon; microcrystalline silicon; crystalline selenium; amorphous selenium; chalcopyrite compounds such as CIGS (CuInGaSe), CIS (CuInSe2), CuInS2, CuAlS2, CuAlSe2, CuGaS2, CuGaSe2, AgAlS2, AgAlSe2, AgInS2, and AgInSe2; or Group III-V compounds such as GaAs, InP, AlGaAs, InGaP, AlGaInP, and InGaAsP; in addition, compound semiconductors such as CdSe, CdS, In2Se3, In2S3, Bi2Se3, Bi2S3, ZnSe, ZnS, PbSe, and PbS. In addition, quantum dots including these materials can also be used in the photoelectric conversion layer.

[0385] The solid-state image pickup devices according to the first and second aspects of the present disclosure and the solid-state image pickup devices of the first and second configurations can constitute a single-plate color solid-state image pickup device.

[0386] In a solid-state imaging device according to the second aspect of the present disclosure that includes a stacked imaging element, unlike a solid-state imaging device that includes an imaging element with a Bayer arrangement (i.e., a color filter layer is not used to perform blue, green, or red color separation), imaging elements sensitive to multiple wavelengths of light are stacked in the direction of light incidence within the same pixel to form a single pixel. Therefore, the sensitivity and pixel density per unit volume can be improved. In addition, since organic materials have a high absorption coefficient, the thickness of the organic photoelectric conversion layer can be reduced compared to existing Si-based photoelectric conversion layers. Therefore, light leakage from adjacent pixels is reduced and restrictions on the angle of light incidence are relaxed. In addition, although existing Si-based imaging elements generate false colors due to interpolation processing performed on pixels of three colors to generate color signals, in a solid-state imaging device according to the second aspect of the present disclosure that includes a stacked imaging element, the generation of false colors can be suppressed. The organic photoelectric conversion layer itself also acts as a color filter layer, so color separation can be performed without arranging a color filter layer.

[0387] At the same time, in the solid-state imaging device according to the first aspect of the present disclosure, by adopting a color filter layer, the requirements for the spectral characteristics of blue, green and red can be relaxed, and high-volume production is provided. Examples of the arrangement of imaging elements in the solid-state imaging device according to the first aspect of the present disclosure include interline arrangement, G stripe RB grid arrangement, G stripe RB full grid arrangement, grid complementary color arrangement, stripe arrangement, oblique stripe arrangement, primary color difference arrangement, field color difference sequential arrangement, frame color difference sequential arrangement, MOS type arrangement, improved MOS type arrangement, frame interleaved arrangement and field interleaved arrangement, and Bayer arrangement. Here, one imaging element constitutes one pixel (or sub-pixel).

[0388] Examples of color filter layers (wavelength selection means) include those that transmit not only red, green, and blue colors but also, depending on the situation, specific wavelengths such as cyan, magenta, and yellow. Color filter layers can be composed not only of organic material-based color filter layers using organic compounds such as pigments or dyes, but also of thin films made of inorganic materials such as photonic crystals, wavelength selection elements based on the application of plasmons (color filter layers having a conductor grid structure having a grid-like pore structure in a conductor thin film; for example, see Japanese Unexamined Patent Application Publication No. 2008-177191), or amorphous silicon.

[0389] The pixel region in which multiple imaging elements of the present disclosure, or stacked imaging elements of the present disclosure, are arranged includes a plurality of pixels regularly arranged in a two-dimensional array. Typically, the pixel region includes: an effective pixel region, in which light is actually received to generate signal charge through photoelectric conversion, and this signal charge is amplified and read out to a drive circuit; and a black reference pixel region (also known as an optical black pixel region (OPB)), which is used to output optical black, which serves as a black level reference. The black reference pixel region is typically arranged outside the effective pixel region.

[0390] In the imaging element and other devices of the present disclosure, including the various preferred embodiments described above, light irradiation is performed, photoelectric conversion occurs in the photoelectric conversion layer, and carrier separation of holes and electrons occurs. Furthermore, the electrode that extracts holes is the anode, and the electrode that extracts electrons is the cathode. The first electrode constitutes the cathode, and the second electrode constitutes the anode.

[0391] A structure can be adopted in which the first electrode, the charge accumulation electrode, the transfer control electrode, the charge transfer control electrode, the charge discharge electrode, and the second electrode include a transparent conductive material. In some cases, the first electrode, the charge accumulation electrode, the transfer control electrode, the charge transfer control electrode, and the charge discharge electrode are collectively referred to as "first electrode, etc.". Alternatively, in the case where the imaging element, etc. of the present disclosure are arranged on a plane in a manner such as a Bayer arrangement, a structure can be adopted in which the second electrode includes a transparent conductive material and the first electrode, etc. include a metal material. In this case, specifically, the following structure can be adopted: the second electrode located on the light incident side includes a transparent conductive material, and the first electrode, etc. includes, for example, Al-Nd (an alloy of aluminum and neodymium) or ASC (an alloy of aluminum, samarium, and copper). In some cases, the electrode including the transparent conductive material is referred to as a "transparent electrode." Here, ideally, the band gap energy of the transparent conductive material is 2.5 eV or more, preferably 3.1 eV or more. Examples of the transparent conductive material included in the transparent electrode include conductive metal oxides. Specifically, examples of the transparent conductive material include: indium oxide; indium tin oxide (ITO: indium tin oxide, including In2O3 doped with Sn, crystalline ITO and amorphous ITO); indium zinc oxide (IZO: indium zinc oxide) in which indium is added as a dopant to zinc oxide; indium gallium oxide (IGO) in which indium is added as a dopant to gallium oxide; indium-gallium-zinc oxide (IGZO: In-GaZnO4) in which indium and gallium are added as dopants to zinc oxide; indium-tin-zinc oxide (ITZO) in which indium and tin are added as dopants to zinc oxide; IFO (In2O3 doped with F); tin oxide ( SnO2); ATO (SnO2 doped with Sb); FTO (SnO2 doped with F); zinc oxide (including ZnO doped with other elements); aluminum zinc oxide (AZO) in which aluminum is added as a dopant to zinc oxide; gallium zinc oxide (GZO) in which gallium is added as a dopant to zinc oxide; titanium oxide (TiO2); niobium titanium oxide (TNO) in which niobium is added as a dopant to titanium oxide; antimony oxide; CuI; InSbO4; ZnMgO; CuInO2; MgIn2O4; CdO; ZnSnO3; spinel-type oxides; and oxides having a YbFe2O4 structure. Alternatively, the transparent electrode may include gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like as a mother layer. An example of the thickness of the transparent electrode may be 2×10 -8 m to 2×10 -7 m, preferably 3×10 -8 m to 1×10 -7 In the case where the first electrode must be transparent, the charge discharge electrode also preferably includes a transparent conductive material from the viewpoint of simplifying the manufacturing process.

[0392] Alternatively, when transparency is not required, as the conductive material contained in the cathode serving as an electrode for extracting electrons, a conductive material having a low work function (e.g., φ = 3.5 eV to 4.5 eV) is preferably used. Specifically, examples of such conductive materials include alkali metals (e.g., Li, Na, and K), alkali metal fluorides or alkali metal oxides, alkaline earth metals (e.g., Mg and Ca), alkali earth metal fluorides or alkaline earth metal oxides, aluminum (Al), zinc (Zn), tin (Sn), thallium (Tl), sodium-potassium alloys, aluminum-lithium alloys, magnesium-silver alloys, indium, rare earth metals such as ytterbium, and alloys of the above materials. Alternatively, examples of materials included in the cathode include conductive materials including: metals such as platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co), or molybdenum (Mo); alloys including these metal elements; conductive particles including these metals; conductive particles containing alloys of these metals; polycrystalline silicon including impurities; carbon-based materials; oxide semiconductor materials; carbon nanotubes; and graphene, and examples of materials included in the cathode include a stacked structure of layers containing these elements. Further examples of materials included in the cathode include organic materials (conductive polymers) such as poly(3,4-ethylenedioxythiophene) / polystyrenesulfonic acid [PEDOT / PSS]. In addition, these conductive materials can be mixed with a binder (polymer) to form a paste or ink, and the paste or ink can be hardened and used as an electrode.

[0393] Dry or wet method can be used as the film forming method of the first electrode etc. and the second electrode (cathode or anode).The example of dry method includes physical vapor deposition (PVD method) and chemical vapor deposition (CVD method).The example of the film forming method using PVD method principle includes vacuum deposition method, EB (electron beam) deposition method, various sputtering methods (magnetron sputtering method, RF-DC coupled bias sputtering method, ECR sputtering method, target sputtering method and high frequency sputtering method), ion plating method, laser ablation method, molecular beam epitaxy method and laser transfer method.In addition, the example of CVD method includes plasma CVD method, thermal CVD method, organometallic (MO) CVD method and light CVD method.Meanwhile, the example of wet method includes electroplating and chemical plating, spin coating, inkjet method, spray coating, stamping method, micro-contact printing method, flexographic printing method, offset printing method, gravure printing method, impregnation method etc. Examples of patterning methods include chemical etching using a shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or lasers. Examples of planarization techniques for the first electrode and the second electrode include laser planarization, reflow, and CMP (Chemical Mechanical Polishing).

[0394] Examples of the material contained in the insulating layer include not only silicon oxide materials, silicon nitride (SiN Y ) and aluminum oxide (Al2O3) as examples of inorganic insulating materials, and also include organic insulating materials (organic polymers) such as the following materials: polymethyl methacrylate (PMMA); polyvinylphenol (PVP); polyvinyl alcohol (PVA); polyimide; polycarbonate (PC); polyethylene terephthalate (PET); polystyrene; silanol derivatives (silane coupling agents) such as N-2 (aminoethyl) 3-aminopropyltrimethoxysilane (AEAPTMS), 3-mercaptopropyltrimethoxysilane (MPTMS) and octadecyltrichlorosilane (OTS); novolac-type phenolic resin; fluorine-based resin; linear hydrocarbons having a functional group capable of bonding to a control electrode at one end such as octadecyl mercaptan and dodecyl isocyanate, and also include combinations of the above materials. Examples of silicon oxide-based materials include silicon oxide (SiO X), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on glass) and low dielectric constant insulating materials (for example, polyarylether, cyclic perfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon and organic SOG). The insulating layer can have a single-layer structure or a structure including a plurality of stacked layers (for example, two layers). In the latter case, an insulating layer / lower layer can be formed at least on the charge accumulation electrode and in the region between the charge accumulation electrode and the first electrode. The insulating layer / lower layer can be flattened to leave an insulating layer / lower layer at least in the region between the charge accumulation electrode and the first electrode. It is sufficient to form an insulating layer / upper layer on the remaining insulating layer / lower layer and the charge accumulation electrode. In this way, the insulating layer can be reliably flattened. It is sufficient to appropriately select materials for forming various interlayer insulating layers, protective material layers and insulating material layers from these materials.

[0395] The configuration and structure of the floating diffusion layer, amplifying transistor, reset transistor, and selection transistor included in the control unit may be similar to those of existing floating diffusion layers, amplifying transistors, reset transistors, and selection transistors. The driving circuit may also have a well-known configuration and structure.

[0396] When the first electrode is connected to the floating diffusion layer and the gate portion of the amplifying transistor, it is sufficient to form a contact hole portion to connect the first electrode to the floating diffusion layer and the gate portion of the amplifying transistor. Examples of materials for forming the contact hole portion include polycrystalline silicon doped with impurities, high melting point metals such as tungsten, Ti, Pt, Pd, Cu, TiW, TiN, TiNW, WSi2, or MoSi2, and metal silicides, as well as stacked structures including layers of these materials (e.g., Ti / TiN / W).

[0397] A first carrier blocking layer may be provided between the inorganic oxide semiconductor material layer and the first electrode, and a second carrier blocking layer may be provided between the organic photoelectric conversion layer and the second electrode. In addition, a first charge injection layer may be provided between the first carrier blocking layer and the first electrode, and a second charge injection layer may be provided between the second carrier blocking layer and the second electrode. For example, examples of materials included in the electron injection layer include: alkali metals, including lithium (Li), sodium (Na), and potassium (K); alkali metal fluorides or alkali metal oxides; alkaline earth metals, including magnesium (Mg) and calcium (Ca); and alkaline earth metal fluorides or alkaline earth metal oxides.

[0398] Examples of film forming methods for various organic layers include dry film forming methods and wet film forming methods. Examples of dry film forming methods include vacuum deposition methods using resistance heating, high-frequency heating, or electron beam heating; flash deposition methods; plasma deposition methods; EB deposition methods; various sputtering methods (bipolar sputtering, DC sputtering, DC magnetron sputtering, high-frequency sputtering, magnetron sputtering, RF-DC coupled bias sputtering, ECR sputtering, target sputtering, ion beam sputtering); DC (Direct Current: DC) method; RF method; multi-cathode method; activation reaction method; electric field deposition method; various ion plating methods including high-frequency ion plating and reactive ion plating; laser ablation method; molecular beam epitaxy; laser transfer method; and molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method. In addition, examples of CVD methods include plasma CVD method, thermal CVD method, MOCVD method, and optical CVD method. Meanwhile, specific examples of wet methods include spin coating, dipping, casting, micro-contact printing, drop casting, various printing methods including screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spray coating, and various coating methods including air knife coater, blade coater, rod coater, knife coater, extrusion coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, casting coater, spray coater, slit hole coater, and calendar coater. In the coating method, examples of solvents include non-polar or low-polar organic solvents including toluene, chloroform, hexane, and ethanol. Examples of patterning methods include chemical etching including shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. Examples of planarization techniques for various organic layers include a laser planarization method, a reflow method, and the like.

[0399] As described above, an on-chip microlens and a light shielding layer can be provided on the imaging element or solid-state imaging device as needed, and a drive circuit and wiring for driving the imaging element can be provided. A shutter for controlling the incidence of light on the imaging element can be provided as needed, and an optical cutoff filter can be provided depending on the purpose of the solid-state imaging device.

[0400] Furthermore, the solid-state imaging devices of the first and second configurations may employ a configuration in which a single on-chip microlens is provided above one of the imaging elements disclosed herein. Alternatively, a configuration may be employed in which two imaging elements disclosed herein constitute an imaging element block, and a single on-chip microlens is provided above the imaging element block.

[0401] For example, when stacking a solid-state imaging device and a readout integrated circuit (ROIC), stacking can be achieved by stacking a drive substrate having the readout integrated circuit and a copper (Cu) connection formed thereon, and an imaging element having a connection formed thereon so that their respective connection portions come into contact with each other, and then bonding these connection portions to each other. The bonding can be achieved using solder bumps or the like.

[0402] Furthermore, the driving method for driving the solid-state image pickup device according to the first and second aspects of the present disclosure may be a driving method for the solid-state image pickup device that repeats the following steps:

[0403] In all imaging elements, while accumulating charges in the inorganic oxide semiconductor material layer (alternatively, the inorganic oxide semiconductor material layer and the photoelectric conversion layer), the charges in the first electrode are immediately discharged to the outside of the system; thereafter,

[0404] In all imaging elements, the charges accumulated in the inorganic oxide semiconductor material layer (alternatively, the inorganic oxide semiconductor material layer and the photoelectric conversion layer) are simultaneously transferred to the first electrode, and after the transfer is completed, the charges transferred to the first electrode are sequentially read out in each imaging element.

[0405] In this driving method for a solid-state imaging device, each imaging element has a structure in which light incident from the second electrode side does not strike the first electrode. In all imaging elements, charge is simultaneously accumulated in the inorganic oxide semiconductor material layer, etc., while the charge in the first electrode is simultaneously discharged to the outside of the system. Therefore, the first electrode can be reliably reset simultaneously in all imaging elements. Subsequently, the charge accumulated in the inorganic oxide semiconductor material layer, etc., is simultaneously transferred to the first electrode in all imaging elements. After the transfer is complete, the charge transferred to the first electrode is sequentially read out in each imaging element. This makes it easy to implement a so-called global shutter function.

[0406] The image pickup element and the solid-state image pickup device of Example 1 will be described in detail below.

[0407] The imaging element of Example 1 further includes a semiconductor substrate (more specifically, a silicon semiconductor layer) 70, and a photoelectric conversion unit is arranged above the semiconductor substrate 70. Furthermore, the imaging element further includes a control unit, which is provided in the semiconductor substrate 70 and includes a drive circuit connected to the first electrode 21 and the second electrode 22. Here, the light incident surface of the semiconductor substrate 70 is defined as the upper side, and the opposite side of the semiconductor substrate 70 is defined as the lower side. A wiring layer 62 including a plurality of wiring lines is provided below the semiconductor substrate 70.

[0408] In the semiconductor substrate 70, at least the floating diffusion layer FD1 and the amplifier transistor TR1 included in the control section are provided. amp , and the first electrode 21 is connected to the floating diffusion layer FD1 and the amplifying transistor TR1 amp The semiconductor substrate 70 is also provided with a reset transistor TR1 included in the control unit. rst and select transistor TR1 sel The floating diffusion layer FD1 is connected to the reset transistor TR1 rst A source / drain region of the amplifier transistor TR1 amp The other source / drain region of the select transistor TR1 is connected to sel A source / drain region of the selection transistor TR1. sel The other source / drain region of the amplifying transistor TR1 is connected to the signal line VSL1. amp , reset transistor TR1 rst and select transistor TR1 sel constitute the driving circuit.

[0409] Specifically, the imaging element and stacked imaging element of Example 1 are back-illuminated imaging elements and stacked imaging elements, and have a structure in which three imaging elements are stacked. These three imaging elements are: the first-type green light imaging element of Example 1 (hereinafter referred to as the "first imaging element"), which includes a first-type green light photoelectric conversion layer that absorbs green light and is sensitive to green light; the conventional second-type blue light imaging element (hereinafter referred to as the "second imaging element"), which includes a second-type blue light photoelectric conversion layer that absorbs blue light and is sensitive to blue light; and the conventional second-type red light imaging element (hereinafter referred to as the "third imaging element"), which includes a second-type red light photoelectric conversion layer that absorbs red light and is sensitive to red light. Here, the red light imaging element (third imaging element) 12 and the blue light imaging element (second imaging element) 11 are provided in the semiconductor substrate 70, and the second imaging element 11 is closer to the light incident side than the third imaging element 12. The green light image sensor (first image sensor 10) is provided above the blue light image sensor (second image sensor 11). The stacked structure of the first image sensor 10, the second image sensor 11, and the third image sensor 12 constitutes one pixel. No color filter layer is provided.

[0410] In the first imaging element 10, the first electrode 21 and the charge accumulation electrode 24 are formed on the interlayer insulating layer 81 and separated from each other. The interlayer insulating layer 81 and the charge accumulation electrode 24 are covered by an insulating layer 82. An inorganic oxide semiconductor material layer 23C, a protective layer 23B, and a photoelectric conversion layer 23A are formed on the insulating layer 82, and the second electrode 22 is formed on the photoelectric conversion layer 23A. A protective material layer 83 is formed over the entire surface including the second electrode 22, and an on-chip microlens 14 is provided on the protective material layer 83. No color filter layer is provided. The first electrode 21, the charge accumulation electrode 24, and the second electrode 22 are formed of transparent electrodes made of, for example, ITO (work function: approximately 4.4 eV). The inorganic oxide semiconductor material layer 23C comprises IGZO. The photoelectric conversion layer 23A includes a layer containing a well-known organic photoelectric conversion material sensitive to at least green light (e.g., an organic material such as a rhodamine-based dye, a merocyanine-based dye, or a quinacridone). The interlayer insulating layer 81, the insulating layer 82, and the protective material layer 83 include well-known insulating materials (e.g., SiO2 or SiN). The inorganic oxide semiconductor material layer 23C and the first electrode 21 are connected to each other via a connection portion 67 provided in the insulating layer 82. The inorganic oxide semiconductor material layer 23C extends in the connection portion 67. In other words, the inorganic oxide semiconductor material layer 23C and the protective layer 23B extend within the opening 84 provided in the insulating layer 82 and are connected to the first electrode 21.

[0411] The charge accumulation electrode 24 is connected to the driving circuit. Specifically, the charge accumulation electrode 24 is connected to the driving circuit via the connection hole 66 provided in the interlayer insulating layer 81, the pad portion 64 and the wiring V OA Connected to the vertical driving circuit 112 included in the driving circuit.

[0412] The size of the charge accumulation electrode 24 is larger than that of the first electrode 21. Although not limited, it is preferable to satisfy:

[0413] 4≤s1' / s1,

[0414] Here, s1′ represents the area of ​​the charge accumulation electrode 24, and s1 represents the area of ​​the first electrode 21. For example, in Example 1, although not limited thereto, the following expression holds.

[0415] s1' / s1=8

[0416] An element isolation region 71 is formed on the first surface (front surface) 70A side of the semiconductor substrate 70, and an insulating material film 72 is formed on the first surface 70A of the semiconductor substrate 70. In addition, a reset transistor TR1 included in the control unit of the first imaging element 10 is provided on the first surface side of the semiconductor substrate 70. rst, Amplifier transistor TR1 amp and select transistor TR1 sel , and a first floating diffusion layer FD1 is also provided.

[0417] Reset transistor TR1 rst The reset transistor TR1 includes a gate portion 51, a channel formation region 51A, and source / drain regions 51B and 51C. rst The gate portion 51 is connected to the reset line RST1, and the reset transistor TR1 rst One source / drain region 51C also serves as the first floating diffusion layer FD1, and the other source / drain region 51B is connected to the power supply V DD .

[0418] The first electrode 21 is connected to the reset transistor TR1 via the connection hole 65 and the pad portion 63 provided in the interlayer insulating layer 81, the contact hole portion 61 formed in the semiconductor substrate 70 and the interlayer insulating layer 76, and the wiring layer 62 formed in the interlayer insulating layer 76. rst A source / drain region 51C (first floating diffusion layer FD1 ) is formed.

[0419] Amplifier transistor TR1 amp The gate portion 52 includes a gate portion 52, a channel formation region 52A, and source / drain regions 52B and 52C. The gate portion 52 is connected to the first electrode 21 and the reset transistor TR1 via a wiring layer 62. rst One source / drain region 51C (first floating diffusion layer FD1) is connected to the power supply V DD .

[0420] Select transistor TR1 sel The transistor 53 includes a gate portion 53, a channel forming region 53A, and source / drain regions 53B and 53C. The gate portion 53 is connected to the selection line SEL1. In addition, one source / drain region 53B is connected to the amplifier transistor TR1. amp The other source / drain region 52C included in the transistor 110 shares one region, and the other source / drain region 53C is connected to the signal line (data output line) VSL1 (117).

[0421] The second imaging element 11 includes an n-type semiconductor region 41 as a photoelectric conversion layer provided in a semiconductor substrate 70. The transfer transistor TR2 includes a vertical transistor. trs The gate portion 45 extends to the n-type semiconductor region 41 and is connected to the transfer gate line TG2. In addition, the second floating diffusion layer FD2 is provided on the semiconductor substrate 70 at the position of the transfer transistor TR2. trsThe charge accumulated in the n-type semiconductor region 41 is read out to the second floating diffusion layer FD2 via a transfer channel formed along the gate portion 45 .

[0422] In the second imaging element 11, a reset transistor TR2 included in the control section of the second imaging element 11 is further provided on the first surface side of the semiconductor substrate 70. rst , amplifier transistor TR2 amp and select transistor TR2 sel .

[0423] Reset transistor TR2 rst It includes a gate portion, a channel formation region, and a source / drain region. Reset transistor TR2 rst The gate portion is connected to the reset line RST2, and the reset transistor TR2 rst One source / drain region is connected to the power supply V DD , and the other source / drain region also serves as a second floating diffusion layer FD2.

[0424] Amplifier transistor TR2 amp The gate portion is connected to the reset transistor TR2. rst The other of the source / drain regions (second floating diffusion layer FD2) is connected to the power supply V DD .

[0425] Select transistor TR2 sel The transistor includes a gate portion, a channel forming region, and a source / drain region. The gate portion is connected to the selection line SEL2. In addition, one of the source / drain regions is connected to the amplifier transistor TR2. amp The other of the source / drain regions included in the VSL2 shares one region, and the other of the source / drain regions is connected to the signal line (data output line) VSL2.

[0426] The third imaging element 12 includes an n-type semiconductor region 43 provided in a semiconductor substrate 70 as a photoelectric conversion layer. The transfer transistor TR3 trs The gate portion 46 is connected to the transfer gate line TG3. In addition, the third floating diffusion layer FD3 is provided on the semiconductor substrate 70 at the position of the transfer transistor TR3. trs The charge accumulated in the n-type semiconductor region 43 is read out to the third floating diffusion layer FD3 via a transfer channel 46A formed along the gate portion 46 .

[0427] In the third imaging element 12, a reset transistor TR3 included in the control unit of the third imaging element 12 is further provided on the first surface side of the semiconductor substrate 70. rst , amplifier transistor TR3 amp and select transistor TR3 sel .

[0428] Reset transistor TR3 rst It includes a gate portion, a channel formation region, and a source / drain region. Reset transistor TR3 rst The gate portion of the reset transistor TR3 is connected to the reset line RST3. rst One of the source / drain regions is connected to the power supply V DD , and the other one of the source / drain regions also functions as a third floating diffusion layer FD3 .

[0429] Amplifier transistor TR3 amp The gate portion is connected to the reset transistor TR3. rst The other of the source / drain regions (third floating diffusion layer FD3). In addition, one of the source / drain regions is connected to the power supply V DD .

[0430] Select transistor TR3 sel The transistor includes a gate portion, a channel forming region, and a source / drain region. The gate portion is connected to the selection line SEL3. In addition, one of the source / drain regions is connected to the amplifier transistor TR3. amp The other of the source / drain regions included in the VSL1 shares one region, and the other of the source / drain regions is connected to a signal line (data output line) VSL3.

[0431] Reset lines RST1, RST2, and RST3, selection lines SEL1, SEL2, and SEL3, and transfer gate lines TG2 and TG3 are connected to the vertical drive circuit 112 included in the drive circuit. Signal lines (data output lines) VSL1, VSL2, and VSL3 are connected to the column signal processing circuit 113 included in the drive circuit.

[0432] A p-type semiconductor region 43 is provided between the n-type semiconductor region 43 and the front surface 70A of the semiconductor substrate 70. + A p-type semiconductor layer 44 is formed between the n-type semiconductor region 41 and the n-type semiconductor region 43 to suppress the generation of dark current. + layer 42, and further, a portion of the side surface of the n-type semiconductor region 43 is p + The semiconductor substrate 70 is surrounded by a p-type layer 42. + Layer 73, and in from p +Layer 73 includes an HfO2 film 74 and an insulating film 75 in a region extending to the portion of semiconductor substrate 70 where contact hole 61 is formed. Although wiring is formed across multiple layers in interlayer insulating layer 76, illustration of the wiring is omitted.

[0433] The HfO2 film 74 is a film having a negative fixed charge. By providing this film, the generation of dark current can be suppressed. The HfO2 film can be made of aluminum oxide (Al2O3) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, titanium oxide (TiO2) film, lanthanum oxide (La2O3) film, praseodymium oxide (Pr2O3) film, cerium oxide (CeO2) film, neodymium oxide (Nd2O3) film, promethium oxide (Pm2O3) film, samarium oxide (Sm2O3) film, europium oxide film, etc. The present invention can be replaced by an uranium oxide (Eu2O3) film, a gadolinium oxide (Gd2O3) film, a terbium oxide (Tb2O3) film, a dysprosium oxide (Dy2O3) film, a holmium oxide (Ho2O3) film, a thulium oxide (Tm2O3) film, a ytterbium oxide (Yb2O3) film, a lutetium oxide (Lu2O3) film, a yttrium oxide (Y2O3) film, a hafnium nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film. Examples of film formation methods for these films include a CVD method, a PVD method, and an ALD method.

[0434] In the following, reference Figure 5 and Figure 6A , the operation of the stacked imaging element (first imaging element 10) including the charge accumulation electrode of Example 1 will be described. The imaging element of Example 1 also includes a control unit, which is provided in the semiconductor substrate 70 and includes a drive circuit. The first electrode 21, the second electrode 22, and the charge accumulation electrode 24 are connected to the drive circuit. Here, the potential of the first electrode 21 is made higher than the potential of the second electrode 22. That is, for example, the first electrode 21 is set to a positive potential, and the second electrode 22 is set to a negative potential. Then, the electrons generated by photoelectric conversion in the photoelectric conversion layer 23A are read out to the floating diffusion layer. This also applies to other embodiments. In addition, in Figure 16 、 Figure 25 、 Figure 28 、 Figure 63 、 Figure 64 、 Figure 65 、 Figure 66 and Figure 67 , the inorganic oxide semiconductor material layer 23C and the protective layer 23B are collectively denoted by reference numeral 23D.

[0435] exist Figure 5 , Example 4 described later Figure 20 and Figure 21 And Example 6 Figure 32 and Figure 33 The reference numerals used in the drawings are as follows.

[0436] P A : Point P in the region of the inorganic oxide semiconductor material layer 23C A The potential of the region faces the region between the charge accumulation electrode 24 and the first electrode 21 or between the transfer control electrode (charge transfer electrode) 25 and the first electrode 21.

[0437] P B : Point P in the region of the inorganic oxide semiconductor material layer 23C facing the charge storage electrode 24 B The potential at

[0438] P C1 : Point P in the region of the inorganic oxide semiconductor material layer 23C facing the charge accumulation electrode segment 24A C1 The potential at

[0439] P C2 : Point P in the region of the inorganic oxide semiconductor material layer 23C facing the charge accumulation electrode segment 24B C2 The potential at

[0440] P C3 : Point P in the region of the inorganic oxide semiconductor material layer 23C facing the charge accumulation electrode segment 24C C3 The potential at

[0441] P D : Point P in the region of the inorganic oxide semiconductor material layer 23C facing the transfer control electrode (charge transfer electrode) 25 D The potential at

[0442] FD: Potential at the first floating diffusion layer FD1

[0443] V OA : Potential at the charge accumulation electrode 24

[0444] V OA-A : Potential at the charge accumulation electrode segment 24A

[0445] V OA-B : Potential at the charge accumulation electrode segment 24B

[0446] V OA-C : Potential at the charge accumulation electrode segment 24C

[0447] V OT : Potential at the transfer control electrode (charge transfer electrode) 25

[0448] RST: Reset transistor TR1 rst The potential at the gate portion 51

[0449] V DD : Power supply potential

[0450] VSL1: Signal line (data output line) VSL1

[0451] TR1 rst : Reset transistor TR1 rst

[0452] TR1 amp : Amplifying transistor TR1 amp

[0453] TR1 sel : Select transistor TR1 sel

[0454] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode 21. 11 , and a potential V is applied to the charge storage electrode 24 31 The light incident on the photoelectric conversion layer 23A is photoelectrically converted in the photoelectric conversion layer 23A. The holes generated by the photoelectric conversion are transmitted from the second electrode 22 to the wiring V OU At the same time, since the potential of the first electrode 21 is higher than the potential of the second electrode 22, that is, since a positive potential is applied to the first electrode 21 and a negative potential is applied to the second electrode 22, V 31 ≥V 11 Established, preferably V 31 >V 11 Therefore, the electrons generated by photoelectric conversion are attracted to the charge accumulation electrode 24 and retained in the region of the inorganic oxide semiconductor material layer 23C facing the charge accumulation electrode 24, or retained in the region of the inorganic oxide semiconductor material layer 23C, the protective layer 23B and the photoelectric conversion layer 23A (hereinafter, these layers are collectively referred to as "inorganic oxide semiconductor material layer 23C, etc.") facing the charge accumulation electrode 24. That is, the charge is accumulated in the inorganic oxide semiconductor material layer 23C, etc. Due to V 31 >V 11 Therefore, electrons generated inside the photoelectric conversion layer 23A do not move toward the first electrode 21. As time passes during photoelectric conversion, the potential in the region of the inorganic oxide semiconductor material layer 23C and the like facing the charge storage electrode 24 becomes more negative.

[0455] At the latter stage of the charge accumulation period, a reset operation is performed. Thus, the potential of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 is shifted to the potential V of the power supply. DD .

[0456] After the reset operation is completed, the charge is read out. That is, during the charge transfer period, the potential V is applied from the drive circuit to the first electrode 21. 12 , and a potential V is applied to the charge storage electrode 24 32 Here, V 32 <V 12 This is established. Consequently, electrons retained in the region of the inorganic oxide semiconductor material layer 23C and the like facing the charge accumulation electrode 24 are read out to the first electrode 21 and further to the first floating diffusion layer FD1. In other words, the charge accumulated in the inorganic oxide semiconductor material layer 23C and the like is read out to the control unit.

[0457] Thus, a series of operations including charge accumulation, reset operation, and charge transfer are completed.

[0458] After reading out electrons to the first floating diffusion layer FD1, the amplifying transistor TR1 amp and select transistor TR1 sel The operation of the transistors is the same as that of conventional transistors. Furthermore, the series of operations of the second and third imaging elements 11 and 12, including charge accumulation, reset operation, and charge transfer, is similar to that of conventional technology. Furthermore, similar to conventional technology, reset noise of the first floating diffusion layer FD1 can be eliminated through correlated double sampling (CDS) processing.

[0459] As described above, in Example 1, a charge accumulation electrode is provided, arranged separately from the first electrode and facing the photoelectric conversion layer across an insulating layer. Therefore, when light is irradiated into the photoelectric conversion layer and photoelectric conversion occurs within the layer, a capacitor is formed by the inorganic oxide semiconductor material layer, the insulating layer, and the charge accumulation electrode, allowing charge to accumulate within the inorganic oxide semiconductor material layer. Consequently, at the start of exposure, the charge accumulation portion can be completely depleted to clear the charge. As a result, the following phenomena can be suppressed: increased kTC noise and worsening random noise, which can lead to reduced captured image quality. Furthermore, since all pixels can be reset simultaneously, a so-called global shutter function can be achieved.

[0460] Figure 68A conceptual diagram of a solid-state imaging device of Example 1 is shown. The solid-state imaging device 100 of Example 1 includes: an imaging area 111 in which stacked imaging elements 101 are arranged in a two-dimensional array; and a vertical driving circuit 112, a column signal processing circuit 113, a horizontal driving circuit 114, an output circuit 115, and a driving control circuit 116 as driving circuits (peripheral circuits) of the imaging area 111. Needless to say, these circuits may be composed of well-known circuits, or may be composed using other circuit structures (for example, various circuits used in existing CCD imaging devices or CMOS imaging devices). Figure 68 , the reference numeral “ 101 ” of the stacked image pickup element 101 is displayed only in one row.

[0461] The drive control circuit 116 generates a clock signal and a control signal based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock, and the clock signal and the control signal serve as a reference for the operation of the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114. In addition, the clock signal and the control signal generated in this way are input to the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114.

[0462] The vertical drive circuit 112 includes, for example, a shift register, and selectively scans the stacked imaging elements 101 in the imaging area 111 sequentially in the vertical direction in rows. A pixel signal (image signal) based on a current (signal) generated in accordance with the amount of light received by each stacked imaging element 101 is transmitted to the column signal processing circuit 113 via a signal line (data output line) 117 or VSL.

[0463] For example, the column signal processing circuit 113 is arranged for each column of the stacked image sensor 101, and performs signal processing including noise cancellation and signal amplification on the image signals output from one row of the stacked image sensor 101, based on signals from black reference pixels (which are not shown but are formed around the effective pixel area). At the output stage of the column signal processing circuit 113, a horizontal selection switch (not shown) is provided so as to be connected between the output stage and the horizontal signal line 118.

[0464] The horizontal drive circuit 114 includes, for example, a shift register, and sequentially outputs horizontal scanning pulses to sequentially select each of the column signal processing circuits 113 , thereby outputting a signal from each of the column signal processing circuits 113 to a horizontal signal line 118 .

[0465] The output circuit 115 performs signal processing on the signals sequentially supplied from the respective column signal processing circuits 113 via the horizontal signal line 118 , and outputs the processed signals.

[0466] Figure 9 is an equivalent circuit diagram of the imaging element of Example 1 and a modified example of the stacked imaging element, and Figure 10 Schematic layout diagram of the first electrode, the charge accumulation electrode and the transistor included in the control unit. As shown in the figure, the reset transistor TR1 rst The other source / drain region 51B may be grounded instead of being connected to the power supply V DD .

[0467] For example, the imaging element and the stacked imaging element of Example 1 can be manufactured by the following method. That is, first, an SOI substrate is prepared. Then, a first silicon layer is formed on the surface of the SOI substrate based on an epitaxial growth method, and a p-type silicon layer is formed on the first silicon layer. + Next, a second silicon layer is formed on the first silicon layer based on an epitaxial growth method, and an element isolation region 71, an insulating material film 72, a p-type semiconductor region 41 are formed on the second silicon layer. + layer 42, n-type semiconductor region 43 and p + Layer 44. In addition, various transistors included in the control part of the imaging element are formed on the second silicon layer, and a wiring layer 62, an interlayer insulating layer 76 and various wirings are further formed on the transistors. Thereafter, the interlayer insulating layer 76 and the supporting substrate (not shown) are bonded to each other. Thereafter, the SOI substrate is removed to expose the first silicon layer. The surface of the second silicon layer corresponds to the front surface 70A of the semiconductor substrate 70, and the surface of the first silicon layer corresponds to the rear surface 70B of the semiconductor substrate 70. In addition, the first silicon layer and the second silicon layer are uniformly represented as the semiconductor substrate 70. Next, an opening for forming the contact hole portion 61 is formed on the rear surface 70B side of the semiconductor substrate 70, and an HfO2 film 74, an insulating material film 75 and the contact hole portion 61 are formed. In addition, pad portions 63 and 64, an interlayer insulating layer 81, connection holes 65 and 66, a first electrode 21, a charge accumulation electrode 24 and an insulating layer 82 are also formed. Next, the connection portion 67 is opened, and the inorganic oxide semiconductor material layer 23C, protective layer 23B, photoelectric conversion layer 23A, second electrode 22, protective material layer 83, and on-chip microlens 14 are formed. In this manner, the imaging element and stacked imaging element of Example 1 can be obtained.

[0468] In addition, although not shown, the insulating layer 82 may have a two-layer structure including an insulating layer / lower layer and an insulating layer / upper layer. That is, it is sufficient to form the insulating layer / lower layer at least above the charge accumulation electrode 24 and in the region between the charge accumulation electrode 24 and the first electrode 21 (more specifically, to form the insulating layer / lower layer on the interlayer insulating layer 81 including the charge accumulation electrode 24), perform a flattening treatment on the insulating layer / lower layer, and thereafter form the insulating layer / upper layer above the insulating layer / lower layer and the charge accumulation electrode 24. Therefore, the flattening of the insulating layer 82 can be reliably achieved. Then, it is sufficient to open the connection portion 67 in the insulating layer 82 obtained in this manner.

[0469] [Example 2]

[0470] Example 2 is a variation of Example 1. Figure 11 This is a schematic partial cross-sectional view of the imaging element and stacked imaging element of Example 2. The imaging element and stacked imaging element of Example 2 are front-illuminated imaging elements and have a structure in which three imaging elements are stacked: the first-type green light imaging element (first imaging element 10) of Example 1, which includes a first-type green light photoelectric conversion layer that absorbs green light and is sensitive to green light; the conventional second-type blue light imaging element (second imaging element 11), which includes a second-type blue light photoelectric conversion layer that absorbs blue light and is sensitive to blue light; and the conventional second-type red light imaging element (third imaging element 12), which includes a second-type red light photoelectric conversion layer that absorbs red light and is sensitive to red light. Here, the red light imaging element (third imaging element 12) and the blue light imaging element (second imaging element 11) are provided in the semiconductor substrate 70, with the second imaging element 11 being closer to the light incident side than the third imaging element 12. In addition, the green light imaging element (first imaging element 10 ) is provided above the blue light imaging element (second imaging element 11 ).

[0471] As in Embodiment 1, various transistors included in the control unit are provided on the front surface 70A side of the semiconductor substrate 70. These transistors can have substantially the same configuration and structure as the transistors described in Embodiment 1. Furthermore, although the second imaging element 11 and the third imaging element 12 are provided on the semiconductor substrate 70, these imaging elements can also have substantially the same configuration and structure as the second imaging element 11 and the third imaging element 12 described in Embodiment 1.

[0472] An interlayer insulating layer 81 is formed above the front surface 70A of the semiconductor substrate 70, and as in the imaging element of Example 1, a first electrode 21, an inorganic oxide semiconductor material layer 23C, a protective layer 23B, a photoelectric conversion layer 23A, a second electrode 22 and a charge accumulation electrode 24 are arranged above the interlayer insulating layer 81.

[0473] In this way, except that the imaging element and the stacked imaging element of Example 2 are front-illuminated imaging elements and stacked imaging elements, the construction and structure of the imaging element and the stacked imaging element of Example 2 can be similar to the construction and structure of the imaging element and the stacked imaging element of Example 1, so their detailed description is omitted.

[0474] [Example 3]

[0475] Example 3 is a variation of Example 1 and Example 2.

[0476] Figure 12 Schematic partial cross-sectional view of the imaging element and the stacked imaging element of Example 3. The imaging element and the stacked imaging element of Example 3 are back-illuminated imaging elements and stacked imaging elements, and have a structure in which two imaging elements are stacked, the two imaging elements being the first imaging element 10 of Example 1 of the first type and the third imaging element 12 of the second type. In addition, Figure 13 This is a schematic partial cross-sectional view of a modified example of the imaging element and stacked imaging element of Example 3. The imaging element and this modified example of the stacked imaging element of Example 3 are front-illuminated and have a structure in which two imaging elements are stacked: the first imaging element 10 of Example 1, which is the first type, and the third imaging element 12, which is the second type. Here, the first imaging element 10 absorbs light of a primary color, and the third imaging element 12 absorbs light of a complementary color. Alternatively, the first imaging element 10 absorbs white light, and the third imaging element 12 absorbs infrared light.

[0477] Figure 14 : is a schematic partial cross-sectional view of a modification of the imaging element of Example 3. This modification of the imaging element of Example 3 is a back-illuminated type, and includes the first imaging element 10 of Example 1 of the first type. Figure 15: is a schematic partial cross-sectional view of a modification of the imaging element of Example 3. This modification of the imaging element of Example 3 is a front-illuminated type, and includes the first imaging element 10 of Example 1 of the first type. Here, the first imaging element 10 includes three types of imaging elements, namely: an imaging element that absorbs red light; an imaging element that absorbs green light; and an imaging element that absorbs blue light. In addition, a plurality of these imaging elements are included in the solid-state imaging device according to the first aspect of the present disclosure. An example of the arrangement of a plurality of these imaging elements includes a Bayer arrangement. On the light incident side of the imaging element, a color filter layer for performing spectral separation on blue, green, and red is arranged as needed.

[0478] Instead of providing one imaging element of the first type according to the first embodiment, two imaging elements of the first type according to the first embodiment may be provided in a stacked configuration (i.e., two photoelectric conversion units are stacked, and a control unit for these two photoelectric conversion units is provided in a semiconductor substrate). Alternatively, three imaging elements of the first type according to the first embodiment may be provided in a stacked configuration (i.e., three photoelectric conversion units are stacked, and a control unit for these three photoelectric conversion units is provided in a semiconductor substrate). The table below shows an example of the stacked configuration of the first-type imaging element and the second-type imaging element.

[0479]

[0480] [Example 4]

[0481] Example 4 is a modification of Example 1 to Example 3, and relates to an image pickup element or the like including a transfer control electrode (charge transfer electrode) of the present disclosure. Figure 16 This is a schematic partial cross-sectional view of a portion of the imaging element and the stacked imaging element of Example 4. Figure 17 and Figure 18 This is an equivalent circuit diagram of the imaging element of Example 4 and a stacked imaging element. Figure 19 This is a schematic layout diagram of a first electrode, a transfer control electrode, a charge accumulation electrode included in the image sensor of Example 4, and a transistor included in the control section. Figure 20 and Figure 21 The potential states at various locations during operation of the image pickup element of Example 4 are schematically shown. Figure 6B : is an equivalent circuit diagram for explaining each part of the imaging element of Example 4. Figure 22 This is a schematic layout diagram of a first electrode, a transfer control electrode, and a charge storage electrode included in a photoelectric conversion portion of an imaging element according to Example 4. Figure 23 It is a schematic perspective view of a first electrode, a transfer control electrode, a charge storage electrode, a second electrode, and a contact hole portion.

[0482] The imaging element and the stacked imaging element of Example 4 further include a transfer control electrode (charge transfer electrode) 25 between the first electrode 21 and the charge accumulation electrode 24. The transfer control electrode 25 is arranged separately from the first electrode 21 and the charge accumulation electrode 24, and is arranged to face the inorganic oxide semiconductor material layer 23C via the insulating layer 82. The transfer control electrode 25 is connected to the inorganic oxide semiconductor material layer 23C via the connection hole 68B provided in the interlayer insulating layer 81, the pad portion 68A, and the wiring V OT Connected to the pixel driving circuit included in the driving circuit. Figure 16 、 Figure 25 、 Figure 28 、 Figure 37 、 Figure 43 、 Figure 46A 、 Figure 46B 、 Figure 47A 、 Figure 47B 、 Figure 66 and Figure 67 In order to simplify the drawings, for convenience, the constituent elements of the imaging element located below the interlayer insulating layer 81 are collectively denoted by reference numeral 13 .

[0483] In the following, reference Figure 20 and Figure 21 , the operation of the imaging element (first imaging element 10) of Example 4 will be described. Figure 20 and Figure 21 The value of the potential applied to the charge storage electrode 24 and the point P D The potential values ​​at are different.

[0484] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode 21. 11 , a potential V is applied to the charge storage electrode 24 31 , and a potential V is applied to the transmission control electrode 25 51 The light incident on the photoelectric conversion layer 23A is photoelectrically converted in the photoelectric conversion layer 23A. The holes generated by the photoelectric conversion are transmitted from the second electrode 22 to the wiring V OU At the same time, the potential of the first electrode 21 is higher than that of the second electrode 22, that is, for example, a positive potential is applied to the first electrode 21, and a negative potential is applied to the second electrode 22. Therefore, V 31 >V 51 (For example, V 31 >V 11 >V 51 or V 11 >V 31 >V 51) is established. Therefore, the electrons generated by photoelectric conversion are attracted to the charge accumulation electrode 24 and retained in the region of the inorganic oxide semiconductor material layer 23C etc. facing the charge accumulation electrode 24. That is, the charge is accumulated in the inorganic oxide semiconductor material layer 23C etc. 31 >V 51 This is established, and thus electrons generated inside the photoelectric conversion layer 23A can be reliably prevented from moving toward the first electrode 21. As time passes during photoelectric conversion, the potential in the region of the inorganic oxide semiconductor material layer 23C and the like facing the charge storage electrode 24 has a more negative value.

[0485] At the latter stage of the charge accumulation period, a reset operation is performed. Thus, the potential of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 is shifted to the potential V of the power supply. DD .

[0486] After the reset operation is completed, the charge is read out. That is, during the charge transfer period, the potential V is applied from the drive circuit to the first electrode 21. 12 , a potential V is applied to the charge storage electrode 24 32 , and a potential V is applied to the transmission control electrode 25 52 Here, V 32 ≤V 52 ≤V 12 (Preferably, V 32 <V 52 <V 12 ) is established. Therefore, electrons retained in the region of the inorganic oxide semiconductor material layer 23C and the like facing the charge accumulation electrode 24 are reliably read out to the first electrode 21 and further to the first floating diffusion layer FD1. In other words, the charge accumulated in the inorganic oxide semiconductor material layer 23C and the like is read out to the control unit.

[0487] Thus, a series of operations including charge accumulation, reset operation, and charge transfer are completed.

[0488] After reading out electrons to the first floating diffusion layer FD1, the amplifying transistor TR1 amp and select transistor TR1 sel The operation of the transistors is the same as that of the conventional transistors. In addition, for example, a series of operations including charge accumulation, reset operation, and charge transfer of the second imaging element 11 and the third imaging element 12 is similar to a series of operations including charge accumulation, reset operation, and charge transfer according to the conventional technology.

[0489] Figure 24This is a schematic layout diagram of the first electrode and the charge accumulation electrode included in the modified example of the imaging element of Example 4, and the transistor included in the control unit. As shown in the figure, the reset transistor TR1 rst The other source / drain region 51B may be grounded instead of being connected to the power supply V DD .

[0490] [Example 5]

[0491] Example 5 is a modification of Example 1 to Example 4, and relates to an image pickup element and the like including a charge discharge electrode of the present disclosure. Figure 25 This is a schematic partial cross-sectional view of a portion of the imaging element of Example 5. Figure 26 This is a schematic layout diagram of a first electrode, a charge storage electrode, and a charge discharge electrode included in a photoelectric conversion portion having a charge storage electrode of an image sensor according to Example 5. Figure 27 It is a schematic perspective view of a first electrode, a charge storage electrode, a charge discharge electrode, a second electrode, and a contact hole portion.

[0492] The imaging element of Example 5 also includes a charge discharge electrode 26, which is connected to the inorganic oxide semiconductor material layer 23C via a connecting portion 69 and is arranged separately from the first electrode 21 and the charge accumulation electrode 24. Here, the charge discharge electrode 26 is arranged to surround the first electrode 21 and the charge accumulation electrode 24 (i.e., in the shape of a photo frame). The charge discharge electrode 26 is connected to the pixel driving circuit included in the driving circuit. The inorganic oxide semiconductor material layer 23C and the protective layer 23B extend in the connecting portion 69. That is, the inorganic oxide semiconductor material layer 23C and the protective layer 23B extend within the second opening portion 85 provided in the insulating layer 82, and the inorganic oxide semiconductor material layer 23C is connected to the charge discharge electrode 26. The charge discharge electrode 26 is shared (shared) by multiple imaging elements. The side surface of the second opening portion 85 can be tilted in a manner that expands the second opening portion 85 upward. The charge discharge electrode 26 can be used, for example, as a floating diffusion portion of a photoelectric conversion portion or an overflow drain of a photoelectric conversion portion.

[0493] In Example 5, during the charge accumulation period, a potential V is applied from the drive circuit to the first electrode 21. 11 , a potential V is applied to the charge storage electrode 24 31 , and a potential V is applied to the charge discharge electrode 26 61 , and charges are accumulated in the inorganic oxide semiconductor material layer 23C and the like. Light incident on the photoelectric conversion layer 23A undergoes photoelectric conversion in the photoelectric conversion layer 23A. Holes generated by the photoelectric conversion are transferred from the second electrode 22 to the wiring V OUAt the same time, the potential of the first electrode 21 is higher than that of the second electrode 22, that is, for example, a positive potential is applied to the first electrode 21, and a negative potential is applied to the second electrode 22. Therefore, V 61 >V 11 (For example, V 31 >V 61 >V 11 ) is established. Therefore, the electrons generated by photoelectric conversion are attracted to the charge accumulation electrode 24 and retained in the region of the inorganic oxide semiconductor material layer 23C or the like facing the charge accumulation electrode 24. Therefore, the electrons can be reliably prevented from moving toward the first electrode 21. However, electrons that are not sufficiently attracted to the charge accumulation electrode 24 or electrons that are not accumulated in the inorganic oxide semiconductor material layer 23C or the like (so-called overflow electrons) are sent to the drive circuit via the charge discharge electrode 26.

[0494] At the latter stage of the charge accumulation period, a reset operation is performed. Thus, the potential of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 is shifted to the potential V of the power supply. DD .

[0495] After the reset operation is completed, the charge is read out. That is, during the charge transfer period, the potential V is applied from the drive circuit to the first electrode 21. 12 , a potential V is applied to the charge storage electrode 24 32 , and a potential V is applied to the charge discharge electrode 26 62 Here, V 62 <V 12 (For example, V 62 <V 32 <V 12 ) is established. Therefore, electrons retained in the region of the inorganic oxide semiconductor material layer 23C and the like facing the charge accumulation electrode 24 are reliably read out to the first electrode 21 and further to the first floating diffusion layer FD1. In other words, the charge accumulated in the inorganic oxide semiconductor material layer 23C and the like is read out to the control unit.

[0496] Thus, a series of operations including charge accumulation, reset operation, and charge transfer are completed.

[0497] After reading out electrons to the first floating diffusion layer FD1, the amplifying transistor TR1 amp and select transistor TR1 sel The operation of the transistors is the same as that of the conventional transistors. In addition, for example, a series of operations including charge accumulation, reset operation, and charge transfer of the second and third imaging elements is similar to a series of operations including charge accumulation, reset operation, and charge transfer according to the conventional technology.

[0498] In Example 5, overflow electrons are sent to the drive circuit via the charge discharge electrode 26. This prevents leakage to the charge storage unit of adjacent pixels and reduces the occurrence of blooming. This improves the imaging performance of the imaging element.

[0499] [Example 6]

[0500] Example 6 is a modification of Example 1 to Example 5, and relates to an image pickup element or the like of the present disclosure including a plurality of charge accumulation electrode segments.

[0501] Figure 28 This is a schematic partial cross-sectional view of a portion of the imaging element of Example 6. Figure 29 and Figure 30 This is an equivalent circuit diagram of the imaging element of Example 6. Figure 31 This is a schematic layout diagram of a first electrode and a charge storage electrode included in a photoelectric conversion portion having a charge storage electrode, and a transistor included in a control portion of an imaging element according to Example 6. Figure 32 and Figure 33 The potential states at various locations during operation of the image pickup element of Example 6 are schematically shown. Figure 6C : is an equivalent circuit diagram for explaining each part of the imaging element of Example 6. Figure 34 This is a schematic layout diagram of a first electrode and a charge storage electrode included in a photoelectric conversion portion having a charge storage electrode in an image sensor according to Example 6. Figure 35 It is a schematic perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion.

[0502] In Example 6, the charge accumulation electrode 24 includes a plurality of charge accumulation electrode segments 24A, 24B, and 24C. The number of charge accumulation electrode segments need only be two or more, and in Example 6, this number is set to three. Furthermore, in the imaging element of Example 6, the potential of the first electrode 21 is higher than that of the second electrode 22. For example, a positive potential is applied to the first electrode 21, and a negative potential is applied to the second electrode 22. Therefore, during the charge transfer period, the potential applied to the charge accumulation electrode segment 24A closest to the first electrode 21 is higher than the potential applied to the charge accumulation electrode segment 24C farthest from the first electrode 21. By applying a potential gradient to the charge accumulation electrode 24 in this manner, electrons retained in the region of the inorganic oxide semiconductor material layer 23C and the like facing the charge accumulation electrode 24 are more reliably read out to the first electrode 21 and, further, to the first floating diffusion layer FD1. In other words, the charge accumulated in the inorganic oxide semiconductor material layer 23C and the like is read out to the control unit.

[0503] exist Figure 32 In the example shown, during the charge transfer period, by satisfying the potential of the charge accumulating electrode segment 24C < the potential of the charge accumulating electrode segment 24B < the potential of the charge accumulating electrode segment 24A, electrons retained in the region of the inorganic oxide semiconductor material layer 23C and the like are simultaneously read out to the first floating diffusion layer FD1. Figure 33 In the example shown, during the charge transfer period, the potentials of the charge accumulation electrode segment 24C, the charge accumulation electrode segment 24B, and the charge accumulation electrode segment 24A gradually change (i.e., change in a step-like or ramp-like manner). Consequently, electrons retained in the region of the inorganic oxide semiconductor material layer 23C or the like facing the charge accumulation electrode segment 24C move to the region of the inorganic oxide semiconductor material layer 23C or the like facing the charge accumulation electrode segment 24B. Subsequently, electrons retained in the region of the inorganic oxide semiconductor material layer 23C or the like facing the charge accumulation electrode segment 24B move to the region of the inorganic oxide semiconductor material layer 23C or the like facing the charge accumulation electrode segment 24A. Consequently, the electrons retained in the region of the inorganic oxide semiconductor material layer 23C or the like facing the charge accumulation electrode segment 24A are reliably read out to the first floating diffusion layer FD1.

[0504] Figure 36 This is a schematic layout diagram of the first electrode and the charge accumulation electrode included in the modified example of the imaging element of Example 6, and the transistor included in the control unit. As shown in the figure, the reset transistor TR1 rst The other source / drain region 51B may be grounded instead of being connected to the power supply V DD .

[0505] [Example 7]

[0506] Example 7 is a variation of Example 1 to Example 6, and Example 7 relates to the imaging element of the present disclosure including a charge transfer control electrode, etc., specifically relates to the imaging element of the present disclosure including a lower charge transfer control electrode (lower side / charge transfer control electrode), etc. Figure 37 This is a schematic partial cross-sectional view of a portion of the imaging element of Example 7. Figure 38 This is a schematic layout diagram of the first electrode, the charge accumulation electrode, and the like included in the imaging element of Example 7, and the transistor included in the control unit. Figure 39 and Figure 40 Schematic layout diagram of the first electrode, the charge accumulation electrode, and the lower charge transfer control electrode included in the photoelectric conversion unit having the charge accumulation electrode of the imaging element of Example 7. Figure 37 、 Figure 43 、 Figure 46A 、 Figure 46B 、 Figure 47A and Figure 47B In FIG. 2 , the photoelectric conversion layer 23A, the protective layer 23B, and the inorganic oxide semiconductor material layer 23C are collectively represented by the photoelectric conversion stack 23 .

[0507] In the imaging element of Example 7, the lower charge transfer control electrode 27 is formed in a region (region-A of the photoelectric conversion layer) 23 between adjacent imaging elements with the insulating layer 82 interposed therebetween. A In other words, the lower charge transfer control electrode 27 is formed in a portion 82 of the insulating layer 82 in the following region (region-a): A Below (region -A of the insulating layer 82): This region is sandwiched between the charge accumulation electrodes 24 and the charge accumulation electrodes 24 included in each adjacent imaging element. The lower charge transfer control electrode 27 is provided separately from the charge accumulation electrodes 24. In other words, the lower charge transfer control electrode 27 surrounds the charge accumulation electrodes 24 and is provided separately from the charge accumulation electrodes 24, and is arranged to face the region -A (23) of the photoelectric conversion layer via the insulating layer 82. A ). The lower charge transfer control electrode 27 is shared by a plurality of imaging elements. In addition, the lower charge transfer control electrode 27 is also connected to the drive circuit. Specifically, the lower charge transfer control electrode 27 is connected to the drive circuit via the connection hole 27A, the pad portion 27B and the wiring V provided in the interlayer insulating layer 81. OBConnected to the vertical drive circuit 112 included in the drive circuit. The lower charge transfer control electrode 27 can be formed on the same horizontal plane as the first electrode 21 or the charge accumulation electrode 24, or can be formed on a horizontal plane different from the first electrode 21 or the charge accumulation electrode 24 (specifically, a horizontal plane below the first electrode 21 or the charge accumulation electrode 24). In the former case, since the distance between the charge transfer control electrode 27 and the photoelectric conversion layer 23A can be shortened, it is easy to control the potential. In contrast, in the latter case, since the distance between the charge transfer control electrode 27 and the charge accumulation electrode 24 can be shortened, it is conducive to miniaturization.

[0508] In the imaging element of Example 7, when light is incident on the photoelectric conversion layer 23A, causing photoelectric conversion in the layer, the absolute value of the potential applied to the portion of the photoelectric conversion layer 23A facing the charge accumulation electrode 24 is greater than the absolute value of the potential applied to region-A of the photoelectric conversion layer 23A. Therefore, the charge generated by photoelectric conversion is strongly attracted to the portion of the inorganic oxide semiconductor material layer 23C facing the charge accumulation electrode 24. As a result, the charge generated by photoelectric conversion is prevented from flowing into adjacent imaging elements. Therefore, the quality of the captured image is not degraded. Furthermore, because the lower charge transfer control electrode 27 is formed in a region opposite region-A of the photoelectric conversion layer 23A via an insulating layer, the electric field or potential of region-A of the photoelectric conversion layer 23A located above the lower charge transfer control electrode 27 can be controlled. As a result, the lower charge transfer control electrode 27 can prevent the charge generated by photoelectric conversion from flowing into adjacent imaging elements. Therefore, the quality of the captured image is not degraded.

[0509] exist Figure 39 and Figure 40 In the example shown, the lower charge transfer control electrode 27 is formed in a portion 82 of the insulating layer 82 in a region (region-a) sandwiched between the charge accumulating electrode 24 and the charge accumulating electrode 24. A Below. Meanwhile, Figure 41 、 Figure 42A and Figure 42B In the example shown, the lower charge transfer control electrode 27 is formed below a portion of the insulating layer 82 in a region surrounded by the four charge accumulation electrodes 24. Figure 41 、 Figure 42A and Figure 42B The example shown also has the solid-state imaging device of the first and second structures. In the four imaging elements, one common first electrode 21 is provided corresponding to the four charge accumulation electrodes 24 .

[0510] exist Figure 42BIn the illustrated example, a common first electrode 21 is provided in four imaging elements corresponding to the four charge accumulation electrodes 24, and the lower charge transfer control electrode 27 is formed below the portion of the insulating layer 82 in the region surrounded by the four charge accumulation electrodes 24. Furthermore, the charge discharge electrode 26 is also formed below the portion of the insulating layer 82 in the region surrounded by the four charge accumulation electrodes 24. As described above, the charge discharge electrode 26 can function as, for example, a floating diffusion of the photoelectric conversion portion or an overflow drain of the photoelectric conversion portion.

[0511] [Example 8]

[0512] Embodiment 8 is a modification of Embodiments 1 to 7, and relates to an image pickup element or the like including an upper charge transfer control electrode (upper-side charge transfer control electrode) of the present disclosure. Figure 43 This is a partial schematic cross-sectional view of an image pickup element according to Example 8 (two image pickup elements arranged side by side). Figure 44 and Figure 45 This is a partial schematic plan view of an imaging element of Example 8 (2×2 imaging elements arranged side by side). In the imaging element of Example 8, instead of the second electrode 22, an upper charge transfer control electrode 28 is formed in a region 23 between adjacent imaging elements of the photoelectric conversion stack 23. A The upper charge transfer control electrode 28 is provided separately from the second electrode 22. In other words, the second electrode 22 is provided for each imaging element, and the upper charge transfer control electrode 28 surrounds at least a portion of the second electrode 22 and is provided separately from the second electrode 22 on region -A of the photoelectric conversion stack 23. The upper charge transfer control electrode 28 is formed on the same horizontal plane as the second electrode 22.

[0513] Please note that Figure 44 In the example shown, in one imaging element, one charge accumulation electrode 24 is provided corresponding to one first electrode 21. Figure 45 In the illustrated modification, one common first electrode 21 is provided corresponding to two charge storage electrodes 24 in two imaging elements. Figure 43 The schematic partial cross-sectional view of the imaging element of Example 8 (two imaging elements arranged side by side) shown corresponds to Figure 45 .

[0514] in addition, Figure 46A : is a partial schematic cross-sectional view of an imaging element (two imaging elements arranged side by side) of Example 8. As shown in the figure, the second electrode 22 can be divided into a plurality of second electrodes, and a different potential can be applied to each of the divided second electrodes 22. In addition, as Figure 46BAs shown, the upper charge transfer control electrode 28 may be provided between the second electrodes 22 and the second electrodes 22 divided in this manner.

[0515] In Example 8, the second electrode 22 located on the light incident side is formed by Figure 44 The image pickup elements arranged in the left and right directions on the paper are shared by Figure 44 The upper charge transfer control electrode 28 is also provided by a pair of imaging elements arranged in the vertical direction on the paper. Figure 44 The image pickup elements arranged in the left and right directions on the paper are shared by Figure 44 The second electrode 22 and the upper charge transfer control electrode 28 are shared by a pair of imaging elements arranged in the vertical direction on the paper of FIG. The second electrode 22 and the upper charge transfer control electrode 28 can be obtained by forming a material layer for constituting the second electrode 22 and the upper charge transfer control electrode 28 on the photoelectric conversion stack 23 and then patterning the material layer. The second electrode 22 and the upper charge transfer control electrode 28 are independently connected to respective wirings (not shown) from each other, and these wirings are connected to the drive circuit. The wiring connected to the second electrode 22 is shared by multiple imaging elements. The wiring connected to the upper charge transfer control electrode 28 is also shared by multiple imaging elements.

[0516] In the image pickup element of Example 8, during the charge accumulation period, the potential V 21 , applying a potential V to the upper charge transfer control electrode 28 41 , and the charge is accumulated in the photoelectric conversion stack 23. During the charge transfer period, a potential V is applied from the drive circuit to the second electrode 22. 22 , applying a potential V to the upper charge transfer control electrode 28 42 , and the charge accumulated in the photoelectric conversion stack 23 is read out to the control section via the first electrode 21. Here, the potential of the first electrode 21 is higher than the potential of the second electrode 22, and therefore, the following expression holds.

[0517] V 21 ≥V 41 and V 22 ≥V 42

[0518] As described above, in the imaging element of Example 8, a charge transfer control electrode is formed in place of the second electrode in the region of the photoelectric conversion layer located between adjacent imaging elements. Therefore, the charge transfer control electrode prevents charge generated by photoelectric conversion from flowing into adjacent imaging elements, thereby preventing degradation in the quality of captured images.

[0519] Figure 47Ais a partial schematic cross-sectional view of a modification of the imaging element of Example 8 (two imaging elements arranged side by side), and Figure 48A and Figure 48B This is a partial schematic plan view of a modified example of the imaging element (two imaging elements arranged side by side) of Example 8. In this modified example, a second electrode 22 is provided for each imaging element, an upper charge transfer control electrode 28 surrounds at least a portion of the second electrode 22 and is provided separately from the second electrode 22, and a portion of the charge accumulation electrode 24 is located below the upper charge transfer control electrode 28. The second electrode 22 is provided above the charge accumulation electrode 24, with a smaller size than the charge accumulation electrode 24.

[0520] Figure 47B is a partial schematic cross-sectional view of a modification of the imaging element of Example 8 (two imaging elements arranged side by side), and Figure 49A and Figure 49B This is a partial schematic plan view of a modified example of the imaging element of Example 8 (two imaging elements arranged side by side). In this modified example, the second electrode 22 is provided for each imaging element, the upper charge transfer control electrode 28 surrounds at least a portion of the second electrode 22 and is provided separately from the second electrode 22, a portion of the charge accumulation electrode 24 exists below the upper charge transfer control electrode 28, and furthermore, the lower charge transfer control electrode (lower charge transfer control electrode) 27 is provided below the upper charge transfer control electrode (upper charge transfer control electrode) 28. The size of the second electrode 22 is smaller than Figure 47A The size of the second electrode 22 in the modified example shown is as follows. That is, the area of ​​the second electrode 22 facing the upper charge transfer control electrode 28 is smaller than Figure 47A In the illustrated modification, a region of the second electrode 22 facing the upper charge transfer control electrode 28 is closer to the first electrode 21. The charge accumulation electrode 24 is surrounded by the lower charge transfer control electrode 27.

[0521] [Example 9]

[0522] Example 9 relates to the solid-state imaging devices of the first and second configurations.

[0523] A solid-state imaging device according to Embodiment 9 includes:

[0524] The photoelectric conversion unit includes a stacked first electrode 21, an inorganic oxide semiconductor material layer 23C, a protective layer 23B, a photoelectric conversion layer 23A, and a second electrode 22, wherein:

[0525] The photoelectric conversion unit further includes a plurality of imaging elements, each of which includes a charge accumulation electrode 24 disposed separately from the first electrode 21 and facing the inorganic oxide semiconductor material layer 23C via the insulating layer 82.

[0526] A plurality of imaging elements constitute an imaging element block, and

[0527] The first electrode 21 is shared by a plurality of imaging elements constituting the imaging element block.

[0528] Alternatively, the solid-state imaging device of Embodiment 9 includes a plurality of imaging elements as described in Embodiments 1 to 8.

[0529] In Example 9, a single floating diffusion layer is provided for multiple imaging elements. Furthermore, by appropriately controlling the timing of the charge transfer period, multiple imaging elements can share a single floating diffusion layer. In this case, multiple imaging elements can share a single contact hole portion.

[0530] Note that the solid-state imaging device of Example 9 has a configuration and structure basically similar to those described in Examples 1 to 8, except that the first electrode 21 is shared by a plurality of imaging elements constituting the imaging element block.

[0531] Figure 50 (Example 9), Figure 51 (First variation of Example 9), Figure 52 (Second variation of Example 9), Figure 53 (Third variation of Example 9) and Figure 54 (Fourth Modification of Embodiment 9) The arrangement state of the first electrode 21 and the charge accumulation electrode 24 in the solid-state imaging device of Embodiment 9 is schematically shown. Figure 50 、 Figure 51 、 Figure 54 and Figure 55 16 imaging elements are shown, and Figure 52 and Figure 53 12 imaging elements are shown. In addition, the imaging element block includes two imaging elements. The imaging element block is represented by being surrounded by a dotted line. The subscripts attached to the first electrode 21 and the charge accumulation electrode 24 are used to distinguish each first electrode 21 and each charge accumulation electrode 24. This also applies to the following description. In addition, an on-chip microlens (on the Figures 50 to 57 In addition, in one imaging element block, two charge accumulating electrodes 24 are provided so as to sandwich the first electrode 21 therebetween (see Figure 50 and Figure 51Alternatively, one first electrode 21 is arranged to face two charge accumulation electrodes 24 arranged side by side (see Figure 54 and Figure 55 ). That is, the first electrode is arranged adjacent to the charge accumulation electrodes of the respective imaging elements. Alternatively, the first electrode is arranged adjacent to some of the charge accumulation electrodes of the plurality of imaging elements and not adjacent to the remaining charge accumulation electrodes of the plurality of imaging elements (see Figure 52 and Figure 53 ), in this case, the movement of charge from the remaining imaging elements among the plurality of imaging elements to the first electrode is via the movement of some imaging elements among the plurality of imaging elements. In order to ensure that the charge moves from each imaging element to the first electrode, preferably, the distance A between the charge accumulation electrode included in the imaging element and the charge accumulation electrode included in the imaging element is longer than the distance B between the first electrode and the charge accumulation electrode in the imaging element adjacent to the first electrode. In addition, preferably, the value of the distance A increases as the imaging element is farther away from the first electrode. In addition, in Figure 51 、 Figure 53 and Figure 55 In the example shown, the charge transfer control electrode 27 is arranged between the plurality of imaging elements constituting the imaging element block. By arranging the charge transfer control electrode 27, the movement of charge in the imaging element block at the position sandwiched by the charge transfer control electrode 27 can be reliably suppressed. 31 >V 17 It is sufficient to establish that V 17 represents the potential applied to the charge transfer control electrode 27 .

[0532] The charge transfer control electrode 27 can be formed on the same horizontal plane as the first electrode 21 or the charge accumulation electrode 24, or it can be formed on a different horizontal plane from the first electrode 21 or the charge accumulation electrode 24 (specifically, a horizontal plane below the first electrode 21 or the charge accumulation electrode 24). In the former case, since the distance between the charge transfer control electrode 27 and the photoelectric conversion layer can be shortened, it is easier to control the potential. In contrast, in the latter case, since the distance between the charge transfer control electrode 27 and the charge accumulation electrode 24 can be shortened, it is advantageous to achieve miniaturization.

[0533] Hereinafter, the first electrode 212 and the two charge accumulation electrodes 24 will be described. 21 and 24 22 The operation of the imaging element block is described.

[0534] During the charge accumulation period, a potential V is applied from the driving circuit to the first electrode 212. 11 , and to the charge accumulating electrode 24 21and 24 22 Applied potential V 31 The light incident on the photoelectric conversion layer 23A is photoelectrically converted in the photoelectric conversion layer 23A. The holes generated by the photoelectric conversion are transmitted from the second electrode 22 to the wiring V OU At the same time, the potential V of the first electrode 212 is 11 Higher than the potential V of the second electrode 22 21 , that is, for example, a positive potential is applied to the first electrode 212, and a negative potential is applied to the second electrode 22. Therefore, V 31 ≥V 11 Established, preferably, V 31 >V 11 Therefore, the electrons generated by photoelectric conversion are attracted to the charge storage electrode 24. 21 and 24 22 , and is retained on the inorganic oxide semiconductor material layer 23C and the like facing the charge accumulating electrode 24 21 and 24 22 That is, charges are accumulated in the inorganic oxide semiconductor material layer 23C and the like. 31 ≥V 11 Therefore, the electrons generated in the photoelectric conversion layer 23A do not move to the first electrode 212. As the time of photoelectric conversion passes, the inorganic oxide semiconductor material layer 23C and the like facing the charge storage electrode 24 21 and 24 22 The potential in the region has a more negative value.

[0535] At the end of the charge accumulation period, a reset operation is performed. As a result, the potential of the first floating diffusion layer is reset, and the potential of the first floating diffusion layer is converted to the potential V DD .

[0536] After the reset operation is completed, the charge is read out. That is, during the charge transfer period, the potential V is applied from the drive circuit to the first electrode 212. 21 , to the charge accumulation electrode 24 21 Applied potential V 32-A , and to the charge accumulating electrode 24 22 Applied potential V 32-B Here, V 32-A <V 21 <V 32-B Therefore, the charge accumulating electrode 24 21The electrons in the region of are read out to the first electrode 212 and further read out to the first floating diffusion layer. That is, the electrons accumulated in the inorganic oxide semiconductor material layer 23C and the like facing the charge accumulation electrode 24 21 The charge in the region is read out to the control unit. Once the readout is completed, V 32-B ≤V 32-A <V 21 Established. It should be noted that Figure 54 and Figure 55 In the example shown, V 32-B <V 21 <V 32-A Therefore, the charge accumulating electrode 24 22 The electrons in the region are read out to the first electrode 212 and further read out to the first floating diffusion layer. Figure 52 and Figure 53 In the example shown, the charge storage electrode 24 22 The electrons in the region can pass through the charge accumulation electrode 24 22 The adjacent first electrode 213 is read out to the first floating diffusion layer. In this way, the charge accumulated in the inorganic oxide semiconductor material layer 23C and the like facing the charge accumulation electrode 24 22 The charge in the region is read out to the control unit. Note that once the charge accumulated in the inorganic oxide semiconductor material layer 23C and the like is completed, the charge accumulating electrode 24 21 The charge in the region is read out to the control unit, and the potential of the first floating diffusion layer can be reset.

[0537] Figure 58A An example of readout and driving in the image pickup element block of the ninth embodiment is shown.

[0538] [Step-A]

[0539] Input the auto-zero signal to the comparator

[0540] [Step-B]

[0541] Reset operation of a shared floating diffusion layer

[0542] [Step-C]

[0543] and the charge accumulating electrode 24 21 The corresponding P-phase readout in the imaging element and the transfer of charges to the first electrode 212

[0544] [Step-D]

[0545] and the charge accumulating electrode 2421 The D-phase readout in the corresponding imaging element and the transfer of charges to the first electrode 212

[0546] [Step-E]

[0547] Reset operation of a shared floating diffusion layer

[0548] [Step-F]

[0549] Input the auto-zero signal to the comparator

[0550] [Step-G]

[0551] and the charge accumulating electrode 24 22 The corresponding P-phase readout in the imaging element and the transfer of charges to the first electrode 212

[0552] [Step-H]

[0553] and the charge accumulating electrode 24 22 The D-phase readout in the corresponding imaging element and the transfer of charges to the first electrode 212

[0554] According to the above process, the charge storage electrode 24 is read. 21 and the charge accumulation electrode 24 22 The difference between the P-phase readout in [Step-C] and the D-phase readout in [Step-D] is the difference between the charge storage electrode 24 and the charge storage electrode 24. 21 The difference between the P-phase readout in [Step-G] and the D-phase readout in [Step-H] is the difference between the charge storage electrode 24 and the charge storage electrode 24. 22 The corresponding imaging element signal.

[0555] Please note that the operation of [Step-E] can be omitted (see Figure 58B ). In addition, the operation of [Step-F] may be omitted, and in this case, [Step-G] may be further omitted (see Figure 58C ); In addition, the difference between the P phase readout in [step-C] and the D phase readout in [step-D] is from the charge accumulation electrode 24 21 The difference between the D-phase readout in [step-D] and the D-phase readout in [step-H] is the difference between the D-phase readout and the charge accumulation electrode 24. 22 The corresponding imaging element signal.

[0556] Figure 56 (Sixth variation of Example 9) and Figure 57(Seventh Modification of Example 9) Schematically shows the arrangement of the first electrode 21 and the charge accumulation electrode 24 in the modification. In these modifications, four imaging elements constitute the imaging element block. The operation of these solid-state imaging devices can be the same as Figures 50 to 55 The operations of the solid-state image pickup devices shown are basically the same.

[0557] In the solid-state imaging device of Example 9, the first electrode is shared by the multiple imaging elements that make up the imaging element block. This allows for simplification and miniaturization of the configuration and structure of the pixel region in which the multiple imaging elements are arranged. Note that the multiple imaging elements provided for a single floating diffusion layer may include multiple first-type imaging elements, or may include at least one first-type imaging element and one or more second-type imaging elements.

[0558] [Example 10]

[0559] Example 10 is a variation of Example 9. Figure 59 、 Figure 60 、 Figure 61 and Figure 62 The arrangement of the first electrode 21 and the charge accumulation electrode 24 is schematically shown. In the solid-state imaging device of Example 10, two imaging elements constitute the imaging element block. In addition, an on-chip microlens 14 is arranged above the imaging element block. It should be noted that Figure 60 and Figure 62 In the illustrated example, the charge transfer control electrode 27 is arranged between a plurality of image pickup elements constituting the image pickup element block.

[0560] For example, the charge storage electrode 24 constituting the image pickup element block 11 ,twenty four 21 ,twenty four 31 and 24 41 The corresponding photoelectric conversion layer has high sensitivity to incident light from the upper right in the figure. 12 ,twenty four 22 ,twenty four 32 and 24 42 The corresponding photoelectric conversion layer has high sensitivity to incident light from the upper left in the figure. Therefore, for example, by 11 The imaging element and the charge accumulating electrode 24 12 In addition, by combining the image pickup element 24 with the charge accumulation electrode 24, the image plane phase difference signal can be obtained. 11 The signal from the imaging element and the charge accumulating electrode 24 12By adding the signals of the imaging elements, a single imaging element can be formed by combining these imaging elements. Figure 59 In the example shown, the first electrode 211 is arranged between the charge accumulation electrode 24 11 and the charge accumulating electrode 24 12 However, as in Figure 61 As in the example shown, by arranging one first electrode 211 to face two charge accumulation electrodes 24 arranged side by side, 11 and 24 12 , which can further improve the sensitivity.

[0561] While the present disclosure has been described based on preferred embodiments, the present disclosure is not limited to these embodiments. The structures and configurations, manufacturing conditions, manufacturing methods, and materials used in the imaging elements, stacked imaging elements, and solid-state imaging devices described in the embodiments are merely illustrative and may be modified as appropriate. The imaging elements of the embodiments may be combined as appropriate. The configurations and structures of the imaging elements of the present disclosure are applicable to light-emitting elements, such as organic EL elements, or to the channel formation region of thin-film transistors.

[0562] As appropriate, as described above, the floating diffusion layers FD1 , FD2 , and FD3 , the source / drain region 51C, the region 45C, and the region 46C may also be shared.

[0563] in addition, Figure 63 This figure shows a modified example of the imaging element and stacked imaging element described in Example 1. As shown in the figure, for example, a configuration can be adopted in which light enters from the second electrode 22 side and a light shielding layer 15 is formed on the light-incident side close to the second electrode 22. It should be noted that various wiring lines provided closer to the light-incident side than the photoelectric conversion layer can also function as a light shielding layer.

[0564] Please note that Figure 63 In the example shown, the light shielding layer 15 is formed above the second electrode 22, that is, the light shielding layer 15 is formed near the light incident side of the second electrode 22 and above the first electrode 21; however, as Figure 64 As shown, the light shielding layer 15 may also be arranged on the surface of the second electrode 22 on the light incident side. Figure 65 As shown, the second electrode 22 may be provided with a light shielding layer 15 as appropriate.

[0565] Alternatively, a structure may be employed in which light is incident from the second electrode 22 side and light is not incident on the first electrode 21. Specifically, as Figure 63 As shown, the light shielding layer 15 is formed on the light incident side close to the second electrode 22 and above the first electrode 21. Alternatively, the following structure may be adopted: Figure 67As shown in FIG. 1 , the on-chip microlens 14 is provided above the charge accumulation electrode 24 and the second electrode 22, and light incident on the on-chip microlens 14 is focused on the charge accumulation electrode 24 and does not reach the first electrode 21. Note that, as described in Example 4, in the case where the transfer control electrode 25 is provided, a configuration in which light is not incident on the first electrode 21 and the transfer control electrode 25 may be employed. Specifically, the following configuration may be employed: Figure 66 As shown, the light shielding layer 15 is formed above the first electrode 21 and the transfer control electrode 25. Alternatively, a structure may be employed in which light incident on the on-chip microlens 14 does not reach the first electrode 21 or both.

[0566] By adopting these configurations and structures, or by providing the light shielding layer 15 to allow light to enter only the portion of the photoelectric conversion unit located above the charge accumulation electrode 24, or by designing the on-chip microlens 14, the portion of the photoelectric conversion unit located above the first electrode 21 (or above the first electrode 21 and the transfer control electrode 25) does not contribute to photoelectric conversion, so all pixels can be reset simultaneously more reliably, and the global shutter function can be more easily implemented. Therefore, in a driving method of a solid-state imaging device including a plurality of imaging elements having these configurations and structures, the following steps are repeated:

[0567] In all the imaging elements, the charge is accumulated in the inorganic oxide semiconductor material layer 23C and the like, while the charge in the first electrode 21 is discharged to the outside of the system; thereafter,

[0568] In all the imaging elements, the charges accumulated in the inorganic oxide semiconductor material layer 23C and the like are simultaneously transferred to the first electrode 21 , and after the transfer is completed, the charges transferred to the first electrode 21 are sequentially read out in the respective imaging elements.

[0569] In this driving method for a solid-state imaging device, each imaging element has a structure in which light incident from the second electrode side does not strike the first electrode. In all imaging elements, charge is simultaneously accumulated in the inorganic oxide semiconductor material layer, etc., while the charge in the first electrode is simultaneously discharged to the outside of the system. Therefore, the first electrode can be reliably reset simultaneously in all imaging elements. Subsequently, the charge accumulated in the inorganic oxide semiconductor material layer, etc., is simultaneously transferred to the first electrode in all imaging elements. After the transfer is complete, the charge transferred to the first electrode is sequentially read out in the imaging elements. This makes it easy to implement a so-called global shutter function.

[0570] In the case where one inorganic oxide semiconductor material layer 23C and one protective layer 23B are formed to be shared by a plurality of imaging elements, it is desirable that the ends of the inorganic oxide semiconductor material layer 23C and the protective layer 23B are covered by at least the photoelectric conversion layer 23A from the perspective of protecting the ends of the inorganic oxide semiconductor material layer 23C and the protective layer 23B. Figure 1 The structure shown at the right end of the schematic cross-sectional view of the inorganic oxide semiconductor material layer 23C and the protective layer 23B is sufficient.

[0571] In addition, as a modification of Example 4, Figure 67 As shown, a plurality of transfer control electrodes may be provided from the position closest to the first electrode 21 toward the charge accumulation electrode 24. Figure 67 An example is shown in which two transfer control electrodes 25A and 25B are provided. Alternatively, a structure may be employed in which the on-chip microlens 14 is provided above the charge accumulation electrode 24 and the second electrode 22 so that light incident on the on-chip microlens 14 is focused on the charge accumulation electrode 24 and does not reach the first electrode 21 and the transfer control electrodes 25A and 25B.

[0572] The first electrode 21 may be configured to extend within the second opening portion 85 provided in the insulating layer 82 and be connected to the inorganic oxide semiconductor material layer 23C.

[0573] In addition, in the embodiment, the case of application to a CMOS type solid-state imaging device has been described as an example, in which the unit pixels for sensing the signal charge corresponding to the amount of incident light as a physical quantity are arranged in a matrix manner; however, the present disclosure is not limited to application to a CMOS type solid-state imaging device, and can also be applied to a CCD type solid-state imaging device. In the latter case, the signal charge is transmitted in the vertical direction through a vertical transfer register having a CCD type structure, and is transmitted in the horizontal direction through a horizontal transfer register, and then amplified, resulting in an output pixel signal (image signal). In addition, possible applications are generally not limited to column-type solid-state imaging devices, in which pixels are formed into a two-dimensional matrix pattern, and a column signal processing circuit is arranged for each pixel column. In addition, depending on the situation, the selection transistor can be omitted.

[0574] Furthermore, the imaging element and stacked imaging element of the present disclosure are applicable not only to solid-state imaging devices that sense the distribution of incident visible light and capture an image of the distribution, but also to solid-state imaging devices that capture an image of the distribution of incident infrared light, X-rays, particles, etc. Furthermore, in a broad sense, the imaging element and stacked imaging element of the present disclosure are generally applicable to solid-state imaging devices (physical quantity distribution sensing devices) that sense the distribution of other physical quantities, including pressure and capacitance, and capture an image of the distribution, such as fingerprint detection sensors.

[0575] Furthermore, possible applications are not limited to solid-state imaging devices that sequentially scan each unit pixel in an imaging area in rows and read out pixel signals from the unit pixels. Application to XY address-type solid-state imaging devices is also possible, which select arbitrary pixels in units of pixels and read out pixel signals from the selected pixels in units of pixels. The solid-state imaging device may be formed as a single chip, or may be in the form of a module having an imaging function in which the imaging area and a drive circuit or optical system are packaged together.

[0576] In addition, possible applications are not limited to solid-state imaging devices, but can also be applied to imaging devices. Here, an imaging device refers to an electronic device with an imaging function, and examples of such electronic devices include camera systems such as digital cameras or video cameras, mobile phones, etc. In some cases, the imaging device may also be an imaging device in the form of a module (i.e., a camera module) mounted on the electronic device.

[0577] Figure 69As a conceptual diagram, an example of using a solid-state imaging device 201 including an imaging element and a stacked imaging element of the present disclosure in an electronic device (camera) 200 is shown. The electronic device 200 includes a solid-state imaging device 201, an optical lens 210, a shutter device 211, a drive circuit 212, and a signal processing circuit 213. The optical lens 210 focuses image light (incident light) from a subject to form an image on an imaging plane of the solid-state imaging device 201. As a result, signal charge is accumulated in the solid-state imaging device 201 for a predetermined period of time. The shutter device 211 controls the illumination period and the light shielding period of the solid-state imaging device 201. The drive circuit 212 supplies a drive signal to control the transmission operation of the solid-state imaging device 201 and the shutter operation of the shutter device 211. Signal transmission is performed in the solid-state imaging device 201 based on the drive signal (timing signal) supplied from the drive circuit 212. The signal processing circuit 213 performs various signal processing. The image signal that has undergone signal processing is stored in a storage medium such as a memory or output to a monitor. In this electronic device 200, the solid-state imaging device 201 enables miniaturization of pixel size and improvement of transmission efficiency, thereby providing an electronic device 200 with improved pixel characteristics. Examples of electronic devices 200 to which the solid-state imaging device 201 is applicable are not limited to cameras, but include digital cameras, camera modules for mobile devices such as mobile phones, and other imaging devices.

[0578] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

[0579] Figure 73 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0580] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 73 In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0581] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating vehicle drive force; a drive force transmission mechanism for transmitting drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating vehicle braking force.

[0582] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as the headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0583] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can perform object detection or distance detection on objects such as people, vehicles, obstacles, signs, or letters on the road.

[0584] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output this electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0585] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 for detecting the driver's condition. Driver status detection unit 12041, for example, includes a camera for capturing the driver's image. Based on the detection information input from driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0586] Based on information about the exterior or interior of the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, the microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), such as collision avoidance or impact mitigation, follow-up driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning, or vehicle lane departure warning.

[0587] In addition, based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform collaborative control such as automatic driving to enable the vehicle to drive autonomously without relying on the driver's operation by controlling the driving force generating device, steering mechanism or braking device, etc.

[0588] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights to switch from high beam to low beam based on the position of a preceding vehicle or an approaching vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare.

[0589] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Figure 73 In the example of FIG, as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0590] Figure 74 This is a diagram showing an example of the installation position of the camera unit 12031.

[0591] exist Figure 74 , the camera unit 12031 includes camera units 12101 , 12102 , 12103 , 12104 and 12105 .

[0592] Camera units 12101, 12102, 12103, 12104, and 12105 are, for example, located on the front nose, rearview mirror, rear bumper, and rear door of vehicle 12100, as well as on the upper portion of the windshield inside the vehicle. Camera unit 12101 located on the front nose and camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Camera units 12102 and 12103 located on the rearview mirror primarily capture images from the side of vehicle 12100. Camera unit 12104 located on the rear bumper or rear door primarily captures images from the rear of vehicle 12100. Camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily detects preceding vehicles, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0593] By the way, Figure 74 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located on the rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of vehicle 12100 as viewed from above is obtained.

[0594] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or an imaging element having pixels for phase difference detection.

[0595] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111-12114 and the temporal change in that distance (relative speed to vehicle 12100) based on the distance information obtained from imaging units 12101-12104. This allows microcomputer 12051 to specifically extract the closest three-dimensional object as the preceding vehicle: the object is located in the path of vehicle 12100 and is traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., greater than or equal to 0 km / h). Furthermore, microcomputer 12051 can pre-set the inter-vehicle distance to be maintained ahead of the preceding vehicle and can execute automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control). This allows for cooperative control, such as automated driving, which allows the vehicle to travel autonomously without relying on driver input.

[0596] For example, based on the distance information obtained from the imaging units 12101-12104, the microcomputer 12051 can classify 3D object data regarding three-dimensional objects into 3D object data for two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, indicating a potential collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or display unit 12062 and executes forced deceleration or evasive steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0597] At least one of the imaging units 12101-12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in the images captured by the imaging units 12101-12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras; and performing pattern matching on a series of feature points representing the outline of an object to determine whether the pedestrian is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a rectangular outline superimposed on the identified pedestrian for emphasis. The audio / video output unit 12052 may also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0598] In addition, for example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0599] Figure 75 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (the present technology) can be applied.

[0600] exist Figure 75, a surgeon (physician) 11131 is shown performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 supporting the endoscope 11100, and a cart 11200 equipped with various devices used for endoscopic surgery.

[0601] Endoscope 11100 includes: a barrel 11101, a region having a predetermined length from the distal end of barrel 11101 being inserted into a body cavity of patient 11132; and a camera 11102 connected to the proximal end of barrel 11101. In the illustrated example, endoscope 11100 is configured as a rigid endoscope having a hard barrel 11101. However, endoscope 11100 may alternatively be configured as a flexible endoscope having a flexible barrel 11101.

[0602] The distal end of the lens barrel 11101 has an opening portion in which an objective lens is mounted. A light source device 11203 is connected to the endoscope 11100 so that light generated by the light source device 11203 is guided to the distal end of the lens barrel 11101 via a light guide extending inside the lens barrel 11101, and the light is irradiated toward an observation object in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 may be a forward-looking endoscope, or may be an oblique-looking endoscope or a side-looking endoscope.

[0603] The camera head 11102 is equipped with an optical system and an imaging element. Light reflected from the observation object (observation light) passes through the optical system and is focused on the imaging element. The observation light undergoes photoelectric conversion by the imaging element to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the Camera Control Unit (CCU) 11201.

[0604] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102 and performs various image processing such as development processing (demosaicing processing) on ​​the image signal for displaying an image based on the image signal.

[0605] Under the control of the CCU 11201 , the display device 11202 displays thereon an image based on an image signal on which image processing has been performed by the CCU 11201 .

[0606] The light source device 11203 includes a light source such as a light emitting diode (LED), for example, and supplies irradiation light for imaging a surgical site to the endoscope 11100 .

[0607] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information or commands to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input commands to change the imaging conditions of the endoscope 11100 (such as the type of irradiation light, magnification, or focal length).

[0608] The treatment tool control device 11205 controls the driving of the energy device 11112 for cauterizing or cutting tissue, sealing blood vessels, and the like. The pneumoperitoneum device 11206 feeds gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of view of the endoscope 11100 and the surgeon's working space. The recorder 11207 is a device capable of recording various surgical information. The printer 11208 is a device capable of printing various surgical information in various formats, such as text, images, or charts.

[0609] It should be noted that the light source device 11203 that supplies irradiation light to the endoscope 11100 when imaging the surgical site may include a white light source, such as an LED, a laser light source, or a combination of an LED and a laser light source. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing can be controlled with high precision for each color (various wavelengths), the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the laser beams from each of the RGB laser light sources are irradiated on the observed object in a time-division manner, and the drive of the imaging element of the camera 11102 is controlled in synchronization with the irradiation timing, images corresponding to the R, G, and B colors, respectively, can also be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0610] Furthermore, the light source device 11203 can be controlled so that the intensity of the light to be output is changed at every predetermined time. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and then synthesizing these images, a high dynamic range image without underexposed shadows or overexposed highlights can be produced.

[0611] In addition, the light source device 11203 can be configured to supply light of a predetermined wavelength band prepared for special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue to irradiate narrowband light compared to the irradiation light (i.e., white light) during ordinary observation, narrowband observation (narrowband imaging) is performed to image predetermined tissues such as blood vessels in the surface portion of the mucous membrane with high contrast. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image based on fluorescence generated by irradiation with excitation light. In fluorescence observation, observation of fluorescence from body tissue can be performed by irradiating excitation light onto the body tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to supply such narrowband light and / or excitation light suitable for special light observation as described above.

[0612] Figure 76 It shows Figure 75 A block diagram of an example of the functional configuration of the camera 11102 and CCU 11201 is shown.

[0613] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400.

[0614] The lens unit 11401 is an optical system provided at a connection position with the lens barrel 11101. Observation light obtained from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0615] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). For example, in the case where the imaging unit 11402 is constructed as a multi-board type imaging unit, the imaging element generates image signals corresponding to R, G and B, respectively, and these image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be constructed to have a pair of imaging elements to respectively obtain an image signal for the right eye and an image signal for the left eye prepared for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of the living tissue in the surgical site. It should be noted that in the case where the imaging unit 11402 is constructed as a stereoscopic type imaging unit, a plurality of lens unit 11401 systems are arranged in a manner corresponding to the respective imaging elements.

[0616] In addition, the imaging unit 11402 does not need to be provided on the camera head 11102. For example, the imaging unit 11402 can be provided inside the lens barrel 11101 immediately behind the objective lens.

[0617] The drive unit 11403 includes an actuator and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the camera unit 11402 can be appropriately adjusted.

[0618] The communication unit 11404 includes a communication device to transmit and receive various information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the imaging unit 11402 to the CCU 11201 as RAW data via the transmission cable 11400.

[0619] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information specifying a frame rate for capturing an image, information specifying an exposure value during imaging, and / or information specifying a magnification and focus of a captured image.

[0620] Note that imaging conditions such as the frame rate, exposure value, magnification, or focus may be specified by the user or automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE: Auto Exposure) function, an automatic focus (AF: Auto Focus) function, and an automatic white balance (AWB: Auto White Balance) function are incorporated into the endoscope 11100.

[0621] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0622] The communication unit 11411 includes a communication device to transmit and receive various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera 11102 through the transmission cable 11400.

[0623] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0624] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data transmitted thereto from the camera 11102 .

[0625] The control unit 11413 performs various controls related to imaging of a surgical site, etc. by the endoscope 11100 and display of images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0626] Furthermore, the control unit 11413 controls the display device 11202 to display a captured image of the surgical site, etc., based on the image signal processed by the image processing unit 11412. This allows the control unit 11413 to use various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can detect the shape and color of the edges of objects included in the captured image to identify surgical tools such as forceps, specific living body parts, bleeding, and mist generated by the energy device 11112. When the control unit 11413 controls the display device 11202 to display the captured image, it can use the recognition results to display various surgical support information superimposed on the image of the surgical site. Displaying this superimposed surgical support information and presenting it to the surgeon 11131 can reduce the burden on the surgeon 11131, allowing the surgeon 11131 to confidently perform the surgery.

[0627] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable prepared for electric signal communication, an optical fiber prepared for optical communication, or a composite cable prepared for both electric and optical communication.

[0628] Here, although in the illustrated example, communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0629] It should be noted that although an endoscopic surgical system is described here as an example, the technology according to the present disclosure can also be applied to, for example, a microsurgery system.

[0630] Note that the present disclosure may also have the following configurations.

[0631] [A01]<<Camera Component>>

[0632] An imaging element includes a photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein:

[0633] Directly below the photoelectric conversion layer, a protective layer and an inorganic oxide semiconductor material layer are formed from the photoelectric conversion unit side, the protective layer including an inorganic oxide.

[0634] [A02]

[0635] The image sensor according to [A01], wherein the oxygen vacancy formation energy of the metal atoms included in the protective layer is 5 eV or more.

[0636] [A03]

[0637] The imaging element according to [A02], wherein the following expression is satisfied:

[0638] E OD-1 -E OD-2 ≥1eV

[0639] Among them, E OD-1 represents the oxygen vacancy formation energy of the metal atoms contained in the protective layer, E OD-2 It represents the oxygen vacancy formation energy of metal atoms contained in the inorganic oxide semiconductor material layer.

[0640] [A04]

[0641] The image sensor according to [A02] or [A03], wherein the oxygen vacancy formation energy of the metal atoms contained in the inorganic oxide semiconductor material layer is 3 eV or more.

[0642] [A05]

[0643] The image pickup element according to any one of [A01] to [A04], wherein the following expression is satisfied:

[0644] E0≥E1

[0645] Here, E0 represents the energy average value of the LUMO values ​​of the photoelectric conversion layer, and E1 represents the energy average value of the maximum energy value of the conduction band of the protective layer.

[0646] [A06]

[0647] The imaging element according to [A05], wherein E0-E1≥0.1 (eV) is satisfied.

[0648] [A07]

[0649] The imaging element according to [A06], wherein the following expression is satisfied:

[0650] E1-E2≥0.1(eV)

[0651] Here, E2 represents the minimum energy value of the conduction band of the material contained in the inorganic oxide semiconductor material layer.

[0652] [A08]

[0653] The image pickup element according to any one of [A01] to [A07], wherein the following expression is satisfied:

[0654] E1-E2≥0.1(eV)

[0655] Here, E1 represents the minimum energy value of the conduction band of the inorganic oxide contained in the protective layer, and E2 represents the minimum energy value of the conduction band of the material contained in the inorganic oxide semiconductor material layer.

[0656] [A09]

[0657] The imaging element according to [A08], wherein E1-E2≥0.1 (eV) is satisfied.

[0658] [A10]

[0659] The image pickup element according to any one of [A01] to [A09], wherein the protective layer includes Nb a Ti b O c (where a+b+c=1.00).

[0660] [A11]

[0661] The image sensor according to [A10], wherein 0.05≤a≤0.25 and 0.05≤b≤0.25 are satisfied.

[0662] [A12]

[0663] The image pickup element according to any one of [A01] to [A11], wherein the protective layer prevents hydrogen from entering the inorganic oxide semiconductor material layer.

[0664] [A13]

[0665] The imaging element according to [A12], wherein the hydrogen barrier capability of the protective layer is such that the relative intensity ratio of hydrogen ions detected when heated to 350°C measured using thermal desorption spectroscopy is 0.1 or less when the intensity ratio of heated titanium detected when heated to 350°C measured using thermal desorption spectroscopy is 1.0.

[0666] [A14]

[0667] The image pickup element according to any one of [A01] to [A13], wherein the photoelectric conversion portion further includes an insulating layer and a charge accumulation electrode that is arranged separately from the first electrode and is arranged to face the inorganic oxide semiconductor material layer with the insulating layer interposed therebetween.

[0668] [A15]

[0669] The image sensor according to any one of [A01] to [A14], wherein the charges generated in the photoelectric conversion layer move to the first electrode via the protective layer and the inorganic oxide semiconductor material layer.

[0670] [A16]

[0671] The imaging element according to [A15], wherein the electric charge includes electrons.

[0672] [A17]

[0673] The imaging element according to any one of [A01] to [A16], wherein the carrier mobility of the material contained in the inorganic oxide semiconductor material layer is 10 cm 2 / V·s or above.

[0674] [A18]

[0675] The imaging element according to any one of [A01] to [A17], wherein the carrier concentration (carrier density) of the inorganic oxide semiconductor material layer is 1×10 16 / cm 3 the following.

[0676] [A19]

[0677] The image sensor according to any one of [A01] to [A18], wherein the inorganic oxide semiconductor material layer is amorphous.

[0678] [A20]

[0679] The imaging element according to any one of [A01] to [A19], wherein the thickness of the inorganic oxide semiconductor material layer is 1×10-8 m to 1.5×10 -7 m.

[0680] [B01]

[0681] The imaging element according to any one of [A01] to [A20], further comprising a semiconductor substrate, wherein

[0682] The photoelectric conversion portion is arranged over the semiconductor substrate.

[0683] [B02]

[0684] The image pickup element according to any one of [A01] to [B01], wherein the first electrode extends within an opening provided in the insulating layer and is connected to the inorganic oxide semiconductor material layer.

[0685] [B03]

[0686] The image pickup element according to any one of [A01] to [B01], wherein the inorganic oxide semiconductor material layer and the protective layer extend within an opening provided in the insulating layer and are connected to the first electrode.

[0687] [B04]

[0688] The imaging element according to [B03], wherein

[0689] The edge of the top surface of the first electrode is covered by the insulating layer,

[0690] The side surface of the opening portion is inclined in a manner that expands the opening portion from the first surface toward the second surface, wherein the first surface is the surface of the insulating layer that contacts the top surface of the first electrode, and the second surface is the surface of the insulating layer that contacts the portion of the inorganic oxide semiconductor material layer that faces the charge accumulation electrode.

[0691] [B05]

[0692] The imaging element according to [B04], wherein a side surface of the opening portion that is inclined so as to expand the opening portion from the first surface toward the second surface is located on the charge storage electrode side.

[0693] [B06] <<Potential Control of the First Electrode and the Charge Accumulation Electrode>>

[0694] The image pickup element according to any one of [A01] to [B05], further comprising a control unit provided in the semiconductor substrate and including a drive circuit, wherein

[0695] The first electrode and the charge accumulation electrode are connected to a drive circuit,

[0696] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31 , and accumulates charges in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer), and

[0697] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode. 12 , apply a potential V to the charge accumulation electrode 32 , and reads out the charge accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer) to the control unit via the first electrode,

[0698] Note that the potential of the first electrode is higher than that of the second electrode, and V 31 ≥V 11 and V 32 <V 12 Established.

[0699] [B07]<<Lower Charge Transfer Control Electrode>>

[0700] The image pickup element according to any one of [A01] to [B06], wherein a lower charge transfer control electrode is formed in a region facing a region of the photoelectric conversion layer located between adjacent image pickup elements via an insulating layer.

[0701] [B08] <<Potential Control of the First Electrode, Charge Accumulation Electrode, and Lower Charge Transfer Control Electrode>>

[0702] The imaging element according to [B07] further includes a control unit provided in the semiconductor substrate and including a drive circuit, wherein:

[0703] The first electrode, the second electrode, the charge accumulation electrode and the lower charge transfer control electrode are connected to a drive circuit.

[0704] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31 , apply a potential V to the lower charge movement control electrode 41 , and accumulates charges in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer), and

[0705] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode. 12 , apply a potential V to the charge accumulation electrode 32 , apply a potential V to the lower charge movement control electrode42 , and reads out the charge accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer) to the control unit via the first electrode,

[0706] Note that V 31 ≥V 11 , V 31 >V 41 and V 12 >V 32 >V 42 Established.

[0707] [B09]<<Upper Charge Transfer Control Electrode>>

[0708] The image pickup element according to any one of [A01] to [B06], wherein an upper charge transfer control electrode is formed on a region of the photoelectric conversion layer between adjacent image pickup elements instead of forming the second electrode.

[0709] [B10]

[0710] The imaging element according to [B09], wherein a second electrode is provided for each imaging element, and the upper charge transfer control electrode surrounds at least a portion of the second electrode and is provided on region -A of the photoelectric conversion layer in a manner separated from the second electrode.

[0711] [B11]

[0712] An imaging element according to [B09], wherein a second electrode is provided for each imaging element, an upper charge transfer control electrode surrounds at least a portion of the second electrode and is provided separately from the second electrode, and a portion of the charge accumulation electrode exists below the upper charge transfer control electrode.

[0713] [B12]

[0714] An imaging element according to any one of [B09] to [B11], wherein a second electrode is provided for each imaging element, an upper charge transfer control electrode surrounds at least a portion of the second electrode and is provided separately from the second electrode, a portion of the charge accumulation electrode exists below the upper charge transfer control electrode, and further, a lower charge transfer control electrode is formed below the upper charge transfer control electrode.

[0715] [B13] <<Potential Control of the First Electrode, Charge Accumulation Electrode, and Charge Transfer Control Electrode>>

[0716] The image pickup element according to any one of [B09] to [B12], further comprising a control unit provided in the semiconductor substrate and including a drive circuit, wherein

[0717] The first electrode, the second electrode, the charge accumulation electrode, and the charge transfer control electrode are connected to a drive circuit.

[0718] During the charge accumulation period, a potential V is applied from the drive circuit to the second electrode. 21 , apply a potential V to the charge transfer control electrode 41 , and accumulates charges in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer), and

[0719] During the charge transfer period, a potential V is applied from the driving circuit to the second electrode. 22 , apply a potential V to the charge transfer control electrode 42 , and reads out the charge accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer) to the control unit via the first electrode,

[0720] Note that V 21 ≥V 41 and V 22 ≥V 42 Established.

[0721] [B14]<<Transmission Control Electrode>>

[0722] The imaging element according to any one of [A01] to [B13], further comprising a transfer control electrode arranged separately from the first electrode and the charge accumulation electrode, and arranged to face the inorganic oxide semiconductor material layer via the insulating layer.

[0723] [B15] <<Potential Control of the First Electrode, Charge Accumulation Electrode, and Transfer Control Electrode>>

[0724] The imaging element according to [B14] further includes a control unit provided in the semiconductor substrate and including a drive circuit, wherein:

[0725] The first electrode, the charge accumulation electrode, and the transfer control electrode are connected to a drive circuit.

[0726] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31 , and apply a potential V to the transmission control electrode 51 , and accumulates charges in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer), and

[0727] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode.12 , apply a potential V to the charge accumulation electrode 32 , apply a potential V to the transmission control electrode 52 , and reads out the charge accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer) to the control unit via the first electrode,

[0728] Note that the potential of the first electrode is higher than that of the second electrode, and V 31 >V 51 and V 32 ≤V 52 ≤V 12 Established.

[0729] [B16] <<Charge Discharge Electrode>>

[0730] The image pickup element according to any one of [A01] to [B15], further comprising a charge discharge electrode connected to the inorganic oxide semiconductor material layer and arranged separately from the first electrode and the charge accumulation electrode.

[0731] [B17]

[0732] The image pickup element according to [B16], wherein the charge discharge electrode is arranged to surround the first electrode and the charge accumulation electrode.

[0733] [B18]

[0734] The imaging element according to [B16] or [B17], wherein:

[0735] The inorganic oxide semiconductor material layer and the protective layer extend within the second opening provided in the insulating layer and are connected to the charge discharge electrode.

[0736] The edge of the top surface of the charge discharge electrode is covered with an insulating layer,

[0737] The charge discharge electrode is exposed at the bottom surface of the second opening, and

[0738] The side surface of the second opening portion is inclined in a manner that expands the second opening portion from the third surface toward the second surface, wherein the third surface is a surface of the insulating layer that contacts the top surface of the charge discharge electrode, and the second surface is a surface of the insulating layer that contacts a portion of the inorganic oxide semiconductor material layer that faces the charge accumulation electrode.

[0739] [B19] <<Potential Control of the First Electrode, the Charge Accumulation Electrode, and the Charge Discharge Electrode>>

[0740] The image pickup element according to any one of [B16] to [B18], further comprising a control unit provided in the semiconductor substrate and including a drive circuit, wherein

[0741] The first electrode, the charge accumulation electrode, and the charge discharge electrode are connected to a drive circuit.

[0742] During the charge accumulation period, a potential V is applied from the drive circuit to the first electrode. 11 , apply a potential V to the charge accumulation electrode 31 , apply a potential V to the charge discharge electrode 61 , and accumulates charges in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer), and

[0743] During the charge transfer period, a potential V is applied from the driving circuit to the first electrode. 12 , apply a potential V to the charge accumulation electrode 32 , apply a potential V to the charge discharge electrode 62 , and reads out the charge accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer, the protective layer, and the photoelectric conversion layer) to the control unit via the first electrode,

[0744] Note that the potential of the first electrode is higher than that of the second electrode, and V 61 >V 11 and V 62 <V 12 Established.

[0745] [B20] <<Charge Accumulation Electrode Section>>

[0746] The image pickup element according to any one of [A01] to [B19], wherein the charge accumulation electrode includes a plurality of charge accumulation electrode segments.

[0747] [B21]

[0748] The imaging element according to [B20], wherein

[0749] In the case where the potential of the first electrode is higher than the potential of the second electrode, during the charge transfer period, the potential applied to the charge accumulation electrode segment closest to the first electrode is higher than the potential applied to the charge accumulation electrode segment farthest from the first electrode, and

[0750] When the potential of the first electrode is lower than that of the second electrode, during the charge transfer period, the potential applied to the charge accumulation electrode segment closest to the first electrode is lower than the potential applied to the charge accumulation electrode segment farthest from the first electrode.

[0751] [B22]

[0752] The imaging element according to any one of [A01] to [B21], wherein

[0753] In the semiconductor substrate, at least a floating diffusion layer and an amplifying transistor included in the control section are provided, and

[0754] The first electrode is connected to the floating diffusion layer and the gate portion of the amplification transistor.

[0755] [B23]

[0756] The imaging element according to [B22], wherein

[0757] In the semiconductor substrate, a reset transistor and a selection transistor included in the control unit are further provided.

[0758] The floating diffusion layer is connected to one of the source / drain regions of the reset transistor, and

[0759] One of the source / drain regions of the amplification transistor is connected to one of the source / drain regions of the selection transistor, and the other of the source / drain regions of the selection transistor is connected to the signal line.

[0760] [B24]

[0761] The image sensor according to any one of [A01] to [B23], wherein the size of the charge accumulation electrode is larger than the size of the first electrode.

[0762] [B25]

[0763] The image pickup element according to any one of [A01] to [B24], wherein light is incident from the second electrode side, and a light shielding layer is formed on the light incident side close to the second electrode.

[0764] [B26]

[0765] The image pickup element according to any one of [A01] to [B24], wherein light is incident from the second electrode side and the light is not incident on the first electrode.

[0766] [B27]

[0767] The image pickup element according to [B26], wherein the light shielding layer is formed on the light incident side close to the second electrode and above the first electrode.

[0768] [B28]

[0769] The imaging element according to [B26], wherein

[0770] An on-chip microlens is provided above the charge accumulation electrode and the second electrode, and

[0771] Light incident on the microlens on the chip is focused on the charge accumulation electrode.

[0772] [B29] <<Image Sensor: First Structure>>

[0773] The imaging element according to any one of [A01] to [B28], wherein

[0774] The photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit segments,

[0775] The inorganic oxide semiconductor material layer, the protective layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0776] The insulating layer includes N insulating layer segments,

[0777] The charge accumulation electrode includes N charge accumulation electrode segments,

[0778] The nth (where n=1, 2, 3, ..., N) photoelectric conversion section includes the nth charge accumulation electrode section, the nth insulating layer section, and the nth photoelectric conversion layer section.

[0779] The photoelectric conversion section with a larger n value is farther away from the first electrode, and

[0780] The thickness of the insulating layer section gradually changes from the first photoelectric conversion region section to the Nth photoelectric conversion region section.

[0781] [B30] <<Image Sensor: Second Structure>>

[0782] The imaging element according to any one of [A01] to [B28], wherein

[0783] The photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit segments,

[0784] The inorganic oxide semiconductor material layer, the protective layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0785] The insulating layer includes N insulating layer segments,

[0786] The charge accumulation electrode includes N charge accumulation electrode segments,

[0787] The nth (where n=1, 2, 3, ..., N) photoelectric conversion section includes the nth charge accumulation electrode section, the nth insulating layer section, and the nth photoelectric conversion layer section.

[0788] The photoelectric conversion section with a larger n value is farther away from the first electrode, and

[0789] The thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion region section to the Nth photoelectric conversion region section.

[0790] [B31] <<Image Sensor: Third Structure>>

[0791] The imaging element according to any one of [A01] to [B28], wherein

[0792] The photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit segments,

[0793] The inorganic oxide semiconductor material layer, the protective layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0794] The insulating layer includes N insulating layer segments,

[0795] The charge accumulation electrode includes N charge accumulation electrode segments,

[0796] The nth (where n=1, 2, 3, ..., N) photoelectric conversion section includes the nth charge accumulation electrode section, the nth insulating layer section, and the nth photoelectric conversion layer section.

[0797] The photoelectric conversion section with a larger n value is farther away from the first electrode, and

[0798] The materials contained in the insulating layer sections are different between adjacent photoelectric conversion region sections.

[0799] [B32] <<Image Sensor: Fourth Structure>>

[0800] The imaging element according to any one of [A01] to [B28], wherein

[0801] The photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit segments,

[0802] The inorganic oxide semiconductor material layer, the protective layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0803] The insulating layer includes N insulating layer segments,

[0804] The charge accumulation electrode includes N charge accumulation electrode segments arranged separately from each other,

[0805] The nth (where n=1, 2, 3, ..., N) photoelectric conversion section includes the nth charge accumulation electrode section, the nth insulating layer section, and the nth photoelectric conversion layer section.

[0806] The photoelectric conversion section with a larger n value is farther away from the first electrode, and

[0807] The material contained in the charge storage electrode section is different between adjacent photoelectric conversion section.

[0808] [B33] <<Image Sensor: Fifth Structure>>

[0809] The imaging element according to any one of [A01] to [B28], wherein

[0810] The photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit segments,

[0811] The inorganic oxide semiconductor material layer, the protective layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0812] The insulating layer includes N insulating layer segments,

[0813] The charge accumulation electrode includes N charge accumulation electrode segments arranged separately from each other,

[0814] The nth (where n=1, 2, 3, ..., N) photoelectric conversion section includes the nth charge accumulation electrode section, the nth insulating layer section, and the nth photoelectric conversion layer section.

[0815] The photoelectric conversion section with a larger n value is farther away from the first electrode, and

[0816] The area of ​​the charge accumulation electrode section gradually decreases from the first photoelectric conversion region section to the Nth photoelectric conversion region section.

[0817] [B34] <<Image Sensor: Sixth Structure>>

[0818] An imaging element according to any one of [A01] to [B28], wherein a cross-sectional area of ​​a stacked portion in which a charge accumulation electrode, an insulating layer, an inorganic oxide semiconductor material layer, and a photoelectric conversion layer are stacked, cut along a YZ imaginary plane, varies depending on a distance from a first electrode, wherein the Z direction is a stacking direction of the charge accumulation electrode, the insulating layer, the inorganic oxide semiconductor material layer, and the photoelectric conversion layer, and the X direction is a direction away from the first electrode.

[0819] [C01] <<Stacked Imaging Element>>

[0820] A stacked imaging element comprising at least one imaging element according to any one of [A01] to [B34].

[0821] [D01] <<Solid-state imaging device: First embodiment>>

[0822] A solid-state imaging device comprising a plurality of imaging elements according to any one of [A01] to [B34].

[0823] [D02] <<Solid-State Imaging Device: Second Form>>

[0824] A solid-state imaging device comprising a plurality of stacked imaging elements according to [C01].

[0825] [E01] <<Solid-state imaging device: First structure>>

[0826] A solid-state imaging device includes a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode stacked together, wherein

[0827] The photoelectric conversion unit includes a plurality of imaging elements according to any one of [A01] to [B34], the plurality of imaging elements constituting an imaging element block, and

[0828] The first electrode is shared by a plurality of imaging elements constituting the imaging element block.

[0829] [E02] <<Solid-state imaging device: Second structure>>

[0830] A solid-state imaging device comprising a plurality of stacked imaging elements according to [C01], wherein:

[0831] A plurality of imaging elements constitute an imaging element block, and

[0832] The first electrode is shared by a plurality of imaging elements constituting the imaging element block.

[0833] [E03]

[0834] The solid-state imaging device according to [E01] or [E02], wherein one on-chip microlens is provided above one imaging element.

[0835] [E04]

[0836] The solid-state imaging device according to [E01] or [E02], wherein:

[0837] Two imaging elements constitute an imaging element block, and

[0838] An on-chip microlens is provided above the image sensor block.

[0839] [E05]

[0840] The solid-state imaging device according to any one of [E01] to [E04], wherein one floating diffusion layer is provided for a plurality of imaging elements.

[0841] [E06]

[0842] The solid-state imaging device according to any one of [E01] to [E05], wherein the first electrode is arranged adjacent to the charge accumulation electrode of each imaging element.

[0843] [E07]

[0844] The solid-state imaging device according to any one of [E01] to [E06], wherein the first electrode is arranged adjacent to some of the charge accumulation electrodes in the plurality of imaging elements and not adjacent to the remaining charge accumulation electrodes in the plurality of imaging elements.

[0845] [E08]

[0846] A solid-state imaging device according to [E07], wherein the distance between the charge accumulation electrode included in the imaging element and the charge accumulation electrode included in the imaging element is longer than the distance between the first electrode and the charge accumulation electrode in the imaging element adjacent to the first electrode.

[0847] [F01]<<Driving Method of Solid-State Image Capture Device>>

[0848] A method for driving a solid-state imaging device, the solid-state imaging device including a plurality of imaging elements, each imaging element including a photoelectric conversion portion including a stacked first electrode, a photoelectric conversion layer, and a second electrode, the photoelectric conversion portion further including a charge accumulation electrode, the charge accumulation electrode being arranged separately from the first electrode and arranged to face the photoelectric conversion layer with an insulating layer interposed therebetween, and each of the plurality of imaging elements having a structure in which light is incident from the second electrode side and light is not incident on the first electrode.

[0849] The driving method of the solid-state imaging device repeats the following steps:

[0850] In all imaging elements, charges are simultaneously accumulated in the inorganic oxide semiconductor material layer while charges in the first electrode are discharged to the outside of the system; thereafter,

[0851] In all the imaging elements, the charges accumulated in the inorganic oxide semiconductor material layer are simultaneously transferred to the first electrode, and after the transfer is completed, the charges transferred to the first electrode in the respective imaging elements are sequentially read out.

[0852] Reference Signs List

[0853] 10. Image sensor (stacked image sensor, first image sensor)

[0854] 11 Second camera element

[0855] 12 Third camera element

[0856] 13 Various imaging element components located below the interlayer insulating layer

[0857] 14 On-Chip Microlens (OCL)

[0858] 15. Light-shielding layer

[0859] 21 First electrode

[0860] 22 Second electrode

[0861] 23 Photoelectric conversion stack

[0862] 23A Photoelectric conversion layer

[0863] 23B protective layer

[0864] 23C inorganic oxide semiconductor material layer

[0865] 23D inorganic oxide semiconductor material layer and protective layer

[0866] 24 Charge accumulation electrode

[0867] 24A, 24B, 24C Charge accumulation electrode segments

[0868] 25, 25A, 25B Transfer control electrodes (charge transfer electrodes)

[0869] 26 Charge discharge electrode

[0870] 27 Lower charge transfer control electrode (lower charge transfer control electrode)

[0871] 27A connection hole

[0872] 27B pad

[0873] 28 Upper charge transfer control electrode (upper charge transfer control electrode)

[0874] 41 n-type semiconductor region included in the second imaging element

[0875] 43 n-type semiconductor region included in the third imaging element

[0876] 42, 44, 73 p + layer

[0877] 45, 46 Gate portion of the transfer transistor

[0878] 51 Reset transistor TR1 rst Gate

[0879] 51A reset transistor TR1 rst Channel formation region

[0880] 51B, 51C reset transistor TR1 rst Source / drain regions

[0881] 52 Amplifier transistor TR1 amp Gate

[0882] 52A amplifier transistor TR1 amp Channel formation region

[0883] 52B, 52C Amplifying transistor TR1 amp Source / drain regions

[0884] 53 Select transistor TR1 sel Gate

[0885] 53A selection transistor TR1 sel Channel formation region

[0886] 53B, 53C select transistor TR1 sel Source / drain regions

[0887] 61 Contact hole part

[0888] 62 wiring layer

[0889] 63, 64, 68A pads

[0890] 65, 68B connection holes

[0891] 66, 67, 69 connection

[0892] 70 semiconductor substrate

[0893] 70A: first surface (front surface) of semiconductor substrate

[0894] 70B: second surface (rear surface) of semiconductor substrate

[0895] 71 Component separation area

[0896] 72 Insulation material film

[0897] 74 HfO2 film

[0898] 75 Insulation material film

[0899] 76, 81 interlayer insulation layer

[0900] 82 insulation layer

[0901] 82 A The area between adjacent imaging elements (area-a)

[0902] 83 protective material layer

[0903] 84 opening

[0904] 85 Second opening

[0905] 100 Solid-state imaging device

[0906] 101 Stacked Camera Element

[0907] 111 Camera Area

[0908] 112 vertical drive circuit

[0909] 113 column signal processing circuit

[0910] 114 Horizontal drive circuit

[0911] 115 Output Circuit

[0912] 116 drive control circuit

[0913] 117 signal line (data output line)

[0914] 118 horizontal signal lines

[0915] 200 Electronic equipment (camera)

[0916] 201 Solid-state imaging device

[0917] 210 optical lens

[0918] 211 Shutter mechanism

[0919] 212 drive circuit

[0920] 213 Signal Processing Circuit

[0921] FD1, FD2, FD3, floating diffusion layer

[0922] 45C, 46C areas

[0923] TR1 trs 、TR2 trs 、TR3 trs Pass transistor

[0924] TR1 rst 、TR2 rst 、TR3 rst Reset transistor

[0925] TR1 amp 、TR2 amp 、TR3 amp Amplifier transistor

[0926] TR1sel 、TR3 sel 、TR3 sel Select transistor

[0927] V DD power supply

[0928] RST1, RST2, RST3 reset lines

[0929] SEL1, SEL2, SEL3 selection lines

[0930] 117, VSL, VSL1, VSL2, VSL3 signal lines (data output lines)

[0931] TG2, TG3 transmission gate lines

[0932] V OA 、V OB 、V OT 、V OU Wiring.

Claims

1. An imaging element comprising a photoelectric conversion unit, wherein the photoelectric conversion unit comprises a first electrode, a photoelectric conversion layer, and a second electrode stacked together, wherein: A protective layer and an inorganic oxide semiconductor material layer are formed directly below the photoelectric conversion layer from the photoelectric conversion unit side, wherein the protective layer includes an inorganic oxide. Wherein, the protective layer includes Nb a Ti b O c , where a+b+c=1.00, and Among them, 0.05≤a≤0.25 and 0.05≤b≤0.25 are satisfied.

2. The imaging element according to claim 1, wherein The oxygen vacancy formation energy of the metal atoms included in the protective layer is 5 eV or more.

3. The imaging element according to claim 2, wherein Satisfies the following expression: AND OD-1 -AND OD-2 ≥1eV Among them, E OD-1 represents the oxygen vacancy formation energy of the metal atoms contained in the protective layer, E OD-2 represents the oxygen vacancy formation energy of metal atoms contained in the inorganic oxide semiconductor material layer.

4. The imaging element according to claim 3, wherein The oxygen vacancy formation energy of the metal atoms included in the inorganic oxide semiconductor material layer is greater than or equal to 3 eV.

5. The imaging element according to any one of claims 1 to 4, wherein Satisfies the following expression: E0≥E1 Wherein, E0 represents the energy average value of the LUMO value of the photoelectric conversion layer, and E1 represents the energy average value of the maximum energy value of the conduction band of the protective layer. The imaging element according to claim 5 , wherein: Satisfy E0-E1≥0.1eV.

7. The imaging element according to claim 6, wherein Satisfies the following expression: E1-E2≥0.1eV Wherein, E2 represents the minimum energy value of the conduction band of the material contained in the inorganic oxide semiconductor material layer.

8. The imaging element according to any one of claims 1 to 4, wherein The protective layer prevents hydrogen from entering the inorganic oxide semiconductor material layer.

9. The imaging element according to claim 8, wherein As the hydrogen barrier capability of the protective layer, when the intensity ratio of heated titanium detected by thermal desorption spectroscopy is 1.0 when heated to 350°C, the relative intensity ratio of hydrogen ions detected by thermal desorption spectroscopy is 0.1 or less when heated to 350°C.

10. The imaging element according to any one of claims 1 to 4, wherein The photoelectric conversion section further includes an insulating layer and a charge accumulation electrode that is arranged separately from the first electrode and is arranged to face the inorganic oxide semiconductor material layer with the insulating layer interposed therebetween.

11. The imaging element according to any one of claims 1 to 4, wherein Charges generated in the photoelectric conversion layer move toward the first electrode via the protective layer and the inorganic oxide semiconductor material layer.

12. The imaging element according to claim 11, wherein The electric charge includes electrons. 13 . A stacked imaging element comprising at least one imaging element according to claim 1 . 14 . A solid-state imaging device comprising a plurality of imaging elements according to claim 1 . 15 . A solid-state imaging device comprising a plurality of stacked imaging elements according to claim 13 .

Images