Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a substrate substrate; and pixel circuits arranged in an array on the substrate substrate, wherein each row of pixel circuits includes a gate line extending in the row direction, and each column of pixel circuits includes a data line extending in the column direction, the gate line and the data line are disposed on different layers, the display panel has a light-transmitting region and a display region surrounding the light-transmitting region, the pixel circuits are disposed in the display region, the gate lines of each row in m rows of pixel circuits are separated by the light-transmitting region into a first gate line portion and a second gate line portion, the first gate line portion is connected to the second gate line portion through an auxiliary gate line, and at least a part of the auxiliary gate line extends along the edge of the light-transmitting region, where m is a natural number and m≥2, the data lines in each column of n columns of pixel circuits are separated by the light-transmitting region into a first data line portion and a second data line portion, the first data line portion is connected to the second data line portion through an auxiliary data line, where n is a natural number and n≥2, the auxiliary gate line includes an auxiliary gate line sub-portion, and there is an overlapping region between the auxiliary gate line sub-portion and the auxiliary data line, the m rows of pixel circuits include at least two rows of pixel circuits, and the overlapping area between the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in one row of pixel circuits in the at least two rows of pixel circuits and the auxiliary data line is different from the overlapping area between the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in another row of pixel circuits in the at least two rows of pixel circuits and the auxiliary data line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the progress of display technologies, organic light emitting diode (OLED) display devices are one of the hotspots in the research field of current flat panel display devices. OLED display light-emitting devices have attracted much attention due to their advantages such as bright colors, good viewing angles, high contrast ratios, fast response speeds, bendability, and low power consumption. OLED display devices have a wider application prospect in the future display field and have broad application spaces in multiple display fields such as mobile displays, in-vehicle displays, and medical displays.

[0003] For display devices with a camera function, such as mobile terminals, people are also increasingly demanding a high screen-to-body ratio. In recent years, the development of full-screen displays with an ultra-high screen-to-body ratio has been very rapid. However, how to enable a mobile terminal to have an ultra-high screen-to-body ratio of a full-screen display while retaining the front camera function is an urgent problem to be solved in this field. Under-screen camera technology is a good solution to achieve a full-screen display.

[0004] Disclosure

[0005] Some embodiments of the present disclosure provide a display panel, including: a substrate; and pixel circuits arranged in an array on the substrate. Each row of pixel circuits includes a gate line extending in the row direction, and each column of pixel circuits includes a data line extending in the column direction. The gate line and the data line are provided on different layers. The display panel has a light-transmitting region and a display region surrounding the light-transmitting region. The pixel circuits are provided in the display region. The gate lines of each row in m rows of pixel circuits are separated by the light-transmitting region into a first gate line portion and a second gate line portion. The first gate line portion is connected to the second gate line portion through an auxiliary gate line. At least a part of the auxiliary gate line extends along the edge of the light-transmitting region, where m is a natural number and m≥2. The data lines in each column of n columns of pixel circuits are separated by the light-transmitting region into a first data line portion and a second data line portion. The first data line portion is connected to the second data line portion through an auxiliary data line, where n is a natural number and n≥2. The auxiliary gate line includes an auxiliary gate line sub-portion, and there is an overlapping region between the auxiliary gate line sub-portion and the auxiliary data line. The m rows of pixel circuits include at least two rows of pixel circuits. The overlapping area between the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in one row of pixel circuits among the at least two rows of pixel circuits and the auxiliary data line is different from the overlapping area between the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in another row of pixel circuits among the at least two rows of pixel circuits and the auxiliary data line.

[0006] In some embodiments, the auxiliary gate line sub-portion is located on a side of the light-transmitting region close to the first gate line portion, and the auxiliary gate line sub-portion extends in the row direction.

[0007] In some embodiments, the number of auxiliary data lines overlapping with the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in one row of pixel circuits among the at least two rows of pixel circuits is different from the number of auxiliary data lines overlapping with the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in another row of pixel circuits among the at least two rows of pixel circuits.

[0008] In some embodiments, the light-transmitting region has a first axis parallel to the row direction. The first group of row pixel circuits among the m rows of pixel circuits is located on one side of the first axis, and the second group of row pixel circuits is located on the other side of the first axis. The auxiliary gate lines for connecting the first gate line portion and the second gate line portion in the first group of row pixel circuits are all located on the one side of the first axis, and the auxiliary gate lines for connecting the first gate line portion and the second gate line portion in the second group of row pixel circuits are located on the other side of the first axis.

[0009] In some embodiments, the auxiliary gate line is disposed on the same layer as the data line, and at least a portion of the auxiliary data line extends along the edge of the light-transmitting region. The auxiliary data line for connecting the first data line portions and the second data line portions of each column in at least a portion of the n column pixel circuits is disposed on the same layer as the gate line.

[0010] In some embodiments, each row of pixel circuits further includes a reset signal line extending in the row direction. The reset signal line is disposed on the same layer as and parallel to the gate line. The reset signal line in each row of the m rows of pixel circuits is separated by the light-transmitting region into a first reset signal line portion and a second reset signal line portion. In the m rows of pixel circuits, the first reset signal line portion of the i-th row of pixel circuits is electrically connected to the first gate line portion of the (i - 1)-th row of pixel circuits, and the second reset signal line portion of the i-th row of pixel circuits is electrically connected to the second gate line portion of the (i - 1)-th row of pixel circuits, where i is a natural number and 1 < i ≤ m.

[0011] In some embodiments, the end of the first reset signal line portion of the i-th row of pixel circuits near the light-transmitting region is electrically connected to the end of the first gate line portion of the (i - 1)-th row of pixel circuits near the light-transmitting region through a first portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in the (i - 1)-th row of pixel circuits. The end of the second reset signal line portion of the i-th row of pixel circuits near the light-transmitting region is electrically connected to the end of the second gate line portion of the (i - 1)-th row of pixel circuits near the light-transmitting region through a second portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in the (i - 1)-th row of pixel circuits.

[0012] In some embodiments, each row of pixel circuits further includes an initialization signal line extending in the row direction. The initialization signal line is not on the same layer as the gate line and the data line. The initialization signal line in each row of the m rows of pixel circuits is separated by the light-transmitting region into a first initialization signal line portion and a second initialization signal line portion. The first initialization signal line portions and the second initialization signal line portions of at least two rows of pixel circuits in the m rows of pixel circuits are connected to an auxiliary initialization signal line. The auxiliary initialization signal line is disposed on the same layer as the initialization signal line and is disposed around the light-transmitting region.

[0013] In some embodiments, at least a portion of the auxiliary data line extends along the edge of the light-transmitting region. The auxiliary data line for connecting the first data line portions and the second data line portions of each column in at least a portion of the n column pixel circuits is disposed on the same layer as the initialization signal line.

[0014] In some embodiments, the first data line portions of each column in the odd-numbered column pixel circuits among the n column pixel circuits are connected to the second data line portions in the same column pixel circuits through first auxiliary data lines, and the first data line portions of each column in the even-numbered column pixel circuits among the n column pixel circuits are connected to the second data line portions in the same column pixel circuits through second auxiliary data lines. The first auxiliary data line is disposed on the same layer as one of the gate lines and the initialization signal lines, and the second auxiliary data line is disposed on the same layer as the other of the gate lines and the initialization signal lines. At least a part of the first auxiliary data line extends along the edge of the light-transmitting region, and at least a part of the second auxiliary data line extends along the edge of the light-transmitting region.

[0015] In some embodiments, the light-transmitting region has a second axis parallel to the column direction. The first group of column pixel circuits among the n column pixel circuits is located on one side of the second axis, and the second group of column pixel circuits is located on the other side of the second axis. The first auxiliary data line or the second auxiliary data line for connecting the first data line portion and the second data line portion in the first group of column pixel circuits is located on the same side of the second axis, and the first auxiliary data line or the second auxiliary data line for connecting the first data line portion and the second data line portion in the second group of column pixel circuits is located on the other side of the second axis.

[0016] In some embodiments, the positive projection of the auxiliary initialization signal line on the substrate surrounds the positive projections of the first auxiliary data line and the second auxiliary data line on the substrate.

[0017] In some embodiments, the auxiliary initialization signal line is a closed loop.

[0018] In some embodiments, each row of pixel circuits further includes a light emission control line extending along the row direction. The light emission control line is disposed on the same layer as the gate line and is parallel to the gate line. The light emission control line in each row among the m rows of pixel circuits is separated by the light-transmitting region into a first light emission control line portion and a second light emission control line portion. The ends of the first light emission control line portion and the second light emission control line portion close to the light-transmitting region are suspended.

[0019] In some embodiments, each column of pixel circuits further includes a power supply signal line extending along the column direction. The power supply signal line is disposed on the same layer as the data line and is parallel to the data line. The power supply signal line in each column among the n columns of pixel circuits is separated by the light-transmitting region into a first power supply signal line portion and a second power supply signal line portion. The ends of the first power supply signal line portion and the second power supply signal line portion close to the light-transmitting region are suspended.

[0020] In some embodiments, the display panel has a winding region located between the light-transmitting region and the display region. The winding region surrounds the light-transmitting region and is surrounded by the display region, and the auxiliary gate line is located in the winding region.

[0021] In some embodiments, in the winding region of the display panel, there are a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a source-drain layer arranged in sequence away from the substrate. The gate line is located in the first gate layer, the data line and the auxiliary gate line are located in the source-drain layer. One end of the first gate line portion close to the light-transmitting region is electrically connected to the first end of the auxiliary gate line through a first via hole, and one end of the second gate line portion close to the light-transmitting region is electrically connected to the second end of the auxiliary gate line through a second via hole. The first via hole and the second via hole penetrate the second gate insulating layer and the interlayer dielectric layer located between the first gate layer and the source-drain layer.

[0022] In some embodiments, the display panel further includes a cathode layer provided on the substrate, and a packaging layer provided on the side of the cathode layer away from the substrate. The packaging layer includes a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer arranged in sequence away from the substrate.

[0023] In some embodiments, the light-transmitting region includes a light-transmitting blind hole or a light-transmitting through hole.

[0024] Some embodiments of the present disclosure provide a display device, including: the display panel described in the foregoing embodiments, and an image acquisition device located on the side of the display panel opposite to the display surface. Description of the Drawings

[0025] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present disclosure will become more apparent:

[0026] Figure 1 It is a schematic plan view of an OLED display panel in the related art;

[0027] Figure 2 For Figure 1 It is a schematic structural view of the pixel circuit in

[0028] Figure 3 It is a schematic plan view of an OLED display panel according to some embodiments of the present disclosure;

[0029] Figure 4 For Figure 3 It is an enlarged schematic view of region D in

[0030] Figure 5 For Figure 3Enlarged schematic view of the middle region E;

[0031] Figure 6 is Figure 3 Enlarged schematic view of the middle region F;

[0032] Figure 7 is Figure 3 Enlarged schematic view of the middle region G;

[0033] Figure 8 is a schematic view of the auxiliary wiring around the light-transmitting region C;

[0034] Figure 9 is Figure 3 Partial cross-sectional view showing the region A in the middle;

[0035] Figure 10 is Figure 3 Partial cross-sectional view of the light-transmitting region C in the middle;

[0036] Figure 11 is Figure 3 Partial cross-sectional view of the winding region B in the middle;

[0037] Figure 12 is Figure 4 Cross-sectional view at M in the middle;

[0038] Figure 13 is a plan view of an OLED display device according to some embodiments of the present disclosure. Detailed implementation manners

[0039] The present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the related invention and not for limiting the invention. Additionally, it should be noted that for the sake of description, only the parts related to the invention are shown in the drawings.

[0040] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

[0041] In addition, in the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can also be implemented without these specific details.

[0042] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, the first element may be named the second element, and similarly, the second element may be named the first element. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0043] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, the element or layer may be formed directly or indirectly on the other element or layer. That is, for example, there may be intermediate elements or intermediate layers. In contrast, when an element or layer is referred to as being "directly formed on" another element or layer, there are no intermediate elements or intermediate layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (for example, "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0044] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the embodiments. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that when the terms "comprise" and / or "include" are used herein, it is stated that the stated features, wholes, steps, operations, elements, and / or components exist, but do not preclude the existence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof.

[0045] In this document, unless otherwise specified, the expressions "located in the same layer" and "arranged in the same layer" generally mean that: the first component and the second component can use the same material and can be formed by the same lithography process. The expressions "located in different layers" and "arranged in different layers" generally mean that: the first component and the second component are formed by different lithography processes.

[0046] In the related art, the under-screen camera technology refers to setting an image acquisition device, such as a camera, etc., on the opposite side of the display surface of the display panel. Usually, a predetermined area needs to be reserved on the display panel, and a physical through-hole or a light-transmitting area is formed in this area, so that external light can be acquired by the image acquisition device through the physical through-hole or the light-transmitting area in the display panel, and thus imaging is realized. The above-mentioned physical through-hole or light-transmitting area usually has a small size. For example, when the physical through-hole or light-transmitting area is circular, the diameter of the physical through-hole or light-transmitting area is, for example, 4 mm or less. Thus, the screen-to-body ratio can be increased while realizing the camera function of the display device.

[0047] For the solution that adopts a light-transmitting region, there are many film layers in the manufacturing process of the display panel. To ensure the normal operation of the image acquisition device located on the opposite side of the display surface of the display panel, there are certain requirements for the transmittance of the light-transmitting region of the display panel. Since the metal film layer has a strong reflection of light, it may have a significant negative impact on the imaging effect of the image acquisition device. Therefore, the metal wiring method at and near the light-transmitting region of the display panel also plays a crucial role in the imaging of the camera.

[0048] Figure 1 is a schematic plan view of an OLED display panel in the related art. As Figure 1 shown, the OLED display panel 100’ includes a substrate 10, and a plurality of pixel circuits PC arranged in an array on the substrate 10. Each pixel circuit is a pixel, for example, providing an electrical signal for a red pixel, a blue pixel or a green pixel to realize the display of the OLED display panel. As shown in the figure, the row direction X and the column direction Y of the pixel circuits PC arranged in an array are perpendicular to each other.

[0049] Figure 2 is Figure 1 a schematic structural view of the pixel circuit in Figure 2 which shows three pixel circuits arranged in the same row. Each pixel circuit PC includes 7 thin film transistors and 1 capacitor; the display panel further includes an initialization signal line Vinit, a gate line Gate, a light emission control line EM, a reset signal line Reset, a data line Data and a power supply signal line VDD. Each trace is electrically connected to each pixel circuit PC to provide signals for each pixel circuit.

[0050] Specifically, the plurality of pixel circuits are arranged in an array, and the plurality of pixel circuits can be divided into multiple rows of pixel circuits (as Figure 2 shown, each row of pixel circuits extends along the row direction X) and multiple columns of pixel circuits (as Figure 2As shown, each column of pixel circuits extends along the column direction Y), and the initialization signal line patterns corresponding to the pixel circuits in the same row are sequentially electrically connected to form an integrated structure, which is the initialization signal line Vinit of the pixel circuits in this row; the gate line patterns corresponding to the pixel circuits in the same row are sequentially electrically connected to form an integrated structure, which is the gate line Gate of the pixel circuits in this row; the emission control signal line patterns corresponding to the pixel circuits in the same row are sequentially electrically connected to form an integrated structure, which is the emission control signal line EM of the pixel circuits in this row; the reset signal line patterns corresponding to the pixel circuits in the same row are sequentially electrically connected to form an integrated structure, which is the reset signal line Reset of the pixel circuits in this row; the data line patterns corresponding to the pixel circuits in the same column are sequentially electrically connected to form an integrated structure, which is the data line Data of the pixel circuits in this row; the power supply signal line patterns corresponding to the pixel circuits in the same column are sequentially electrically connected to form an integrated structure, which is the power supply signal line VDD of the pixel circuits in this row.

[0051] Exemplarily, each row of pixel circuits includes a plurality of pixel circuits arranged in sequence along the X direction, and the initialization signal line Vinit, the reset signal line Reset, the gate line Gate, and the emission control signal line EM all extend along the X direction. Each of the plurality of pixel circuits included in each row of pixel circuits can be respectively coupled to the corresponding initialization signal line Vinit, reset signal line Reset, gate line Gate, and emission control signal line EM, and as Figure 2 shown, for each row of pixel circuits, in the Y direction, the initialization signal line Vinit, the reset signal line Reset, the gate line Gate, and the emission control signal line EM are arranged in sequence; each column of pixel circuits includes a plurality of pixel circuits arranged in sequence along the Y direction, and the data line Data and the power supply signal line VDD both extend along the Y direction. Each of the plurality of pixel circuits included in each column of pixel circuits can be respectively coupled to the corresponding data line Data and power supply signal line VDD.

[0052] Some embodiments of the present disclosure provide an OLED display panel. Figure 3 A schematic plan view of an OLED display panel according to some embodiments of the present disclosure is shown. Figure 3 The OLED display panel shown is substantially the same in structure as the display panel shown in the related art. As Figure 1 shown. Figure 3As shown, the OLED display panel 100 also includes a substrate 10, and a plurality of pixel circuits PC arranged in an array on the substrate 10. Each pixel circuit is a pixel, which provides an electrical signal for, for example, a red pixel, a blue pixel, or a green pixel, to realize the display of the OLED display panel. Each pixel is, for example, an OLED device, including an anode, a light-emitting functional layer, and a cathode arranged successively away from the substrate 10. As shown in the figure, the row direction X and the column direction Y of the pixel circuits PC arranged in an array are perpendicular to each other.

[0053] The main difference between the two is that, for a display device with a camera function and a high screen-to-body ratio, Figure 3 the shown display panel 100 is provided with a light-transmitting area C and a display area A surrounding the light-transmitting area C. The light-transmitting area C is used to allow external light to enter the display panel 100 from the display surface of the display panel 100, pass through the light-transmitting area C, and be acquired by an image acquisition device, such as a camera, arranged on one side of the display panel 100, thereby realizing the imaging function.

[0054] The pixel circuit and its corresponding OLED device are located in the display area A, while in the light-transmitting area C, there are no pixel circuits and their corresponding OLED devices. The anode of the OLED display device is usually an opaque metal material, and there are also a plurality of patterns formed of opaque metal materials in the pixel circuit. The light-transmitting area C is mainly provided with a transparent material film layer forming the OLED display panel. Thus, the light-transmitting area C can allow as much external light as possible to pass through.

[0055] In some embodiments, the light-transmitting area C is not a physical through-hole. Therefore, in the OLED display panels in these embodiments, the function of under-screen camera can be realized without a complex hole-opening process. Compared with the technology of opening physical holes in the OLED panel, the solution of setting the light-transmitting area in some embodiments of the present disclosure can occupy a smaller area, further improve the screen-to-body ratio, and enhance the user experience. As Figure 3 shown, the orthographic projection of the light-transmitting area C on the substrate 10 is circular, with a diameter of, for example, 4 millimeters. In other embodiments, the orthographic projection of the light-transmitting area C on the substrate 10 can also be other shapes such as a square, a rectangle, a rhombus, etc. In other embodiments, the light-transmitting area C can also be a physical through-hole.

[0056] Due to the setting of the light-transmitting area C, originally, as Figure 1 and Figure 2 the m row pixel circuits passing through the position of the light-transmitting area C are separated, and the n column pixel circuits passing through the position of the light-transmitting area C are separated, where m and n are natural numbers and m, n ≥ 2.

[0057] Each of the m rows of pixel circuits is separated by a light-transmitting region C into a first pixel row segment and a second pixel row segment. The first pixel row segment is, for example, located on the left side of the light-transmitting region C shown in Figure 3 and the second pixel row segment is, for example, located on the right side of the light-transmitting region C shown in Figure 3 .

[0058] Each of the n columns of pixel circuits is separated by a light-transmitting region C into a first pixel column segment and a second pixel column segment. The first pixel column segment is, for example, located on the upper side of the light-transmitting region C shown in Figure 3 and the second pixel column segment is, for example, located on the lower side of the light-transmitting region C shown in Figure 3 .

[0059] In order for the OLED display panel 100 to display normally, in each row of the m rows of pixel circuits, the initialization signal line Vinit, reset signal line Reset, gate line Gate, and emission control line EM corresponding to the first pixel row segment need to transmit the same signals as the initialization signal line Vinit, reset signal line Reset, gate line Gate, and emission control line EM corresponding to the second pixel row segment, respectively. For example, the initialization signal line Vinit, reset signal line Reset, gate line Gate, and emission control line EM corresponding to the first pixel row segment are electrically connected to the initialization signal line Vinit, reset signal line Reset, gate line Gate, and emission control line EM corresponding to the second pixel row segment, respectively; in each column of the n columns of pixel circuits, the data line Data and power supply signal line VDD corresponding to the first pixel column segment transmit the same signals as the data line Data and power supply signal line VDD corresponding to the second pixel column segment, respectively. For example, the data line Data and power supply signal line VDD corresponding to the first pixel column segment are electrically connected to the data line Data and power supply signal line VDD corresponding to the second pixel column segment, respectively.

[0060] In order to make the light-transmitting region C of the OLED display panel 100 have as high a light transmittance as possible, patterns of light-blocking materials should be avoided as much as possible within the light-transmitting region C. Thus, as shown in Figure 3 , the OLED display panel 100 further includes a wiring winding region B configured to arrange auxiliary wirings. The auxiliary wirings can electrically connect the initialization signal line Vinit, reset signal line Reset, gate line Gate, and emission control line EM corresponding to the first pixel row segment to the initialization signal line Vinit, reset signal line Reset, gate line Gate, and emission control line EM corresponding to the second pixel row segment, respectively. The auxiliary wirings can also electrically connect the data line Data and power supply signal line VDD corresponding to the first pixel column segment to the data line Data and power supply signal line VDD corresponding to the second pixel column segment, respectively.

[0061] As shown in Figure 3As shown, the winding region B is disposed around the light-transmitting region C and is surrounded by the display region A. The width of the projection of the winding region B on the substrate 10 is, for example, 250 to 350 micrometers, that is, the distance between the light-transmitting region C and the display region A is 250 to 350 micrometers.

[0062] The wiring arrangement in the winding region B in some embodiments of the present disclosure will be described in detail below.

[0063] Figures 4 - 7 Respectively Figure 3 are enlarged schematic views of regions D, E, F, and G in. In Figures 4 - 7 the traces in, traces represented by the same type of line are in the same layer, and traces represented by different types of lines are in different layers. The type mentioned here refers to the thickness and gray scale of the line. The thickness of the line is only for distinguishing traces in different layers and does not represent the thickness of the trace.

[0064] As Figure 3 , Figures 4 and 5 show, each row of pixel circuits in multiple rows of pixel circuits is separated by the light-transmitting region C into a first pixel circuit row segment and a second pixel circuit row segment. As described above, each row of pixel circuits in m rows of pixel circuits is separated by the light-transmitting region C into a first pixel circuit row segment and a second pixel circuit row segment, where m is a natural number and m≥2, for example, m is 50, 60, 70, 80, 90, 100. The specific value of m is related to the size of the hole and the size of the pixel. Figure 4 , Figure 5 only shows 6 rows of pixel circuits in the middle of m rows of pixel circuits for illustrative purposes. As Figure 3 , Figures 6 and 7 show, each column of pixel circuits in multiple columns of pixel circuits is separated by the light-transmitting region C into a first pixel circuit column segment and a second pixel circuit column segment. As described above, each column of pixel circuits in n columns of pixel circuits is separated by the light-transmitting region C into a first pixel circuit column segment and a second pixel circuit column segment, where n is a natural number and n≥2, for example, n is 50, 60, 70, 80, 90, 100. The specific value of n is related to the size of the hole and the size of the pixel. Figure 6 , Figure 7 only shows 10 columns of pixel circuits in the middle of n columns of pixel circuits for illustrative purposes.

[0065] As Figure 3, as shown in FIGS. 4, 5, for each row of pixel circuits separated by the light-transmitting region C among the m rows of pixel circuits, each includes an initialization signal line Vinit, a reset signal line Reset, a gate line Gate, and an emission control line EM that are arranged and extended along the row direction. The initialization signal line Vinit is separated by the light-transmitting region C into a first initialization signal line portion VS1 and a second initialization signal line portion VS2. The reset signal line Reset is separated by the light-transmitting region C into a first reset signal line portion RS1 and a second reset signal line portion RS2. The gate line Gate is separated by the light-transmitting region C into a first gate line portion GS1 and a second gate line portion GS2. The emission control line EM is separated by the light-transmitting region C into a first emission control line portion ES1 and a second emission control line portion ES2. The first initialization signal line portion VS1, the first reset signal line portion RS1, the first gate line portion GS1, and the first emission control line portion ES1 are formed by Figure 4 shown and are located on the left side of the light-transmitting region C. The second initialization signal line portion VS2, the second reset signal line portion RS2, the second gate line portion GS2, and the second emission control line portion ES2 are formed by Figure 5 shown and are located on the right side of the light-transmitting region C.

[0066] As Figure 3 , as shown in FIGS. 6, 7, for each column of pixel circuits among the n columns of pixel circuits, each includes a data line Data and a power supply signal line VDD that are arranged and extended along the column direction. The data line Data is separated by the light-transmitting region C into a first data line portion DS1 and a second data line portion DS2. The power supply signal line VDD is separated by the light-transmitting region C into a first power supply signal line portion VDS1 and a second power supply signal line portion VDS2. The first data line portion DS1 and the first power supply signal line portion VDS1 are formed by Figure 6 shown and are located on the upper side of the light-transmitting region C. The second data line portion DS2 and the second power supply signal line portion VDS2 are formed by Figure 7 shown and are located on the lower side of the light-transmitting region C.

[0067] Combined with Figures 3 - 7 shown, in some embodiments, for each row of pixel circuits among the m rows of pixel circuits, the first gate line portion GS1 is connected to the second gate line portion GS2 through an auxiliary gate line AG. The auxiliary gate line AG and the gate line Gate are arranged in different layers. For example, the auxiliary gate line AG can be arranged in the same layer as the data line Data. Those skilled in the art can understand that generally, the gate line Gate and the data line Data in an OLED display panel are arranged in different layers. At least a part of the auxiliary gate line AG extends along the edge of the light-transmitting region C, bypasses the light-transmitting region C, and connects the first gate line portion GS1 and the second gate line portion GS2. The auxiliary gate line AG is a continuous line, Figure 4 only the first segment of the auxiliary gate line AG, such as the left segment, is shown, Figure 5Only the second segment of the auxiliary gate line AG is shown, for example, the right segment. Figure 6 Or Figure 7 Only the third segment of the auxiliary gate line AG is shown, for example, the middle segment. Those skilled in the art can understand that the first, second, and third segments of the auxiliary gate line AG are only part of the auxiliary gate line AG, and the three are connected through Figures 4 - 7 The winding part of the auxiliary gate line AG not shown in the figure.

[0068] Take Figure 4 , Figure 5 The pixel circuit behavior at the top in the figure as an example. As Figure 4 shown, the end of the first gate line part GS1 close to the light-transmitting area C is jump-connected to the first end of the auxiliary gate line AG at M. For example, the end of the first gate line part GS1 close to the light-transmitting area C located on different layers is electrically connected to the first end of the auxiliary gate line AG through a via. As Figure 5 shown, the end of the second gate line part GS2 close to the light-transmitting area C is jump-connected to the second end of the auxiliary gate line AG at M'. For example, the end of the second gate line part GS2 close to the light-transmitting area C located on different layers is electrically connected to the second end of the auxiliary gate line AG through a via. In other embodiments, the auxiliary gate line AG can also be in the same layer as the gate line Gate. At this time, the auxiliary gate line AG and the first gate line part GS1 and the second gate line part GS2 of the gate line Gate can be integrally formed without jump connection.

[0069] Take Figures 3 - 5 shown, the light-transmitting area C has a first axis AX1 parallel to the row direction X. The m rows of pixel circuits separated by the light-transmitting area C include a first group of row pixel circuits and a second group of row pixel circuits. The number of rows of the first group of row pixel circuits and the second group of row pixel circuits can be the same or different. The first group of row pixel circuits is located on one side of the first axis AX1, for example, Figures 3 - 5 shown, on the upper side of the first axis AX1, and the second group of row pixel circuits is located on the other side of the first axis AX1, for example, Figures 3 - 5 shown, on the lower side of the first axis AX1. The auxiliary gate lines AG used to connect the first gate line part GS1 and the second gate line part GS2 in the first group of row pixel circuits are all located on one side of the first axis AX1, for example, Figures 3 - 5 shown, on the upper side of the first axis AX1. The auxiliary gate lines AG used to connect the first gate line part GS1 and the second gate line part GS2 in the second group of row pixel circuits are all located on the other side of the first axis AX1, for example, Figures 3 - 5 shown, on the lower side of the first axis AX1. Figure 6 Shows the third segment of the auxiliary gate line AG, for example, the middle segment, used to connect the first gate line part GS1 and the second gate line part GS2 in the first group of row pixel circuits. Figure 7Shows the third segment of the auxiliary gate line AG for connecting the first gate line portion GS1 and the second gate line portion GS2 in the second set of row pixel circuits, for example, the middle segment.

[0070] As Figure 4 shown, the first segment of the m auxiliary gate lines AG corresponding to the m row pixel circuits, for example, the left segment, includes a horizontal segment extending along the row direction X and a winding segment whose extending direction forms a certain angle with the X direction. As Figure 5 shown, the second segment of the m auxiliary gate lines AG corresponding to the m row pixel circuits, for example, the right segment, includes a horizontal segment extending along the row direction X and a winding segment whose extending direction forms a certain angle with the X direction. It can be understood by those skilled in the art that although the winding segment shown in the figure is linear, only a part of the winding segment is shown in the figure. In actual processes, the winding can be formed by connecting multiple line segments and is arc-shaped as a whole. In some embodiments, the winding can also be a smooth arc-shaped winding.

[0071] Based on the above settings, for each row of pixel circuits in the m row pixel circuits separated by the light-transmitting region C, the first gate line portion GS1 is connected to the second gate line portion GS2 through the auxiliary gate line AG. Thus, the first gate line portion GS1 and the second gate line portion GS2 of the gate line Gate in the same row of pixel circuits can transmit the same gate signal simultaneously, thereby ensuring the normal display of the OLED display panel.

[0072] As Figure 3 and 4 shown, in some embodiments, for each row of pixel circuits in the m row pixel circuits, the auxiliary gate line AG includes an auxiliary gate line sub-portion AGS. The auxiliary gate line sub-portion AGS is located on the side of the light-transmitting region C close to the first gate line portion GS1, and the auxiliary gate line sub-portion AGS extends along the row direction X. The auxiliary gate line sub-portion AGS and the auxiliary data line AD have an overlapping region. The overlapping areas of the auxiliary gate line sub-portions AGS of the auxiliary gate lines AG corresponding to at least two rows of pixel circuits in the m row pixel circuits and the auxiliary data line AD are different. As Figure 4 shown, the auxiliary gate line sub-portion AGS of the auxiliary gate line AG far from the first axis AX1 is arranged to overlap with more auxiliary data lines AD compared with the auxiliary gate line sub-portion AGS of the auxiliary gate line AG close to the first axis AX1. That is, the overlapping area of the auxiliary gate line sub-portion AGS of the auxiliary gate line AG far from the first axis AX1 and the auxiliary data line AD can be larger compared with the auxiliary gate line sub-portion AGS of the auxiliary gate line AG close to the first axis AX1. Thus, the gate line Gate corresponding to the auxiliary gate line AG far from the first axis AX1 can obtain a larger capacitance compensation. It can be understood by those skilled in the art that as Figure 3 and 5As shown, in some embodiments, for each row of pixel circuits among the m rows of pixel circuits, the auxiliary gate line AG further includes another auxiliary gate line sub - part AGS', and the another auxiliary gate line sub - part AGS' is located on the side of the light - transmitting region C closer to the second gate line part GS2, and the another auxiliary gate line sub - part AGS' extends along the row direction X.

[0073] In some embodiments, for each row of pixel circuits among the m rows of pixel circuits, the first reset signal segment RS1 and the second reset signal segment RS2 can be connected through an auxiliary reset signal line in a manner similar to the connection of the first gate line part GS1 and the second gate line part GS2. However, this method will increase the wiring, resulting in a relatively large size of the winding region B.

[0074] In some embodiments, among the m rows of pixel circuits separated by the light - transmitting region C, the first row of pixel circuits to the mth row of pixel circuits are sequentially scanned. The first reset signal line part RS1 of the ith row of pixel circuits is electrically connected to the first gate line part GS1 of the (i - 1)th row of pixel circuits, and the second reset signal line part RS2 of the ith row of pixel circuits is electrically connected to the second gate line part GS2 of the (i - 1)th row of pixel circuits, where i is a natural number and 1 < i ≤ m. In the OLED display panel, among the sequentially scanned rows of pixel circuits, the signal transmitted by the reset signal line RS of each row of pixel circuits is the same as the signal transmitted by the gate line of the previous row of pixel circuits. Thus, for two adjacent rows of pixel circuits among the m rows of pixel circuits, the first reset signal line part RS1 and the second reset signal line part RS2 of the latter row of pixel circuits can be electrically connected through the corresponding auxiliary gate AG of the previous row of pixel circuits. Thus, there is no need to separately set the auxiliary reset signal line, which can reduce the size of the winding region B and increase the effective display area of the OLED display panel.

[0075] Specifically, as Figure 3 , Figures 4 and 5 show, the rows of pixel circuits are sequentially scanned from top to bottom. Taking Figure 4 , Figure 5Taking the top two rows of pixel circuits as an example, the end of the first reset signal line part RS1 of the relatively lower row of pixel circuits close to the light-transmitting region C is jump-connected to the auxiliary gate line AG corresponding to the relatively upper row of pixel circuits at N, for example, through a via. The end of the second reset signal line part RS2 of the relatively lower row of pixel circuits close to the light-transmitting region C is jump-connected to the auxiliary gate line AG corresponding to the relatively upper row of pixel circuits at N', for example, through a via. Thus, the end of the first reset signal line part RS1 of the relatively lower row of pixel circuits close to the light-transmitting region C is electrically connected to the first gate line part GS1 of the relatively upper row of pixel circuits through the first part of the auxiliary gate line AG corresponding to the relatively upper row of pixel circuits between M and N. The end of the second reset signal line part RS2 of the relatively lower row of pixel circuits close to the light-transmitting region C is electrically connected to the second gate line part GS2 of the relatively upper row of pixel circuits through the second part of the auxiliary gate line AG corresponding to the relatively upper row of pixel circuits between M' and N'. In some embodiments, the reset signal line Reset and the gate line Gate are arranged on the same layer, and the auxiliary gate line AG and the data line Data are arranged on the same layer.

[0076] In some embodiments, all the first initialization signal line parts VS1 and the first initialization signal line parts VS2 in the m rows of pixel circuits separated by the light-transmitting region C are connected to the same auxiliary initialization signal line AV. In the OLED display panel, the Vinit signals transmitted by the initialization signal lines Vinit of all pixel circuit rows are the same, being a constant value. Thus, all the first initialization signal line parts VS1 and the first initialization signal line parts VS2 in the m rows of pixel circuits can be connected to the same auxiliary initialization signal line AV, and the auxiliary initialization signal line AV is arranged around the light-transmitting region C. The auxiliary initialization signal line AV is, for example, arranged on the same layer as the initialization signal line Vinit.

[0077] Specifically, taking Figure 4 , the top row of pixel circuits in 5 as an example, the end of the first initialization signal line part VS1 close to the light-transmitting region C is electrically connected to the auxiliary initialization signal line AV at S, and the end of the second initialization signal line part VS1 close to the light-transmitting region C is electrically connected to the auxiliary initialization signal line AV at S'. Figures 4 - 7 Only a part of the auxiliary initialization signal line AV is shown in Figures 4 - 7 . In some embodiments, the auxiliary initialization signal line AV can form a closed loop around the light-transmitting region C. As

[0078] In the above embodiments, since only one auxiliary initialization signal line AV is provided, the size of the wiring area B can be reduced, and the effective display area of the OLED display panel can be increased. Since the auxiliary initialization signal line AV is, for example, arranged on the same layer as the initialization signal line Vinit, the auxiliary initialization signal line AV and the initialization signal line Vinit including the first initialization signal line part VS1 and the second initialization signal line part VS2 can be formed of the same material using the same patterning process. The auxiliary initialization signal line AV is integrally formed with the first initialization signal line part VS1 and the second initialization signal line part VS2, and no specific connection process is required for connection.

[0079] In some embodiments, for each pixel circuit row in the m pixel circuits separated by the light-transmitting region C, the first light-emitting control line part ES1 and the second light-emitting control line part ES2 can be connected through an auxiliary light-emitting control line in a manner similar to the connection between the first gate line part GS1 and the second gate line part GS2. This method will increase the wiring, and the size of the wiring area B is relatively large.

[0080] In some embodiments, the ends of all the first light-emitting control line parts ES1 and the second light-emitting control line parts ES2 in the m pixel circuits separated by the light-transmitting region C that are close to the light-transmitting region C are suspended. In these embodiments, for each row of pixel circuits in the OLED display panel, the light-emitting control signal can be input simultaneously from both ends located at the two side edges of the OLED display panel to the light-emitting control line EM. In practical applications, in the m pixel circuits separated by the light-transmitting region C, the requirements for the synchronization and the same amplitude of the light-emitting control signals transmitted on the first light-emitting control line part ES1 and the corresponding second light-emitting control line part ES2 are not high. By suspending the ends of the first light-emitting control line part ES1 and the second light-emitting control line part ES2 that are close to the light-transmitting region C, and inputting the light-emitting control signals simultaneously from the ends located on both sides of the OLED display panel and away from the light-transmitting region C to the first light-emitting control line part ES1 and the second light-emitting control line part ES2 respectively, the requirements for normal display of the OLED can be met. Therefore, there is no need to separately provide an auxiliary light-emitting control line, the size of the wiring area B can be reduced, and the effective display area of the OLED display panel can be increased.

[0081] Combined with Figures 3 - 7As shown, in some embodiments, for each column of pixel circuits in the n columns of pixel circuits separated by the light-transmitting region C, the first data line portion DS1 is connected to the second data line portion DS2 through the auxiliary data line AD. The auxiliary data line AD and the data line Data are disposed in different layers. For example, the auxiliary data line AD can be disposed in the same layer as the gate line Gate or the initialization signal line Vinit. Those skilled in the art can understand that generally, the gate line Gate, the initialization signal line Vinit, and the data line Data in the OLED display panel are disposed in different layers. At least a part of the auxiliary data line AD extends along the edge of the light-transmitting region C, bypasses the light-transmitting region C, and connects the first data line portion DS1 and the second data line portion DS2. The auxiliary data line AD is a continuous line, Figure 6 only the first segment of the auxiliary data line AD is shown, for example, the upper segment, Figure 7 only the second segment of the auxiliary data line AD is shown, for example, the lower segment, Figure 4 or Figure 5 only the third segment of the auxiliary data line AD is shown, for example, the middle segment. Those skilled in the art can understand that the first segment, the second segment, and the third segment of the auxiliary data line AD are only parts of the auxiliary data line AD, and the three are connected through Figures 4 - 7 the winding portion of the auxiliary data line AD not shown in the figure. The auxiliary data line AD includes a first auxiliary data line AD1 and a second auxiliary data line AD2. For each column in the odd-numbered columns of pixel circuits in the n columns of pixel circuits separated by the light-transmitting region C, the first data line portion DS1 is connected to the second data line portion DS2 through the first auxiliary data line AD1. For each column in the even-numbered columns of pixel circuits in the n columns of pixel circuits separated by the light-transmitting region C, the first data line portion DS1 is connected to the second data line portion DS2 through the second auxiliary data line AD2. The first auxiliary data line AD1 can be disposed in the same layer as one of the gate line Gate and the initialization signal line Vinit, and the second auxiliary data line AD2 can be disposed in the same layer as the other of the gate line Gate and the initialization signal line Vinit. For example, as Figure 6 , as shown in FIG. 7, the first auxiliary data line AD1 is disposed in the same layer as the gate line Gate, and the second auxiliary data line AD2 is disposed in the same layer as the initialization signal line Vinit. At least a part of each of the first auxiliary data line AD1 and the second auxiliary data line AD2 extends along the edge of the light-transmitting region C, bypasses the light-transmitting region C, and connects the corresponding first data line portion DS1 and the second data line portion DS2.

[0082] Taking Figure 6 , Figure 7 the two leftmost pixel circuit columns in the figure as an example, as Figure 6As shown, the first end portion of the first data line part DS1 of the pixel circuit column on the relatively left side is skip-layer connected to the first end portion of the second auxiliary data line AD2 at Q, for example, by via electrical connection; the first end portion of the first data line part DS1 of the pixel circuit column on the relatively right side is skip-layer connected to the first end portion of the first auxiliary data line AD1 at T, for example, by via electrical connection. As Figure 7 shown, the second end portion of the second data line part DS2 of the pixel circuit column on the relatively left side is skip-layer connected to the second end portion of the second auxiliary data line AD2 at Q', for example, by via electrical connection; the second end portion of the second data line part DS2 of the pixel circuit column on the relatively right side is skip-layer connected to the second end portion of the first auxiliary data line AD1 at T', for example, by via electrical connection. The first auxiliary data line AD1 is arranged on the same layer as the gate line Gate, and the second auxiliary data line AD2 is arranged on the same layer as the initialization signal line Vinit.

[0083] In other embodiments, the auxiliary data line AD can also be located in the same layer as the data line Data. At this time, the first data line part DS1 and the second data line part DS2 of the auxiliary data line AD and the data line Data can be integrally formed, and skip-layer connection is not required.

[0084] As Figure 3 , Figures 6 and 7 show that the light-transmitting region C has a second axis AX2 parallel to the column direction Y. The n columns of pixel circuits separated by the light-transmitting region C include a first group of column pixel circuits and a second group of column pixel circuits. The number of columns of the first group of column pixel circuits and the second group of column pixel circuits can be the same or different. The first group of column pixel circuits is located on one side of the second axis AX2, for example, Figure 3 , on the left side of the second axis AX2 shown in Figures 6 and 7. The second group of column pixel circuits is located on the other side of the second axis AX2, for example, Figure 3 , on the right side of the second axis AX2 shown in Figures 6 and 7. The auxiliary data lines AD for connecting the first data line part DS1 and the second data line part DS2 in the first group of column pixel circuits are all located on one side of the second axis AX2, for example, Figure 3 , on the left side of the second axis AX2 shown in Figures 6 and 7. The auxiliary data lines AD for connecting the first data line part DS1 and the second data line part DS2 in the second group of column pixel circuits are all located on the other side of the second axis AX2, for example, Figure 3 , on the right side of the second axis AX2 shown in Figures 6 and 7. Figure 4 Figure 20 shows the third segment, for example, the middle segment, of the auxiliary data line AD for connecting the first data line part DS1 and the second data line part DS2 in the first group of column pixel circuits. Figure 7Shows the third segment of the auxiliary data line AD for connecting the first data line portion DS1 and the second data line portion DS2 in the second group of column pixel circuits, such as the middle segment.

[0085] As Figure 6 shown, the first segment of the n auxiliary data lines AD corresponding to the n row pixel circuits, for example, the upper side segment, includes a vertical segment extending in the row direction Y and a winding segment whose extending direction forms a certain angle with the Y direction. As Figure 7 shown, the second segment of the n auxiliary data lines AG corresponding to the n column pixel circuits, for example, the lower side segment, includes a vertical segment extending in the row direction Y and a winding segment whose extending direction forms a certain angle with the Y direction. Those skilled in the art can understand that although the winding segment shown in the figure is linear, only a part of the winding segment is shown in the figure. In actual process, the winding can be formed by connecting multiple segments and is arc-shaped as a whole.

[0086] As Figures 3 - 7 shown, the positive projection of the auxiliary initialization signal line AV on the substrate surrounds the positive projection of the auxiliary data line AD including the first auxiliary data line AD1 and the second auxiliary data line AD2 on the substrate.

[0087] Based on the above settings, for each pixel circuit column in the n column pixel circuits separated by the light-transmitting region C, the first data line portion DS1 is connected to the second data line portion DS2 through the auxiliary gate line AD. The first data line portion DS1 and the second data line portion DS2 of the data line data in the same pixel circuit column can transmit the same data line signal simultaneously, thus ensuring the normal display of the OLED display panel. And, by electrically connecting the first data line portion DS1 and the second data line portion DS2 of the odd-column pixel circuits through the first auxiliary data line AD1, and electrically connecting the first data line portion DS1 and the second data line portion DS2 of the even-column pixel circuits through the second auxiliary data line AD2, and the first auxiliary data line AD1 and the second auxiliary data line AD2 are located in different layers, the auxiliary data lines can be set more densely, further reducing the size of the winding region B and increasing the effective display area of the OLED display panel.

[0088] The above Figures 4 - 7 only shows the schematic diagrams of the Figure 3 regions D, E, F, and G in Figures 4 - 7 respectively, and each in Figure 8 only shows a part of the auxiliary wiring, that is, a part of the auxiliary gate line AG, a part of the auxiliary data line AD, and a part of the auxiliary initialization signal line AV. Figure 8As shown, some auxiliary gate lines AG bypass the light-transmitting region C from the upper side of the light-transmitting region C, and some other auxiliary gate lines AG bypass the light-transmitting region C from the lower side of the light-transmitting region C. Some of the first auxiliary data lines AD1 and some of the second auxiliary data lines AD2 bypass the light-transmitting region C from the left side of the light-transmitting region C, and some other first auxiliary data lines AD1 and some other second auxiliary data lines AD2 bypass the light-transmitting region C from the right side of the light-transmitting region C. The auxiliary initialization signal line AV is in a ring shape around the light-transmitting region C, and the winding parts of each auxiliary wiring around the light-transmitting region C are basically arc-shaped. Those skilled in the art can understand that Figure 8 only schematically shows the overall morphology of each auxiliary wiring, that is, the auxiliary gate line AG, the first auxiliary data line AD1, the second auxiliary data line AD2, and the auxiliary initialization signal line AV, and does not represent the real relative position relationship between them. In some embodiments, in Figure 3 the D region shown ([ Figure 4 is an enlarged view of the D region), the first auxiliary data lines AD1 corresponding to the odd-numbered pixel circuits and the second auxiliary data lines AD2 corresponding to the even-numbered pixel circuits are alternately arranged along the row direction X. The orthographic projections of adjacent first auxiliary data lines AD1 and second auxiliary data lines AD2 on the substrate have a small interval, for example, the orthographic projections of adjacent first auxiliary data lines AD1 and second auxiliary data lines AD2 on the substrate are basically adjacent. Thus, including the first auxiliary data lines AD1 and the second auxiliary data lines AD2 can be closely arranged, so that the winding region B occupies a small space.

[0089] Although in the foregoing embodiments, the first auxiliary data lines AD1 corresponding to the odd-numbered pixel circuits and the second auxiliary data lines AD2 corresponding to the even-numbered pixel circuits are arranged in different layers, those skilled in the art can understand that in other embodiments, the first auxiliary data lines AD1 and the second auxiliary data lines AD2 may not be distinguished, and all the auxiliary data lines AD are arranged in the same layer, for example, in the same layer as one of the gate lines Gate and the initialization signal.

[0090] In some embodiments, for each pixel circuit column in the n column pixel circuits separated by the light-transmitting region C, the first power supply signal line part VDS1 and the second power supply signal line part VDS2 can be connected by an auxiliary power supply signal line in a manner similar to the connection between the first data line part DS1 and the second data line part DS2, but this method will increase the wiring, resulting in a relatively large size of the winding region B.

[0091] In some embodiments, all the end portions of the first power signal line portions VDS1 and the second power signal line portions VDS2 that are close to the light-transmissive region C in the n columns of pixel circuits separated by the light-transmissive region C are suspended. In these embodiments, due to the design of the pixel circuits in the OLED display panel, the power signal lines VDD of all the pixel circuits are electrically connected through other conductive layers. Therefore, there is no need to provide auxiliary power signal lines to electrically connect the first power signal line portions VDS1 and the second power signal line portions VDS2. The size of the winding region B can be reduced, and the effective display area of the OLED display panel can be increased.

[0092] Figure 9 For Figure 3 a partial cross-sectional schematic view of the display region A in. As Figure 9 shown, in some embodiments, the OLED display panel includes a substrate 10 and a buffer layer 20, an active layer 30, a first gate insulating layer 40, a first gate layer 50, a second gate insulating layer 60, a second gate layer 70, an interlayer dielectric layer 80, a source-drain layer 90, a passivation layer 110, a planarization layer 120, an anode layer 130, a pixel defining layer 140, a light-emitting functional layer 150, a cathode layer 160, and a packaging layer 170 that are sequentially located on the substrate 10.

[0093] Specifically, the substrate 10 is, for example, a flexible PI (polyimide) substrate made of a transparent material;

[0094] The buffer layer 20 is made of a transparent insulating material, such as silicon oxide, silicon nitride, etc., and substantially covers the entire surface of the substrate 10; the entire surface coverage described herein can be understood as a coverage area greater than 50%.

[0095] The active layer 30 includes the active regions in the thin-film transistors in the pixel circuits, can be made of a semiconductor material, and has poor light transmittance;

[0096] The first gate insulating layer 40 is made of a transparent insulating material, such as silicon oxide, silicon nitride, etc., and substantially covers the entire surface of the substrate 10;

[0097] The first gate layer 50 is made of a metal material and includes the reset signal line Reset, the gate line Gate, and the emission control line EM in the pixel circuits, as well as the gates in the thin-film transistors. That is to say, the reset signal line Reset, the gate line Gate, and the emission control line EM in the pixel circuits and the gates in the thin-film transistors are arranged in the same layer and are located in the first gate layer 50, and can be formed by the same lithography process;

[0098] The second gate insulating layer 60 is made of a transparent insulating material, such as silicon oxide, silicon nitride, etc., and substantially covers the entire surface of the substrate 10;

[0099] The second gate layer 70 includes the initialization signal line Vinit in the pixel circuit. That is to say, the reset signal line Reset, the gate line Gate, and the emission control line EM in the pixel circuit, as well as the gate of the thin-film transistor, are formed on the same layer and are located in the second gate layer 70, and can be formed by the same lithography process.

[0100] The interlayer dielectric layer 80 is made of a transparent insulating material, such as silicon oxide, silicon nitride, etc., and substantially covers the entire substrate 10.

[0101] The source-drain layer 90 is made of a metal material and includes the data line Data, the power supply signal line VDD in the pixel circuit, and the source and drain of the thin-film transistor. That is to say, the data line Data, the power supply signal line VDD in the pixel circuit, and the source and drain of the thin-film transistor are formed on the same layer and are located in the source-drain layer 90, and can be formed by the same lithography process.

[0102] The passivation layer 110 is made of a transparent insulating material, such as silicon oxide, silicon nitride, etc., and substantially covers the entire substrate 10.

[0103] The planarization layer 120 is made of a transparent organic material, such as silicon oxide, silicon nitride, etc., and substantially covers the entire substrate 10.

[0104] The anode layer 130 is made of a metal material and includes the anode of the OLED source. The anode of the OLED source can be formed by a lithography process.

[0105] The pixel defining layer 140 is supported by a transparent organic material and is used to define the light-emitting area of the OLED display panel. It can be formed by a lithography process.

[0106] The light-emitting functional layer 150 includes a first particle transport layer 151, a light-emitting layer 152, and a second particle transport layer 153 that are sequentially arranged away from the substrate 10. The first particle transport layer 151 includes, for example, a hole injection layer, a hole transport layer, an electron blocking layer, etc. The second particle transport layer 153 includes, for example, an electron injection layer, an electron transport layer, a hole blocking layer, etc. The first particle transport layer 151 and the second particle transport layer 153 both cover the entire substrate 10 and are made of a transparent material. The light-emitting layer 152 is only provided in the light-emitting area defined by the pixel defining layer 140 and can be formed by evaporation using an FMM mask.

[0107] The cathode layer 160 is made of a transparent conductive material, such as ITO, ZnO, etc., and substantially covers the entire substrate 10.

[0108] The encapsulation layer 170 includes a first inorganic encapsulation layer 171, an organic encapsulation layer 172, and a second inorganic encapsulation layer 173 that are sequentially disposed away from the substrate 10. The first inorganic encapsulation layer 171, the organic encapsulation layer 172, and the second inorganic encapsulation layer 173 are stacked and substantially cover the entire substrate 10. The encapsulation layer 170 is light-transmissive.

[0109] Those skilled in the art should understand that Figure 9 only shows a cross-sectional structure of the display area A of the OLED display panel schematically, mainly reflecting the layer structure of the OLED display panel, and reflecting that the signal of the pixel circuit is transmitted to the OLED element through the thin-film transistor to cause the OLED element to emit light.

[0110] Figure 10 For Figure 3 a partial cross-sectional schematic view of the light-transmissive area C in. In some embodiments, in the light-transmissive area C, the OLED display panel includes a substrate 10 and a buffer layer 20, a first gate insulating layer 40, a second gate insulating layer 60, an interlayer dielectric layer 80, a passivation layer 110, a first particle transport layer 151, a second particle transport layer 153, a cathode layer 160, and an encapsulation layer 170 that are sequentially located on the substrate 10.

[0111] Compared with Figure 9 the partial cross-sectional schematic view of the display area A of the OLED display panel shown, it can be seen that in the light-transmissive area C, there is no active layer 30 made of semiconductor material; there is no first gate layer 50, second gate layer 70, source-drain layer 90, and anode layer 130 made of metal material; there is no planarization layer 120 and pixel definition layer made of thick organic material, nor is there a light-emitting layer 152. At this time, the total thickness of the film layers in the light-transmissive area C is significantly smaller than the total thickness of the film layers in the display area A, and it can be considered that a blind hole is formed in the light-transmissive area C. This can enable the light-transmissive area C to transmit as much external light as possible, so that the image acquisition device located on one side of the OLED display panel has a better imaging effect.

[0112] In summary, in the light-transmissive area C, the OLED display panel removes the metal material film layer, the patterned film layer, and the thick organic film layer that hinder light transmission, so that the light-transmissive area C has good light transmittance.

[0113] In some embodiments, the OLED display panel can also remove at least one of the buffer layer 20, the first gate insulating layer 40, the second gate insulating layer 60, the interlayer dielectric layer 80, the passivation layer 110, the first particle transport layer 151, the second particle transport layer 153, the cathode layer 160, and the encapsulation layer 170 located on the substrate 10 in the light-transmissive area C to further improve the light transmittance of the light-transmissive area C.

[0114] Figure 11 is Figure 3 A partial cross-sectional view of the winding area B in the figure. In some embodiments, in the winding area B, the OLED display panel includes a substrate 10 and, in sequence, a buffer layer 20, a first gate insulating layer 40, a first gate layer 50, a second gate insulating layer 60, a second gate layer 70, an interlayer dielectric layer 80, a source-drain layer 90, a passivation layer 110, a first particle transport layer 151, a second particle transport layer 153, a cathode layer 160, and a packaging layer 170 disposed on the substrate 10.

[0115] Compared with Figure 11 A partial cross-sectional view of the light-transmitting area C of the OLED display panel shown, it can be seen that in the winding area B, the first gate layer 50, the second gate layer 70, and the source-drain layer 90 are added. The first gate layer 50 is used to form the first auxiliary data line AD1, the second gate layer 70 is used to form the second auxiliary data line AD2 and the auxiliary initialization signal line AV, and the source-drain layer 90 is used to form the auxiliary gate line AG.

[0116] Those skilled in the art should understand that Figure 11 only schematically shows the cross-sectional structure of the winding area B of the OLED display panel, mainly reflecting the layer structure of the OLED display panel in the winding area B.

[0117] Figure 12 is Figure 4 The cross-sectional view at M in the figure. As Figure 12 shown, at M, the first end of the first gate line part GS1 in the first gate layer 50 near the end of the light-transmitting area C is electrically connected to the first end of the auxiliary gate line AG in the source-drain layer 90 through a first via 180. Among them, the first via 180 penetrates the second gate insulating layer 60 and the interlayer dielectric layer 80 between the first gate layer 50 and the source-drain layer 90.

[0118] In Figures 4 - 7 the skip-layer connection structures at M', N, N', Q, T, Q', T' in the figure are similar to the skip-layer connection structure at M in Figure 4 the figure, and will not be elaborated here.

[0119] In the foregoing embodiments, the wiring structure around the light-transmitting area C is explained in detail for an OLED display panel without forming a physical through hole. Those skilled in the art can understand that this wiring structure around the light-transmitting area C can also be applied to an OLED display panel provided with a physical through hole.

[0120] In the foregoing embodiments, the OLED display panel has a source-drain layer. In other embodiments, the OLED display panel may also have two source-drain layers, namely, a first source-drain layer and a second source-drain layer located in different layers. The first source-drain layer is used to form the data lines in the pixel circuit and the source and drain of the thin-film transistor, and the second source-drain layer is used to form the power signal lines. At this time, the auxiliary gate can also be disposed in the second source-drain layer. For example, part of the auxiliary gate lines are disposed in the first source-drain layer, and the other part of the auxiliary gate lines are disposed in the second source-drain layer.

[0121] Those skilled in the art should understand that the foregoing embodiments are explained by taking the OLED display panel as an example. In other embodiments, other types of display panels may also be used, such as PLED display panels and the like.

[0122] Some embodiments of the present disclosure also provide a display device. Figure 13 As a schematic plan view of an OLED display device according to some embodiments of the present disclosure, as Figure 13 shown, the display device 1000 includes the display panel 100 in any of the foregoing embodiments and an image acquisition device 200 located on the side of the back display surface 101 of the display panel, such as a camera. The display device may be: a television, a monitor, a digital photo frame, a mobile phone, a smart watch, a tablet computer, or any other product or component having a display function and a camera function.

[0123] In some embodiments, the orthographic projection of the image acquisition device 200 on the display panel 100 at least partially overlaps with the light-transmitting region C. Thus, the image acquisition device 200 acquires external light passing through the light-transmitting region C of the display panel 100, and further realizes imaging.

[0124] In some embodiments, the optical axis of the image acquisition device 200 coincides with a third axis perpendicular to the display panel 100 in the light-transmitting region C of the display panel 100.

[0125] The above description is only a preferred embodiment of the present disclosure and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present disclosure.

Claims

1. A display panel, comprising: a substrate substrate; and a pixel circuit arranged in an array on the substrate substrate, wherein each row of pixel circuits includes a gate line extending in the row direction, and each column of pixel circuits includes a data line extending in the column direction, and the gate line and the data line are disposed on different layers; the display panel has a light-transmitting region and a display region surrounding the light-transmitting region, the pixel circuit is disposed in the display region, the gate lines of each row in the m rows of pixel circuits are separated by the light-transmitting region into a first gate line portion and a second gate line portion, the first gate line portion is connected to the second gate line portion through an auxiliary gate line, and at least a part of the auxiliary gate line extends along the edge of the light-transmitting region, where m is a natural number and m≥2; the data lines in each column of the n columns of pixel circuits are separated by the light-transmitting region into a first data line portion and a second data line portion, the first data line portion is connected to the second data line portion through an auxiliary data line, where n is a natural number and n≥2; the auxiliary gate line includes an auxiliary gate line sub-portion, and there is an overlapping region between the auxiliary gate line sub-portion and the auxiliary data line; the m rows of pixel circuits include at least two rows of pixel circuits, and the overlapping area between the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in one row of pixel circuits among the at least two rows of pixel circuits and the auxiliary data line is different from the overlapping area between the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in another row of pixel circuits among the at least two rows of pixel circuits and the auxiliary data line; wherein, each row of pixel circuits further includes a reset signal line extending in the row direction, the reset signal line is disposed on the same layer as and parallel to the gate line, and the reset signal lines in each row of the m rows of pixel circuits are separated by the light-transmitting region into a first reset signal line portion and a second reset signal line portion; in the m rows of pixel circuits, the first reset signal line portion of the i-th row of pixel circuits is electrically connected to the first gate line portion of the (i - 1)-th row of pixel circuits, and the second reset signal line portion of the i-th row of pixel circuits is electrically connected to the second gate line portion of the (i - 1)-th row of pixel circuits, where i is a natural number and 1<i≤m.

2. The display panel according to claim 1, wherein the auxiliary gate line sub-portion is located on a side of the light-transmitting region close to the first gate line portion, and the auxiliary gate line sub-portion extends in the row direction.

3. The display panel according to claim 2, wherein the number of the auxiliary data lines overlapping with the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in one row of pixel circuits among the at least two rows of pixel circuits is different from the number of the auxiliary data lines overlapping with the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in another row of pixel circuits among the at least two rows of pixel circuits.

4. The display panel according to claim 1, wherein, The light-transmitting region has a first axis parallel to the row direction. A first group of row pixel circuits among the m row pixel circuits is located on one side of the first axis, and a second group of row pixel circuits is located on the other side of the first axis. Auxiliary gate lines for connecting a first gate line portion and a second gate line portion in the first group of row pixel circuits are all located on the one side of the first axis, and auxiliary gate lines for connecting a first gate line portion and a second gate line portion in the second group of row pixel circuits are located on the other side of the first axis.

5. The display panel according to claim 1, wherein, The auxiliary gate lines are provided on the same layer as the data lines. At least a part of the auxiliary data lines extends along the edge of the light-transmitting region. Auxiliary data lines for connecting a first data line portion and a second data line portion of each column in at least a part of the column pixel circuits of the n column pixel circuits are provided on the same layer as the gate lines.

6. The display panel according to claim 1, wherein, A first reset signal line portion of the i-th row pixel circuit near the end of the light-transmitting region is electrically connected to a first gate line portion of the (i - 1)-th row pixel circuit near the end of the light-transmitting region through a first part of the auxiliary gate line for connecting a first gate line portion and a second gate line portion in the (i - 1)-th row pixel circuit. A second reset signal line portion of the i-th row pixel circuit near the end of the light-transmitting region is electrically connected to a second gate line portion of the (i - 1)-th row pixel circuit near the end of the light-transmitting region through a second part of the auxiliary gate line for connecting a first gate line portion and a second gate line portion in the (i - 1)-th row pixel circuit.

7. The display panel according to claim 1, wherein, Each row of pixel circuits further includes an initialization signal line extending in the row direction. The initialization signal line is not on the same layer as the gate lines and the data lines. The initialization signal line of each row among the m row pixel circuits is separated by the light-transmitting region into a first initialization signal line portion and a second initialization signal line portion. The first initialization signal line portions and the second initialization signal line portions of at least two rows of pixel circuits among the m row pixel circuits are connected to an auxiliary initialization signal line. The auxiliary initialization signal line is provided on the same layer as the initialization signal line and is disposed around the light-transmitting region.

8. The display panel according to claim 7, wherein At least a part of the auxiliary data lines extends along the edge of the light-transmitting region. Auxiliary data lines for connecting a first data line portion and a second data line portion of each column in at least a part of the column pixel circuits of the n column pixel circuits are provided on the same layer as the initialization signal lines.

9. The display panel according to claim 7, wherein, The first data line portion of each column in the odd-numbered column pixel circuits among the n column pixel circuits is connected to the second data line portion in the same column pixel circuit through a first auxiliary data line. The first data line portion of each column in the even-numbered column pixel circuits of the n column pixel circuits is connected to the second data line portion in the same column pixel circuit through a second auxiliary data line. The first auxiliary data line is provided on the same layer as one of the gate lines and the initialization signal lines, and the second auxiliary data line is provided on the same layer as the other of the gate lines and the initialization signal lines. At least a part of the first auxiliary data line extends along the edge of the light-transmitting region, and at least a part of the second auxiliary data line extends along the edge of the light-transmitting region.

10. The display panel according to claim 9, wherein the light-transmissive region has a second axis parallel to the column direction, a first group of column pixel circuits among the n column pixel circuits is located on one side of the second axis, and a second group of column pixel circuits is located on the other side of the second axis. The first auxiliary data line or the second auxiliary data line for connecting the first data line portion and the second data line portion in the first group of column pixel circuits is located on the same side of the second axis, and the first auxiliary data line or the second auxiliary data line for connecting the first data line portion and the second data line portion in the second group of column pixel circuits is located on the other side of the second axis.

11. The display panel according to claim 9, wherein, The positive projection of the auxiliary initialization signal line on the substrate surrounds the positive projections of the first auxiliary data line and the second auxiliary data line on the substrate.

12. The display panel according to claim 8, wherein, Wherein the auxiliary initialization signal line is a closed loop.

13. The display panel according to claim 1, wherein, Each row of pixel circuits further includes a light emission control line extending along the row direction. The light emission control line is in the same layer as and parallel to the gate line. The light emission control line in each row of the m rows of pixel circuits is separated by the light-transmissive region into a first light emission control line portion and a second light emission control line portion. The ends of the first light emission control line portion and the second light emission control line portion close to the light-transmissive region are suspended.

14. The display panel according to claim 1, wherein, Each column of pixel circuits further includes a power supply signal line extending along the column direction. The power supply signal line is in the same layer as and parallel to the data line. The power supply signal line in each column of the n column pixel circuits is separated by the light-transmissive region into a first power supply signal line portion and a second power supply signal line portion. The ends of the first power supply signal line portion and the second power supply signal line portion close to the light-transmissive region are suspended.

15. The display panel according to any one of claims 1-14, wherein the display panel has a wire winding region located between the light-transmissive region and the display region. The wire winding region surrounds the light-transmissive region and is surrounded by the display region. The auxiliary gate line is located in the wire winding region.

16. The display panel according to claim 15, wherein, The display panel in the wire winding region includes a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a source-drain layer arranged away from the substrate in sequence. The gate line is located in the first gate layer, and the data line and the auxiliary gate line are located in the source-drain layer. The end of the first gate line portion close to the light-transmissive region is electrically connected to the first end of the auxiliary gate line through a first via hole, and the end of the second gate line portion close to the light-transmissive region is electrically connected to the second end of the auxiliary gate line through a second via hole. The first via hole and the second via hole penetrate the second gate insulating layer and the interlayer dielectric layer located between the first gate layer and the source-drain layer.

17. The display panel according to claim 15 further includes a cathode layer provided on the substrate, and a packaging layer provided on a side of the cathode layer away from the substrate. The packaging layer includes a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer arranged away from the substrate in sequence.

18. The display panel according to claim 1, wherein, The light-transmissive region includes a light-transmissive blind hole or a light-transmissive through hole.

19. A display device, comprising: The display panel according to any one of claims 1-18, An image acquisition device, located on the side of the display panel opposite to the display surface.

Images