Integrated dipole current transistor

Abstract

Methods of forming and processing semiconductor devices are described. Certain embodiments relate to electronic devices including a dipole region having an interlayer dielectric, a high-K dielectric material, and a dipole layer. The dipole layer includes one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN), titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbide nitride (HfCN).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular to transistors. More particularly, embodiments of the present disclosure relate to FinFET devices and methods of manufacturing FinFET devices. Background Art

[0002] Integrated circuits have evolved into complex devices that may include millions of transistors, capacitors, and resistors on a single chip. During the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has gradually increased while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Integrated circuits incorporate planar field effect transistors (FETs) in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] As device sizes have shrunk, device geometries and materials have suffered from difficulties in maintaining switching speeds without causing failures. Several new technologies have emerged that allow chip designers to continue to reduce gate lengths. For current and future technology generations, dimensional control of device structures is a key challenge. Since 1970, the number of components per chip has doubled every two years. As a result of this trend, circuit miniaturization by shrinking transistors has been the main driving force of the semiconductor technology roadmap. Due to changes in basic properties (such as threshold voltage), the reduction of materials now used as N-MOS and P-MOS has been a challenge. In addition, the migration of transistor technology from planar to FinFET requires conformal work function layers with solutions for multiple threshold voltages. As device sizes are further reduced, the voltage adjustment range is limited by thickness changes. Therefore, there is a need to develop alternative materials to achieve better performance while reducing size. Summary of the invention

[0005] One or more embodiments relate to electronic devices and methods of manufacturing electronic devices. In one or more embodiments, the electronic device includes: a source region, a drain region, and a channel separating the source region and the drain region; and a dipole region on a top surface of the channel, the dipole region including an interlayer dielectric, a high-K dielectric material, and a dipole layer.

[0006] In one or more embodiments, a method of manufacturing an electronic device includes: depositing an interlayer dielectric on a top surface of a channel between a source and a drain on a substrate; depositing a high-K dielectric material on the interlayer dielectric; and depositing a dipole layer on the high-K dielectric material.

[0007] In one or more embodiments, an electronic device includes: a source region having a source and a source contact, the source region being on a top surface of a substrate; a drain region having a drain and a drain contact, the drain region being on a top surface of the substrate; a channel located between the source and the drain; and a dipole region located on the top surface of the channel, the dipole region including an interlayer dielectric, a high-K dielectric material, and a dipole layer, the dipole layer including one or more of: titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN), titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbide nitride (HfCN). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] By referring to the embodiments, some of which are illustrated in the accompanying drawings, a more specific description of the disclosure briefly summarized above can be obtained so that the above-mentioned features of the disclosure can be understood in detail. However, it will be noted that the drawings only illustrate typical embodiments of the disclosure and are therefore not to be considered as limiting the scope of the disclosure, as the disclosure may admit of other equivalent embodiments. The embodiments described herein are illustrated as examples and are not limited to the illustrations of the accompanying drawings, in which similar reference numerals indicate similar elements.

[0009] Figure 1 a process flow diagram depicting one embodiment of a method according to embodiments described herein;

[0010] Figure 2 depicts a cross-sectional view of a substrate according to one or more embodiments;

[0011] Figure 3A depicts a cross-sectional view of a substrate according to one or more embodiments;

[0012] Figure 3B depicts a cross-sectional view of a substrate according to one or more embodiments; and

[0013] Figure 4 A cluster tool according to one or more embodiments of the present disclosure is depicted. DETAILED DESCRIPTION

[0014] Before describing several example embodiments of the present disclosure, it will be understood that the present disclosure is not limited to the details of the architecture or processing steps set forth in the following description. The present disclosure is capable of other embodiments and can be implemented or carried out in various ways.

[0015] The term "about" as used herein means approximately or nearly, and in the context of a stated value or range means a variation of ±15% of that value, or less. For example, a difference in values ​​of ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of about.

[0016] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to a surface or a portion of a surface upon which processing may be performed. Unless the context clearly indicates otherwise, one skilled in the art will also understand that reference to a substrate may refer to only a portion of such substrate. Additionally, reference to depositing on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0017] As used herein, "substrate" refers to any substrate or a material surface formed on a substrate, on which film processing is performed during the manufacturing process. For example, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material, such as metal, metal nitride, metal alloy, and other conductive materials, depending on the application. The substrate includes, without limitation, a semiconductor wafer. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to the film processing directly on the surface of the substrate itself, in the present disclosure, any film processing step disclosed may also be performed on an underlying layer formed on the substrate, as disclosed in more detail later, and the term "substrate surface" is intended to include this underlying layer as indicated by the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gaseous species that can react with a substrate surface.

[0019] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to adsorb and / or react on the substrate surface and then be cleared from the processing chamber. The reactive compounds are shown as being exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface or material on the substrate surface are simultaneously exposed to two or more reactive compounds, such that any given point on the substrate is not substantially exposed to more than one reactive compound simultaneously. As used in this specification and the appended claims, as would be understood by one skilled in the art, the term "substantially" as used in this context means that there is a possibility that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and this simultaneous exposure is unintentional.

[0020] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into a reaction zone followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone followed by a second time delay. During each time delay, a purge gas such as argon is introduced into the process chamber to purge the reaction zone or remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are alternatively pulsed until a desired film or film thickness is formed on the substrate surface. In either embodiment, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. A cycle may start with either compound A or compound B and continue in the corresponding order of the cycle until a film having a predetermined thickness is obtained.

[0021] In an embodiment of a spatial ALD process, a first reactant gas and a second reactant gas (e.g., nitrogen) are delivered to the reaction zone simultaneously, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery apparatus so that any given point on the substrate is exposed to the first reactant gas and the second reactant gas.

[0022] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Typically, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric between a gate electrode inserted into the substrate and the channel region.

[0023] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field effect transistor is a voltage controlled device in which its current carrying capacity is varied by the application of an electric field. Field effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain terminal and the source terminal is controlled by an electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which regulates the channel conductivity. Traditionally, the current entering the channel at the source (S) is labeled I S The current entering the channel at the drain (D) is marked as I D The drain-to-source voltage is denoted by V DS The voltage applied to the gate (G) controls the current (I D ).

[0024] A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET) and is used in integrated circuits and high-speed switching applications. A MOSFET has an insulated gate whose voltage determines the conductivity of the device. The ability to change the conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on charge concentration regulation by a metal oxide semiconductor (MOS) capacitor between a body electrode and a gate electrode, which is located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a highly doped region separated by a body region. These regions can be either p-type or n-type, but they are all of the same type and of the opposite type to the body region. The source and drain (unlike the body) are highly doped and are indicated by a "+" sign after the doping type.

[0025] If the MOSFET is an n-channel or nMOS FET, then the source and drain are n+ regions and the bulk is the p-type substrate region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are p+ regions and the bulk is the n-type substrate region. The source is called this because it is the source of charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0026] An nMOS FET is made of an n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the bulk (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current carried by electrons passes through the induced n-type channel from source to drain. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. There are three operating modes in NMOS, called cutoff, triode, and saturation. Because DC current flows through the logic gate when the output is low, circuits with NMOS logic gates dissipate static power when the circuit is idle.

[0027] The pMOS FET is made of p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (negative voltage between the gate and source), a p-type channel is formed between the source and drain with opposite polarity. The current carried by the holes passes through the induced p-type channel from the source to the drain. A high voltage on the gate will cause the PMOS to not conduct, while a low voltage on the gate will cause the PMOS to conduct. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low cost and has good noise immunity.

[0028] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts, while PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct while PMOS conducts. NMOS is considered faster than PMOS because the carriers in NMOS are electrons, which travel twice as fast as holes, which are the carriers in PMOS. However, PMOS devices have higher noise immunity compared to NMOS devices. Furthermore, NMOS ICs will be smaller than PMOS ICs (giving the same functionality) because NMOS can provide half the impedance provided by PMOS (with the same geometry and operating conditions).

[0029] As used herein, the term "Fin Field Effect Transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate where the gate is placed on 2, 3, or 4 sides of the channel or surrounds the channel, forming a dual gate structure. FinFET devices have been given this generic name FinFET because the source / drain regions form a "fin" on the substrate. FinFET devices have fast switching times and high current density.

[0030] In one or more embodiments, hafnium-based materials that exhibit p-metal behavior are advantageously provided. The materials of one or more embodiments include, but are not limited to, hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAlN), and hafnium carbide nitride (HfCN).

[0031] In one or more embodiments, provided are films comprising hafnium-based materials. The films deposited by atomic layer deposition show PMOS work function capabilities. The growth of hafnium-based materials is developed in an ALD chamber having a temperature range from 200° C. to 500° C. The precursors used to grow hafnium carbide are selected from hafnium tetrachloride, hafnium tetraiodide, and aluminum-based precursors such as, but not limited to, triethylaluminum, trimethylaluminum, trisneopentylaluminum, tetrabutylaluminum. An in-situ capping layer such as TiN or TiAl can be used to control film oxidation after deposition.

[0032] One or more embodiments advantageously provide a composite stacked TiX2O3 layer deposited as n and p dipoles by atomic layer deposition. 1 N and TiX 2 N dipole current to shift the work function. TiX for n dipole 1 N compositions include but are not limited to TiLaN, TiYN, TiSrN, and TiMgN. TiX 2 N includes, but is not limited to, TiAlN and TiTaN.

[0033] Embodiments of the present disclosure are illustrated by the accompanying drawings, which depict devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses for the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0034] Figure 1 A flowchart depicting a method 100 according to one or more embodiments of the present disclosure is shown. Figure 1, method 100 begins at operation 102 by depositing an interlayer dielectric on a top surface of a channel between a source and a drain on a substrate. At operation 104, a high-K dielectric material is deposited on the interlayer dielectric. At operation 106, a dipole layer is deposited on the high-K dielectric material. At operation 108, a capping layer is optionally deposited on the dipole layer.

[0035] Figure 2 as well as Figure 3A and Figure 3B is a cross-sectional view of an electronic device (eg, transistor) 200 according to one or more embodiments. Figure 2 and Figure 3A , the electronic device 200 includes a semiconductor substrate 202 having a top surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination of the foregoing. In one or more embodiments, the semiconductor substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). Although several examples of materials that can form the substrate 202 are described herein, any material that can serve as a basis for the construction of passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) falls within the spirit and scope of the present disclosure.

[0036] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type comes from the negative charge of the electron. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a greater concentration of holes than electrons. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0037] Reference Figure 2 and Figure 3A, the source region 204a is located on the top surface 203 of the semiconductor substrate 202. In one or more embodiments, the source region 204a has a source and a source contact (not shown). The drain region 204b is located on the top surface 203 of the semiconductor substrate 202 and is opposite to the source region 204a. In one or more embodiments, the drain region 204b has a drain and a drain contact (not shown).

[0038] In one or more embodiments, the source region 204a and / or the drain region 204b may be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b may have more than one layer. For example, the source region 204a and / or the drain region 204b may independently include three layers. In one or more embodiments, the source region 204a and the drain region 204b may independently include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and the drain region 204b may independently include a bottom layer having doped epitaxial silicon (e.g., SiGe, SiP, and the like), a second layer of silicide that may contain nickel (Ni), titanium (Ti), aluminum (Al), and the like, and a third or top layer, which may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, and the like.

[0039] In some embodiments, the source region 204 a and the drain region 204 b may be elevated source / drain regions formed by epitaxial growth.

[0040] In one or more embodiments, the source contact and / or the drain contact may be independently selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source contact and / or the drain contact is performed by any suitable process known to those skilled in the art, including but not limited to ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art.

[0041] In one or more embodiments, the channel 206 is located between the source 204 a and the drain 204 b .

[0042] In one or more embodiments, the dipole region 208 covers the channel 206 and contacts one or more of the channel 206, the source region 204a, and the drain region 204b. In one or more embodiments, the dipole layer has a thickness of less than about Thickness.

[0043] In one or more embodiments, the dipole region 208 includes one or more of an interlayer dielectric (ILD) 210, a high-K dielectric material 212, and a dipole layer 214. In certain embodiments, the dipole region 208 includes an interlayer dielectric (ILD) 210, a high-K dielectric material 212, and a dipole layer 214.

[0044] In one or more embodiments, an interlayer dielectric (ILD) 210 is deposited on the top surface 205 of the trench 206. In one or more embodiments, the interlayer dielectric 210 may be any suitable material known to those skilled in the art. For example, in one or more embodiments, the interlayer dielectric 210 includes a low-K dielectric. In one or more embodiments, the low-K dielectric is selected from one or more of silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon oxynitride and carbon nitride, SiCONH, doped silicon, doped silicon oxide, doped silicon nitride, doped silicon oxynitride, spin-on dielectric, or diffused species growth. In one or more embodiments, the interlayer dielectric 210 includes silicon oxide. The interlayer dielectric (ILD) 210 may be deposited using one or more deposition techniques known to those skilled in the art of microelectronic device manufacturing. In one or more embodiments, the interlayer dielectric (ILD) 210 is deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the interlayer dielectric (ILD) 210 may be formed by etching and forming an oxide on the surface.

[0045] In one or more embodiments, a high-K dielectric material 212 is deposited on a top surface 211 of the interlayer dielectric (ILD) 210. The high-K dielectric material 212 may be any suitable high-K dielectric material known to those skilled in the art. In one or more embodiments, the high-K dielectric material 212 includes hafnium oxide or lanthanum (La) doped high-K dielectric. In one or more embodiments, the high-K dielectric material 212 is deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art.

[0046] Typically, a high-K capping layer, such as titanium nitride (TiN), is deposited on the top surface of the high-K dielectric material. However, in one or more embodiments, a dipole layer 214 is deposited instead of a high-K dielectric material.

[0047] In one or more embodiments, the dipole layer 214 is deposited on the top surface 213 of the high-K dielectric material 212. In one or more embodiments, the dipole layer 214 is deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. In one or more specific embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD). In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition at a temperature in a range of about 200° C. to about 500° C.

[0048] In one or more embodiments, when the channel 206 comprises an n-type material, the dipole layer 214 comprises TiX 1 N materials, where X 1 is a metal selected from one or more of lanthanum (La), yttrium (Y), strontium (Sr), or magnesium (Mg). Other metals known to those skilled in the art may be used as X 1 Thus, in one or more embodiments, where the channel 206 includes an n-type material, the dipole layer 214 includes one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), or titanium magnesium nitride (TiMgN).

[0049] Reference Figure 3A and Figure 3B In one or more embodiments, the dipole layer 214 includes TiX deposited by atomic layer deposition at a temperature between about 200° C. and about 500° C. 1 In one or more embodiments, TiN and X 1 N alternate cycles to deposit TiX 1 N(X 1 In one or more embodiments, by adjusting the TiN and X 1 The cycle ratio between N and X in the composite dipole layer 214 can be adjusted. 1 N content. Figure 3B In one or more embodiments, the TiX on the PFET side 250 is removed by patterning. 1 N dipole layer 214 .

[0050] In one or more embodiments, when the channel 206 includes a p-type material, the dipole layer 214 includes TiX 2 N materials, where X 2is a metal selected from one or more of aluminum (Al), tantalum (Ta), or vanadium (V). In one or more embodiments, the P-type dipole layer 214 composite TiX is deposited by atomic layer deposition at a temperature between about 200° C. and about 500° C. 2 In one or more embodiments, TiN and X 2 N alternate cycles to deposit TiX 2 N(X 2 In one or more embodiments, by adjusting the TiN and X 2 The cycle ratio between N and X in the composite dipole layer 214 can be adjusted. 2 N content.

[0051] In one or more embodiments, the channel 206 includes a p-type material and the dipole layer 214 includes one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium hafnium nitride (TiHfN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbide nitride (HfCN).

[0052] In one or more embodiments, a high temperature thermal anneal is performed to drive the X 1 With X 2 The remaining TiN directly serves as a high-K capping layer.

[0053] Unwilling to be limited by theory, I believe that including TiX 1 N or TiX 2 The dipole layer of N material simplifies the existing integration process and reduces the integration cost. 1 N or X 2 When N is embedded in the TiN layer, it is believed that oxidation can be reduced, which can potentially reduce the required annealing temperature. 1 or X 2 Excellent control of the content of allows multi-voltage maintainability of electronic devices.

[0054] In one or more embodiments, a hafnium-based material exhibiting p-metal behavior may be deposited on a semiconductor substrate by atomic layer deposition as a dipole layer 214 or a work function layer (not shown). In one or more embodiments, the hafnium-based material includes, but is not limited to, hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAIN), and hafnium carbide nitride (HfCN). In one or more embodiments, the hafnium-based material exhibits PMOS work function capability. In one or more embodiments, the growth of the hafnium-based material is developed in an ALD chamber at a temperature ranging from about 200° C. to about 500° C. In one or more embodiments, precursors for growing hafnium carbide include, but are not limited to, hafnium tetrachloride and aluminum-based precursors such as triethylaluminum, trimethylaluminum, trinepentaluminum, and tetrabutylaluminum. In one or more embodiments, an in-situ capping layer, such as titanium nitride (TiN) or titanium aluminum (TiAl), may be used to control film oxidation after deposition.

[0055] Without wishing to be bound by theory, it is believed that the advantages of hafnium-based materials as p-type work function materials include work functions above 5.0 eV, which is higher than the current industry baseline of TiN, enabling transistor scaling; MOSCAP shifts to the PMOS range creating a p-metal work function; electrical data show better EOT compared to titanium nitride (TiN) films; lower hafnium carbide leakage current is observed when compared to titanium aluminum (TiAl); hafnium-based films show a unique thickness dependence as p-type materials (with thinner hafnium-based films, the flat band voltage of MOSCAP shifts toward the Si valence band edge, allowing the use of extremely thin films for transistor scaling without affecting device performance); and the threshold voltage of electronic devices having hafnium-based films as p-type work function materials can be tuned by titanium nitride (TiN) capping. Thus, in one or more embodiments, hafnium-based materials can be used as work function layers or as dipole layers.

[0056] In one or more embodiments, a gate including one or more of a gate metal (not shown) or a gate contact (not shown) may be optionally formed or deposited on the exposed surface of the dipole region 208. The gate metal may be any material known to those skilled in the art. In one or more embodiments, the gate metal includes one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more specific embodiments, the gate metal includes a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), iridium (Ir), aluminum (Al), or platinum (Pt). In other specific embodiments, the gate metal 226 includes a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), or ruthenium (Ru). In one or more embodiments, the gate contact may be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact is selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0057] In one or more embodiments, a capping layer may be deposited on the exposed surface of the dipole region 208. In one or more embodiments, the capping layer may include one or more of titanium nitride (TiN) or titanium aluminum (TiAl).

[0058] One or more embodiments are directed to an electronic device, comprising a source region having a source and a source contact, the source region being on a top surface of a substrate; a drain region having a drain and a drain contact, the drain region being on the top surface of the substrate; a channel located between the source and the drain; and a dipole region on the top surface of the channel, the dipole region comprising an interlayer dielectric, a high-K dielectric material, and a dipole layer, the dipole layer comprising one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN), titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAIN), or hafnium carbide nitride (HfCN).

[0059] Additional embodiments of the present disclosure relate to a processing tool 900 for forming and using the described logic / memory devices, such as Figure 4 shown.

[0060] The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to transfer robot blades and wafers to each of the multiple sides.

[0061] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, which are also referred to as processing stations and are connected to a central transfer station. Various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers may be any suitable chamber, including, but not limited to, pre-cleaning chambers, buffer chambers, transfer spaces, wafer positioning / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, thermal treatment (RTP) chambers, plasma oxidation chambers, plasma nitridation chambers, and atomic layer deposition (ALD) chambers. The specific arrangement of the processing chambers and components may vary depending on the cluster tool and should not be taken as limiting the scope of the present disclosure.

[0062] In one or more embodiments, the cluster tool 900 includes a silicon oxide (SiO2) chamber to deposit silicon oxide (SiO2). The silicon oxide (SiO2) deposition chamber of certain embodiments includes an atomic layer deposition chamber, a plasma enhanced atomic layer deposition chamber, or a spatial atomic layer deposition chamber. In one or more embodiments, the cluster tool 900 includes a pre-clean chamber connected to a central transfer station.

[0063] exist Figure 4 In the illustrated embodiment, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this is merely representative of one possible configuration.

[0064] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending on, for example, the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette having a plurality of wafers positioned in the cassette.

[0065] The robot 952 is within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to the load lock chamber 960. The robot 952 can also transfer wafers from the load lock chamber 962 through the factory interface 950 to the cassette in the unloading chamber 956. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0066] The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921, and the first transfer chamber 921 has at least one robot 925 positioned therein. The robot 925 is also referred to as a robot wafer transfer mechanism. The first transfer chamber 921 is located centrally relative to the load lock chambers 960, 962, the processing chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 of certain embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In one or more embodiments, the first transfer chamber 921 includes more than one robot wafer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Each wafer is carried on a wafer transfer blade located at a distal end of the first robot mechanism.

[0067] After processing the wafer in the first section 920, the wafer can be transferred to the second section 930 through the pass-through chamber. For example, the chambers 922, 924 can be single-directional or double-directional pass-through chambers. The pass-through chambers 922, 924 can be used, for example, to cryogenically cool the wafer before processing in the second section 930, or to allow cooling or post-processing of the wafer before moving back to the first section 920.

[0068] The system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 990 may be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0069] The process may typically be stored as a software program in a memory of the system controller 990, which, when executed by a processor, causes the processing chamber to perform the process of the present disclosure. The software program may also be stored and / or executed by a second processor (not shown), which is located at a remote end of the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software and executed in hardware using a computer system, such as, for example, an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software program transforms a general purpose computer into a special purpose computer (controller) that controls the operation of the chamber to perform the process.

[0070] In one or more embodiments, the processing tool 900 includes a central transfer station 921, 931, the central transfer station 921, 931 including at least one robot 925, 935 configured to move wafers; one or more of a rapid thermal processing (RTP) station, a decoupled plasma oxidation (DPO), or a decoupled plasma nitridation (DPN) station connected to the central transfer station; an atomic layer deposition (ALD) station connected to the central transfer station; an optional pre-cleaning station connected to the central transfer station; and at least one controller connected to one or more of the central transfer station, the RTP station, the DPO station, the DPN station, the ALD station, or the optional pre-cleaning station. In one or more embodiments, the at least one controller has at least one configuration selected from the following: a configuration to move wafers between stations using a robot; a configuration to perform rapid thermal processing; a configuration to perform decoupled plasma processing; a configuration to control the flow of an oxidizing gas into an RTP station or a DPO station; a configuration to control the flow of a nitriding gas into an RTP station or a DPN station; a configuration to deposit a silicon oxide film by atomic layer deposition; and a configuration to pre-clean wafers.

[0071] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used herein to simplify the description to illustrate the relationship of one element or feature relative to another element or feature as illustrated in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the example term "below" may encompass both orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptions used herein are interpreted accordingly.

[0072] The use of the terms "a" and "an" and "said" and similar indicators in the context of the materials and methods discussed herein (especially in the context of the claims thereafter) is interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradictory to the context. The enumeration of the range of numerical values ​​herein is intended only as a shorthand method of referring to each individual numerical value falling within this range, unless otherwise indicated herein, and each individual numerical value is incorporated into this specification as if it were separately enumerated herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradictory to the context. The use of any and all examples or example language (e.g., "such as") provided herein is intended only to better illustrate materials and methods and not to impose limitations on the scope, unless otherwise stated. The language in this specification should not be taken as indicating that any unclaimed element is necessary for the implementation of the disclosed materials and methods.

[0073] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment are included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "certain embodiments," "in an embodiment," or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the specific features, structures, materials, or characteristics are combined in any suitable manner.

[0074] Although the present disclosure has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. An electronic device, comprising: a source region, a drain region, and a channel separating the source region and the drain region; and a dipole region on a top surface of the channel, the dipole region comprising, from bottom to top, an interlayer dielectric, a high-K dielectric material, and a dipole layer deposited by atomic layer deposition (ALD) of titanium nitride (TiN) and a dipole precursor at a temperature in a range from 200° C. to 500° C., The dipole layer includes one or more of the following: titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), or titanium magnesium nitride (TiMgN), titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), or titanium hafnium nitride (TiHfN).

2. The electronic device of claim 1, further comprising a gate located on the dipole region.

3. An electronic device as described in claim 1, wherein the source region and the drain region independently include one or more of the following: copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr).

4. The electronic device of claim 1, wherein the interlayer dielectric comprises a low-K dielectric.

5. The electronic device of claim 4, wherein the low-K dielectric is silicon oxide.

6. The electronic device of claim 4, wherein the low-K dielectric is doped silicon oxide.

7. The electronic device of claim 4, wherein the low-K dielectric is a spin-on dielectric.

8. The electronic device of claim 1, wherein the high-K dielectric material comprises one or more of: hafnium oxide or lanthanum (La) doped high-K dielectric.

9. The electronic device of claim 1, further comprising a capping layer on the dipole region, the capping layer comprising one or more of: titanium nitride or titanium aluminum.

10. The electronic device of claim 1, wherein the dipole layer has a Thickness.

11. An electronic device comprising: a source region, a drain region, and a channel separating the source region and the drain region; and a dipole region on a top surface of the channel, the dipole region comprising, from bottom to top, an interlayer dielectric, a high-K dielectric material, and a dipole layer deposited by atomic layer deposition (ALD) of alternating cycles of a hafnium precursor and a second precursor at a temperature in a range from 200° C. to 500° C., wherein the channel comprises a p-type material, and the dipole layer comprises one or more of: hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbide nitride (HfCN).

12. A method for manufacturing an electronic device, the method comprising: depositing an interlayer dielectric on a top surface of a channel, the channel being located between a source electrode and a drain electrode on the substrate; depositing a high-K dielectric material on the interlayer dielectric; and depositing a dipole layer on the high-K dielectric material, wherein depositing the dipole layer comprises atomic layer deposition of titanium nitride (TiN) and a dipole precursor at a temperature in the range of 200° C. to 500° C., The dipole layer includes one or more of the following: titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN), titanium aluminum nitride (TiAlN), or titanium tantalum nitride (TiTaN).

13. The method of claim 12, wherein the dipole precursor comprises one or more of: lanthanum nitride (LaN), yttrium nitride (YN), strontium nitride (SrN), magnesium nitride (MgN), aluminum nitride (AlN), or tantalum nitride (TaN).

14. The method of claim 12, wherein the dipole layer has a value less than Thickness.

15. A method of manufacturing an electronic device, the method comprising: depositing an interlayer dielectric on a top surface of a channel, the channel being located between a source electrode and a drain electrode on the substrate; depositing a high-K dielectric material on the interlayer dielectric; and A dipole layer is deposited on the high-K dielectric material, wherein the dipole layer comprises one or more of: hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbide nitride (HfCN), and wherein depositing the dipole layer comprises atomic layer deposition of alternating cycles of a hafnium precursor and a second precursor at a temperature in the range of 200°C to 500°C.

16. The method of claim 15, wherein the hafnium precursor comprises hafnium tetrachloride and the second precursor comprises one or more of: triethylaluminum, trimethylaluminum, trinepentaluminum, tetrabutylaluminum, or ammonia.

17. The method of claim 16, further comprising in-situ deposition of a capping layer, the capping layer comprising one or more of: titanium nitride or titanium aluminum.

18. An electronic device comprising: a source region having a source and a source contact, the source region being located on the top surface of the substrate; a drain region having a drain and a drain contact, the drain region being located on the top surface of the substrate; a channel located between the source and the drain; and a dipole region, the dipole region being located on a top surface of the channel, the dipole region comprising an interlayer dielectric, a high-K dielectric material, and a dipole layer from bottom to top, wherein the dipole layer is deposited by atomic layer deposition (ALD) of alternating cycles of titanium nitride (TiN) and a dipole precursor at a temperature in the range of 200°C to 500°C, and the dipole layer comprises one or more of: titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN), titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN); or Or wherein the dipole layer is deposited by atomic layer deposition (ALD) of alternating cycles of a hafnium precursor and a second precursor at a temperature in a range from 200°C to 500°C, and the dipole layer comprises one or more of: hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium aluminum carbide (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbide nitride (HfCN).

Images