Performance Tuning Techniques

Abstract

Various implementations described herein relate to a device having a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for use in adjusting the output voltage.

Description

[0001] Statement Regarding Federally Funded Research

[0002] This invention was made with Government support under Agreement No. HR0011-17-9-0025 awarded by DARPA. The Government has certain rights in this invention. Background Art

[0003] This section is intended to provide information relevant to understanding the various techniques described herein. As the title of this section implies, this is a discussion of related art and should in no way be construed as prior art. Generally speaking, related art may or may not be considered prior art. Therefore, it should be understood that any statements in this section are to be read in this light and are not intended to be an admission that they are prior art.

[0004] The performance of digital circuits often depends on the supply voltage, process variations, and temperature. Conventional digitally controlled DC-DC converters typically use an analog-to-digital converter (ADC) to convert the output voltage into a digital feedback signal, which is compared with a reference signal to set the desired voltage level of the output voltage. Conventional systems generate a reference voltage based on the desired performance level of the digital circuit. However, conventional approaches require some voltage margin between the output voltage of the digital system and the maximum clock frequency. This voltage margin can account for dynamic regulation of DC voltage drops on the power delivery network of the digital system and sensor errors. In addition, this voltage margin may result in additional power dissipation because the supply voltage of the digital system is higher than necessary, and as the dynamic power dissipated by the digital system increases, leakage power also increases, with little performance benefit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention describes various technical implementations with reference to the accompanying drawings. However, it should be understood that the accompanying drawings only illustrate various implementations described herein and are not intended to limit the implementation of the various technologies described herein.

[0006] Figure 1A to Figure 1B Various diagrams illustrating performance scaling circuits according to implementations described herein.

[0007] Figures 2A to 2B Shown are diagrams related to a time-delay converter (TDC) according to specific implementations described herein.

[0008] Figures 3A to 3C A diagram related to a delay circuit according to an implementation described herein is shown.

[0009] Figures 4A to 4B A diagram illustrating a performance scaling circuit according to an implementation described herein is shown. DETAILED DESCRIPTION

[0010] Various embodiments described herein relate to control architectures for implementing performance scaling schemes and techniques. For example, various embodiments described herein provide a control architecture for implementing an ultra-low-power buck converter circuit for an Internet of Things (IoT) node sensor. The control architecture utilizes a time-to-digital (TDC) converter and a buck converter, which can be a DC-DC converter capable of performing a step-down conversion. Furthermore, the control architecture can utilize various clock scaling techniques in the supply loop.

[0011] The control architecture described herein provides performance regulation while maintaining low control quiescent current. The control architecture described herein uses a time-to-digital converter (TDC) to determine the performance delay of a digital chain. This performance delay is measured at regular intervals and compared to a reference delay. Based on this comparison, a delay error can be determined and used to feed a modulator, which is adapted to adjust the output voltage provided to a load. For example, if the propagation delay is too long, the TDC can increase the output voltage provided to the load, and if the propagation delay is too short, the TDC can decrease the output voltage provided to the load.

[0012] Typically, performance regulation (PR) rather than voltage regulation (VR) has become preferred for ultra-low power systems, where the energy-per-cycle figure for a digital subsystem is more important than the absolute maximum performance figure. An unfortunate characteristic of the energy-per-cycle figure for a digital system is that its sweet spot can occur near the device threshold voltage, and this is where CMOS transistors can be more sensitive to process and temperature variations.

[0013] This article will refer to Figures 1A to 4B Various specific implementations of performance tuning schemes and techniques are described in more detail.

[0014] Figure 1A to Figure 1B Various diagrams of performance adjustment circuits according to specific implementations described herein are shown. Specifically, Figure 1A FIG100A shows a performance adjustment circuit 102, and Figure 1B Another diagram 100B shows the performance scaling circuit 102 coupled to a tuned clock ring oscillator (TCRO) 150 and a central processing unit (CPU) 160 .

[0015] As reference Figure 1AAs shown, performance adjustment circuit 102 is a device having multiple stages, including, for example, a power stage 110, a clock stage 120, a delay chain stage 130, and a time-to-digital converter (TDC) stage 140. In some cases, performance adjustment circuit 102 can be implemented as a system of various circuit components that are arranged and coupled together as a collection or combination of components forming a circuit structure. Furthermore, in some cases, methods of performance adjustment can involve using various circuit components to implement the various performance adjustment schemes and techniques described herein.

[0016] The power stage 110 can be implemented as a voltage regulator that uses a modulator (MOD 122) to adjust the output voltage (Vout). In some cases, the voltage regulator 110 can be coupled to a load 118 to provide and regulate the supply voltage (e.g., Vdd) of the load 118, and the voltage regulator 110 can refer to a DC-DC voltage converter or a buck converter. The voltage regulator 110 can include a first power inverter 114A and a second power inverter 114B connected in parallel between the gates of the modulator (MOD 122) and the power transistors (T1, T2). As shown, the first power inverter 114A can be coupled between the modulator (MOD 122) and the first power transistor (T1), and the second power inverter 114B can be coupled between the modulator (MOD 122) and the second power transistor (T2). The power transistors (T1, T2) are connected in series between a voltage source (Vdd) and ground (or Vss). Furthermore, the voltage regulator 110 may include a first diode (D1) coupled in parallel with the first power transistor (T1) and a second diode (D2) coupled in parallel with the second power transistor (T2). The voltage regulator 110 may also include a power coil, such as, for example, an inductor (I), coupled between the power transistors (T1, T2) at node (n1) and a load at node (n2). The voltage regulator 110 may include a charge storage device, such as, for example, a capacitor (C), coupled between node (n2) and ground (or Vss). In some cases, a load 118 may be coupled between node (n2) and ground (or Vss), and the load 118 may receive the output voltage (Vout) via node (n2).

[0017] Clock stage 120 may include a modulator (MOD 122) and a combinational logic component 124. Modulator (MOD 122) may use combinational logic component 124 to compare a feedback signal (N_feed) with a reference signal (N_ref) and also determine the difference between the feedback signal (N_feed) and the reference signal (N_ref). In some cases, combinational logic component 124 may include logic associated with computational or arithmetic operations (e.g., the difference and / or total of the inputs). Combinatorial logic component 124 may receive the feedback signal (N_feed) from TDC 140, receive an external reference signal (N_ref), and provide an output signal to modulator (MOD 122). Modulator (MOD 122) may receive an input clock signal (CLK) and provide an output clock signal (CLK_tdc), which may be used as a sampling clock signal.

[0018] The delay chain stage 130 may include a logic chain 132 that provides a delay signal (tdc_out_delay) associated with a signal (tdc_out) passing through the logic chain 132. In some cases, the logic chain 132 may be configured to sense process variations in circuit components associated with the performance adjustment circuit 102. The logic chain 132 may include an inverter logic chain (e.g., inverters connected in series that operate as a ring oscillator) for determining the performance of the load 118. As shown, the logic chain 132 may be coupled between a node (n2) and ground (or Vss), and the logic chain 132 may receive an output voltage (Vout) at the node (n2). The output voltage (Vout) may be provided to the power supply inputs of the inverters in the delay chain 132.

[0019] The time-to-digital converter (TDC) stage 140 may be configured to measure a timing delay of the delay signal (tdc_out_delay) from the logic chain 132, compare the timing delay with a reference delay to determine a timing delay error, and provide the timing delay error to the modulator (MOD 122) via the logic component 124 for use in adjusting the output voltage (Vout). The time-to-digital converter (TDC) 140 may provide the timing delay error as a feedback signal (N_feed) to the modulator (MOD 122) via the logic component 124 for use in adjusting the output voltage (Vout) based on the timing delay error. For example, if the timing delay error is greater than a predetermined interval, the time-to-digital converter (TDC) 140 may provide the feedback signal (N_feed) to the modulator (MOD 122) to increase the output voltage (Vout). TDC 140 may receive an output clock signal (CLK_tdc) from modulator (MOD 122) as a sampling clock signal, and may generate a feedback signal (N_feed) based on the sampling clock signal (CLK_tdc) from modulator (MOD 122) and / or a delay signal (tdc_out_delay) from delay chain 132.

[0020] The time-to-digital converter (TDC) 140 may measure (or sample) the timing delay of the logic chain 132 at periodic timing intervals. In some cases, if the timing delay error is greater than a predetermined interval, the time-to-digital converter (TDC) 140 may provide the timing delay error to the modulator (MOD 122) to increase the output voltage (Vout). Otherwise, if the timing delay error is less than the predetermined interval, the time-to-digital converter (TDC) 140 may provide the timing delay error to the modulator (MOD 122) to decrease the output voltage (Vout).

[0021] As reference Figure 1B As shown, performance scaling circuit 102 is a device coupled to tuned clock ring oscillator (TCRO) 150 and central processing unit (CPU) 160. In some cases, TCRO 150 and CPU 160 may be coupled between node (n2) and ground (or Vss), and TCRO 150 may provide an output pulse signal (ops) to CPU 160 that is independent of the delay signal (tdc_out_delay) provided by delay chain 132. The output pulse signal (ops) may be used as a clock signal for operating CPU 160.

[0022] In some implementations, the measured delay chain 132 can be coupled to the main CPU clock generation circuit (e.g., TCRO 150), allowing for a high-performance mode with only a small margin for the transient response of the voltage regulator 110 and the minimum phase noise of the CPU clock (ops). The CPU 160 can operate at a constant frequency and desired performance at the expense of slightly suboptimal energy per cycle performance. If energy per cycle performance is preferred over tight control of the CPU clock (ops), the delay chain 132 can be tightly coupled to the ring oscillator 150 that generates the CPU clock (ops).

[0023] The bandwidth and aliasing characteristics of voltage regulator 110 can be defined by setting its sampling clock (CLK_tdc) independently of the CPU clock (ops). Because the performance of digital gates can be measured directly by TDC 140, this control architecture may not require the incorporation of a process monitor or temperature sensor. In some cases, TDC power consumption can be lower than ADC power consumption (as used in conventional techniques), especially at low sampling clock rates, because a precise, always-on voltage reference circuit may not be required. In contrast, an RC-based time reference can use ultra-low quiescent current.

[0024] Figures 2A to 2B FIGURE 1 shows a diagram related to a time-delay converter (TDC) according to an implementation described herein. Specifically, Figure 2A A diagram 200A is shown relating to the time-delay converter (TDC) 140, and Figure 2B A waveform diagram 200B related to the operation of the TDC 140 is shown.

[0025] As reference Figure 2A As shown, time-delay converter (TDC) 140 is a device having multiple components, including, for example, a delay circuit 210, a latch circuit 212, and a logic circuit 236. In some cases, delay circuit 210 receives a clock signal (e.g., CLK_tdc) and provides a differential timing signal (dts_1, dts_2) to latch circuit 212. Delay circuit 210 can include multiple components, including, for example, one or more coarse delays 220 and one or more fine delays 224A, 224B.

[0026] In some cases, delay circuit 210 may be coupled to a logic chain (e.g., Figure 1A 132) to receive a timing delay signal (N_set_tc) from the logic chain as a timing delay associated with the performance of the logic chain 132. In some cases, the timing delay signal (N_set_tc) may refer to a delay signal (tdc_outdelay) associated with a signal (tdc_out) passing through the logic chain 132, as described herein above with reference to Figure 1A As stated.

[0027] Latch circuit 212 receives the differential timing signal (dts_1, dts_2) from the delay circuit and provides a pulsed sense signal (pss_1, pss_2) when activated (or triggered) by a reference delay signal (rds). Latch circuit 212 may include multiple components, including, for example, a timing reference 228 and one or more latches 232A, 232B. In some cases, timing reference 228 may refer to a trigger circuit that receives a clock signal (CLK_tdc) and activates one or more latches 232A, 232B by providing a timing reference signal (such as, for example, a reference delay signal (rds)) to a power input of one or more latches 232A, 232B. In some cases, one or more latches 232A, 232B may refer to one or more latch-based sense amplifiers adapted to receive the differential timing signal (dts_1, dts_2) from delay circuit 210 and provide a pulsed sense signal (pss_1, pss_2) when activated.

[0028] Logic circuit 236 receives the pulse sense signals (pss_1, pss_2) from latch circuit 212 and provides an output signal (eg, N_tdc) as a timing delay error. In some cases, the output signal (N_tdc) may be implemented as Figure 1A The logic circuit 236 may include one or more logic gates, such as, for example, one or more AND gates, or similar logic gates.

[0029] One or more coarse delays 220 (T_coarse) may receive a clock signal (CLK_tdc) from the modulator (MOD 122), a timing delay signal (N_set_tc) from the delay chain 140, and provide a modified clock signal (mcs) having a shorter pulse width. One or more coarse delays 220 (T_coarse) provide a first delay stage within the time-to-delay (TDC) converter 140. Figures 3B to 3C The one or more coarse delays 220 (T-coarse) are described in more detail.

[0030] One or more fine delays 224A, 224B (T_fine) may receive a clock signal (CLK_tdc) from a modulator (MOD 122), a modified clock signal (mcs) with a shorter pulse width from one or more coarse delays 220, and provide differential timing signals (dts_1, dts_2) to one or more latches 232A, 232B. In some cases, a first fine delay 224A receives a clock signal (CLK_tdc) from a modulator (MOD 122), a modified clock signal (mcs) from a coarse delay 220, and provides a first differential timing signal (dts_1) to a first latch 232A. Furthermore, a second fine delay 224B receives a clock signal (CLK_tdc) from a modulator (MOD 122), a modified clock signal (mcs) from the first fine delay 224A, and provides a second differential timing signal (dts_2) to a second latch 232B. The first latch 232A provides a first pulse sense signal (pss_1) to the logic circuit 236, and the second latch 232B provides a second pulse sense signal (pss_2) to the logic circuit 236. One or more fine delays 224A, 224B (T_fine) provide a secondary delay stage within the time-delay (TDC) converter 140. Figure 3A The one or more fine delays 224A, 224B (T-fine) are described in more detail.

[0031] Timing reference 228 (or trigger circuit: T_on) can receive the clock signal (CLK_tdc) from the modulator (MOD 122), receive the reference delay signal (N_set_tr) as a trigger signal, and provide the reference delay signal (rds) to one or more latches 232A, 232B. In some cases, the reference delay signal (rds) can be used as an enable signal to activate or trigger one or more latches 232A, 232B.

[0032] The logic circuit 236 may receive the pulse sense signals (pss_1, pss_2) from one or more latches 232A, 232B and provide an output signal (e.g., N_tdc) as a timing delay error. In some cases, the output signal (N_tdc) may be implemented as Figure 1A The logic circuit 236 may be implemented with one or more logic gates, such as, for example, one or more AND gates or similar logic gates.

[0033] In some implementations, the time-to-digital converter (TDC) 140 receives the timing delay signal (N_set_tc) from the logic chain 132, measures the timing delay of the logic chain 132 based on the timing delay signal (N_set_tc), and provides a timing delay error to the modulator (MOD 122) for adjusting the output voltage (Vout) from the voltage regulator 110. In this case, when the timing delay error is positive, the output signal (Vout) is used to trigger the conduction mode of the voltage regulator 110.

[0034] In some implementations, the TDC 140 receives a clock signal (CLK_tdc) and provides an output signal (e.g., N_tdc) as a timing delay error. In some cases, when the clock signal (CLK_tdc) is low, the propagation of the clock signal (CLK_tdc) through the TDC 140 can be blocked (e.g., as shown in FIG. Figure 2B As shown), the differential timing signals (dts_1, dts_2) from the delay circuit 210 may be forced to a logic low state (e.g., a logic zero having a potential close to ground or close to 0V). In some cases, the output signal (N_tdc) may be implemented as Figure 1A The feedback signal (N_feed) in.

[0035] In some specific implementations, Figure 2A A time-to-digital (TDC) architecture is provided in FIG, and the TDC 140 is built on a time reference (eg, N_set_tr), a coarse delay element (T_coarse 220), an optional coarse delay selector (eg, Figure 3C1 ), one or more fine delay elements (e.g., T-fine 224A, 224B), and one or more sense amplifiers (e.g., latches 232A, 232B). The architecture of TDC 140 differs from conventional time-to-digital converters as described below. For example, TDC 140 uses sense amplifiers (e.g., latches 232A, 232B) instead of conventional D flip-flops, which allows operation with a Vout voltage significantly lower than the control supply voltage (Vdd), which is typically not possible with conventional time-to-digital converters. Furthermore, the fine delay elements (e.g., T-fine 224A, 224B) can have differential output characteristics, i.e., one output is low and the other is high, where one of the outputs can be the input (e.g., when using inverters, where the input and output of the inverter are the output of the cell). In another example, the coarse delay and / or the fine delay can have propagation-blocking inputs. This can be used to avoid aliasing when the TDC propagation delay is longer than the sampling period. This may occur when the TDC 140 is operating outside the operating region of the CPU subsystem at a low supply voltage, and in some cases, a fine delay may be used as a blocking mechanism. Also, the number of output bits may be small (e.g., 1 or 2), and for some operating modes, only one bit may be required.

[0036] In some implementations, the TDC 140 can be modeled as a comparator that compares two time durations, such that the TDC output Ntdc follows the logical formula:

[0037] N TDC =((T c +N f ·T f )≥T on ), where Nf is the number of fine delay elements.

[0038] In operation, the converter regulates the output voltage such that the propagation delay of the TDC is equal to the time reference:

[0039] T c +N f T f ≈T on

[0040] A clock system can be constructed using a ring oscillator (TCRO 150) that oscillates as a function of its supply voltage (e.g., Vout from power converter 110), process, and temperature. The oscillation frequency of TCRO 150 can be described as a function of the propagation delay through the ring oscillator chain:

[0041]

[0042] The TCRO delay chain and the TDC delay chain can be designed using similar gates and layout, so that some matching between the two delays can be assumed:

[0043] K(T c +N f T f )≈T TCRO , where K is defined by the design of the two chains.

[0044] For example, if the TCRO delay chain is constructed with multiple inverters (e.g., 81 inverters), and if the TDC delay chain also employs multiple inverters (e.g., 161 inverters), then K can be approximately 0.5. Furthermore, in some cases, reorganizing the three previous equations can yield a converter performance scaling equation:

[0045]

[0046] This formula shows that by adjusting the converter's output voltage so that the TDC output is at its trip point, the CPU clock frequency can be adjusted.

[0047] As reference Figure 2B As shown, the waveform 200B is Figure 2A The operation of the time-delay converter (TDC) 140 in FIG. Figure 2A The numbered signals 1-6 correspond to Figure 2B The waveforms are numbered 1-6. Therefore, Figure 2A The signals 1-6 shown in FIG are provided as Figure 2B Waveforms 1-6 in timing diagram 210 in FIG. In some cases, the TDC input clock (CLK_tdc) can be used as a clock signal and as a blocking signal. When CLK_tdc is low, propagation through TDC 140 can be blocked, and the output signals (2, 3, 4, 5) from delay elements (220, 224A, 224B) can be forced low. The time reference signal (N_set_tr) can be triggered by the TDC clock signal (CLK_tdc) and can generate a pulse (low pulse) with a value determined by a digital setting. The time reference signal (N_set_tr) can be designed to be independent of process-voltage-temperature (PVT). TDC 140 can provide a clock on-time signal (T_on:1) that is as long as or longer than the time reference pulse (N_set_tr).

[0048] Furthermore, in some cases, the sense amplifiers (e.g., latches 232A, 232B) can be triggered once the reference time pulse (N_set_tr) has elapsed. Latch-based sense amplifiers (e.g., latches 232A, 232B) allow for much lower operating voltages than using conventional D flip-flops. Referring to signal 1, shortly after the rising edge of the time reference signal (N_set_tr), the sense amplifier (e.g., latches 232A, 232B) output result (at signal 6) stabilizes and propagates through the combinational logic component 236 that encodes it.

[0049] Figures 3A to 3C FIGURE 1 shows a diagram related to a delay circuit according to a specific implementation described herein. Specifically, Figure 3A FIG. 300A shows a fine delay circuit 302. Figure 3B FIG300B shows a coarse delay circuit 304, and Figure 3C Diagram 300C of coarse delay unit 330 is shown.

[0050] The fine delay circuit 302 can be implemented as Figure 2A One or more fine delays 224A, 224B (T_fine) in Figure 3A As shown, fine delay circuit 302 is a unit or device having a plurality of logic gates 310, 312 coupled together to receive a sampling clock signal (CLK_tdc), a modified clock signal (NCLK_tdc) from coarse delay 220, and provide differential timing signals (dts_1, dts_2) as a low-voltage output (OUTN) and a high-voltage output (OUT). The modified clock signal (mcs) may refer to an inverted clock signal (NCLK_tdc). Furthermore, in some cases, fine delay circuit 302 may receive an input signal (IN) as a propagation-blocking input, which may be required to prevent aliasing when the TDC propagation delay is longer than the sampling period. This may occur when TDC 140 is operating outside the operating region of CPU subsystem 160 at a low supply voltage (Vdd).

[0051] The coarse delay circuit 304 may be implemented as Figure 2A One or more coarse delays 220 (T_coarse). Figure 3B As shown, the coarse delay circuit 304 is a unit or device having a plurality of coarse delay units (CDUs) 314A, 314B, ..., 314N, which are connected in series with a plurality of logic gates 318A, 318B, ..., 318N. Figure 3CAs shown, multiple logic gates 318A, 318B, ..., 318N may be implemented using AND gates or similar logic gates. In some cases, the first CDU 314A may receive a sampling clock signal (CLK_tdc) and provide an output signal to the first logic gate 318A. The first logic gate 318A may receive the output signal from the CDU 314A, receive the sampling clock signal (CLK_tdc), and provide the output signal to the second (or next) CDU 314B. The second CDU 314B may receive the output signal from the first (or previous) CDU 314A and provide the output signal to the last (or next) logic gate 318N. The last logic gate 318N may receive the output signal from the second (or previous) CDU 314B, receive the sampling clock signal (CLK_tdc), and provide a coarse delay output signal (OUT). In various implementations, the coarse delay circuit 304 may include any number (N) of coarse delay units (CDUs) 314A, 314B, ..., 314N and any number (N) of logic gates 318A, 318B, ..., 318N.

[0052] The coarse delay unit 330 may be implemented as Figure 3B The coarse delay units (CDUs) 314A, 314B, ..., 314N in FIG. Figure 3CAs shown, the coarse delay unit 330 is a unit or device having a plurality of logic delay chains 340, 342, 350, 352, 354, 356, which are coupled between the input multiplexer (M1) and the output multiplexer (M2). In some cases, the first inverter delay chain 340 may include any number (N) of inverters Inv1, Inv2, ..., InvN (e.g., N=8), which are coupled in series between the multiplexers (M1, M2). Furthermore, the second inverter delay chain 342 may include any number (N) of inverters Inv1, Inv2, ..., InvN (e.g., N=5), which are coupled in series between the multiplexers (M1, M2). Furthermore, the first logic gate delay chain 350 can be coupled in series with a third inverter delay chain 352 between the multiplexers (M1, M2), and the second logic gate delay chain 354 can also be coupled in series with a fourth inverter delay chain 356 between the multiplexers (M1, M2). In some cases, the first logic gate delay chain 350 can include any number (N) of logic gates coupled in series (e.g., NAND gates: Nand1, Nand2, ..., NandN, where N=5), and the third inverter delay chain 352 can include one or more inverters coupled in series (e.g., Inv1, Inv2, where N=2). As shown, each of the logic gates (Nand1, Nand2, ..., NandN) in the first logic gate delay chain 350 can be provided with a logic one ("1") as another input. Furthermore, in some cases, the second logic gate delay chain 354 may include any number (N) of logic gates coupled in series (e.g., NOR gates: Nor1, Nor2, ..., NorN, where N=5), and the fourth inverter delay chain 356 may include one or more inverters coupled in series (e.g., Inv1, where N=1). As shown, each of the logic gates (Nor1, Nor2, ..., NorN) in the second logic gate delay chain 354 may be provided with a logic zero ("0") as another input.

[0053] Moreover, if Figure 3CAs shown, the first multiplexer (M1) can be implemented as a 1-to-4 multiplexer that receives a sampling clock signal (CLK_tdc) from the modulator (MOD 122) and provides the sampling clock signal (CLK_tdc) to at least one of the logic delay chains 340, 342, 350 / 352, 354 / 356 based on a select signal (sel). In addition, the second multiplexer (M2) can be implemented as a 4-to-1 multiplexer that receives a modified clock signal (mcs) from at least one of the logic delay chains 340, 342, 350 / 352, 354 / 356 and provides an output signal (OUT) based on a select signal (sel). The modified clock signal (mcs) can be based on the sampling clock signal (CLK_tdc) and / or a delayed clock and / or an inverted clock associated with the sampling clock signal. In some implementations, the first multiplexer (M1) can be implemented as a 1-to-4 multiplexer coupled to the logical chains 340, 342, 350 / 352, 354 / 356. However, in other implementations, the first multiplexer (M1) can be implemented with any type of multiplexer, such as, for example, a 1-to-3 multiplexer, a 1-to-5 multiplexer, or any other type of multiplexer coupled to any number of logical chains. Furthermore, the second multiplexer (M2) can be referred to as an output demultiplexer, and in some implementations, the second multiplexer (M2) can be implemented as a 4-to-1 multiplexer coupled to the logical chains 340, 342, 350 / 352, 354 / 356. However, in other implementations, the second multiplexer (M2) can be implemented with any type of multiplexer, such as, for example, a 3-to-1 multiplexer, a 5-to-1 multiplexer, or any other type of multiplexer coupled to any number of logic chains.

[0054] Reference time aliasing problem and time aliasing blocking, TDC delay line Figure 3C The coarse delay unit 330 in FIG. 3 may include a plurality of coarse delay units (e.g., 24 coarse delay units) that use an architecture similar to the delay units of the ring oscillator (TCRO 150) that clocks the CPU 160. The schematic diagram of the coarse delay unit 330 and the coarse delay blocks 220, 314A, 314B, ..., 314N may be used to block the propagation of the clock signal (CLK_tdc) only at the end of the coarse delay block (e.g., with 24 CDUs). In some cases, at least one propagation blocker unit may be coupled between each coarse delay unit 314A, 314B, ..., 314N, and the propagation blocker may also be implemented using one or more logic gates, such as, for example, Figure 3B One or more AND gates 318A, 318B, ..., 318N are shown.

[0055] Figures 4A to 4BVarious diagrams of performance adjustment circuits according to specific implementations described herein are shown. Specifically, Figure 4A FIG400A shows a performance scaling circuit 402A having a clock scaling controller 420A, and Figure 4B Diagram 400B shows a performance scaling circuit 402B with another clock scaling controller 420B. Figures 4A to 4B The various stages and their associated components shown in Figure 1A Similar components shown in FIG. 1 and FIG. 2 operate and function similarly.

[0056] As reference Figure 4A As shown, the performance adjustment circuit 402A refers to a device having multiple components, including, for example, the power stage 110 (or voltage regulator), the delay chain stage 130, the time-to-digital converter (TDC) 140, and the clock scaling controller 420A. As described herein, the power stage 110 (or voltage regulator) can be configured to receive and utilize a modulated control signal from the modulator (MOD 122) to adjust the output voltage (Vout) provided to the load 118. Furthermore, as described herein, the TDC 140 can be configured to determine a timing delay error associated with the output voltage (Vout) and provide the timing delay error as a feedback signal (N_feed) to the modulator (MOD 122).

[0057] The clock scaling controller 420A may be configured to receive a feedback signal (N_feed) from the TDC 140, generate a modulation control signal based on the feedback signal (N_feed) using the modulator (MOD 122), analyze the behavior of the feedback signal (N_feed) to adjust the modulation control signal, and provide the modulation control signal to the voltage regulator 110 to adjust the output voltage (Vout) provided to the load 118. Figure 4A As shown, the clock scaling controller 420A may include an oscillator (OSC 430) that provides a sampling clock (SC) for sampling the feedback signal (N_feed). The clock scaling controller 420A may include a logic circuit 438 that receives a modulation control signal from the modulator (MOD 122) and tracks the pulse density (PD) of the modulation control signal.

[0058] In some implementations, the clock scaling controller 420A may include a clock divider (Div R 433) that receives a sampling clock (SC) from an oscillator (OSC 430), receives a pulse density (PD) from a logic circuit 438 as a reference signal (R1), adjusts the sampling clock (SC) based on the pulse density (PD), and then provides the adjusted sampling clock (ASC) to the modulator (MOD 122). Furthermore, as shown, the clock scaling controller 420A may include a modulator (MOD 122) that receives a feedback signal (N_feed) from the TDC 140, receives the adjusted sampling clock (ASC) from the clock divider (Div R 434), and then generates a modulation control signal based on the feedback signal (N_feed) and the adjusted sampling clock (ASC).

[0059] In some implementations, the clock scaling controller 420A can be configured to analyze the behavior of the feedback signal (N_feed) with adaptive clock scaling (ACS) by sampling the feedback signal using a sampling clock (SC), tracking the pulse density (PD) of the feedback signal (N_feed), and adjusting the sampling clock (SC) to adjust the modulation control signal. In some cases, if the pulse density (PD) is less than a predetermined value, the clock divider (DivR 434) increments, and the clock divider (DivR 434) decreases the sampling clock (SC) to reduce the power of the modulation control signal and reduce the output voltage (Vout). In other cases, if the pulse density (PD) is greater than a predetermined value, the clock divider (Div R 434) decrements, and the clock divider (Div R 434) increases the sampling clock (SC) to increase the power of the modulation control signal and increase the output voltage (Vout).

[0060] As reference Figure 4B As shown, the performance adjustment circuit 402B refers to a device having a power stage 110 (or voltage regulator), a delay chain stage 130, a time-to-digital converter (TDC) 140, and a clock scaling controller 420B. As described herein, the power stage 110 (or voltage regulator stage) can be configured to receive and use a modulation control signal from a modulator (MOD 122) to adjust the output voltage (Vout) provided to the load 118. Furthermore, the TDC 140 can be configured to determine a timing delay error associated with the output voltage (Vout) and provide the timing delay error as a feedback signal (N_feed) to the modulator (MOD 122).

[0061] In some implementations, the clock scaling controller 420B can be configured to receive a feedback signal (N_feed) from the TDC 140, generate a modulation control signal based on the feedback signal (N_feed) using the modulator (MOD 122), analyze the behavior of the feedback signal (N_feed) to adjust the modulation control signal, and provide the modulation control signal to the voltage regulator 110 to adjust the output voltage (Vout) provided to the load 118. Figure 4B In some embodiments, the performance adjustment circuit 402B may include an oscillator (OSC 430) that provides a sampling clock (SC) for sampling the feedback signal (N_feed). In some cases, the performance adjustment circuit 402B may include a filter circuit 440 that receives the modulation control signal, determines a pulse density (PD) of the modulation control signal, compares the pulse density (PD) with a reference value (X) to identify an error, and provides an adjustment control signal (R2) based on the error.

[0062] In some implementations, the performance adjustment circuit 402B includes a clock divider (DivR) that receives a sampling clock (SC) from an oscillator (OSC 430), receives an adjustment control signal (R2) from a filter circuit 440, adjusts the sampling clock (SC) based on a pulse density (PD), and provides an adjusted sampling clock (ASC). Furthermore, the performance adjustment circuit 402B may include a modulator (MOD 122) that receives a feedback signal (N_feed) from a TDC 140, receives the adjusted sampling clock (ASC) from a clock divider (DivR 434), and generates a modulation control signal based on the feedback signal (N_feed) and the adjusted sampling clock (ASC). The clock scaling controller 420B may be configured to analyze behavior of a feedback signal (N_feed) having a regulated control signal clock scaling (RCS) by determining a pulse density (PD) of the modulation control signal, adjusting a scaling ratio to a reference value (X), comparing the pulse density (PD) to the reference value (X) to identify an error, providing a regulated control signal (R2) based on the error, and adjusting the modulation control signal based on the regulated control signal (R2).

[0063] With reference to the clock scaling and automatic clock scaling of the DC / DC conversion performed by the regulator 110, the static power dissipated by the regulator 110 can be concentrated in the generation of the clock that feeds the TDC 140. The power switches (e.g., T1, T2) can remain in high-impedance mode until the TDC 140 measures a propagation delay that is longer than the time reference. This can occur when the output voltage (Vout) is too low, and in this case, the regulator 110 can generate a conduction mode by turning on the high-side power switch until the inductor current reaches a peak, then turning on the low-side power switch until the inductor current reaches 0A, and then finally returning to high-impedance mode.

[0064] In some implementations, the rate of drop of the output voltage (Vout) can refer to the discharge of the output capacitor (C: C_out) divided by the load current (I_load of the load 118) such that:

[0065]

[0066] The output decoupling capacitor is known in design, and a large value can help keep the ripple low, while understanding the application can maximize the load current (I_load of the load 118). On the other hand, the amount of charge absorbed by the output capacitor (C: C_out) in operating mode can be:

[0067]

[0068] The voltage regulator 110 can only implement one mode in each TDC-clock cycle, and the output current of the voltage regulator 110 can be defined as follows:

[0069]

[0070] Ipk and Tclk-Ttdc can be optimized during the design phase, as increasing Ipk increases output ripple for a given output capacitor (C:C_out) but helps reduce the TDC clock frequency. Furthermore, other considerations may necessitate maintaining the TDC clock frequency higher than the maximum output current provided. This design step can be performed for the maximum output current; however, the current may be 10 or 100 times lower than the maximum output current and may cause the TDC clock to be one or two orders of magnitude higher than necessary. In this case, the power consumption of TDC 140 may be primarily determined by the TDC operating clock and the quiescent current of the entire control circuitry. Therefore, when the load current is low, the quiescent power of the control circuitry can be reduced by reducing the TDC clock. This can result in a significant improvement in system efficiency.

[0071] Various implementations of a device are described herein. The device may include a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for use in adjusting the output voltage.

[0072] Various implementations of a device are described herein. The device may include a delay circuit that receives a clock signal and provides a differential timing signal. The device may include a latch circuit that, when activated, receives the differential timing signal from the delay circuit and provides a pulse sense signal. The device may include a logic circuit that receives the pulse sense signal from the latch circuit and provides an output signal as a timing delay error.

[0073] Various implementations of a device are described herein. The device may include a voltage regulator that receives and uses a modulation control signal to adjust an output voltage provided to a load. The device may include a time-to-digital converter that determines a timing delay error associated with the output voltage and provides the timing delay error as a feedback signal. The device may include a clock scaling controller that receives a feedback signal from the time-to-digital converter, generates a modulation control signal based on the feedback signal, analyzes behavior of the feedback signal to adjust the modulation control signal, and provides the modulation control signal to the voltage regulator to adjust the output voltage provided to the load.

[0074] Various implementations of a method are described herein. The method may include adjusting an output voltage using a voltage regulator and a modulator. The method may include measuring a timing delay of a logic chain using a time-to-digital converter. The method may include comparing the timing delay with a reference delay to determine a timing delay error using the time-to-digital converter. The method may include providing the timing delay error to a modulator for use in adjusting the output voltage using the time-to-digital converter.

[0075] Implementations of the various techniques described herein can be implemented using a variety of general-purpose or special-purpose computing system environments or configurations. Examples of computing systems, environments, and / or configurations suitable for use with the various techniques described herein include, but are not limited to, personal computers, server computers, handheld or laptop computer devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, minicomputers, mainframe computers, smartphones, tablet computers, wearable computers, cloud computing systems, virtual computers, marine electronics, and the like.

[0076] The various techniques described herein can be implemented in the general context of computer-executable instructions, such as program modules executed by a computer. Program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. Furthermore, each program module can be implemented in its own way, and not all program modules need to be implemented in the same way. Although program modules can be executed on a single computing system, it should be understood that in some implementations, program modules can be implemented on independent computing systems or devices that are suitable for communicating with each other. Program modules can also be some combination of hardware and software, wherein the specific tasks performed by the program modules can be completed by hardware, software, or some combination of the two.

[0077] The various techniques described herein may be implemented in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network (e.g., by hardwired links, wireless links, or various combinations thereof). In a distributed computing environment, program modules may be located in both local and remote computer storage media, including, for example, memory storage devices and the like.

[0078] Furthermore, the discussion provided herein may be viewed with respect to certain specific implementations. It should be understood that the discussion provided herein is intended to enable one of ordinary skill in the art to make and use any subject matter defined herein by the subject matter of the claims.

[0079] It is intended that the subject matter of the claims is not limited to the specific implementations and illustrations provided herein, but rather includes modifications of those implementations according to the claims, including portions of implementations and combinations of elements of different implementations. It should be understood that in the development of any such implementation, as in any engineering or design project, many implementation-specific decisions should be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Furthermore, it should be understood that such development work may be complex and time-consuming, but nevertheless remains a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure.

[0080] Reference has been made in detail to various specific implementations, examples of which are shown in the accompanying drawings and diagrams. In the following detailed description, many specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein can be practiced without these specific details. In some other cases, well-known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the details of the embodiments.

[0081] It should also be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The first element and the second element are each elements, but they are not considered to be the same element.

[0082] The terms used in the description of the present disclosure provided herein are for the purpose of describing specific specific implementations and are not intended to limit the disclosure provided herein. As used in the description of the disclosure provided herein and the appended claims, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. As used herein, the term "and / or" refers to and encompasses any and all possible combinations of one or more of the associated listed items. When used in this specification, the terms "comprises", "comprising" and / or "containing" specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups.

[0083] As used herein, the term "if" may be interpreted to mean "when" or "at" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined that" or "if [the condition or event] is detected" may be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the condition or event]" or "in response to detecting [the condition or event]," depending on the context. The terms "up" and "down"; "upper" and "lower"; "upward" and "downward"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some implementations of the various techniques described herein.

[0084] While the foregoing is directed to specific implementations of the various techniques described herein, other and further implementations are contemplated based on the disclosure herein, which can be determined by the appended claims.

[0085] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A performance adjustment device, comprising: a voltage regulator that uses a modulator to adjust the output voltage; a logic chain having a plurality of inverters coupled in series between a single input and a single output; as well as a time-to-digital converter that measures a timing delay of the logic chain via the single input and the single output, compares the timing delay with a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for use in adjusting the output voltage.

2. The apparatus of claim 1 , wherein the time-to-digital converter measures the timing delay of the logic chain at periodic timing intervals, and wherein the logic chain senses process variations of circuit components associated with the apparatus.

3. The apparatus of claim 1, wherein the logic chain comprises an inverter logic chain for determining performance of a load.

4. The apparatus of claim 3, wherein the voltage regulator is coupled to the load to provide and regulate a supply voltage for the load, and wherein the voltage regulator comprises a DC-DC regulator.

5. A performance adjustment device, comprising: a voltage regulator that uses a modulator to adjust the output voltage; as well as a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for use in adjusting the output voltage, wherein: If the timing delay error is greater than a predetermined interval, the time-to-digital converter provides the timing delay error to the modulator to increase the output voltage, and If the timing delay error is less than the predetermined interval, the time-to-digital converter provides the timing delay error to the modulator to reduce the output voltage.

6. A performance adjustment device, comprising: a voltage regulator that uses a modulator to adjust the output voltage; a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for use in adjusting the output voltage, wherein: The time-to-digital converter provides the timing delay error as a feedback signal to the modulator for adjusting the output voltage based on the timing delay error, and If the timing delay error is greater than a predetermined interval, the time-to-digital converter provides the feedback signal to the modulator to increase the output voltage. 7 . The apparatus of claim 6 , wherein the modulator uses combinational logic to compare the feedback signal with a reference signal and to determine a difference between the feedback signal and the reference signal.

8. A performance adjustment device, comprising: a delay circuit that receives a clock signal, receives a timing delay signal from a logic link, and provides a differential timing signal; a latch circuit that, when activated, receives the differential timing signal from the delay circuit and provides a pulsed sense signal; as well as a logic circuit that receives the pulse sense signal from the latch circuit and provides an output signal as a timing delay error, The device includes a time-to-digital converter that receives a timing delay signal from a logic link, measures a timing delay of the logic chain based on the timing delay signal, and provides the timing delay error to a modulator for adjusting an output voltage from a voltage regulator.

9. The apparatus of claim 8, wherein the output signal is used to trigger a conduction mode of the regulator when the timing delay error is positive.

10. The device according to claim 8, further comprising: a trigger circuit that receives the clock signal and activates the latch circuit by providing a timing reference signal to a power input of the latch circuit, The latch circuit has one or more latch-based sense amplifiers that, when activated, receive the differential timing signal from the delay circuit and provide the pulsed sense signal.

11. The apparatus of claim 8, wherein the delay circuit is coupled to a logic chain so as to receive a timing delay signal from the logic chain as a timing delay associated with a performance of the logic chain.

12. The apparatus of claim 11, wherein the delay circuit has a coarse delay that receives the clock signal, receives the timing delay signal, and provides a modified clock signal having a shorter pulse width.

13. The apparatus of claim 12, wherein the delay circuit has a fine delay that receives the clock signal, receives the modified clock signal having a shorter pulse width from the coarse delay, and provides the differential timing signal to the latch circuit.

14. The apparatus of claim 13, wherein the fine delay has a plurality of logic gates coupled together to receive the clock signal, receive the modified clock signal from the coarse delay, and provide the differential timing signal as a low voltage output and a high voltage output.

15. A performance adjustment device, comprising: a delay circuit that receives the clock signal and provides a differential timing signal; a latch circuit that, when activated, receives the differential timing signal from the delay circuit and provides a pulsed sense signal; as well as a logic circuit that receives the pulse sense signal from the latch circuit and provides an output signal as a timing delay error, wherein, when the clock signal is low, propagation of the clock signal through the device is blocked and the differential timing signal from the delay circuit is forced to a logic low state, The device includes a time-to-digital converter that receives a timing delay signal from a logic link, measures a timing delay of the logic chain based on the timing delay signal, and provides the timing delay error to a modulator for adjusting an output voltage from a voltage regulator.

16. A performance adjustment device, comprising: a voltage regulator that receives and uses the modulated control signal to adjust an output voltage provided to a load; as well as a time-to-digital converter that determines a timing delay error associated with the output voltage and provides the timing delay error as a feedback signal; as well as a clock scaling controller that receives the feedback signal from the time-to-digital converter, generates the modulation control signal based on the feedback signal, analyzes behavior of the feedback signal using adjusted clock scaling to adjust the modulation control signal, and provides the modulation control signal to the voltage regulator to adjust the output voltage provided to the load.

17. The apparatus of claim 16, wherein the clock scaling controller analyzes behavior of the feedback signal using adjusted clock scaling by: determining a pulse density of the modulated control signal, Adjust the scaling to the reference value, comparing the pulse density with the reference value to identify an error, providing an adjustment control signal based on the error, and The modulation control signal is adjusted based on the adjustment control signal.

18. A performance adjustment device, comprising: a voltage regulator that receives and uses the modulated control signal to adjust an output voltage provided to a load; as well as a time-to-digital converter that determines a timing delay error associated with the output voltage and provides the timing delay error as a feedback signal; as well as a clock scaling controller that receives the feedback signal from the time-to-digital converter, generates the modulation control signal based on the feedback signal, analyzes behavior of the feedback signal to adjust the modulation control signal, and provides the modulation control signal to the voltage regulator to adjust the output voltage provided to the load, wherein the clock scaling controller includes: an oscillator that provides a sampling clock for sampling the feedback signal; a logic circuit, the logic circuit receiving the modulation control signal and tracking the pulse density of the modulation control signal; a clock divider that receives the sampling clock from the oscillator, receives the pulse density from the logic circuit, adjusts the sampling clock based on the pulse density, and provides an adjusted sampling clock; and A modulator receives the feedback signal from the time-to-digital converter, receives the adjusted sampling clock from the clock divider, and generates the modulation control signal based on the feedback signal and the adjusted sampling clock.

19. A performance adjustment device, comprising: a voltage regulator that receives and uses the modulated control signal to adjust an output voltage provided to a load; as well as a time-to-digital converter that determines a timing delay error associated with the output voltage and provides the timing delay error as a feedback signal; as well as a clock scaling controller that receives the feedback signal from the time-to-digital converter, generates the modulation control signal based on the feedback signal, analyzes behavior of the feedback signal to adjust the modulation control signal, and provides the modulation control signal to the voltage regulator to adjust the output voltage provided to the load, wherein the clock scaling controller analyzes behavior of the feedback signal using adaptive clock scaling by sampling the feedback signal using a sampling clock, tracking a pulse density of the feedback signal, and adjusting the sampling clock to adjust the modulation control signal, and wherein: If the pulse density is less than a predetermined value, the clock divider increments, and the clock divider decreases the sampling clock to reduce the power of the modulated control signal and reduce the output voltage, and If the pulse density is greater than the predetermined value, the clock divider is decremented, and the clock divider increases the sampling clock to increase the power of the modulated control signal and increase the output voltage.

20. A performance adjustment device, comprising: a voltage regulator that receives and uses the modulated control signal to adjust an output voltage provided to a load; as well as a time-to-digital converter that determines a timing delay error associated with the output voltage and provides the timing delay error as a feedback signal; as well as a clock scaling controller that receives the feedback signal from the time-to-digital converter, generates the modulation control signal based on the feedback signal, analyzes behavior of the feedback signal to adjust the modulation control signal, and provides the modulation control signal to the voltage regulator to adjust the output voltage provided to the load, The clock scaling controller comprises: an oscillator, the oscillator providing a sampling clock for sampling the feedback signal; a filter circuit that receives the modulated control signal, determines a pulse density of the modulated control signal, compares the pulse density to a reference value to identify an error, and provides an adjustment control signal based on the error; a clock divider that receives the sampling clock from the oscillator, receives the adjustment control signal from the filter circuit, adjusts the sampling clock based on the pulse density, and provides an adjusted sampling clock; and A modulator receives the feedback signal from the time-to-digital converter, receives the adjusted sampling clock from the clock divider, and generates the modulation control signal based on the feedback signal and the adjusted sampling clock.

21. A method for regulating performance, the method comprising: Adjust the output voltage using a voltage regulator and modulator; measuring a timing delay of a logic chain with a time-to-digital converter, wherein the logic chain has a plurality of inverters coupled in series between a single input and a single output, and wherein the timing delay of the logic chain is measured by the time-to-digital converter via the single input and the single output; comparing the timing delay to a reference delay to determine a timing delay error using the time-to-digital converter; and The timing delay error is provided to the modulator for use in adjusting the output voltage with the time-to-digital converter.

22. The method of claim 21, wherein the time-to-digital converter measures the timing delay of the logic chain at periodic timing intervals, and wherein the logic chain senses process variations of circuit components associated with a device.

23. The method of claim 21, wherein the logic chain comprises an inverter logic chain for determining performance of a load, and wherein the voltage regulator is coupled to the load to provide and regulate a supply voltage for the load.

24. A method for regulating performance, the method comprising: Adjust the output voltage using a voltage regulator and modulator; Measuring timing delays in logic chains using time-to-digital converters, comparing the timing delay to a reference delay to determine a timing delay error using the time-to-digital converter; and providing the timing delay error to the modulator for use in adjusting the output voltage using the time-to-digital converter, wherein: If the timing delay error is greater than a predetermined interval, the time-to-digital converter provides the timing delay error to the modulator to increase the output voltage, and If the timing delay error is less than the predetermined interval, the time-to-digital converter provides the timing delay error to the modulator to reduce the output voltage.

25. A method for regulating performance, the method comprising: Adjust the output voltage using a voltage regulator and modulator; Measuring timing delays in logic chains using time-to-digital converters, comparing the timing delay to a reference delay to determine a timing delay error using the time-to-digital converter; and Providing the timing delay error to the modulator for use in adjusting the output voltage using the time-to-digital converter wherein the time-to-digital converter provides the timing delay error as a feedback signal to the modulator for adjusting the output voltage based on the timing delay error, and The modulator uses combinational logic components to compare the feedback signal with a reference signal and determine a difference between the feedback signal and the reference signal.

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