A program configuration method supporting heterogeneous multi-processor architecture

Abstract

A program configuration method supporting heterogeneous multi-processor architecture includes the following steps: storing two CPU programs and two DSP programs in a NOR-flash memory, both of which are isomorphic backups; storing one CPU program and one DSP program in an EEPROM memory; heterogeneous fault tolerance with the stored programs in NOR-flash; the configuration parameters of program management are stored in the EEPROM, and a bit-by-bit triple-module redundant storage structure is adopted; the CPU is used as the main control processor and the DSP is used as a coprocessor, and the CPU performs unified management of the program. The CPU loads the programs of the CPU and DSP according to the configuration parameter requirements and starts the multi-processor operation; when the configuration parameters are modified on-orbit, the CPU resets the CPU and DSP, stops the original program operation, and loads the program according to the new configuration parameter requirements, restarts the multi-processor operation, and completes the on-orbit update operation of the program.

Description

Technical Field

[0001] The invention relates to a program configuration method supporting a heterogeneous multi-processor architecture, and belongs to the technical field of satellite-borne computers. Background Art

[0002] my country's first Mars exploration achieved the goal of "orbiting, landing, and patrolling" Mars through a flight mission. The lander and rover "Zhurong" Mars rover broke through key technologies such as Mars surface patrol and long-term autonomous management. The navigation control unit of the Mars rover GNC subsystem, as the data processing core of the system, adopts a heterogeneous multi-processor high-performance computing architecture of CPU+DSP. Therefore, in order to successfully complete functions such as environmental perception, autonomous planning, posture determination, and motion control, the system must have a management mechanism that supports efficient and reliable operation of heterogeneous multi-processor programs, so that the Mars rover can achieve long-distance safe driving in the complex and unknown surface environment of Mars. Summary of the invention

[0003] The technical problem to be solved by the present invention is: to overcome the shortcomings of the prior art and provide a program configuration method that supports a heterogeneous multi-processor architecture, thereby ensuring the efficient and reliable operation of the Mars rover navigation control unit by adopting measures such as heterogeneous storage backup, on-orbit configuration program loading strategy, and unified management of multi-processor programs.

[0004] The purpose of the present invention is achieved through the following technical solutions:

[0005] A program configuration method supporting a heterogeneous multi-processor architecture adopts a CPU+DSP heterogeneous multi-processor architecture, comprising the following steps:

[0006] In the NOR-flash memory, two CPU programs and two DSP programs are stored. The two CPU programs have the same content, independent storage space, and are isomorphic backups of each other. The two DSP programs have the same content, independent storage space, and are isomorphic backups of each other.

[0007] In the EEPROM memory, a CPU program is stored and a DSP program is stored; the program stored in the EEPROM has the same function as the program stored in the NOR-flash, realizing heterogeneous fault tolerance of program codes;

[0008] The configuration parameters of program management are stored in EEPROM, using a bit-by-bit triple-module redundant storage structure;

[0009] In the configuration parameters, set the CPU program content consistency flag in NOR-flash and EEPROM, the DSP program content consistency flag in NOR-flash and EEPROM, the CPU program loading strategy flag, and the DSP program loading strategy flag;

[0010] The CPU is the main processor and the DSP is the coprocessor. The CPU manages the programs uniformly. The CPU loads the programs of the CPU and DSP according to the configuration parameter requirements and starts the multi-processor operation.

[0011] When the configuration parameters are modified in-orbit, the CPU resets the CPU and DSP, stops the original program, loads the program according to the new configuration parameter requirements, restarts the multi-processor operation, and completes the in-orbit update operation of the program.

[0012] Preferably, the CPU program content consistency identifier in NOR-flash and EEPROM has a value of 0xeb90146f or 0x00000000; the value 0xeb90146f indicates that the CPU program content in NOR-flash and EEPROM is consistent, belonging to heterogeneous storage and homogeneous backup; the value 0x00000000 indicates that the CPU program content in NOR-flash and EEPROM is inconsistent, belonging to heterogeneous storage and heterogeneous backup;

[0013] The consistency flag value of the DSP program content in NOR-flash and EEPROM is 0xeb90146f or 0x00000000. The value 0xeb90146f indicates that the DSP program content in NOR-flash and EEPROM is consistent, which belongs to heterogeneous storage and homogeneous backup; the value 0x00000000 indicates that the DSP program content in NOR-flash and EEPROM is inconsistent, which belongs to heterogeneous storage and heterogeneous backup;

[0014] The value of the CPU program loading strategy identifier is 0xeb90146f or 0x00000000. The value 0xeb90146f indicates that the CPU program in NOR-flash is loaded; the value 0x00000000 indicates that the CPU program in EEPROM is loaded;

[0015] The DSP program loading strategy identifier has a value of 0xeb90146f or 0x00000000; the value 0xeb90146f indicates loading the DSP program in NOR-flash; the value 0x00000000 indicates loading the DSP program in EEPROM.

[0016] Preferably, the configuration parameters of program management also include: 1) the starting storage address of the first CPU program in NOR-flash; 2) the starting storage address of the second CPU program in NOR-flash; 3) the number of bytes of the CPU program in NOR-flash; 4) the starting storage address of the first DSP program in NOR-flash; 5) the starting storage address of the second DSP program in NOR-flash; 6) the number of bytes of the DSP program in NOR-flash; 7) the starting storage address of the CPU program in EEPROM; 8) the number of bytes of the CPU program in EEPROM; 9) the starting storage address of the DSP program in EEPROM; 10) the number of bytes of the DSP program in EEPROM.

[0017] Preferably, the configuration parameters of the program management are modified in an on-track modification manner.

[0018] Preferably, the configuration parameters of the program management are stored in the EEPROM and are kept spatially isolated from the programs stored in the EEPROM.

[0019] Preferably,

[0020] When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "CPU program loading strategy identifier" is set to 0xeb90146f, the program will be loaded from the address of the first CPU program stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the address of the second CPU program stored in NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the address of the CPU program stored in EEPROM until all programs are loaded;

[0021] When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "CPU program loading strategy identifier" is set to 0x00000000, the program will be loaded from the CPU program address stored in the EEPROM; if data errors occur during the loading process, the program will continue to be loaded from the first CPU program address stored in the NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the second CPU program address stored in the NOR-flash until all programs are loaded;

[0022] When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency flag in NOR-flash and EEPROM" is set to 0x00000000, and the configuration parameter "CPU program loading strategy flag" is set to 0xeb90146f, the program will be loaded from the first CPU program address stored in NOR-flash; if a data error occurs during the loading process, the program will continue to be loaded from the second CPU program address stored in NOR-flash until all programs are loaded;

[0023] When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency flag in NOR-flash, EEPROM" is set to 0x00000000, and the configuration parameter "CPU program loading strategy flag" is set to 0x00000000, the program will be loaded from the CPU program address stored in the EEPROM until all programs are loaded;

[0024] When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f, and the configuration parameter "DSP program loading strategy identifier" is set to 0xeb90146f, the program will be loaded from the first DSP program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second DSP program address stored in NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the DSP program address stored in EEPROM until all programs are loaded;

[0025] When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f, and the configuration parameter "DSP program loading strategy identifier" is set to 0x00000000, the program will be loaded from the DSP program address stored in the EEPROM; if data errors occur during the loading process, the program will continue to be loaded from the first DSP program address stored in the NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the second DSP program address stored in the NOR-flash until all programs are loaded;

[0026] When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency flag in NOR-flash and EEPROM" is set to 0x00000000, and the configuration parameter "DSP program loading strategy flag" is set to 0xeb90146f, the program will be loaded from the first DSP program address stored in NOR-flash; if a data error occurs during the loading process, the program will continue to be loaded from the second DSP program address stored in NOR-flash until all programs are loaded;

[0027] When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash, EEPROM" is 0x00000000, and the configuration parameter "DSP program loading strategy identifier" is 0x00000000, the program will be loaded from the DSP program address stored in the EEPROM until all programs are loaded.

[0028] A heterogeneous multi-processor architecture uses the above program configuration method to perform program configuration.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) The present invention supports the system's access to two types of memories, NOR-flash and EEPROM, to achieve heterogeneous redundant backup of program storage and improve program storage reliability;

[0031] (2) The present invention supports both homogeneous and heterogeneous backup of program content, thus improving program function reliability;

[0032] (3) The present invention supports program management strategies for on-orbit configuration, improving system operation flexibility;

[0033] (4) The program configuration parameters of the present invention adopt bit-by-bit triple-module redundancy to support bit-level fault tolerance;

[0034] (5) The storage location and size of the program of the present invention can be changed dynamically. When part of the storage space becomes invalid, the program can be stored in the remaining valid space, thereby improving the maintainability of the system;

[0035] (6) The present invention supports unified management of multi-processor programs and improves the usability of heterogeneous multi-processor systems;

[0036] (7) Under the unified configuration framework of the present invention, different processors can be configured with different management strategies to adapt to the operation of programs of different critical levels. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the configuration of the method of the present invention. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0039] A program configuration method supporting heterogeneous multi-processor architecture, that is, a program management method supporting heterogeneous multi-processor architecture, such as Figure 1 As shown, the specific implementation is as follows:

[0040] 1. The system uses NOR-flash and EEPROM memories to store CPU and DSP programs, realizing heterogeneous redundant backup of program storage;

[0041] 2. Two CPU programs and two DSP programs are stored in the NOR-flash memory. The two CPU programs have the same content, independent storage space, and are isomorphic backups of each other; the two DSP programs also have the same content, independent storage space, and are isomorphic backups of each other;

[0042] 3. In the EEPROM memory, store a CPU program and a DSP program. The program in the EEPROM has the same function as the program in the NOR-flash, achieving heterogeneous fault tolerance of the program code;

[0043] 4. The configuration parameters of program management are stored in EEPROM, using a triple-module redundant storage structure to maintain spatial isolation from the programs in EEPROM;

[0044] 5. The configuration parameters of program management include: 1) the starting storage address of the first CPU program in NOR-flash; 2) the starting storage address of the second CPU program in NOR-flash; 3) the number of bytes of the CPU program in NOR-flash; 4) the starting storage address of the first DSP program in NOR-flash; 5) the starting storage address of the second DSP program in NOR-flash; 6) the number of bytes of the DSP program in NOR-flash; 7) the starting storage address of the CPU program in EEPROM; 8) the number of bytes of the CPU program in EEPROM; 9) the starting storage address of the DSP program in EEPROM; 10) the number of bytes of the DSP program in EEPROM; 11) the CPU program content consistency mark in NOR-flash and EEPROM; 12) the DSP program content consistency mark in NOR-flash and EEPROM; 13) the CPU program loading strategy mark; 14) the DSP program loading strategy mark;

[0045] 6. The value of "CPU program content consistency flag in NOR-flash and EEPROM" in the configuration parameters is 0xeb90146f or 0x00000000. The value 0xeb90146f indicates that the CPU program content in NOR-flash and EEPROM is consistent, which belongs to heterogeneous storage and homogeneous backup; the value 0x00000000 indicates that the CPU program content in NOR-flash and EEPROM is inconsistent, which belongs to heterogeneous storage and heterogeneous backup;

[0046] 7. The value of "Consistency flag of DSP program content in NOR-flash and EEPROM" in the configuration parameters is 0xeb90146f or 0x00000000. The value 0xeb90146f indicates that the DSP program content in NOR-flash and EEPROM is consistent, belonging to heterogeneous storage and homogeneous backup; the value 0x00000000 indicates that the DSP program content in NOR-flash and EEPROM is inconsistent, belonging to heterogeneous storage and heterogeneous backup;

[0047] 8. The value of "CPU program loading strategy identification" in the configuration parameters is 0xeb90146f or 0x00000000. The value 0xeb90146f means loading the CPU program in NOR-flash; the value 0x00000000 means loading the CPU program in EEPROM;

[0048] 9. The value of "DSP program loading strategy identification" in the configuration parameters is 0xeb90146f or 0x00000000. The value 0xeb90146f means loading the DSP program in NOR-flash; the value 0x00000000 means loading the DSP program in EEPROM;

[0049] 10. Configuration parameters can be modified on-orbit, supporting efficient and flexible management of programs;

[0050] 11. In the CPU+DSP heterogeneous multi-processor high-performance computing architecture, the CPU is the main processor and the DSP is the coprocessor. The CPU is responsible for unified management of the program. The CPU is responsible for loading the CPU and DSP programs according to the configuration parameter requirements and starting the multi-processor operation;

[0051] 12. When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "CPU program loading strategy identifier" is set to 0xeb90146f, the program will be loaded from the first CPU program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second CPU program address stored in NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the CPU program address stored in EEPROM until all programs are loaded;

[0052] 13. When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "CPU program loading strategy identifier" is set to 0x00000000, the program will be loaded from the CPU program address stored in the EEPROM; if a data error occurs during the loading process, the program will continue to be loaded from the first CPU program address stored in the NOR-flash; if a data error occurs again during the loading process, the program will continue to be loaded from the second CPU program address stored in the NOR-flash until all programs are loaded;

[0053] 14. When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is 0x00000000, and the configuration parameter "CPU program loading strategy identifier" is 0xeb90146f, the program will be loaded from the first CPU program address stored in NOR-flash; if the data is wrong during the loading process, the program will continue to be loaded from the second CPU program address stored in NOR-flash until all programs are loaded;

[0054] 15. When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is 0x00000000, and the configuration parameter "CPU program loading strategy identifier" is 0x00000000, the program will be loaded from the CPU program address stored in the EEPROM until all programs are loaded;

[0055] 16. When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "DSP program loading strategy identifier" is set to 0xeb90146f, the program will be loaded from the first DSP program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second DSP program address stored in NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the DSP program address stored in EEPROM until all programs are loaded;

[0056] 17. When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "DSP program loading strategy identifier" is set to 0x00000000, the program will be loaded from the DSP program address stored in the EEPROM; if a data error occurs during the loading process, the program will continue to be loaded from the first DSP program address stored in the NOR-flash; if a data error occurs again during the loading process, the program will continue to be loaded from the second DSP program address stored in the NOR-flash until all programs are loaded;

[0057] 18. When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency flag in NOR-flash and EEPROM" is 0x00000000, and the configuration parameter "DSP program loading strategy flag" is 0xeb90146f, the program will be loaded from the first DSP program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second DSP program address stored in NOR-flash until all programs are loaded;

[0058] 19. When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency flag in NOR-flash and EEPROM" is 0x00000000, and the configuration parameter "DSP program loading strategy flag" is 0x00000000, the program will be loaded from the DSP program address stored in the EEPROM until all programs are loaded;

[0059] 20. When the configuration parameters are modified in orbit, the CPU can reset itself and the DSP processor, stop the original program, load the program according to the new configuration parameters, restart the multi-processor operation, and realize the in-orbit update of the program.

[0060] In summary, the use of a heterogeneous multi-processor high-performance computing architecture is an effective technical approach to improve the performance of spacecraft information processing systems, meet the needs of spacecraft informatization, autonomy, and intelligence, and especially the on-orbit information fusion and processing capabilities of deep space probes. Therefore, in order to achieve reliable on-orbit operation of spacecraft, the system must have a management mechanism that supports efficient and reliable operation of heterogeneous multi-processor programs. The present invention proposes an efficient program management method that supports a heterogeneous multi-processor architecture, which adopts heterogeneous storage backup, on-orbit configuration program loading strategy, and unified management of multi-processor programs. It can be well suited to the high-reliability operation requirements of spacecraft that adopt a heterogeneous multi-processor high-performance computing architecture, and has a broad application prospect.

[0061] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0062] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A program configuration method supporting a heterogeneous multi-processor architecture, characterized in that: The heterogeneous multi-processor architecture of CPU+DSP is adopted, including the following steps: In the NOR-flash memory, two CPU programs and two DSP programs are stored. The two CPU programs have the same content, independent storage space, and are isomorphic backups of each other. The two DSP programs have the same content, independent storage space, and are isomorphic backups of each other. In the EEPROM memory, a CPU program is stored and a DSP program is stored; the program stored in the EEPROM has the same function as the program stored in the NOR-flash, realizing heterogeneous fault tolerance of program codes; The configuration parameters of program management are stored in EEPROM, using a bit-by-bit triple-module redundant storage structure; In the configuration parameters, set the CPU program content consistency flag in NOR-flash and EEPROM, the DSP program content consistency flag in NOR-flash and EEPROM, the CPU program loading strategy flag, and the DSP program loading strategy flag; The CPU is used as the main processor and the DSP is used as the coprocessor. The CPU manages the programs uniformly. The CPU loads the programs of the CPU and DSP according to the configuration parameter requirements and starts the multi-processor operation. When the configuration parameters are modified in-orbit, the CPU resets the CPU and DSP, stops the original program, loads the program according to the new configuration parameter requirements, restarts the multi-processor operation, and completes the in-orbit update operation of the program.

2. The program configuration method according to claim 1, characterized in that: The consistency flag value of the CPU program content in NOR-flash and EEPROM is 0xeb90146f or 0x00000000; the value 0xeb90146f indicates that the CPU program content in NOR-flash and EEPROM is consistent, belonging to heterogeneous storage and homogeneous backup; the value 0x00000000 indicates that the CPU program content in NOR-flash and EEPROM is inconsistent, belonging to heterogeneous storage and heterogeneous backup; The consistency flag value of the DSP program content in NOR-flash and EEPROM is 0xeb90146f or 0x00000000. The value 0xeb90146f indicates that the DSP program content in NOR-flash and EEPROM is consistent, which belongs to heterogeneous storage and homogeneous backup; the value 0x00000000 indicates that the DSP program content in NOR-flash and EEPROM is inconsistent, which belongs to heterogeneous storage and heterogeneous backup; The CPU program loading strategy identifier value is 0xeb90146f or 0x00000000. The value 0xeb90146f indicates loading the CPU program in NOR-flash; the value 0x00000000 indicates loading the CPU program in EEPROM. The DSP program loading strategy identifier has a value of 0xeb90146f or 0x00000000; the value 0xeb90146f indicates loading the DSP program in NOR-flash; the value 0x00000000 indicates loading the DSP program in EEPROM.

3. The program configuration method according to claim 1, characterized in that: The configuration parameters of program management also include: 1) the starting storage address of the first CPU program in NOR-flash; 2) the starting storage address of the second CPU program in NOR-flash; 3) the number of bytes of the CPU program in NOR-flash; 4) the starting storage address of the first DSP program in NOR-flash; 5) the starting storage address of the second DSP program in NOR-flash; 6) the number of bytes of the DSP program in NOR-flash; 7) the starting storage address of the CPU program in EEPROM; 8) the number of bytes of the CPU program in EEPROM; 9) the starting storage address of the DSP program in EEPROM; 10) the number of bytes of the DSP program in EEPROM.

4. The program configuration method according to claim 1, characterized in that: The configuration parameters of program management are modified in-orbit.

5. The program configuration method according to claim 1, characterized in that: Configuration parameters for program management are stored in EEPROM, keeping them spatially isolated from the programs stored in EEPROM.

6. The program configuration method according to claim 2, characterized in that: When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "CPU program loading strategy identifier" is set to 0xeb90146f, the program will be loaded from the first CPU program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second CPU program address stored in NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the CPU program address stored in EEPROM until all programs are loaded; When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f, and the configuration parameter "CPU program loading strategy identifier" is set to 0x00000000, the program will be loaded from the CPU program address stored in the EEPROM; if data errors occur during the loading process, the program will continue to be loaded from the first CPU program address stored in the NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the second CPU program address stored in the NOR-flash until all programs are loaded; When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency flag in NOR-flash and EEPROM" is 0x00000000, and the configuration parameter "CPU program loading strategy flag" is 0xeb90146f, the program will be loaded from the first CPU program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second CPU program address stored in NOR-flash until all programs are loaded; When the CPU loads the CPU program according to the configuration parameters, if the configuration parameter "CPU program content consistency flag in NOR-flash, EEPROM" is set to 0x00000000, and the configuration parameter "CPU program loading strategy flag" is set to 0x00000000, the program will be loaded from the CPU program address stored in the EEPROM until all programs are loaded; When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f, and the configuration parameter "DSP program loading strategy identifier" is set to 0xeb90146f, the program will be loaded from the first DSP program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second DSP program address stored in NOR-flash; if data errors occur again during the loading process, the program will continue to be loaded from the DSP program address stored in EEPROM until all programs are loaded; When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash and EEPROM" is set to 0xeb90146f and the configuration parameter "DSP program loading strategy identifier" is set to 0x00000000, the program will be loaded from the DSP program address stored in the EEPROM. If data error occurs during loading, the program will continue to be loaded from the first DSP program address stored in NOR-flash; if data error occurs again during loading, the program will continue to be loaded from the second DSP program address stored in NOR-flash until all programs are loaded; When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency flag in NOR-flash and EEPROM" is set to 0x00000000, and the configuration parameter "DSP program loading strategy flag" is set to 0xeb90146f, the program will be loaded from the first DSP program address stored in NOR-flash; if data errors occur during the loading process, the program will continue to be loaded from the second DSP program address stored in NOR-flash until all programs are loaded; When the CPU loads the DSP program according to the configuration parameters, if the configuration parameter "DSP program content consistency identifier in NOR-flash, EEPROM" is 0x00000000, and the configuration parameter "DSP program loading strategy identifier" is 0x00000000, the program will be loaded from the DSP program address stored in the EEPROM until all programs are loaded.

7. A heterogeneous multi-processor architecture, characterized in that: The program configuration is performed using the program configuration method described in any one of claims 1 to 6.

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