Adaptive Address Tracking

Abstract

This application relates to adaptive address tracking. The described devices and methods track access metadata related to activity within a corresponding address range. The access metadata can be used to inform prefetch operations within the corresponding address range. The prefetch operations can involve deriving access patterns from the access metadata covering the corresponding range. However, for accurate pattern detection, the appropriate address range size can vary significantly between different regions of the address space, especially based on the workload generated by the programs utilizing the regions. Advantageously, the described devices and methods can adapt the address range covered by the access metadata to improve prefetch performance.

Description

[0001] Cross - Reference to Related Applications

[0002] This application is a continuation application of U.S. Patent Application No. 16 / 928,932, filed on July 14, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to adaptive address tracking. Background Art

[0004] To operate efficiently, some computing systems include hierarchical memory systems, which may include multiple levels of memory. Here, efficient operation means cost efficiency and speed efficiency. Faster memories are generally more expensive than relatively slower memories, so designers attempt to balance their relative costs and benefits. One approach is to use a smaller amount of faster memory and a larger amount of slower memory. Faster memories are deployed at higher levels in the hierarchical memory system compared to slower memories, such that access to the faster memories is prioritized. Examples of relatively fast memories are referred to as cache memories. Examples of relatively slow memories are backing memories, which may include main memory, main memory, backing memory, etc.

[0005] A cache memory can accelerate data operations by storing and retrieving data from a backing memory using, for example, high-performance memory cells. The high-performance memory cells enable the cache memory to respond to memory requests faster than the backing memory. Thus, the cache memory can achieve a faster response from the memory system based on the desired data present in the cache. One way to increase the likelihood that the desired data is present in the cache is to prefetch data before it is requested. To this end, a prefetching system attempts to predict which data the processor will request and then loads the predicted data into the cache. Although the prefetching system can make it more likely that the cache memory will accelerate memory access operations, data prefetching can introduce operational complexities that engineers and other computer designers strive to overcome. Summary of the Invention

[0006] In one aspect, this application provides a method that includes: representing an address range of a memory address space by nodes within multiple layers of a data structure, each of the multiple layers of the data structure corresponding to an address range size among multiple address range sizes; maintaining access metadata within an entry of a data set, each entry of the data set being associated with a corresponding node of the data structure and covering the address range represented by the associated node; modifying the data structure at least in part based on one or more metrics related to prefetch performance; and updating at least one address range covered by at least one of the entries of the data set in response to modifying the data structure.

[0007] In another aspect, the present application further provides a device, comprising: a memory; an interface configured to receive an indication of a command involving an address of a memory address space; and a logic coupled to the memory and the interface, the logic being configured to: maintain a data structure in the memory, the data structure being configured to represent an address range of the memory address space through nodes in a plurality of layers of the data structure, each of the plurality of layers corresponding to an address range size among a plurality of address range sizes; in response to an indication to store access metadata in the memory, store the access metadata in an entry of a data set, each entry of the data set being associated with a corresponding node of the data structure and covering the address range represented by the associated node; modify the data structure at least in part based on at least one metric related to prefetch performance within one or more of the address ranges represented by the data structure; and in response to a modification of the data structure, update at least one address range covered by at least one of the entries of the data set.

[0008] In yet another aspect, the present application further provides a system, comprising: means for representing an address range of a memory address space through nodes in a plurality of layers of a data structure maintained in a memory, each of the plurality of layers of the data structure corresponding to an address range size among a plurality of address range sizes; means for maintaining access metadata in the memory, maintaining the access metadata in an entry of a data set, each entry of the data set being associated with a corresponding node of the data structure and covering the address range represented by the associated node; means for modifying the data structure at least in part based on at least one metric related to prefetch performance; and means for updating at least one address range covered by at least one of the entries of the data set in response to a modification of the data structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Details of one or more aspects of adaptive address tracking are described herein with reference to the following drawings. The same reference numerals are used throughout the drawings to denote the same features and components:

[0010] Figure 1 - 1 An example device in which adaptive address tracking can be implemented is illustrated.

[0011] Figure 1 - 2 A further example of a device in which adaptive address tracking can be implemented is illustrated.

[0012] Figure 2 An example device for implementing adaptive address tracking is illustrated.

[0013] Figure 3 An example of a device and a data structure for implementing adaptive address tracking is illustrated.

[0014] Figure 4Illustrates further examples of devices and data structures for implementing adaptive address tracking.

[0015] Figure 5 - 1 Illustrates further examples of devices and data structures for implementing adaptive address tracking.

[0016] Figures 5 - 2 to 5 - 9 Illustrates example techniques for managing address ranges in various adaptive address tracking implementations.

[0017] Figure 6 Illustrates another example device that can implement adaptive address tracking.

[0018] Figure 7 Illustrates another example device that can implement adaptive address tracking.

[0019] Figure 8 Illustrates an example cache memory that can implement adaptive address tracking.

[0020] Figure 9 and 10 Illustrates an example flowchart depicting operations for adaptive address tracking.

[0021] Figure 11 Illustrates an example flowchart depicting operations for modifying the address range and / or the size of the address range covered by access metadata of an adaptive tracking engine.

[0022] Figure 12 - 1 and 12-2 Illustrates an example flowchart depicting operations for reducing the size of the address range covered by an adaptive tracking engine within access metadata.

[0023] Figure 13 - 1 and 13-2 Illustrates an example flowchart depicting operations for increasing the size of the address range covered by an adaptive tracking engine within access metadata.

[0024] Figure 14 Illustrates an example flowchart depicting operations for merging related access metadata entries of an adaptive tracking engine.

[0025] Figure 15 Illustrates an example flowchart depicting operations for adaptive address tracking.

[0026] Figure 16 Illustrates an example flowchart depicting operations for adapting the size of the address range covered by access metadata to improve prefetch performance.

[0027] Figure 17 Illustrates an example of a system for implementing adaptive address tracking.

[0028] Figure 18 Another example of a system for implementing adaptive address tracking is illustrated. Detailed implementation

[0029] Overview

[0030] Advances in semiconductor processing technology and microarchitecture have led to a significant reduction in processor cycle time and an increase in processor density. At the same time, advances in memory technology have led to an increase in memory density, but the reduction in memory access time has been relatively small. As a result, the memory latency measured in processor clock cycles has been increasing. However, a cache can help bridge the processor-memory latency gap. A cache that can store data from a backing memory can service requests faster than the backing memory. In some aspects, a cache can be deployed "above" or "in front of" the backing memory in the memory hierarchy, such that the cache is preferably accessed before accessing the slower backing memory.

[0031] Particularly due to cost considerations, a cache may have a lower capacity than the backing memory. Thus, a cache can load a selected subset of the address space of the backing memory. According to appropriate criteria, such as cache admission policies, eviction policies, replacement policies, etc., data can be selectively admitted and / or evicted from the cache.

[0032] During operation, data can be loaded into the cache in response to a "cache miss". A cache miss refers to a request related to an address that is not loaded into the cache and / or not included in the working set. Cache misses can significantly degrade performance. Maintaining cache misses may involve fetching data from the backing memory. In contrast, servicing a request that results in a "cache hit" may involve accessing the relatively high-performance cache without incurring the latency of accessing the relatively low-performance backing memory.

[0033] Cache performance can be enhanced through prefetching. Prefetching involves loading addresses from the backing memory into the working set of the cache before the requested address. A prefetcher can predict the address of an upcoming request especially based on previously requested addresses. The predicted addresses can be loaded into the cache in a background operation such that when a request for a predicted address is subsequently received, the request can be serviced from the cache without causing a cache miss. In other words, the relatively high-performance cache can be used to service requests for prefetched addresses without incurring the latency of the relatively low-performance backing memory. In some aspects, prefetching can be implemented by using idle resources. For example, when resources are needed to service incoming requests, prefetching can be terminated or paused, and prefetching can be restarted or resumed when resources are available.

[0034] The benefits of prefetching, or "prefetch utility", can be quantified according to "useful prefetching" or the ratio of useful prefetching to "bad" prefetching. As used herein, "useful" or "accurate" prefetching refers to the prefetching of addresses that result in subsequent cache hits. Useful or accurate prefetching can be the result of useful or accurate address prediction by a prefetcher. In contrast, "bad" prefetching refers to the prefetching of addresses that are not accessed before being evicted from the cache (e.g., do not result in subsequent cache hits). Bad prefetching can have an adverse effect on performance. Bad prefetching can consume limited cache memory resources with addresses that are not subsequently requested, which otherwise could have been used to cache other more frequently accessed data. Thus, inaccurate address prediction can lead to increased cache miss rates, cause system thrashing, increase bandwidth consumption to / from the backing store, etc.

[0035] Some prefetcher attempts to avoid these problems by trying to detect patterns in which memory is accessed and then prefetching data based on the detected patterns. However, access patterns can vary between regions of the address space. The access pattern for accessing memory within a particular address range can depend on several factors, including but not limited to: the program's utilization of the address region, the state of the program, the processing tasks being performed by the program, the execution phase of the program, the type of data structures being accessed by the program within the region, etc. Since access patterns can vary with regions of the address space, an access pattern that produces accurate prefetching within one region of the address space can result in inaccurate address prediction in other regions. As a non-limiting example, a program running within one region of the address space can access memory according to a first pattern in which consecutively requested addresses are offset by a first increment Δ1. A program running within another region of the address space can access addresses according to a different second pattern in which consecutive requests are separated by a different second increment Δ2. Although the first pattern can produce useful prefetching within the first region, if the first pattern is used in the second region, the first pattern will likely produce poor results (and vice versa) because the addresses in the second region are offset by Δ2 rather than Δ1.

[0036] Prefetch performance can be improved by tracking access metadata within various regions of an address space. The access metadata can include information about memory accesses within the corresponding regions, such as the sequence of previously requested addresses, address offsets, how many accesses have occurred within a given time span, etc., which can be used to determine the access patterns within the corresponding regions. These access patterns can be used to prefetch data that is likely to be requested in the near future. These regions can cover an appropriately sized address range where the pattern is consistent. For example, a region can attempt to cover the address range where a program accesses a particular type of data structure. Tracking access metadata in this way can yield access patterns specific to each region, which can then be used to determine accurate address predictions within each region.

[0037] Due to resource considerations, the number of regions in which access metadata is tracked, and the mechanism for determining the fixed size of the regions, can be limited. Examples of such resource considerations include the availability of hardware resources, memory consumption, storage consumption, computational complexity, etc. Additionally, the address space of modern computing systems can be very large, which exacerbates the resource consumption problem. The memory management systems of many modern computing systems utilize 64-bit or even larger virtual address spaces. To manage resource consumption, access metadata can be tracked within fixed-sized regions or "concentrations" that span at least part of the address space. The fixed size of the regions can be selected through online trial and error, testing, and experience, etc., because other more computationally intensive region sizing techniques may not be executable in real time and may incur unacceptable overhead. The fixed size of the tracking regions is typically set as large as possible while still yielding acceptable prefetch performance in order to manage resource consumption.

[0038] Although techniques that utilize fixed-sized regions can impose relatively low overhead, these techniques often can lead to suboptimal or even poor results because prefetch performance can be highly sensitive to the size of the address range. More specifically, good prefetch performance can depend on access metadata that covers an appropriately sized address range. The size of the fixed-sized tracking regions is sized to precisely capture the access patterns of the memory workload. For example, to accurately capture the stride access patterns within a region, the fixed size of the tracking region should roughly match the size of the data structure being accessed in that region. A region with too large a fixed size may overlap with workloads having different access patterns. Conversely, a region with too small a fixed size may not capture the full range of patterns generated under other workloads, making it difficult or even impossible to extract accurate and consistent access patterns.

[0039] In addition, workload characteristics such as data structure size can vary between programs and thus between regions, meaning that a fixed range size suitable for use in some parts of the address space may not be suitable for use in other parts (and vice versa). More specifically, a fixed range size that can precisely capture the access patterns generated by some programs may not precisely capture the access patterns generated by other programs. In addition, the workload characteristics of a program can change over time based on program state, such as execution phase, processing task, data set, etc. Although it is possible to select a fixed range size that can capture the access patterns of some programs during certain execution phases, the selected fixed range size may not precisely capture the access patterns during other execution phases, and the access patterns generated by other programs are much less. Therefore, a fixed-size region is unlikely to achieve optimal prefetcher performance and may even lead to performance degradation. Additionally, since access metadata is typically tracked at and / or within performance-sensitive components such as the memory I / O path, the overhead typically involved in managing dynamically sized address regions can lead designers away from alternatives to fixed-size techniques.

[0040] To address these and other problems, this document describes an adaptive address tracking technique that can track access metadata within a dynamically sized address region. The size of the address region in which access metadata is tracked can be adjusted to provide improved prefetcher performance with reduced overhead. In some aspects, access metadata for the address space is maintained within a set of adaptive tracking regions, each corresponding region being configured to cover a corresponding address range of the address space. The size of the address range covered by the access metadata can vary by region. Access metadata can be tracked in a set of entries, where each entry covers a specified address range. The address range (and range size) of a corresponding entry can be adjusted based on the prefetcher performance within the corresponding address region. The range size can be adjusted dynamically while ensuring that the address ranges covered by the access metadata are distinct (e.g., non-overlapping). Capturing access metadata within adaptively sized regions can achieve improved prefetch accuracy while limiting resource consumption. The access metadata maintained can be "sparse" and only cover address ranges that benefit from prefetching and are active (e.g., in use).

[0041] The described adaptive address tracking technique may also include using a range management data structure to manage the address ranges covered by access metadata. The data structure may manage a set of access metadata entries of dynamic size, which may be stored as part of a data set such that the address ranges covered by the set are different. As used herein, "different" access metadata entries refer to a set of entries that cover different, non-overlapping address ranges. The data structure may be implemented using, for example, a tree with multiple nodes. The data structure may be used to configure and dynamically adjust the address ranges through low-complexity operations that follow discriminatory constraints (e.g., constraints that make the address ranges covered by the respective access metadata entries different). The address ranges may be adjusted based on feedback (such as feedback related to prefetch performance within the respective address ranges covered by the access metadata). The address ranges may be adjusted to improve prefetch performance, reduce overhead, etc. Some of the example implementation scenarios described below relate to caches, correlation-based prefetching, machine learning-based prefetching, combinations thereof, etc.

[0042] The disclosed adaptive address tracking technique can improve cache performance. For example, consider a stride prefetching technique where an "stride pattern" is extracted using access metadata captured within a respective address range, where consecutive requested addresses are separated by a constant offset (stride S). The stride pattern can be extracted from access history metadata (e.g., the N most recently requested addresses within the respective address range). For example, access metadata covering a first region of the address space may result in a stride pattern where consecutive requests are separated by a first stride amount S1. In response to a cache miss at address a within the first region, the addresses a, a+S1, a+2S1... to a+dS1 may be prefetched into the cache, where a is the cache miss address and d is the prefetch degree. Since there are significant differences in the stride patterns between regions, a stride prefetcher can use access metadata covering each region to detect the unit stride pattern within each region. However, as disclosed herein, accurate detection of the stride pattern can depend on access metadata covering an appropriately sized address region, which can depend on the size of the data structures accessed by the program operating within each region. Thus, the appropriate address range size can vary significantly between regions. Therefore, access metadata tracked within a fixed-size region may not accurately model the stride patterns across different regions of the address space. However, the adaptive address tracking technique disclosed herein can adjust the size and / or range of the address regions within which access metadata is tracked, thereby improving the accuracy of stride pattern detection and, in turn, the utility of the stride prefetch operation.

[0043] In other instances, the adaptive address tracking techniques disclosed herein may improve other prefetch mechanisms, such as correlation prefetchers. Correlation prefetchers attempt to learn patterns that may repeat but are not as consistent as simple stride or incremental address patterns. Correlation prefetching techniques are capable of detecting cyclic incremental sequences within address sequences captured in various regions of the address space. Correlation prefetching for an incremental sequence containing two elements (Δ1, Δ2) may include prefetch addresses a+Δ1, a+Δ1+Δ2, a+2Δ1+Δ2, a+2Δ1+2Δ2, etc. (depending on the degree of correlation prefetch operation), where a is the address at which a cache miss that triggers correlation prefetching occurs. Since correlation prefetching techniques attempt to extract more complex patterns from access metadata, these techniques are even more sensitive to the size of the address range. Thus, using a fixed-size tracking region in correlation prefetching may result in poor performance due to a mismatch between the appropriate address range size within the corresponding region and the fixed range size. However, the adaptive address tracking techniques disclosed herein may be able to adjust the address range size to accurately capture correlation and / or incremental sequence patterns within different regions of the address space.

[0044] The disclosed adaptive address tracking techniques may also improve the performance of machine learning and / or machine learning (ML) prefetch implementations, such as classification-based prefetchers, artificial neural network (NN) prefetchers, recurrent NN (RNN) prefetchers, long short-term memory (LSTM) prefetchers, etc. For example, an LSTM prefetchers can be trained to model the "local context" of memory accesses within the address space (each "local context" corresponding to a corresponding address range of the address space). These types of ML prefetching techniques may attempt to exploit the local context because, as disclosed herein, data structures accessed by programs running within the corresponding local context tend to be stored in contiguous blocks that are repeatedly accessed (or in a regular pattern). An ML prefetchers can be trained to develop and / or refine an ML model within the corresponding local context, and the ML model can be used to implement prefetch operations. However, due to differences in the workloads generated by programs operating within various parts of the address space, the local context can vary significantly across the address space. For example, a local context in which a program repeatedly accesses a first type of data structure can be significantly different from other regions of the address space in which other programs may access other types of data structures according to different access patterns. Thus, an ML model trained to learn the local context within one region of the address space (and / or generated by one program) may not accurately model the local context within other regions of the address space (and / or generated by other programs).

[0045] In addition, the ML model can rely on access metadata that covers an address range of an appropriate size. The address range of the access metadata used to develop, train, or apply the ML model for a particular local context should be sized according to the size, scope, area, or extent covered by the particular local context. More specifically, the size of the address range should be sufficient to cover the particular local context without overlapping with other local contexts. Similar to the range size, the appropriate local context size can vary significantly based on the program associated with the local context, the state of the program, the execution phase, the data structures accessed within the local context, and so on. Thus, access metadata tracked within a fixed-size address range may not be suitable for use with ML techniques, let alone ML techniques that attempt to model access patterns within a variable-size local context. However, the disclosed adaptive address tracking techniques can be used to capture, maintain, and / or otherwise manage access metadata that covers address ranges corresponding to local contexts of different sizes. More specifically, the size of the address range covered by each access metadata entry can be adapted to cover each local context modeled by the ML prefetcher.

[0046] Accordingly, the techniques described for adaptive address tracking can be used with caches and other hierarchical memory systems, with different types of prefetching, with implementations that combine prefetching and caching, and so on. To this end, the memory address space of the memory system is divided into multiple address ranges. The adaptive tracking engine generates a data set that contains one or more entries, each of which covers an address range of the address space and contains access metadata for the covered address range. Instances of access metadata include information related to memory accesses within the covered address range, access statistics, access pattern statistics, access history, access sequences, access frequency metadata, access time metadata, access pattern metadata, stride patterns, correlation patterns, incremental sequences, access modeling metadata, ML modeling metadata, ML feature data, and so on.

[0047] In operation, the adaptive tracking engine can adjust the set of address ranges covered by the access metadata, which can include adjusting the size of the address ranges covered by one or more entries of the data set. To facilitate adjusting the address range size, the adaptive tracking engine can maintain a data structure. For example, the data structure can be implemented using at least one tree with multiple nodes or a multi-level map data structure. The data structure can include multiple node levels, each corresponding to a particular address range size. Nodes at relatively lower levels of the tree can correspond to relatively smaller address ranges compared to nodes at relatively higher levels of the tree. Each leaf node or node at the end of a tree branch can link or point to an associated entry of the data set. Thus, there can be a correspondence between the node level of a given node in the tree and the address range size indicated by the associated entry pointed to by the given node. The data structure can encode the parent-child relationships between the nodes, which can correspond to the inclusion relationships between the address ranges represented by the nodes. In some embodiments, each child node of a parent node represents a corresponding subset of the address range represented by the parent node.

[0048] To adjust the address range size, effective data structure operations can manipulate the nodes of the tree. For example, the operations can move a given node to a different node level corresponding to a different address range size. Such data structure operations include splitting nodes, merging nodes, etc. A node in the upper level of the data structure is split into multiple lower-level nodes, each lower-level node covering a corresponding subset of the address space covered by the upper-level node. A group of one or more nodes in the lower level of the data structure can be merged into a higher-level node, and the address range covered by the higher-level node is larger than and includes the address range covered by the group of lower-level nodes. Similar operations are performed on one or more associated entries of the data set to maintain the consistency between the nodes of the data structure and the entries of the data set. In some cases, the entries of the data set can be stored together with the nodes of the data structure. In these ways, the techniques described for adaptive address tracking facilitate using efficient storage and operation mechanisms to track metadata regarding address requests with variable granularity. The memory address range granularity can be adaptively changed during operation to accommodate or account for different programs, different program states, various data structures or data structure types, completely different prefetching strategies (e.g., related or ML-based), etc.

[0049] Example Operating Environments

[0050] Figure 1 - 1FIG. illustrates an example device 100 that can implement adaptive address tracking. Device 100 can be implemented as, for example, at least one electronic device. Example electronic device implementations include Internet of Things (IoT) device 100-1, tablet reloader 100-2, smartphone 100-3, laptop computer 100-4, desktop computer 100-5, server computer 100-6, server cluster 100-7, and so on. Other device examples include wearable devices such as smartwatches or smart glasses; entertainment devices such as set-top boxes or smart TVs; motherboards or server blades; consumer appliances; vehicles; industrial equipment; and so on. Each type of electronic device includes one or more components to provide certain computing functions or features.

[0051] In an example implementation, device 100 includes at least one host 102, at least one processor 103, at least one memory controller 104, and at least one cache 106. Device 100 may also include at least one interconnect 105 and at least one backup memory 108. Backup memory 108 may represent main memory, system memory, backup memory, combinations thereof, and so on. Backup memory 108 can be implemented with any suitable memory facility, including but not limited to: memory arrays, semiconductor memories, random access memory (RAM), dynamic RAM (DRAM) devices or modules, static RAM (SRAM) devices or modules, three-dimensional (3D) stacked DRAM devices or modules, double data rate (DDR) memories, synchronous DRAM (SDRAM) devices or modules, high bandwidth memory (HBM) devices or modules, hybrid memory cube (HMC), etc. Alternatively or additionally, backup memory 108 can be implemented with a device or module that includes storage class memory, such as solid state memory, flash memory, 3DXPoint TM memory, phase change memory (PCM), etc. Other examples of backup memory 108 are described herein. In some aspects, host 102 may further include a non-transitory storage device and / or be coupled to a non-transitory storage device, and the non-transitory storage device can be implemented with a device or module that includes any suitable non-transitory, persistent, solid state, and / or non-volatile memory.

[0052] As shown, host 102 or host device 102 may include processor 103 and / or memory controller 104. Processor 103 may be coupled to cache 106-1, and cache 106-1 may be coupled to memory controller 104. Processor 103 may also be directly or indirectly coupled to memory controller 104. Host 102 may be coupled to cache 106-2 through interconnect 105. Cache 106-2 may be coupled to backup memory 108.

[0053] The components of the depicted device 100 represent an example computing architecture having a memory hierarchy (or hierarchical memory system). For example, cache memory 106-1 can be logically coupled between processor 103 and cache memory 106-2. In addition, cache memory 106-2 can be logically coupled between processor 103 and backing memory 108. Figure 1 - 1 In the example of , cache 106-1 is at a higher memory hierarchy than cache 106-2. Similarly, cache 106-2 is at a higher memory hierarchy than backing store 108. The indicated interconnect 105 and other interconnects coupling various components may enable data to be transferred between or among the various components. Examples of interconnects include a bus, a switch fabric, one or more wires carrying voltage or current signals, and the like.

[0054] Despite Figure 1 - 1 Specific embodiments of device 100 are shown in and described herein, but device 100 may be implemented in alternative ways. For example, host 102 may include additional cache memory, including multiple levels of cache memory (e.g., multiple cache layers). In some embodiments, processor 103 may include one or more internal memories and / or cache layers, such as instruction registers, data registers, L1 cache, L2 cache, L3 cache, etc. In addition, at least one other cache memory and backup memory pair may be coupled "below" the cache memory 106-2 and backup memory 108 shown. Cache memory 106-2 and backup memory 108 can be implemented in various ways. In some cases, cache memory 106-2 and backup memory 108 are both arranged on the motherboard or physically supported by the motherboard, wherein backup memory 108 includes "main memory". In other cases, cache memory 106-2 includes DRAM and / or is implemented therefrom, and backup memory 108 includes non-temporary memory devices or modules and / or is implemented therefrom. However, these components may be implemented in alternative ways, included in distributed or shared memory systems. In addition, a given device 100 may include more, fewer or different components.

[0055] Cache memory 106-2 may be configured to speed up memory I / O by, among other things, storing the address of backing memory 108 within the relatively high performance cache memory 106-2. Figure 1 - 1In an example, cache memory 106-2 may include and / or be coupled to an adaptive tracking engine 110, which may be configured to capture, hold, track, and / or otherwise manage metadata related to accesses within a corresponding address range of an address space (access metadata 112). The access metadata 112 may include information related to any suitable address space, including but not limited to: a memory address space, a storage address space, a host address space, an input / output (I / O) address space, a storage address space, an address space of the backing memory 108, a main memory address space, a virtual memory address space, and in particular an address space managed by the processor 103, the memory controller 104, a memory management unit (MMU), etc.

[0056] The adaptive tracking engine 110 captures access metadata 112 related to a corresponding region and / or address range of an address space. The adaptive tracking engine 110 may also be configured to adapt the region and / or address range based on feedback from a consumer 115 of the access metadata 112. As used herein, a consumer 115 refers to any component, element, module, and / or process that is configured to and / or capable of utilizing and / or otherwise consuming the access metadata 112 held by the adaptive tracking engine 110, including but not limited to: the processor 103, the memory controller 104, the MMU, a cache layer, cache memories 106 (e.g., cache memories 106-1 and 106-2), cache control logic, cache prefetch logic, prefetch logic, a prefetching unit, a scheduler, an I / O scheduler, etc.

[0057] In Figure 1 - 1 an example, cache memory 106-2 is a consumer 115 of the access metadata 112 and may utilize the access metadata 112 to prefetch addresses of the backing memory 108. The adaptive tracking engine 110 may receive feedback related to prefetch performance within each region covered by the access metadata 112 and may adjust the address range covered by the access metadata 112 to improve accuracy, thereby producing a more accurate address prediction with a limited resource overhead. Thus, the adaptive tracking engine 110 may improve memory I / O performance by, in particular, enabling cache memory 106-2 to improve prefetch performance, resulting in a lower cache miss rate.

[0058] Although in Figure 1 - 1 an example, the adaptive tracking engine 110 is shown as a component of cache memory 106-2, the present disclosure is not limited thereto. In other examples, the adaptive tracking engine 110 may be coupled to any suitable consumer 115 through any suitable interconnection. In Figure 1 - 2In the illustrated example, the adaptive tracking engine 110 is coupled to the interconnect 105 of the host 102 and is configured to capture access metadata 112 by, among other things, monitoring traffic on the interconnect 105 and / or the interconnects of the memory hierarchy, including but not limited to the interconnects coupling the processor 103 to the cache memory 106-1, coupling the cache memory 106-1 to the memory controller 104, coupling the cache memory 106-2 to the backing memory 108, etc. The adaptive tracking engine 110 may provide the access metadata 112 (and / or portions thereof) to one or more consumers 115 via the interconnect 105 or other interconnects.

[0059] Example Schemes and Devices for Adaptive Address Tracking

[0060] Figure 2 An example device 200 implementing the adaptive tracking engine 110 is illustrated. The adaptive tracking engine 110 is configured to capture, hold, and / or manage access metadata 112 covering multiple regions and / or address ranges of an address space. In Figure 2 the example, the access metadata 112 is included and / or held within an access data set 210 (or data set 210). The access data set 210 includes a set of one or more access metadata entries 211 (or multiple entries 211), each entry 211 being defined to cover a corresponding address range and including access metadata 112 related to the covered address range. The data set 210 may include any number of entries 211. In Figure 2 the example, the data set 210 includes N entries 2111 through 211-N. The access data set 210 may be implemented, stored, and / or embodied in any suitable memory and / or storage resource. In Figure 2 the example, the access data set 210 is held within the memory 208. The memory 208 may be configured as an access data set 210 and / or access metadata 112 memory. The memory 208 may be implemented by a semiconductor integrated circuit, a memory array, a memory bank, a memory chip, a memory cell, DRAM, SRAM, SDRAM, on-board memory resources of the adaptive tracking engine 110, memory resources of the host device 102, main memory, cache memory 106, cache lines, backing memory 108, external memory resources, peripheral memory resources, etc. The access data set 210 may be implemented using any suitable type of structured data, including but not limited to: tables, lookup tables, mapping tables, arrays, lists, trees, prefix trees, trie trees, radix trees, etc.

[0061] As Figure 2As shown, the entry 211 of the access data set 210 includes access metadata 112 related to a specified address range. Thus, the access metadata entry 211 can be configured as a range entry 211, a tracking entry 211, a range tracking entry 211, an access metadata tracking entry 211, etc. The entry 211 can include any suitable information related to the access metadata 112, including but not limited to: range metadata 214 to specify the address range covered by the entry 211, access the metadata 112 related to the covered address range, and so on. The range metadata 214 can define the covered address range using any suitable information, including but not limited to: address boundaries, minimum and maximum address boundaries, address labels, address label boundaries, minimum and maximum address labels, base address and length, one or more tuples, etc. Thus, the address range covered by the entry 211 can be specified, defined, modified, and / or manipulated, particularly by writing one or more bits to the memory 208 (e.g., writing one or more bits to the range metadata 214 of the entry 211 held in the memory 208).

[0062] The access metadata 112 of the entry 211 can include any information related to the address range covered by the entry 211, which can include but not limited to: information related to accesses within the covered address range, access statistics, access pattern statistics, access history, access sequence, access frequency metadata, access time metadata, access pattern metadata, stride pattern, correlation pattern, incremental sequence, access modeling metadata, ML modeling metadata, ML feature data, etc.

[0063] In some instances, the adaptive tracking engine 110 includes and / or is coupled to the logic 220. The logic 220 can be configured to implement the functionality of the adaptive tracking engine 110 as disclosed herein. In Figure 2 an instance, the logic 220 is configured to and / or is configured to implement interface logic (interface 222), update logic 224, and management logic 226. The logic 220 and / or other components disclosed herein can be provided, implemented, and / or realized by logic elements, which can include but not limited to: circuits, logic circuits, control circuits, interface circuits, I / O circuits, fuse logic, analog circuits, digital circuits, logic gates, registers, switches, multiplexers, arithmetic logic units (ALUs), state machines, microprocessors, processors in memory (PIM) circuits, etc. Alternatively or additionally, in some instances, portions of the adaptive tracking engine 110, such as the logic 220, interface 222, update logic 224, management logic 226, etc., can be embodied as processor-executable instructions stored on a non-transitory storage medium. In some instances, portions of the logic 220 and / or its functions can be implemented by processing resources of a host device 102 such as the processor 103.

[0064] Interface 222 can be configured to provide access metadata 112 (and / or portions thereof) to one or more consumers 115. Interface 222 can provide access metadata 112 to consumer 115 in response to a data request. Interface 222 can receive a request for access metadata 112 related to a specified address and, in response, can return the access metadata 112 corresponding to the specified address as a response. Alternatively or additionally, interface 222 can be configured to enable consumer 115 to interact with access metadata 112. Interface 222 can provide and / or implement an application programming interface (API) and / or other lower-level interfaces through which consumer 115 retrieves access metadata 112. Interface 222 can enable consumer 115 to issue queries related to access metadata 112, such as queries for: identifying the corresponding address ranges covered by respective entries 211 of access metadata 112, determining the address ranges and / or range sizes covered by entry 211, retrieving access metadata 112 covered by a specified entry 211, retrieving access metadata 112 covering a specified address and / or address range, and the like.

[0065] Update logic 224 is configured to update, refine, and / or determine access metadata 112 in particular response to operations related to the addresses 202 covered by access metadata 112. Access metadata 112 can be updated in response to any suitable type of operation, instruction, message, command, and / or indication thereof to retrieve, modify, operate on, and / or otherwise access data (commonly referred to herein as command 201), including but not limited to: data access requests, read requests, write requests, copy requests, clone requests, trim requests, erase requests, delete requests, cache misses, cache hits, etc. In response to command 201, update logic 224 maps the address 202 (or address range) related to command 201 to entry 211 covering address 202 and updates the access metadata 112 of entry 211 accordingly (e.g., based on event type, event characteristics, event data, etc.). Update logic 224 can be configured to map address 202 to entry 211 by, in particular, comparing address 202 with the range metadata 214 of entry 211. As disclosed in more detail herein, commands 201 related to addresses 202 not mapped to the address ranges covered by access metadata 112 may result in a tracking miss.

[0066] The interface 222 of the adaptive tracking engine 110 can receive commands 201 (and / or indications of commands 201) from one or more sources 215. As used herein, source 215 refers to any suitable source of information related to commands 201 in an address space, such as processor 103, memory controller 104, MMU, interconnect 105, cache 106, prefetcher, cache prefetch logic, etc. In some aspects, the interface 222 can be configured to obtain commands 201 and / or information related to commands 201 by, in particular, monitoring traffic on the interconnect coupling components of the memory hierarchy of the host device 102, such as the interconnect coupling processor 103 to cache 106-1, cache 106-1 to memory controller 104, memory controller 104 to cache 106-2, cache 106-2 to back-up memory 108, etc. Alternatively or additionally, the interface 222 can receive information related to commands 201 captured and / or generated by other components, such as commands 201 corresponding to cache misses generated by cache 106. In some aspects, the consumer 115 can be configured as the source 215 (and vice versa). As a non-limiting example, cache 106 can be configured as both a consumer 115 and a source 215 of the adaptive tracking engine 110. The adaptive tracking engine 110 can: receive commands 201 related to the memory address space and / or indications of commands 201, such as cache misses, from cache 106, and provide access metadata 112 to cache 106 (and / or its prefetch logic).

[0067] The adaptive tracking engine 110 provides access to metadata 112 to the consumer 115 particularly through the interface 222. The consumer 115 can utilize the access to metadata 112 to perform operations within the corresponding address range covered by the access metadata 112 and can generate feedback 204 related to these operations. The feedback 204 can be configured to quantify the utility of the access metadata 112 in the operations performed by the consumer 115 within the corresponding address range. The update logic 224 can be configured to determine, update, and / or modify the utility metric 213 of the corresponding entry 211 of the access dataset 210 in response to feedback related to the access metadata 112 of the entry 211 and / or the address range covered by the entry 211. In one example, the adaptive tracking engine 110 determines the utility metric 213 based on feedback 204 from a prefetcher that is configured to perform a prefetch operation using access metadata 112 that covers the corresponding address range. The feedback 204 received from the prefetcher can quantify the prefetch utility and / or performance within the covered address range. Alternatively or additionally, the adaptive tracking engine 110 can determine the utility metric 213 at least in part based on commands 201 related to addresses 202 within the corresponding address range. The adaptive tracking engine 110 can be configured to estimate the prefetcher performance within the address range based on the frequency and / or ratio of cache hits and cache misses detected within the address range, the number of cache hits and prefetch addresses, the eviction of prefetch addresses, etc. Thus, the utility metric 213 determined for the access metadata 112 and / or the corresponding entry 211 of the access dataset 210 can quantify the prefetcher performance within the corresponding address range covered by the access metadata 112. The utility metric 213 can include any information related to prefetch performance and / or utility, including but not limited to: the number of useful prefetches determined within the corresponding address range covered by the access metadata 112, useful prefetches during individual windows, the ratio of useful prefetches to bad prefetches, the ratio of useful prefetches to bad prefetches during individual windows, the number of accurate address predictions, accurate address predictions during individual windows, the ratio of accurate address predictions to inaccurate predictions, the ratio of accurate address predictions to inaccurate address predictions during individual windows, etc.

[0068] As disclosed in more detail herein, the management logic 226 of the adaptive tracking engine 110 can be configured to adjust the address ranges covered by the access metadata 112 and / or the sizes of such ranges, particularly in accordance with the utility metrics 213 of the access metadata. In some instances, the address ranges covered by access metadata entries 211 having relatively high utility metrics 213 can be expanded, while the address ranges covered by entries 211 having relatively low utility metrics 213 can be shrunk (or removed). Access metadata entries 211 that cover adjacent address ranges and have similar utility metrics 213 can be merged, thereby reducing overhead. In some aspects, the address ranges covered by the respective access metadata entries 211 of the data set 210 and / or the range sizes can be adjusted in accordance with an adjustment policy. The adjustment policy can define thresholds and / or other criteria to trigger modifications to the set of address ranges covered by the access metadata 112, such as modifications to increase the size of one or more address ranges, decrease the size of one or more address ranges, merge one or more address ranges, split one or more address ranges, remove one or more address ranges, etc. Alternatively or additionally, the set of address ranges covered by the access metadata 112 can be adjusted in accordance with an optimization algorithm. The optimization algorithm can be configured to determine the address ranges of the respective entries 211 that produce an optimal utility metric 213 at a minimum cost, which can be quantified in terms of resource requirements, management overhead, etc.

[0069] Figure 3 An example of an apparatus 300 for implementing an adaptive address tracking and / or an adaptive tracking engine 110 as disclosed herein is illustrated. In Figure 3 an example, the access data set 210 is implemented as and / or within a range management data structure (data structure 310). The data structure 310 can define the address ranges covered by the access metadata entries 211 of the data set 210. In some aspects, the data structure 310 can implement and / or embody the access data set 210. Alternatively, and as disclosed in more detail herein, the data structure 310 and the access data set 210 can be maintained separately and / or within different memory resources.

[0070] The management logic 226 of the adaptive tracking engine 110 utilizes the data structure 310 to map, associate, correlate, and / or otherwise relate the address 202 to the address ranges covered by the respective entries 211 of the access metadata 112. The data structure 310 can be configured to represent a sparse set of address ranges of different sizes that cover a subset of the address space. The data structure 310 can implement the address ranges covered by the respective access metadata entries 211 of the data set 210 to improve accuracy and reduce overhead while ensuring uniqueness. The data structure 310 can comprise and / or be implemented by any suitable type of data management structure, including but not limited to: tables, lookup tables, mapping tables, multi-level mapping tables, trees, tries, prefix trees, radix trees, etc.

[0071] In some aspects, the management logic 226 configures the data structure 310 to define multiple address range sizes. As Figure 3 shown, the data structure 310 may include multiple layers 320, with each layer 320 corresponding to a respective one of the multiple range sizes. Nodes 311 within each layer 320 of the data structure 310 may be configured to represent an address range of a respective one of the range sizes. The layers 320 of the data structure 310 may be hierarchically organized. In some aspects, the layers 320 of the data structure 310 are arranged in a range size hierarchy (or size hierarchy), where the layer 320 corresponds to a larger address range at the top of the hierarchy, and the layer 320 corresponds to a smaller address range at a lower level of the hierarchy. In Figure 3 an example, the data structure 310 includes N layers 320, including a first or bottom layer 320-1 corresponding to the smallest or minimum address range size of the multiple range sizes, a second layer 320-2 corresponding to the next larger range size, and so on, with the last or top layer 320-N of the data structure 310 corresponding to the largest range size of the multiple address range sizes.

[0072] The adaptive tracking engine 110 may use the data structure 310 to divide the address 202 into multiple segments, including an address label 302 and a minimum offset 301. The minimum offset 301 may be defined within the least significant bit (LSB) address region. The number of bits included in the minimum offset 301 (B MO ) may determine the smallest or minimum range size of the multiple range sizes defined by the data structure 310. The minimum range size may be expressed as where S1 is the minimum range size and B MO is the number of bits included in the minimum offset 301. Thus, the minimum range size may be adjusted, in particular, by adjusting the number of bits included in the minimum offset 301.

[0073] The data structure 310 also divides the address label 302 into multiple sub-labels 304, with each sub-label 304 being assigned to a respective layer 320 of the data structure 310 and corresponding to a respective segment, portion, or region of the address label 302. The sub-labels 304 may be assigned to the layers 320 of the data structure 310 according to the range size hierarchy of the data structure 310. More specifically, the sub-labels 304 may be assigned to the respective layers 320 by range size (and / or based on the position of the individual layers 320 within the range size hierarchy). In some aspects, as shown below Figure 3 and in Table 1, the sub-labels 304 are assigned from the LSB to the most significant bit (MSB).

[0074]

[0075]

[0076] Table 1

[0077] Table 1 illustrates the partitioning of a 64-bit address by an example data structure 310 having N layers 320. The minimum range size of the example data structure 310 is set to 4K (4096 addresses) by designating the 12 LSBs of the address 202 as the minimum offset 301 and the remaining 52 MSBs as the address tag 302. The minimum range size can be set to any suitable amount. In some aspects, the minimum range size is set according to the characteristics of the address space (and / or the backing store 108). The minimum range size can be set to the memory page size (e.g., when used with a backing store 108 having 4K pages, a memory controller 104 having a 4K virtual page size, etc., the minimum range size can be set to 4K). In Table 1, the address tag 302 is further partitioned into sub-tags 304-1 through 304-N. The sub-tags 304 can be assigned to the layers 320 of the data structure 310 according to the range size hierarchy of the data structure 310. The LSB sub-tag 304-1 can be assigned to the bottommost layer 320-1 of the data structure 310, the next MSB sub-tag 304-2 can be assigned to the next higher layer 320-2 of the data structure 310, and so on, where the MSB sub-tag 304-N is assigned to the topmost layer 320-N of the data structure 310. Although the address 202 is shown and described herein with reference to a big-endian format, the present disclosure is not limited thereto and can be applied to addresses 202 in any suitable format, encoding, or endianness.

[0078] The sub-tags 304 can be used to form region tags 332 for each layer 320 of the data structure 310. The region tags 332 can be formed, in particular, by traversing the layers 320 of the data structure 310 from the top of the hierarchy (layer 320-N) to the lower layers 320 of the hierarchy (towards layer 320-1). Thus, the region tags 332 of the respective layers 320 can determine the size of the address ranges represented by the nodes 311 within the respective layers 320.

[0079] As Figure 3 shown in and the following Table 2, the region tag 332 for each layer 320 can be formed from the sub-tag 304 assigned to the layer 320 and the sub-tag 304 of the corresponding upper layer 320 (e.g., if any, the layer 320 above the layer 320 in the size hierarchy), while the remaining portion of the address forms the region offset 331 of the layer 320. Thus, each layer 320 of the data structure 310 can have a corresponding region scheme 322 that defines the corresponding region tag 332, the region tag 332 being configured to uniquely identify an address range of a corresponding size (the size of each region being determined, in particular, by the number of address bits included in its region offset 331):

[0080]

[0081] Table 2

[0082] In the example of Table 2, the sub - tag 304 - N assigned to layer 320 - N contains the 12 MSBs of the address tag 302. In the region scheme 322 - N of layer 320 - N, the region tag 332 - N is formed by the sub - tag 304 - N (since layer 320 - N is at the top of the size hierarchy), and the remaining 52 bits form the region offset 331 - N of layer 320 - N. The region offset 331 - N defines the range size of layer 320 - N. In the example of Table 2, the node 311 of layer 320 - N (N - layer node 311) represents an address range with a range size of 2^56 for each region offset 331 - N. Thus, the respective N - layer nodes 311 of the data structure 310 can cover respective different ranges of 2^56 addresses of the address space, each address range being uniquely identified by the respective region tag 332 - N value. A sub - tag 304 formed by the next 24 MSBs of the sub - tag 304 can be assigned to the intermediate layer 320 between layer 320 - N and 320 - 2 (not shown in Table 2 or Figure 3 to avoid confusing the details of the shown example). In the region scheme 322 - 2 of layer 320 - 2 of the data structure 310, the sub - tag 304 - 2 assigned to layer 320 - 2 contains 8 bits, and the region tag 332 - 2 of layer 320 - 2 is formed by the sub - tag 304 - 2 and the sub - tag 304 of the upper layer 320, including the sub - tag 304 - N of layer 320 - N and the sub - tag 304 assigned to any intermediate layer 320. As shown, the region tag 332 - 2 is constructed according to the hierarchical structure defined by the data structure 310, where the MSBs of the region tag 332 - 2 are formed by the top - level sub - tag 304 - N and the LSBs of the region tag 332 - 2 are formed by the sub - tag 304 - 2. The region tag 332 - 2 of layer 320 - 2 contains 44 bits, and the remaining 20 bits form the region offset 331 - 2. Thus, layer 320 - 2 of the data structure 310 can correspond to a range size of 2^20. The node 311 of the second layer 320 - 2 of the data structure 310 (second - layer node 311) can cover the corresponding address range of 2^20 addresses, each address being uniquely identified by the corresponding 44 - bit region tag 332 - 2 value. In the region scheme 322 - 1 of the first bottom - most layer 320 - 1 of the data structure 310, the region tag 332 - 1 is formed by the sub - tags 304 - N to 304 - 1. Thus, the region tag 332 - 1 can contain 52 bits, and the remaining 12 bits define the minimum range size of the data structure 310. The first - layer node 311 of layer 320 - 1 can cover the corresponding range of 2^12 addresses, each range being uniquely identified by the corresponding 52 - bit region tag 332 - 1 value.

[0083] Figure 3Illustrates a further example of a node 311 of the disclosed data structure 310. A node 311 of the data structure 310 may contain any information related to an address range, including but not limited to: a node label 314, overlay data 316, etc. The node label 314 may be configured to uniquely identify a node 311 within each layer 320 of the data structure 310. The node labels 314 of the nodes 311 within each layer 320 of the data structure 310 may be assigned unique values corresponding to the sub-labels 304 of the layer 320. The size of the node label 314 may be determined by the region scheme 322 of the layer 320 (e.g., based on the number of bits included in the sub-label 304 assigned to the layer). In the example of Table 2, the node label 314 of the node 311 within layer 320-N of the data structure 310 contains a 12-bit value corresponding to sub-label 304-N (address bits 63-52), the node label 314 of the node 311 within layer 320-2 is an 8-bit value corresponding to sub-label 304-2 (address bits 27-20); the node label 314 of the node 311 within layer 320-1 is an 8-bit value corresponding to sub-label 304-1 (address bits 19-12), and so on.

[0084] In Figure 3In an example, the coverage data 316 of the corresponding node 311 may include and / or reference: a) access metadata 112 and / or access metadata entries 211 configured to cover the address range defined by the node 311, or b) child nodes 311 organized within the lower-level sub-structure 312. The management logic 226 may configure the access metadata entries 211 included within and / or referenced by the corresponding node 311 of the data structure 310 to cover the address range defined by the corresponding node 311. Thus, the access metadata entries 211 included within and / or referenced by the corresponding node 311 of the data structure 310 may be configured to cover or "occupy" the address range of the corresponding node 311. Conversely, a node 311 having coverage data 316 that does not include and / or reference an access metadata entry 211 may be designated as "open" or "unoccupied". The management logic 226 may require an open node 311 to reference a sub-structure 312 within an adjacent lower layer 320 of the data structure 310; a node 311 having coverage data 316 that does not include or reference an access metadata entry 211 or a sub-structure 312 may be removed from the data structure 310. The management logic 226 may enforce address range discrimination by, among other things, preventing an occupied node 311 (a node 311 that includes and / or references an access metadata entry 211) from having a child node 311 within the data structure 310, removing the child node 311 of the occupied node 311 from the data structure 310 (and invalidating and / or removing the corresponding entry 211 of the child node 311 from the data set 210), etc. In a tree-based implementation, the management logic 226 may configure an occupied node 311 as a leaf node 311 (a node 311 that does not reference any lower-level child nodes 311), and may configure an open node 311 as a non-leaf node 311 (a node 311 that references a child node 311 within an adjacent lower layer 320 of the data structure 310).

[0085] The data structure 310 can be configured to encode hierarchical parent - child relationships between nodes 311 disposed within different layers 320 of the data structure. A parent node 311 within the upper layer 320 of the data structure 310 can reference a child node 311 within the lower layer of the data structure 310. The hierarchical parent - child relationships encoded within the data structure 310 can correspond to address range containment. More specifically, each child node 311 of a parent node 311 can cover a respective unique subset of the address range covered by the parent node 311. In the example of Table 2, the node label 314 of a node 311 (N - layer node 311) within layer 320 - N of the data structure 310 can be assigned "0x000". Thus, the N - layer node 311 covers an address range of size 2^52 with boundaries {"0x0000 0000 0000", "0x000F FFFF FFFF FFFF"}. (For clarity, the portion of the address range corresponding to a region label 332 (such as region label 332 - N "0x000") is shown in bold herein). Since the region label 332 of a child node 311 inherits the node label 314 (sub - label 304) of the upper - layer parent node 311, the child nodes 311 of the N - layer node 311 "0x000" will cover a subset of the address range covered by the N - layer node 311 "0x000". For example, the N - layer node 311 "0x000" can reference a child (or grand - child) node 311 within the second layer 320 - 2 of the data structure 310. Since the second - layer node 311 includes the "0x000" node label 314 of its N - layer parent node 311, the second - layer node 311 must cover a subset of the address range covered by the N - layer parent node 311. For example, the second - layer node 311 can have a node label 314 of "0x22", and the node label 314 of the intermediate parent node 311 can be "0x000000", resulting in a 44 - bit region label 332 - 2 of "0x0000 0000 022" and a coverage of an address range of 2^20 with boundaries {"0x0000 0000 0220 0000", "0x0000 0000 022F FFFF"}. As shown, the 2^20 address range covered by the second - layer node 311 "0x22" is contained within the address range covered by the N - layer parent node 311 "0x000". Similarly, the child nodes 311 of the second - layer node 311 "0x22" within the first bottom - most layer 320 - 1 of the data structure 310 cover a subset of the address range covered by the second - layer node 311 "0x22" (and the address range covered by the higher - layer parent node 311 that includes the N - layer node 311 "0x000").As another example, the second-layer node 311 "0x22" may reference the first-layer child node 311 with the node label 314 "0x11", thereby obtaining the region label 332-1 "0x0000 0000 0221 1" and the coverage of the 2^12 address space with the boundary {"0x0000 0000 0221 1000", "0x0000 0000 0221 1FFF"}. As shown in the figure, the 2-12 address ranges covered by the first-layer node 311 "0x11" cover a subset of the address ranges covered by the second-layer parent node 311 "0x22" and its N-layer parent node 311 "0x000". The first-layer child nodes 311 of the second-layer node 311 "0x22" may be included in the sub-structure 312, as shown in Figure 3 . Figure 3 As shown. The sub-structures 312 within the corresponding lower layer 320 of the data structure 310 may be arranged, organized, and / or indexed by their node labels 314 (the nodes 311 within the corresponding sub-structure 312 may be uniquely identified by their node labels 314). The lower layer 320 of the data structure 310 may include sub-structures 312 for each unique parent node 311 within the adjacent upper layer 320.

[0086] As disclosed herein, the management logic 226 may configure the relationships between the nodes 311 of the data structure 310 to represent address range relationships. The parent-child relationship between the upper-layer nodes 311 and the lower-layer nodes 311 may be configured to represent an address range inclusion relationship, where the lower-layer child nodes 311 of the upper-layer parent node 311 cover a corresponding subset of the address range covered by the upper-layer parent node 311. As shown in Figure 3 , the data structure 310 may define the parent-child relationship between the upper-layer nodes 311 and the lower-layer nodes 311 (or the sub-structure 312 including the lower-layer child nodes 311 of each upper-layer parent node 311). As disclosed herein, the parent-child relationship may correspond to an address range inclusion relationship. The child nodes 311 of the upper-layer parent node 311 include lower-layer nodes 311 that cover a subset of the address range covered by the parent node 311. As described above, the management logic 226 may utilize the data structure 310 to ensure that the address ranges covered by the occupied nodes 311 are different, particularly by removing the child nodes (if any) of the occupied nodes 311 from the lower layer 320 of the data structure 310 and / or preventing the child nodes (and / or the corresponding access metadata entries 211) of the occupied nodes 311 from being created. Figure 3 As shown, the data structure 310 may define the parent-child relationship between the upper-layer nodes 311 and the lower-layer nodes 311 (or the sub-structure 312 including the lower-layer child nodes 311 of each upper-layer parent node 311). As disclosed herein, the parent-child relationship may correspond to an address range inclusion relationship. The child nodes 311 of the upper-layer parent node 311 include lower-layer nodes 311 that cover a subset of the address range covered by the parent node 311. As described above, the management logic 226 may utilize the data structure 310 to ensure that the address ranges covered by the occupied nodes 311 are different, particularly by removing the child nodes (if any) of the occupied nodes 311 from the lower layer 320 of the data structure 310 and / or preventing the child nodes (and / or the corresponding access metadata entries 211) of the occupied nodes 311 from being created.

[0087] The management logic 226 can also be configured to encode sibling relationships between nodes 311 within the data structure 310. Sibling nodes 311 refer to the following nodes 311: a) being set within the same layer 320 of the data structure 310, and b) being referenced by the same parent node 311 within an adjacent upper layer 320 of the data structure 310. Sibling nodes 311 can be set within corresponding sub-structures 312, each sub-structure 312 corresponding to a unique parent node 311 within an adjacent upper layer 320 of the data structure 310. The sibling nodes 311 within each sub-structure 312 can be uniquely identified by their node labels 314 (by sub-labels 304 assigned to the layer 320), thereby ensuring that the address ranges covered by the sibling nodes 311 at each layer 320 of the data structure 310 are unique and distinct. In addition, since the sub-structures 312 within each layer 320 of the data structure 310 correspond to unique upper-layer parent nodes 311, the nodes 311 within each layer 320 (and / or on the sub-structures 312 of each layer 320) are different and unique.

[0088] The management logic 226 can utilize the hierarchical relationships encoded within the data structure 310 to effectively define different address ranges of different sizes and / or extents. The management logic 226 can utilize the hierarchical relationships of the data structure 310 to implement address range manipulations that impose a low computational overhead while ensuring distinctiveness. The management logic 226 can effectively define a set of address ranges within the data structure 310 and configure the access metadata 112 accordingly. For example, the management logic 226 can configure the access metadata entries 211 of the data set 210 to cover the set of address ranges defined by the corresponding nodes 311 of the data structure 310. The management logic 226 can in particular effectively adjust the size and / or extent of the set of address ranges by manipulating the data structure 310. The management logic 226 can implement manipulations that define a set of modified address ranges that are guaranteed to be unique and distinct (according to the hierarchical relationships of the data structure 310). The management logic 226 can then configure the access metadata entries 211 of the data set 210 to cover the set of modified address ranges.

[0089] The management logic 226 can modify the data structure 310 to adjust the defined set of address ranges, at least in part, based on the utility metric 213 of accessing the metadata 112. The modification to the data structure 310 can be propagated to and / or implemented within the access data set 210, particularly by reconfiguring the set of address ranges covered by each access metadata entry 211 to correspond to the adjusted set of address ranges of the data structure 310. In one example, the management logic 226 can increase the size of the address range covered by an access metadata entry 211 by one or more of the following: merging the node 311 associated with the entry 211 with one or more sibling nodes 311, merging the node 311 into a parent node 311 within the upper layer 320 of the data structure 310, promoting the node 311 to a higher layer 320 of the data structure 310, and so on. In another example, the management logic 226 can decrease the size of the address range covered by an access metadata entry 211 by one or more of the following: splitting the node 311 associated with the entry 211 into one or more sibling nodes 311, splitting the node 311 into one or more child nodes 311 within a lower layer 320 of the data structure 310, demoting the node 311 to a lower layer 320 of the data structure 310, removing the node 311 (and invalidating the corresponding entry 211), etc.

[0090] The data structure 310 can also be configured to define a hierarchical and / or multi-level mapping scheme that can be searched from the top layer 320-N to the lower layers 320. Due to the parent-child range containment relationship of the data structure 310, search operations performed at the lower layers 320 of the data structure 310 can incorporate the results of search operations performed at the higher layers 320 of the data structure 310. The search Figure 3 The illustrated N-layer data structure can involve first searching the top layer 320-N of the data structure 310 and then searching one or more lower layers 320 if necessary. The hierarchical search for a node 311 (or access metadata entry 211) that covers a specified address 202 can involve: a) searching the top layer 320-N of the data structure using the sub-tag 304-N of the specified address 202, and b) returning "entry not found" if no matching top-level node 311 is found. If a top-level node 311 that matches the sub-tag 304-N of the specified address 202 is found, the hierarchical search can also include: c) returning the access metadata entry 211 of the top-level node 311 if the coverage data 316 of the top-level node 311 contains or references the entry 211, or d) otherwise searching the lower-level sub-structure 312 referenced by the top-level node 311. The hierarchical search operation can continue through successive lower layers 320 of the data structure 310 until a node 311 with coverage data 316 that contains and / or references the access metadata entry 211 is found, or the search fails.

[0091] As disclosed herein, the address space can be very large, and correspondingly, the data structure 310 and the corresponding access data set 210 can be "sparse" because the nodes 311 of the data structure 310 (and the corresponding access metadata entries 211 of the data set 210) may not cover the entire address space. Instead, the adaptive tracking engine 110 can add nodes 311 and corresponding access metadata entries 211 when utilizing regions of the address space (e.g., when commands 201 and / or indications of commands 201 are received at the adaptive tracking engine 110 as disclosed herein). The management logic 226 can also be configured to remove nodes 311 that do not contain or reference access metadata entries 211 or child nodes 311 (e.g., open leaf nodes 311 can be pruned from the data structure 310). The management logic 226 can also be configured to remove or evict nodes 311 and corresponding access metadata entries 211 that meet eviction criteria; e.g., not accessed within a time threshold, not frequently enough, have consistently poor utility metrics 213, produce poor prefetching, etc. The management logic 226 can dynamically add nodes 311 and corresponding access metadata entries 211 in response to a tracking miss. A tracking miss occurs when the address 202 of the command 201 falls outside the address range covered by the access metadata 112 (falls outside the address range covered by the access metadata entries 211 of the data set 210). In response to a tracking miss, the management logic 226 can add a node 311 to the bottommost layer 320-1 of the data structure such that the corresponding entry 211 covers an address range of a minimum range size. Subsequently, the range size of the entry 211 can be modified based on the utility metric 213 (e.g., based on the prefetch performance within the address range covered by the access metadata entry 211).

[0092] In some aspects, the management logic 226 can initialize and / or clear the access metadata 112, which can include removing and / or invalidating nodes 311 of the data structure 310 and / or the corresponding access metadata entries 211 of the data set 210. The management logic 226 can clear the access metadata 112 during a user command or message, configuration setting, or in response to a user command or message, configuration setting, in response to a shutdown and / or restart operation, etc. After initialization, as disclosed herein, the management logic 226 can reconstruct the access data set 210 and / or the data structure 310 at least in part based on the utility metric 213 related to the covered address range, in response to a tracking miss and / or to adjust the address range covered by the access metadata.

[0093] Although specific instances of the data structure 310 defining a particular configuration and / or region scheme 322 are described herein, the present disclosure is not limited thereto and can be applied to any suitable type of data structure 310 having any suitable number of layers 320 and / or any suitable region scheme 322.

[0094] Figure 4 FIG. illustrates a further example of a device 300 for implementing an adaptive tracking engine 110 as disclosed herein. In Figure 4 this example, the management logic 226 of the adaptive tracking engine 110 is configured to manage the address ranges covered by the access metadata 112 by using a four-layer data structure 310. In some embodiments, the access metadata entries 211 of the data set 210 may be maintained within the data structure 310 (e.g., within the occupied nodes 311 of the data structure 310). In Figure 4 this example, the access data set 210 is maintained separately from the data structure 310. The access data set 210 may be maintained in a different portion of the memory 208 than the data structure 310; e.g., within a different array, region, section, memory bank, plane, etc. As disclosed herein, the access data set 210 may be implemented by a suitable structure, such as: a table, lookup table, mapping table, array, list, tree, prefix tree, trie, radix tree, etc.

[0095] As Figure 4 shown, the management logic 226 divides the address tag 302 into four sub-tags 304-1 to 304-4 and defines the minimum range size as 4K (by specifying a 12-bit minimum offset 301, as in Figure 3 this example). Table 3 illustrates the region tags 332 and corresponding region offsets 331 of an example data structure 310 including 4 layers as Figure 4 shown.

[0096]

[0097] Table 3

[0098] As shown in Table 3, the region scheme 322-4 of the highest layer 320-4 of the data structure 310 defines a 13-bit region tag 332-4 that uniquely identifies the corresponding ranges of 2^51 addresses of the 64-bit address space (the maximum range size of the multiple range sizes defined by the data structure 310), the region scheme 322-3 of layer 320-3 defines a 26-bit region tag 332-3 formed by sub-tags 304-4 and 304-3 that uniquely identifies the corresponding ranges of 2^38 addresses, the region scheme 322-2 defines a 39-bit region tag 332-2 formed by sub-tags 304-4 to 304-2 that uniquely identifies the corresponding ranges of 2^25 addresses, and the region scheme 322-1 of layer 320-1 defines a 52-bit region tag 332-1 formed by sub-tags 304-4 to 304-1 that uniquely identifies the corresponding ranges of 2^12 addresses (the minimum range size of the multiple range sizes defined by the data structure 310).

[0099] A node 311 of the data structure 310 may include a node label 314, which may hold a value of a sub-label 304 corresponding to the layer 320 in which the node 311 is set, and may uniquely identify the node 311 within the corresponding sub-structure 312 within the layer 320. In Figure 4 an example, a node 311 of the data structure 310 further includes a next valid indicator 410, a next pointer 411, an entry valid indicator 421, an entry pointer 422, etc. The next valid indicator 410 and / or the entry valid indicator 421 may specify whether the node 311 is open or occupied. More specifically, the next valid indicator 410 may specify whether the next pointer 411 of the node 311 references a valid sub-structure 312 in a lower layer 320 of the data structure 310 (indicating whether the node 311 is open), and the entry valid indicator 421 may specify whether the entry pointer 422 references a valid access metadata entry 211 that covers the address range defined by the node 311 (indicating whether the node 311 is occupied). The next valid indicator 410 and / or the entry pointer 422 may be omitted from a node 311 that cannot reference a lower-layer child node 311, such as a node 311 set in the lowest layer 320-1 of the data structure 310.

[0100] Figure 5 - 1 illustrates a further example of a device 300 for implementing the adaptive tracking engine 110 as disclosed herein. In Figure 5 - 1 an example, as disclosed herein, the management logic 226 manages the address ranges (and range sizes) covered by the respective access metadata entries 211 of the data set 210 by and / or by using the data structure 310. In Figure 5 - 1 an example, the management logic 226 uses a multi-layer data structure 310 including three layers 320-1 to 320-3 to manage the address ranges covered by the access metadata 112, with each layer 320 corresponding to a respective one of a plurality of range sizes.

[0101] The adaptive tracking engine 110 may include and / or be coupled to a memory 208, which may be implemented, realized, and / or provided by any suitable memory resource, including but not limited to: semiconductor integrated circuits, memory cells, memory arrays, memory banks, memory chips, on-board memory of the adaptive tracking engine 110, host memory resources, main memory, backup memory 108, cache memory 106, memory resources of the consumer 115 and / or the source 215, RAM, DRAM, SRAM, SDRAM, etc. The management logic 226 may be configured to maintain the access metadata 112 and / or portions thereof within the memory 208.

[0102] As disclosed herein, the management logic 226 can be configured to manage the address range (and / or range size) covered by the respective entries 211 of the access data set 210 via the data structure 310. The configuration of the data structure 310 can in particular be specified by the configuration data 524 of the adaptive tracking engine 110. The configuration data 524 can include any suitable configuration information, including but not limited to: the configuration of the data structure 310, the type of the data structure 310 (e.g., specifying a table, a mapping table, a multi-level mapping table, a tree, a radix tree, etc.), the number of levels 320 to be included in the data structure 310, the region scheme 322 of each level 320, the range size of each level 320, the configuration of the sub-tags 304 assigned to each level 320 (e.g., the address bits included in each sub-tag 304), the region tag 332 of each level 320, the region offset 331 of each level 320, the range size of each level 320 (defining multiple range sizes, each corresponding to a respective level 320 of the data structure 310), the minimum range size of the data structure 310, the minimum offset 301, etc. In Figure 5 - 1 the example of

[0103]

[0104] Table 4

[0105] According to the region scheme 322 of Table 3, the minimum offset 301 corresponds to address bits 7 to 0 (the minimum range size is 2^8), level 320-1 is assigned sub-tag 304-1, corresponding to address bits 11 to 8 (and the minimum range size), level 320-2 is assigned sub-tag 304-2, corresponding to address bits 15 - 12 (and the next larger range size of 2^12), and level 320-3 is assigned sub-tag 304-3, corresponding to address bits 23 - 16 (and the maximum range size of 2^16).

[0106] As Figure 5 - 1As shown, a node 311 of the data structure 310 may include a node label 314, coverage data 316, etc. The node label 314 of the node 311 may correspond to a sub-label 304 of a layer 320 of the data structure 310 in which the node 311 is set. The coverage data 316 may include and / or reference: as disclosed herein, access metadata entries 211 or sub-structures 312 (e.g., one or more sub-nodes 311) within a lower layer 320 of the data structure 310. The coverage data 316 may distinguish occupied nodes 311 that are prevented from referencing sub-nodes 311 in the lower layer 320 of the data structure 310 from open nodes 311. The management logic 226 prevents the data structure 310 from including sub-nodes 311 below the occupied nodes 311. Due to the address range inclusion relationship defined by the data structure 310, it prevents access metadata entries 211 of the data set 210 from covering overlapping address ranges. Although Figure 5 - 1 FIG. illustrates an example of a node 311, but the present disclosure is not limited thereto and may be configured to express, represent, and / or encode information related to corresponding address ranges of access metadata 112 and / or coverage of address ranges using any suitable techniques and / or formats.

[0107] The management logic 226 of the adaptive tracking engine 110 is configured to add a node 311 to the data structure 310 (and create a corresponding access metadata entry 211) in response to a tracking miss. Figure 5 - 2 FIG. illustrates operations implemented by the adaptive tracking engine 110 (and / or its management logic 226) in response to a tracking miss for a target address 202 “0x332105”. The management logic 226 may detect a tracking miss in response to a command 201 related to the address 202 (e.g., in response to determining that the access data set 210 does not include an access metadata entry 211 that covers the target address 202). As Figure 5 - 2 shown, the management logic 226 processes the tracking miss particularly by creating nodes 311 representing the target address 202 within respective layers 320 of the data structure 310. Node labels 314 of the nodes 311-1 to 311-3 created for the target address 202 within respective layers 320 of the data structure 310 are assigned values corresponding to the sub-labels 304 assigned to the respective layers 320 (according to the region scheme 322 of the respective layers 320). The node 311-1 created within the layer 320-1 covers an address range that includes the target address 202 and has a minimum address range size defined by the data structure 310. The node 311-1 includes and / or references an access metadata entry 211 configured to cover the address range defined by the node 311-1. Thus, the management logic 226 may designate the node 311-1 as occupied and the nodes 311-2 and 311-3 as open.

[0108] In Figures 5 - 2 to 5 - 9In the illustrated example data structure 310, occupied nodes 311 that contain and / or reference access metadata entries 211 are highlighted with a diagonal fill pattern for easy reference (and to distinguish occupied nodes 311 from open nodes 311 that do not contain the diagonal fill pattern).

[0109] As disclosed herein, management logic 226 can ensure uniqueness by leveraging the address range relationships encoded within data structure 310. More specifically, management logic 226 configures data structure 310 such that nodes 311 created within the lower levels 320 of the data structure are referenced by open parent nodes 311, and child nodes 311 are removed from occupied nodes 311 (and cannot be created thereunder). Thus, creating node 311-1 within level 320-1 can include verifying that level 320-2 does not contain an occupied second-level node 311 that overlays target address 202, and creating parent node 311-2 within the second level 320-2 of the data structure (if node 311-2 does not already exist). Similarly, creating node 311-2 within level 320-2 can include verifying that level 320-3 does not contain an occupied third-level node 311 that overlays target address 202, and creating parent node 311-3 within the third level 320-3 of data structure 310 (if node 311-2 does not already exist). The node labels 314 of nodes 311 created within the respective levels 320 of data structure 310 are extracted from target address 202 based on sub-labels 304 assigned to the respective levels: the node label 314 of node 311-1 is assigned "0x1" (each sub-label 304-1 extracts "0x332105" from bits 11 through 7 of target address 202); the node label 314 of node 311-2 is assigned "0x2" (each sub-label 304-2 is extracted from bits 15-12 of target address 202); and the node label 314 of node 311-2 is assigned "0x33" (each sub-label 304-3 is extracted from the 8 MSBs of target address 202).

[0110] As Figure 5 - 2As shown, the data structure 310 encodes the parent - child relationships between nodes 311, which correspond to address inclusion relationships between the address ranges covered by the nodes 311 (and their access metadata entries 211). The region label 332 - N of the top - level parent node 311 - 3 is the 8 - bit value "0x33", which uniquely identifies the third - level address range (2^16 address range size) with boundaries {"0x330000", "0x33FFFF"}. According to the hierarchical address inclusion relationship of the data structure 310, the child nodes 311 (e.g., nodes 311 - 2 and 311 - 1) of the third - level parent node 311 - 3 cover a subset within the address range it covers. The second - level node 311 - 2 has a 12 - bit region label 332 - 2 of "0x332" and covers the second - level address range (2^12 address range size) defined by {"0x332000", "0x332FFF"}. As shown, the second - level address range covered by the node 311 - 2 is included in the third - level address range covered by its upper - level parent node 311 - 3. The first - level node 311 - 1 has a 16 - bit region label 332 - 1 of "0x3321" and covers the first - level address range (2^8 addresses) defined by {"0x332100", "0x3321FF"}. As shown, the first - level address range covered by the node 311 - 1 is included in the second - level address range covered by its second - level parent node 311 - 2 and the third - level address range covered by its third - level "grandparent" node 311 - 3.

[0111] Creating the first - level node 311 - 1 may also include configuring the access metadata entry 211 - 1 of the configuration data set 210 to cover the address range defined by the node 311 - 1. As shown, the access metadata entry 211 - 1 included within and / or referenced by the node 311 - 1 contains the access metadata 112 - 1 related to the address range covered by the node 311 - 1. The address range covered by the access metadata entry 211 - 1 (address range {"0x332100", "0x3321FF"}) can be specified in the range metadata 214 - 1 of the entry 211. Alternatively, since the address range covered by the entry 211 - 1 is defined by the node 311 - 1, the range metadata 214 - 1 of the entry 211 - 1 can be omitted. Since the node 311 - 1 contains and / or references the access metadata entry 211 - 1, the node 311 - 1 can be designated as occupied. Nodes 311 - 2 and 311 - 3 that do not contain and / or reference the access metadata entry 211 with the covering data 316 can be designated as open.

[0112] As disclosed herein, nodes 311 within the lower layer 320 of the data structure 310 may be organized into corresponding sub-structures 312, each sub-structure corresponding to a corresponding parent node 311 in the adjacent upper layer 320 and indexed by a node label 314, where the node label 314 may correspond to a sub-label 304 assigned to layer 320. As Figure 5 - 2 shown, the first layer nodes 311-1 are included in the sub-structure 312-1 referenced by their second layer parent node 311-2, and the node 311-2 is included in the sub-structure 312-2 referenced by its third layer parent node 311-3. The sub-structure 312-2 includes second layer nodes 311 that cover a subset of the address range covered by the third layer nodes 311-3. More specifically, the sub-structure 312-2 includes second layer nodes 311 having a region label 332-2 that incorporates the third layer region label 332-3 of the parent node 311-3 (“0x33”), and thus covers a subset of the address range covered by the third layer nodes 311-3 (e.g., second layer nodes 311 having a region label 332-2 that incorporates the region label 332-3 “0x33”). Similarly, the sub-structure 312-1 referenced by the second layer node 311-2 includes first layer nodes 311 that cover a subset of the address range covered by the second layer node 311-2. More specifically, the sub-structure 312-1 includes first layer nodes 311 having a region label 332-1 that incorporates the second layer region label 332-2 of the second layer node 311-2 (“0x332”), and thus covers a subset of the second layer address range covered by the second layer node 311-2.

[0113] As Figure 5 - 2As further shown, traversing the respective layers 320 of the data structure 310 during a hierarchical lookup and / or search operation can result in the construction of region labels 332 for the respective layers 320. A lookup of an access metadata entry 211 that covers a specified address 202 (e.g., "0x332188") can include: a) searching layer 320-3 to identify a third layer node 311-3 having a node label 314 that matches a sub-label 304-3 of the specified address 202 (e.g., "0x33"), b) searching a sub-structure 312-2 referenced by the identified third layer node 311-3 (and / or third layer sub-label 304-4 "0x33") to identify a second layer node 311-2 having a node label 314 that matches a sub-label 304-2 of the specified address 202 (e.g., "0x2"), and c) searching a sub-structure 312-1 referenced by the identified second layer node 311-2 (and / or second layer sub-label 304-2 "0x2") to identify a first layer node 311-1 having a node label 314 that matches a sub-label 304-1 of the specified address 202 (e.g., "0x1"). Thus, traversing the data structure 310 can result in the construction of a value for the region label 332-1 for layer 320-1 (e.g., constructing a 16-bit value, "0x3321", for the region label 332-1 of layer 320-1). Similarly, traversing the data structure 310 to the second layer 320-2 results in the construction of a 12-bit value for the region label 332-2 ("0x332"), and so on.

[0114] Figure 5 - 3Illustrated are further operations implemented by the adaptive tracking engine 110 in response to a tracking miss for additional addresses 202 including a second address 202 “0x33240F” and a third address 202 “0x66210B”. In response to a tracking miss for the second address 202 “0x33240F”, the management logic 226 creates a node 311-4 and a corresponding access metadata entry 211-2 within the first layer 320-1 of the data structure 310. Since the node 311-4 covers a subset of the region covered by a second layer node 311-2 (which is a child node of the node 311-2) and a third layer node 311-3 (which is a grandchild node of the node 311-3), the node 311-4 is included in the sub-structure 312-1. In response to traversing the data structure 310 using the corresponding sub-tag 304 of the second address 202, the node 311-4 may be included in the first layer sub-structure 312-1. The traversal may include: a) selecting the third layer node 311-3 (and thus the second layer sub-structure 312-2 referenced thereby) by using the sub-tag 304-3 of the second address 202 (“0x33”), b) selecting the second layer node 311-2 (and thus the first layer sub-structure 312-1 referenced thereby) by using the sub-tag 303-2 of the second address 202 (“0x2”), and c) determining that the first layer sub-structure 312-1 does not contain a node 311 covering the second address 202 (e.g., determining that “0x33240F” is outside the address range covered by the node 311-1 and / or the access metadata entry 211-1). The node 311-4 may contain and / or reference the access metadata entry 211-2, which contains access metadata 112-2 (and / or range metadata 214-2) related to the address range specified by the node 311-4.

[0115] The management logic 226 creates nodes 311-5, 311-6, and 311-7 in response to a tracking miss for the third address 202 “0x66210B”. The third address 202 is outside the address range covered by the third layer node 311-3 and / or the second layer node 311-2. The management logic 226 can determine that the third address 202 is outside the third layer address range of the node 311-3 (and thus also outside the second layer address range of the node 311-2) especially in response to comparing the sub-tag 304-3 of the third address 202 “0x66” with the node label 314 of the node 311-3 “0x33”. As Figure 5 - 3As shown, the management logic 226 creates a sub-structure 312-3 and a node 311-5 within the first layer 320-1 of the data structure 310, and assigns the node label 314 of the node 311-5 to "0x1" for each sub-label 304-1 of the third address 202. The node 311-5 contains and / or references an access metadata entry 211-3 having access metadata 112-3 related to the address range (e.g., the address range {"0x662100", "0x6621FF"}) covered by the node 311-5. The management logic 226 creates a parent node 311-6 within the upper adjacent layer 320-2 of the data structure 310 to reference the sub-structure 312-3. According to the sub-label 304-2 of the third address 202, the node label 314 of the second-layer parent node 311-6 is set to "0x2". The management logic 226 also creates a parent node 311-7 within the next layer 320-3 of the data structure 310 to reference the second-layer sub-structure 312-4. According to the sub-label 304-3 of the third address 202, the node label 314 of the third-layer parent node 311-7 is set to "0x66".

[0116] Return reference Figure 5 - 1 , the adaptive tracking engine 110 can be configured to update the access metadata 112 in response to a command 201 related to an address space. In Figure 5 - 3 an instance, the adaptive tracking engine 110 updates the access metadata 112-1 of the entry 211-1 in response to a command 201 related to an address 202 within the address range {"0x332100", "0x3321FF"}, updates the access metadata 112-2 of the entry 211-2 in response to a command 201 related to an address 202 within the address range {"0x332400", "0x3324FF"}, and / or updates the access metadata 112-3 of the entry 211-3 in response to a command 201 related to an address 202 within the address range {"0x662100", "0x6621FF"}. A consumer 115 such as a prefetch logic 515 can use the access metadata 112 to implement prefetch operations in various regions of the address space. The prefetch logic 515 can use the access metadata 112-1 of the entry 211-1 to implement prefetch operations within the address range {"0x332100", "0x3321FF"}, can use the access metadata 112-2 of the entry 211-2 to implement prefetch operations within the address range {"0x332400", "0x3324FF"}, and can use the access metadata 112-3 of the entry 211-3 to implement prefetch operations within the address range {"0x662100", "0x6621FF"}.

[0117] The prefetch logic 515 may implement a prefetch operation according to a specific prefetch technique or algorithm. Different prefetch implementations may utilize different types of access metadata 112. In one example, the prefetch logic 515 implements a stride-based prefetcher that uses the access metadata 112 to detect a stride pattern within a corresponding address region. In another example, the prefetch logic 515 implements a related prefetcher that attempts to detect a loop increment sequence within an address sequence covered by the access metadata 112. In yet another example, the prefetch logic 515 implements an ML prefetcher, such as an LSTM prefetcher, and uses the access metadata 112 (and / or extracts ML features therefrom) in an ML model of the local context covered by the access metadata 112. The management logic 226 may be configured to adapt the access metadata 112 for the prefetch logic 515 (e.g., especially based on the characteristics of the prefetch logic 515). The management logic 226 may be configured to capture address stride metadata in response to determining that the prefetch logic 515 implements a stride-based prefetch, may capture an address sequence (and / or an increment sequence) in response to determining that the prefetch logic 515 implements a related prefetcher, may capture ML model data and / or features in response to determining that the prefetch logic 515 implements an ML prefetcher, and so on.

[0118] Alternatively or additionally, the management logic 226 may capture the access metadata 112 according to a programmable metadata configuration 525. The metadata configuration 525 may include any suitable information related to the capture, retention, and / or format of the access metadata 112. The management logic 226 may retain the metadata configuration 525 within the memory resources of the adaptive tracking engine 110 (e.g., using other configuration data 524). The management logic 226 may receive and / or import the metadata configuration 525 from a consumer 115 such as the prefetch logic 515. The prefetch logic 515 may receive the metadata configuration 525 (and / or portions thereof) through an interface 222 of the adaptive tracking engine 110 (e.g., through an API or other mechanism implemented by the interface 222). The management logic 226 uses the metadata configuration 525 to adapt the access metadata 112 for the prefetch implementation of the prefetch logic 515. The management logic 226 may use the metadata configuration 525 to capture the access metadata 112 suitable for use by one or more of a stride prefetcher, a related prefetcher, an ML prefetcher, an NN prefetcher, an RNN prefetcher, an LSTM prefetcher, etc.

[0119] The management logic 226 can in particular determine a utility metric 213 for each access metadata entry 211 based on feedback 204 from the prefetch logic 515. The management logic 226 can use the utility metric 213 to adjust the extent size of an address range. The extent size can be adjusted by manipulating the data structure 310 and implementing the manipulation within the access data set 210. More specifically, the management logic 226 can modify the data structure 310 to adjust the address range represented by the corresponding node 311 and reconfigure the access metadata entry 211 accordingly. The management logic 226 can in particular increase the size of the access metadata entry 211 by promoting the corresponding node 311 to a higher level 320 of the data structure 310, merging the node 311 with one or more other nodes 311 of the data structure, merging the node 311 into a higher-level parent node 311, etc. The management logic 226 can in particular decrease the size of the access entry 211 by demoting the node associated with the entry 211 to a lower level 320 of the data structure 310, splitting the node 311, splitting the node 311 into one or more child nodes 311 within the lower level 320 of the data structure 310, removing the node 311 (and invalidating the corresponding access metadata entry 211), etc.

[0120] In Figure 5 - 3 an example, the utility metric 213-3 of the access metadata entry 211-3 can trigger a demotion operation of the management logic 226. Since the entry 211-3 covers the smallest extent size defined by the data structure 310 (associated with the node 311-5 in the first level 320-1 of the data structure), the demotion operation can include removing the access metadata entry 211-3 and the corresponding node 311-5 from the data structure 310. Removing the access metadata entry 211 can include invalidating and / or removing the entry 211 from the data set 210 and / or removing the node 311 that contains and / or references the entry 211 from the data structure 310. The removal operation can also include removing and / or invalidating upper-level parent nodes 311 and / or substructures 312 that no longer reference any child nodes 311, especially due to the removal of the node 311 associated with the access metadata entry 211. As Figure 5 - 4 shown, demoting the access metadata entry 211-3 includes removing the entry 211-3 from the data set 210, removing the first-level node 311-5 from the data structure 310, removing the upper-level parent nodes 311-6 and 311-7 that no longer reference child nodes 311 within the lower level 320 of the data structure 310, removing the empty substructures 312-3 and 312-4, etc.

[0121] In another example, the utility metric 213-3 of access metadata entry 211-3 is sufficient to trigger an upgrade of entry 211-3. As disclosed herein, upgrading access metadata entry 211 may include increasing the size of the address range covered by entry 211. Upgrading access metadata entry 211 may include modifying node 311 associated with entry 211, particularly by merging node 311 into the next higher level 320 of data structure 310 and setting the address range of access metadata entry 211 to the address range defined by the modified node 311 (or associating access metadata entry 211 with a parent node 311 and removing child node 311 from data structure 310). In Figure 5 - 5 the example of, upgrading access metadata entry 211-3 includes merging the first-level node 311-5 initially associated with entry 211-3 into the second-level node 311-6 (and / or associating entry 211-3 with the second-level node 311-6). As shown, the second-level node 311-6 is transformed from an open node 311 with lower-level child nodes 311 to an occupied node 311 that is prevented from having and / or referencing any lower-level child nodes 311. Thus, upgrading access metadata entry 211-3 may include removing and / or invalidating the first-level node 311-5 (and the resulting empty sub-structure 312-3). The size of the address range covered by the modified access metadata entry 211-3 may be upgraded from the minimum range size to the next larger range size of layer 320-2. As Figure 5 - 5 shown, entry 211-3 is modified to cover the second-level address range {"0x662000", "0x662FFF"} of node 311-6, rather than the smaller first-level address range {"0x662100", "0x6621FF"}.

[0122] Management logic 226 may monitor the utility metric 213-3 of access metadata entry 211-3 after the upgrade operation and determine whether to keep entry 211-3 in the second level 320-2, downgrade entry 211-3 back to the first level 320-1, upgrade entry 211-3 to the next higher level 320-3, etc., at least in part based on the utility metric 213-3. In Figure 5 - 6In the illustrated example, the utility metric 213-3 of access metadata entry 211-3 triggers a further upgrade of entry 211-3 to the third level 320-3 of data structure 310. In response, the management logic 226 merges the node 311 in particular by associating the entry 211-3 with the third-level node 311-7: configuring the access metadata entry 211-3 to overwrite the third-level address range defined by the node 311-7 (e.g., the address range {"0x660000", "0x66FFFF"}), setting the override data 316 of the node 311-7 to include and / or reference the entry 211-3, converting the node 311-7 from an open node 311 to an occupied node 311, removing the lower-level child nodes 311 of the node 311-7, such as the second-level node 311-6, removing the lower-level substructure 312, etc.

[0123] Return reference Figure 5 - 5 , after upgrading to the second level 320-2, the utility metric 213-3 of the access metadata entry 211-3 can decrease, rather than increase as in the Figure 5 - 6 illustrated example. The decrease can occur after the access metadata 112-3 related to the second-level address range {"0x662000", "0x662FFF"} has been captured. The decrease in the utility metric 213-3 can trigger a downgrade of the access metadata entry 211-3 back to the lower level 320-1 of the data structure 310. Since the access metadata entry 211 associated with the node 311 at the lower level 320 of the data structure 310 covers a smaller address range than the access metadata entry 211 of the node 311 within the higher level 320, the downgrading of the higher-level access metadata entry 211 can include an inter-level splitting operation, where the higher-level node 311 associated with the access metadata entry 211 is split into a group of one or more lower-level nodes 311, each lower-level node 311 covering a smaller lower-level address range within the larger address range covered by the upper-level node 311. In some aspects, the upper-level node 311 can be split into lower-level nodes 311 that span the address range covered by the upper-level node 311. The upper-level node 311 can be split into 2^B LST lower-level nodes 311, where B LSTis the number of bits in the sub-tag 304 of the lower layer 320 and determines the maximum number of unique nodes 311 of the lower layer that can be associated with the corresponding parent node 311 of the adjacent upper layer 320. Alternatively, the upper layer node 311 accessing the metadata entry 211 can be split, in particular, based on the access metadata 112 of the entry 211. The upper layer node 311 can be split into lower layer nodes 311 that cover a selected portion of the address range covered by the upper layer node 311, as indicated, in particular, by the access metadata entry 211 of the upper layer node 311. The management logic 226 can omit the lower layer nodes 311 corresponding to the following: address ranges that have not been accessed within a time threshold (and / or at a threshold frequency), that fail to meet an activity threshold, that are associated with a low utility metric 213, that are associated with poor prefetching performance, etc. The access metadata 112 of the higher layer entry 211 can be replicated in the lower layer entry 211. Alternatively, the access metadata 112 of each lower layer entry 211 can be derived from the corresponding portion of the access metadata 112 of the upper layer access metadata entry 211. The access metadata 112 of the lower layer entry 211 can be combined with the access metadata 112 corresponding to the portion of the address range covered by the lower layer entry 211.

[0124] Figure 5 - 7 illustrates the operation of demoting the access metadata entry 211-3 associated with the second layer node 311-6 in Figure 5 - 5 back to the first layer 320-1 of the data structure 310. The demotion operation can include an inter-layer split operation, in which the associated second layer nodes 311-6 within the access metadata entry 211-3 are split into one or more first layer child nodes 311, each child node covering a corresponding subset of the second layer address range covered by the second layer node 311-6. In some aspects, the access metadata entry 211-3 can be split into 16 lower layer entries 211, each lower layer entry covering a corresponding subset of the address range {"0x662000", "0x662FFF"} (according to the 4-bit sub-tag 304-1 of the lower layer 320-1). In Figure 5 - 7In the illustrated example, access metadata entry 211-3 is split into three lower-level child nodes 311-8, 311-9, and 311-10, which can respectively define the address ranges covered by access metadata entries 211-4, 211-5, and 211-6. The address ranges can be determined based on the access metadata 112-3 of access metadata entry 211-3 (e.g., can correspond to the active portion of the address range). As shown, access metadata entry 211-4 covers the address range {"0x662300", "0x6623FF"}, entry 211-5 covers the address range {"0x662500", "0x6625FF"}, and entry 211-6 covers the address range {"0x662F00", "0x662FFF"}. Access metadata entry 211-3 can be invalidated and / or removed from the data set 210, and the second-level node 311-6 is configured to reference the first-level sub-structure 312-3 that includes child nodes 311-8 to 311-10 (transition from occupied to open).

[0125] Return reference Figure 5 - 1 , the management logic 226 of the adaptive tracking engine 110 can also be configured to identify and merge access metadata entries 211 that a) cover adjacent address ranges and b) have similar utility metrics 213. As used herein, "adjacent" address ranges refer to address ranges that have the same or similar range sizes and are within a threshold distance of each other. In some aspects, adjacent address ranges refer to the address ranges covered by sibling nodes 311 of the data structure 310. Sibling nodes 311 refer to nodes 311 that are within the same layer 320 of the data structure 310 and have a common parent node in an adjacent upper layer 320. In Figure 5 - 3 the example of, nodes 311-1 and 311-4 included in the sub-structure 312-1 of layer 320-1 are sibling nodes. The utility metrics 213-1 and 213-2 of sibling entries 211-1 and 211-2 can trigger the merge operation of the management logic 226. As Figure 5 - 8As shown, the merge operation may include merging nodes 311-1 and 311-4 into the common parent node 311-2 of the sibling nodes by: a) configuring the destination access metadata entry 211-7 of the merged entries 211-1 and 211-2 to overwrite the address range {"0x332000", "0x332FFF"} of the upper layer node 311-2, b) merging the access metadata 112-1 and 112-2 of the entries 211-1 and 211-2 into the destination entry 211-7, c) removing and / or invalidating the merged entries 211-1 and 211-2 and the corresponding nodes 311-1 and 311-4 within the first layer 320-1 of the data structure 310 (and the empty sub-structure 312-1), and / or d) configuring the overwrite data 316 of the upper layer node 311-2 to include and / or reference the access metadata entry 211-7.

[0126] Such as Figure 5 - 8 Inter-layer merge or upgrade operations, such as the inter-layer merge operation shown, involve combining nodes 311 within the lower layer 320 into nodes within the higher layer 320 of the data structure 310, which can result in a significant size increase. Figure 5 - 9 Illustrates an example of an intra-layer merge and / or upgrade operation implemented by the adaptive tracking engine 110 and / or the management logic 226, where nodes 311 are merged within the same layer 320 of the data structure 310 (and / or the size of the address range covered by the nodes 311 and the corresponding access metadata entries 211 increase within the same layer 320 of the data structure). In Figure 5 - 9 the example, the first layer sibling nodes 311-1 and 311-4 are combined into a composite node 311-11 within the same layer 320-1 of the data structure 310 (as opposed to the nodes 311 within the second layer 320-2 of the data structure 310). The node label 314 of the composite node 311-11 contains multiple values spanning the node labels 314 of the merged nodes 311-1 and 311-4 (e.g., containing and / or spanning "0x1" to "0x4"). Thus, the address range defined by the composite node 311-11 and the corresponding merged entry 211-8 spans the sub-label set 304-1 "0x1" to "0x4" or {"0x332100", "0x3324FF"}. Figure 5 - 9 The example intra-layer merge operation may result in a more gradual size increase than the inter-layer merge. In some aspects, the management logic 226 implements the intra-layer merge operation until an internal merge threshold is reached.

[0127] Although specific examples of manipulation operations have been described, the present disclosure is not limited thereto. The management logic 226 may be configured to implement any suitable type of manipulation operation. As Figure 5 - 7As shown, the management logic 226 can be configured to implement inter-layer demotion or splitting operations, where the upper-level node 311 (and the corresponding access metadata entry 211) is split into smaller lower-level nodes 311. The management logic 226 can also be configured to implement intra-layer demotion or splitting operations, where the composite node 311 and the corresponding access metadata entry 211 are split into one or more smaller and / or non-composite nodes 311 within the same layer 320 of the data structure 310.

[0128] Figure 6 A further example of a device 600 for implementing adaptive address tracking and / or an adaptive tracking engine 110 is illustrated (an example of an adaptive address tracking device 600). In some embodiments, the access metadata entries 211 of the data set 210 are maintained within the range management data structure 310. For example, the access metadata entry 211 can be contained within the corresponding occupied node 311 of the data structure 310. In contrast, in Figure 6 the example, the access metadata entries 211 of the data set 210 are maintained separately from the data structure 310. As shown, the adaptive tracking engine 110 can include and / or be coupled to a range tracking memory (a first memory 608), which is configured to store, maintain, and / or provide the data set 210 including one or more access metadata entries 211. The first memory 608 can be configured as a range tracking memory and / or be configured to store and / or implement access to the data set 210, as disclosed herein. More specifically, the first memory 608 is configured to maintain a set of access metadata entries 211, each of which covers a corresponding address range. In Figure 6 the example, the access metadata entry 211 includes range metadata 214, which defines the boundaries of the address range covered by the entry 211 (e.g., having a minimum and a maximum address value).

[0129] The adaptive tracking engine 110 can also include and / or be coupled to a range management memory (a second memory 618) that maintains the range management data structure 310. The second memory 618 can be configured as a range management memory and / or be configured to implement the range management data structure 310.

[0130] In some aspects, the first memory 608 is separate and / or independent from the second memory 618. The first memory 608 can be implemented and / or realized by a memory component that is separate and / or independent from the memory component that implements and / or realizes the second memory 618.

[0131] As disclosed herein, the access dataset 210 can be accessed and / or updated frequently. In addition, the access to the dataset 210 can be related to performance-sensitive components such as memory I / O paths. Therefore, the first memory 608 can be implemented, provided, and / or realized by high-performance memory resources such as memory circuits, semiconductor memory circuits, memory arrays, memory banks, caches, cache lines, SRAMs, SDRAMs, dedicated memory resources, on-board memory resources, etc. The second memory 618 may not be as performance-sensitive as the first memory 608, and thus can be implemented, provided, and / or realized by other memory resources such as the memory resources of the host device 102, main memory, backup memory 108, the memory resources of the consumer 115 and / or the source 215, DRAM, etc.

[0132] The first memory 608 can include and / or be coupled to first logic 624. The first logic 624 is coupled to the interface 222 and the first memory 608. The first logic 624 can be configured to provide access to the entry 211 of the dataset 210. The first logic 624 can implement an interface for accessing the access metadata 112 (and / or the first memory 608). The first logic 624 can also be configured to update the access metadata of the corresponding entry 211 in response to a command 201 related to an address 202 within the address range covered by the corresponding entry 211 (e.g., can include and / or implement update logic 224). In Figure 6In an example, the first logic 624 also includes and / or is coupled to search logic 625, which is configured to look up an entry 211 corresponding to a specified address 202 in response to, among other things, a command 201 related to the address 202, a request from a consumer 115 (such as a prefetch logic 515), feedback 204 related to access metadata 112 that overrides the address 202, etc. The search logic 625 may be configured to implement fast, low-overhead search operations within an access data set 210 maintained in the first memory 608. The search logic 625 may be configured to implement search and / or look-up operations without accessing the data structure 310 and / or the second memory 618. The search and / or look-up operations implemented by the search logic 625 may involve comparing the address 202 and / or the address tag 302 with the extent metadata 214 of the corresponding entry 211. The search logic 625 may implement a direct single-level comparison as opposed to a hierarchical search operation within the various layers 320 of the data structure 310. The search logic 625 may include comparison logic configured to compare the address 202 (and / or the address tag 302) with the minimum and / or maximum address boundaries covered by the corresponding entry 211 (as defined by the extent metadata 214 of the entry 211). The search logic 625 may be configured to compare the address 202 (and / or the address tag 302) with the extent metadata 214 of multiple entries 211 at least partially in parallel. The first logic 624 (and / or its search logic 625) may be provided, implemented, and / or realized in hardware. The search logic 625 may include a hardware search engine and / or a hardware search circuit coupled to the first memory 608. In some examples, the first logic 624 (and / or its search logic 625) is implemented by using on-board logic components (such as PIM circuits, etc.) of the first memory 608. In some embodiments, the search logic 625 is integrated with the first memory 608. The search logic 625 may be implemented within the die and / or substrate of the first memory 608. Alternatively or additionally, the hardware search engine and / or the hardware search circuit of the search logic 625 may be implemented within the same package or module as the first memory 608, etc.

[0133] The adaptive tracking engine 110 may also include and / or be coupled to a second logic 626. The second logic 626 may be coupled to the first memory 608, the second memory 618, and / or the interface 222. The second logic 626 may include and / or be coupled to a management logic 226, which is configured to manage entries 211 of the access dataset 210, in particular via and / or by means of a data structure 310 held in the second memory 618. In some instances, the second logic 626 (and / or its management logic 226) is included in and / or coupled to the second memory 618. The second logic 626 (and / or its management logic 226) may also be coupled to the first memory 608 and may be configured to create, remove, invalidate, modify, and / or otherwise manage the entries 211 of the dataset 210. As disclosed in more detail herein, the management logic 226 may be configured to effect modifications performed on the data structure 310 within the access dataset 210, in particular by configuring the entries 211 of the dataset 210 to override the address ranges defined by the corresponding nodes 311 of the data structure 310.

[0134] As disclosed herein, the data structure 310 may be constructed according to configuration data 524. In Figure 6 an instance, the management logic 226 constructs a data structure 310 including N layers 320-1 to 320-N, each layer 320 being assigned a corresponding sub-label 304 and corresponding to a respective range size among a plurality of range sizes. The layers 320-1 to 320-N may be organized into a hierarchical structure corresponding to the range sizes, where the first layer 320-1 corresponds to the smallest range size among the plurality of range sizes at the bottom of the hierarchy, and the last layer 320-N corresponds to the largest range size at the top of the hierarchy. The region scheme 322 of the respective layers 320 of the data structure defines the sub-labels 304, region labels 332, and / or region offsets 331 of the layer 320 based on the position of the respective layer 320 within the hierarchy, which in particular defines the range sizes of the respective layers 320.

[0135] A node 311 of the data structure may include a node label 314, status data 616, an entry reference 621, a sub-reference 631, etc. The status data 616 of the node 311 indicates whether the node 311 refers to an access metadata entry 211 or a sub-structure 312 within a lower layer 320 of the data structure 310. Thus, as disclosed herein, the status data 616 may indicate whether the node 311 is occupied or open. The status data 616 may also be configured to indicate whether the node 311 refers to a valid access metadata entry 211 and / or a valid sub-structure 312. The entry reference 621 of the node 311 may refer to an access metadata entry 211 of a data set 210 held in a first memory 608. A node 311 held in a second memory 618 may refer to an entry 211 held in the first memory 608 using any suitable information including but not limited to: a reference value, an index value, a pointer value (a pointer to a location within the first memory 608), a memory address, an address offset, etc. The sub-reference 631 of the node 311 may include and / or refer to a sub-structure 312 within a lower layer 320 of the data structure 310. The sub-reference 631 may be omitted from a node 311 within the first layer 320-1 of the data structure 310.

[0136] In Figure 6 an instance of, a node 311 of the data structure 310 also includes a utility metric 213, which may quantify the utility of the address range covered thereby, as disclosed herein. The utility metric 213 of an occupied node 311 may quantify the utility of the entry 211 referred to by the node 311 according to prefetch performance (or capture the utility of the access metadata 112 covering the address range defined by the node 311). The utility metric 213 of an open node 311 that does not directly refer to an entry 211 may be empty. Alternatively, the utility metric 213 of an open node may be configured to quantify the utility of the sub-nodes of the node 311. The utility metric 213 of an open node 311 may include an average value, a mean value, or other combination of the utility metrics 213 of the occupied sub-nodes 311 of the open node 311.

[0137] As disclosed herein, the management logic 226 encodes the address range relationships within the data structure 310. The management logic 226 encodes the address range inclusion relationships through the parent-child relationships between the nodes 311, where the address range covered by an upper-layer parent node 311 includes the address range covered by a lower-layer child node 311. The sibling relationships between nodes 311 within a layer 320 and sharing the same upper-layer parent node 311 in adjacent upper layers 320 of the data structure 310 cover the address ranges included within the upper-layer address range covered by the parent node 311. More specifically, sibling nodes 311 (and corresponding entries 211) cover corresponding subsets within the upper-layer parent address range.

[0138] In Figure 6In an example, the management logic 226 requires that the leaf nodes 311 be occupied. Accordingly, each node 311 in the lowest layer 320-1 references the access metadata entry 211, and nodes that do not reference a valid entry 211 are removed. Similarly, nodes 311 in the upper layer 320 of the data structure 310 that do not reference a valid access metadata entry 211 or sub-structure 312 are removed. In some aspects, the management logic 226 requires that each node 311 in the lower layer 320 (layers 320 other than the top layer 320-N) of the data structure 310 have a single unique parent node 311 in the upper adjacent layer 320 and be included in the sub-structure 312 referenced by the parent node 311. Nodes 311 within the sub-structure 312 can be indexed and / or referenced by their node labels 314. Nodes 311 in the top layer 320-N of the data structure 310 can be indexed and / or referenced in a similar manner (e.g., as if included in the same or a common sub-structure 312) by their node labels 314. Sibling nodes 311 within each sub-structure 312 can be uniquely identified by sub-label values recorded in their node labels 314. Accordingly, the lower sibling nodes 311 of each upper parent node 311 can cover different subsets of the address range covered by each upper parent node 311. However, node labels 314 of nodes 311 having different parent nodes 311 and thus included in different sub-structures 312 can have the same value (the address ranges of such nodes 311 cannot overlap because the nodes 311 have different parent nodes and are thus included in different address ranges).

[0139] The management logic 226 can adjust the address range covered by the access metadata 112 by modifying the data structure 310 and implementing the modification within the access data set 210. As disclosed herein, the management logic 226 can modify the range size of one or more entries 211 of the data set 210 by, in particular, implementing manipulation operations within the data structure 310, which can include but are not limited to: merge operations, inter-layer merge operations, intra-layer merge operations, split operations, inter-layer split operations, intra-layer split operations, removal operations, upgrade operations, inter-layer upgrade operations, intra-layer upgrade operations, downgrade operations, inter-layer downgrade operations, intra-layer downgrade operations, etc. Implementing the manipulation operations can include propagating the modifications made within the data structure 310 to the access data set 210, which can include but are not limited to: modifying the address range covered by one or more access metadata entries 211, increasing the size of the address range covered by one or more entries 211, decreasing the size of the address range covered by one or more entries 211, removing and / or invalidating one or more entries 211, etc. As disclosed herein, the management logic 226 can adjust the range size of one or more entries 211 at least in part based on the utility metric 213 of the entries 211.

[0140] The management logic 226 can be configured to evaluate the utility metric 213 and implement corresponding modifications to the address range covered by the access metadata 112 (if any) in a background operation. The background operation can be configured to utilize the idle resources available to the adaptive tracking engine 110. The background operation can be suspended, paused, and / or terminated during and / or in response to a foreground operation. The foreground operation can include, but is not limited to: receiving a command 201 (and / or an indication of the command 201) at the interface 222, updating the access metadata 112 in response to the command 201, updating the utility metric 213 in response to the feedback 204 (and / or the command 201), receiving a request for the access metadata 112 from the consumer 115, providing the access metadata 112 to the consumer 115, sending the access metadata 112 to the consumer 115, etc. The background operation can resume and / or restart when the idle resources become available and / or the foreground operation has been completed. The management logic 226 can implement a background scan operation to evaluate the utility metric 213 and implement corresponding modifications to the address range covered by the access metadata 112 in a background scan operation that is periodically implemented at a specified interval, during an idle period, etc. The background scan operation can include traversing the nodes 311 of the data structure 310 (and / or the corresponding entries 211 of the data set 210) to identify entries 211 for demotion, promotion, merging (related entries 211), etc.

[0141] The management logic 226 may also be configured to remove and / or invalidate nodes 311 of the data structure 310. Nodes 311 within the first layer 320-1 of the data structure 310 may be removed and / or invalidated during a demotion and / or split operation. The management logic 226 may remove the first layer nodes 311 in response to determining that the utility metric 213 of the first layer nodes 311 is below a threshold (and / or remains below the threshold for a determined period of time). Removing the first layer nodes 311 may also include removing the entries 211 referenced by the first layer nodes 311 from the data set 210. In some instances, the management logic 226 may determine that the address range covered by a node 311 is not suitable for prefetching. As disclosed herein, some address ranges may not be suitable for prefetching and / or certain prefetching techniques. Inappropriate address ranges may exhibit poor prefetch performance over time and at different range sizes. The management logic 226 may identify inappropriate address ranges and, in response, identify that the records of the address ranges without tracking metadata 612 are not suitable for prefetching. In some instances, the without tracking metadata 612 includes one or more entries (without tracking entries 611), each of which identifies a corresponding without tracking address range. The without tracking metadata 612 may be recorded within the access metadata 112 and / or be available to a consumer 115 (such as the prefetch logic 515). The prefetch logic 515 may use the without tracking metadata 612 to avoid performing prefetch operations within inappropriate address ranges. Similarly, the management logic 226 may use the without tracking metadata 612 to prevent tracking inappropriate address ranges in response to subsequent tracking misses. The without tracking metadata 612 may be maintained in one or more of the data set 210, the range management data structure 310, and / or other portions of the access metadata 112. In Figure 6 an instance, the management logic 226 is configured to maintain the without tracking metadata 612 within the access data set 210. The without tracking metadata 612 may include one or more without tracking entries 611, each of which is configured to identify a corresponding address range. The without tracking entries 611 may identify inappropriate address ranges by any suitable mechanism. In some instances, the without tracking entry 611 includes a timestamp indicating the time when the without tracking entry 611 was created and / or other information. The management logic 226 may clear the without tracking entries 611 when one or more conditions are met (when the workload within the address range may have changed), such as after a determined period of time, after a restart or shutdown operation, etc. Alternatively or additionally, the management logic 226 may be configured to maintain the without tracking metadata 612 within the data structure 310. The management logic 226 may use nodes 311 marked with a without tracking indicator (e.g., marked as without tracking within the status data 616, entry reference 621, sub-reference 631, utility metric 213, and / or other fields of the node 311) to represent inappropriate address regions.

[0142] Figure 7Illustrated is a further example of a device 700 for implementing an adaptive tracker and / or an adaptive tracking engine 110. In Figure 7 the example of, a second logic 626 of the adaptive tracking engine 110 includes and / or is coupled to an adaptation logic 726. The adaptation logic 726 utilizes management logic 226 to adjust the set of address ranges covered by access metadata 112 so as to improve prefetch performance in particular. The adaptation logic 726 may determine a modification operation to be implemented within the data set 210 based at least in part on a utility metric 213 of the access metadata 112.

[0143] In some aspects, the adaptation logic 726 is configured to build the access metadata 112 from an initial or initialized state in which the data set 210 and / or the data structure 310 is substantially empty. The adaptation 726 may build the access metadata 112 according to configuration data 524, which may define modification operations to be implemented in response to a tracking miss. In some examples, the configuration data 524 specifies that a tracking miss is handled by adding an entry 211 of a minimum size to the access data set 210, which may include configuring the management logic 226 to: modify the data structure 310 to add a node 311 covering an address 202 associated with the tracking miss to the lowest layer 320-1 of the data structure 310, and implement the modification within the data set 210 by creating an entry 211 of the data set 210 held within the first memory 608 that is covered by the address range defined by the node 311 and configuring the coverage data 316 of the node 311 to reference the entry 211. In another example, the configuration data 524 may specify that a tracking miss is handled by adding an entry 211 of a larger size to the data set 210, which may include configuring the management logic 226 to create a node 311 covering the address 202 within a higher layer 320 of the data structure 310, and implement the modification within the data set 210 as disclosed herein (e.g., configuring an access metadata entry 211 of the data set 210 to cover the address range defined by the node 311).

[0144] The adaptation logic 726 may also be configured to tune, adjust, and / or optimize the set of address ranges covered by the access metadata 112 in a background operation. The adaptation logic 726 may adapt the address ranges and / or the range sizes covered by the entries 211 of the access data set 210 so as to improve prefetch performance in particular. As disclosed herein, the adaptation logic 726 may implement operations involving manipulating the data structure 310 within the data set 210 by using the management logic 226.

[0145] The adaptation logic 726 can adjust the address range and / or range size of the access metadata 112 according to the adaptation policy of the configuration data 524. In one example, the adaptation policy can configure the adaptation logic 726 to demote entries 211 that are determined to have a utility metric 213 below a threshold (e.g., a specified demotion threshold). The adaptation logic 726 can select entries 211 for demotion or other modification, in particular by scanning the access metadata 112, which can include traversing the nodes 311 of the data structure 310 (and / or the entries 211 referenced thereby), scanning the entries 211 of the data set 210, etc. The adaptation logic 726 can be configured to perform background scan operations (and perform corresponding address range adjustments) periodically, at specified intervals, during idle periods, etc.

[0146] As disclosed herein, demoting selected entries 211 associated with upper-level nodes 311 of the data structure 310 can include: demoting the upper-level nodes 311 from occupied to open, creating one or more lower-level child nodes 311 that cover a corresponding subset of the address range covered by the upper-level nodes 311, allocating entries 211 of the data set 210 to the lower-level child nodes 311, importing the access metadata 112 of the selected entries 211 into the specified entries 211, and removing and / or invalidating the selected entries 211. Demoting entries 211 within the lowest level 320-1 of the data structure 310 can include removing and / or invalidating nodes 311 from the data structure 310, removing and / or invalidating the corresponding entries 211 from the data set 210, etc. The demotion operation can also include recording a no-tracking indication in the access metadata 112, which can prevent the adaptation tracking engine 110 from attempting to track the address range in response to a subsequent tracking miss, as disclosed herein.

[0147] In yet another example, the adaptation policy configures the adaptation logic 726 to facilitate access metadata entries 211 having a utility metric 213 determined to be above a threshold (e.g., above a specified facilitation threshold). As disclosed herein, the upgrade entry 211 can include increasing the size of the address range covered by the entry 211. The adaptation logic 726 can select the entry 211 (and / or the corresponding node 311) for upgrade during a background scan operation, as disclosed herein. The adaptation logic 726 can implement operations to upgrade the entry 211 by using the management logic 226. The management logic 226 can upgrade the entry 211 by manipulating the data structure 310. The adaptation logic 726 can configure the management logic 226 to implement: an inter - layer upgrade operation in which the entry 211 is upgraded from a lower layer 320 of the data structure 310 to a higher layer 320, an intra - layer upgrade operation (intra - layer merge operation) in which the entry 211 is extended to include additional address ranges within the same layer 320 of the data structure 310 (e.g., by manipulating the composite node 311 of the data structure 310), etc. An inter - layer merge operation that merges the entry 211 associated with a lower - level node 311 into a parent node 311 in the higher layer 320 of the data structure 310 can include: merging the entry 211 of the child node 311 of the parent node 311 into the destination entry 211, removing and / or invalidating the entry 211 of the child node 311 from the data set 210, removing the child node 311 from the data structure 310, and configuring the parent node 311 to reference the destination entry 211 (designating the parent node 311 as occupied rather than open).

[0148] In another example, the adaptation logic 726 is configured to merge selected groups of related access metadata entries 211. The adaptation policy can define related entries 211 as entries 211 that: a) cover an address range within a proximity threshold (and / or have the same range size), and b) have a utility metric 213 within a utility threshold. As disclosed herein, the adaptation logic 726 can identify groups of related entries 211 in response to a background scan operation. The adaptation logic 726 can merge the identified group of entries 211 by using the management logic 226 (e.g., by configuring the management logic 226 to implement merge operations, inter - layer merge operations, intra - layer merge operations, etc.).

[0149] The adaptation logic 726 may also be configured to adjust, tune, and / or optimize the access metadata configuration 725 of the adaptive tracking engine 110. As used herein, the access metadata configuration 725 of the adaptive tracking engine 110 refers to information related to the configuration of the access metadata 112 captured and / or held by the adaptive tracking engine 110. The access metadata configuration 725 may correspond to the set of address ranges covered by the access metadata 112 and / or the configuration of the data set 210, such as the number of access metadata entries 211 included in the data set 210, the set of address ranges covered by the access metadata entries 211, and the like. Alternatively or additionally, the access metadata configuration 725 may include information related to the data structure 310, as disclosed herein, which may define the set of address ranges covered by the access metadata entries 211 of the data set 210. The adaptation logic 726 may adjust the access metadata configuration 725 by: a) determining, monitoring, adjusting, and / or otherwise maintaining the utility metadata 723 of the access metadata configuration 725, and b) implementing a modification operation to modify the access metadata configuration 725 based at least in part on the utility metadata 723. The utility metadata 723 of the access metadata configuration 725 may be based at least in part on the utility metric 213 of the access metadata entries 211 of the data set 210 (and / or the utility metric 213 of the corresponding nodes 311 of the data structure 310). Determining the utility metadata 723 may include, but is not limited to, averaging, weighting, aggregating, combining, and / or otherwise combining the utility metrics 213 of the access metadata entries 211 (and / or the corresponding nodes 311). In some instances, the utility metric 213 may be weighted by the address range size, where the weighting of the utility metric 213 corresponding to a larger address range size is heavier than the weighting of the utility metric 213 corresponding to a smaller address range size (e.g., the utility metric 213 associated with the corresponding node 311 may be multiplied by the weighting factor of the layer 320 assigned to the data structure 310 in which the corresponding node 311 is set). Alternatively or additionally, the utility metric 213 may be weighted according to the activity level, where the weighting of the utility metric 213 corresponding to an address range with a higher activity level (e.g., higher request frequency, prefetch activity, etc.) is heavier than the weighting of the utility metric of an address range with a lower activity level. The activity level of each access metadata entry 211 may be determined based on the number and / or frequency of commands 201 related to the address 202 covered by the corresponding entry 211 (and / or the corresponding node).

[0150] In some instances, the adaptation logic 726 implements an iterative tuning process, where each iteration may include but is not limited to: a) determining the utility metadata 723 of the access metadata configuration 725 of the adaptive tracking engine 110, b) evaluating an adaptation function or model (e.g., an optimization function or model) to determine the utility amount of the access metadata configuration 725, and c) determining whether to modify the access metadata configuration 725 at least in part based on the utility amount. The objective function can in particular be defined by the adaptation strategy of the configuration data 524. The objective function can be configured to balance the utility of the access metadata configuration 725 (as quantified by the utility metadata 723) and the cost associated with the access metadata configuration 725, which can be quantified according to memory overhead, computational overhead, latency overhead, complexity, memory overhead of the data set 210, memory overhead of the access metadata entries 211 of the data set 210 (e.g., within the first memory 608), the number of entries 211 included in the data set 210, memory overhead of the data structure 310 (e.g., in the second memory 618), the number of nodes 311 and / or sub-structures 312 included in the data structure 310, complexity of the data structure 310, etc.

[0151] The adaptation logic 726 can determine a modification to the access metadata configuration 725 that, based on the adaptation function or model, will increase the utility of the address tracking engine 110 (e.g., result in an increase in the utility metric 213 and / or a decrease in cost). The adaptation logic 726 can implement the iterations of the optimization process in a background operation. The adaptation logic 726 can continue the iterative optimization process until one or more termination criteria are met, such as convergence to an optimal access metadata configuration 725, convergence to a local optimum, convergence to a stable set of access metadata configurations 725, reaching an iteration threshold, etc. Alternatively or additionally, the adaptation logic 726 can be configured to periodically implement iterations of the optimization process and / or resume the optimization process in response to changing workload conditions, which can in particular result in a decrease in the utility metric 213 within one or more address ranges of the access metadata configuration 725. The adaptation logic 726 can be configured to implement any suitable optimization process, algorithm, technique, or model, including but not limited to: gradient descent, steepest descent, conditional gradient, stochastic gradient descent, heuristic algorithms (e.g., memetic algorithms, evolutionary algorithms, differential evolution algorithms, genetic algorithms, dynamic relaxation algorithms, hill climbing algorithms, particle swarm algorithms, etc.), ML optimization algorithms, etc.

[0152] Although Figure 7 illustrates the adaptation logic 726 implemented in the example device 600, where the entries 211 of the access data set 210 and the data structure 310 are maintained in separate memory resources, but the present disclosure is not limited thereto, and the adaptation logic 726 and / or its functionality can be incorporated into other implementations, such as where the access metadata entries 211 of the data set 210 are included in, for exampleFigure 3 Embodiments in corresponding nodes 311 of the data structure 310 shown.

[0153] Figure 8 FIG. illustrates a further example of a device 800 for implementing adaptive address tracking. In Figure 8 this example, the adaptive tracking engine 110 is coupled to and / or included within the cache memory 106, which particularly includes cache logic 802 and a memory array 806. The adaptive tracking engine 110 includes and / or is coupled to a first memory 608 configured to access metadata 112 and / or access the data set 210. In some examples, the first memory 608 is implemented by and / or within the memory array 806. The first memory 608 may be implemented in a dedicated area of the memory array 806. The search logic 625 may also be implemented by and / or within the memory array 806 (as a PIM circuit, etc.).

[0154] The adaptive tracking engine 110 also includes a second memory 618 configured to range manage the data structure 310 and the management logic 226. In some examples, the second memory 618 is implemented by and / or within the memory array 806. Alternatively, the second memory 618 may be implemented by and / or within other memory resources, such as a backup memory 108, on-board memory, DRAM, etc. The management logic 226 configures the data structure 310 to define a plurality of range sizes, each range size corresponding to a respective one of the layers 320 of the data structure 310. As disclosed herein, the adaptive tracking engine 110 captures access metadata 112 related to the address regions covered by the respective entries 211 of the data set 210. The entries 211 may be updated in response to cache requests such as cache hits, cache misses, etc.

[0155] The cache memory 106 can be configured to cache addresses related to the backing memory 108 within the memory array 806. The cache logic 802 can be configured to load addresses into the memory array 806, particularly in response to a cache miss. The cache logic 802 can also be configured to prefetch addresses within a corresponding address range at least in part based on access metadata 112 held within an entry 211 of the coverage dataset 210 that covers the corresponding address range. The cache logic 802 can implement any suitable prefetching technique and / or prefetching type, including but not limited to: stride prefetcher, correlation prefetcher, ML prefetcher, etc. In some embodiments, the stride prefetcher implemented by the cache logic 802 uses the access metadata 112 covering the corresponding address range to particularly detect stride patterns within the corresponding address range. In other embodiments, the correlation prefetcher implemented by the cache logic 802 uses the access metadata 112 covering the corresponding address range to particularly detect incremental correlations and / or incremental sequences within the corresponding address range. Alternatively or additionally, an ML prefetcher such as an LSTM prefetcher uses the access metadata 112 to develop an ML model within the corresponding address range covered or to apply the access metadata 112 covering the corresponding address range to an ML model corresponding to the corresponding address range.

[0156] The cache logic 802 can also be configured to provide feedback related to the prefetch performance within the address range of the corresponding entry 211. The management logic 226 uses this feedback to determine the utility metric 213 of the corresponding entry 211 (and / or the corresponding node 311 of the data structure 310). As disclosed herein, the device 800 further includes adaptation logic 726 that adjusts the range size and / or the address range covered by the entry 211 to improve the prefetch performance.

[0157] Example methods for adaptive address tracking

[0158] In this section, reference is made Figures 9 to 15 to the flowcharts and flow diagram descriptions of example methods. These descriptions are by way of example only with reference to the components, entities, and other aspects depicted in FIGS. 1 - 8. Figure 9An example method for implementing adaptive address tracking in a device is illustrated by flowchart 900. Flowchart 900 includes blocks 902 through 906. In some embodiments, host device 102 (and / or its components) may perform one or more operations of flowchart 900. Alternatively or additionally, one or more operations may be performed by a memory, a memory controller, PIM logic, a cache, cache logic, prefetch logic, an embedded processor, and the like. At 902, adaptive tracking engine 110 receives command 201 (and / or an indication of command 201) related to an address of a memory address space, such as a command 201 to retrieve, modify, manipulate, and / or otherwise access data associated with address 202. Command 201 may be received and / or obtained from a source 215 such as processor 103, memory controller 104, interconnect 105, cache 106, cache prefetch logic, a prefetch unit, and the like. For example, when a program accesses various regions of a memory address space, command 201 may correspond to a memory I / O workload generated by a program running on processor 103 of host 102.

[0159] At 904, access metadata 112 related to command 201 received at 902 is stored in a memory (e.g., memory 208, first memory 608, etc.). Access metadata 112 may be stored in a data set 210 including one or more entries 211 responsive to command 201, where each entry 211 of data set 210 covers an address range of the memory address space and includes access metadata 112 related to addresses within the covered address range. Access metadata 112 held within entry 211 may include any information related to the address range covered by entry 211, which may include but is not limited to: information related to accesses within the covered address range, access statistics, access pattern statistics, access history, access sequences, access frequency metadata, access time metadata, access pattern metadata, stride patterns, correlation patterns, delta sequences, access modeling metadata, ML modeling metadata, ML feature data, and the like. Access metadata 112 may be maintained and / or updated in response to any suitable type of command 201, which includes but is not limited to: data access requests, read requests, write requests, copy requests, clone requests, trim requests, erase requests, delete requests, cache misses, cache hits, and the like.

[0160] At 906, the management logic 226 adjusts the size of the address range covered by at least one entry 211 of the data set 210 based at least in part on one or more metrics 214 representing prefetch performance within the address range covered by one or more entries 211 of the data set 210. In some instances, the adaptive tracking engine 110 provides access metadata 112 to the prefetch logic 515, and the prefetch logic 515 uses the access metadata 112 to inform prefetch operations within the address range covered by the access metadata 112. The prefetch logic 515 may also be configured to provide feedback 204 regarding prefetch performance within the address range, such as the number of available prefetches performed within the address range, the ratio of available prefetches to bad prefetches, etc. At 906, the address range covered by an entry 211 having relatively high prefetch performance may be increased, while the address range covered by an entry 211 having relatively low prefetch performance may be decreased (and / or the low-performance entry 211 may be removed). At 906, the set of address ranges defined by the data structure 310 may be modified, in particular, by manipulating one or more of its nodes 311. The entries 211 of the data set 210 may be configured to implement the modified set of address ranges. The address range covered by an entry 211 may be modified by writing one or more bits to the first memory 608 (writing bits to modify the range metadata 214 of the entry 211).

[0161] Figure 10 A further example of a method for a device implementing adaptive address tracking is illustrated in flowchart 1000. At 1002, the management logic 226 of the adaptive tracking engine 110 represents address ranges of a memory address space through nodes 311 within respective layers 320 of the data structure 310, each layer 320 corresponding to one of a plurality of address range sizes. The management logic 226 may also be configured to encode parent-child relationships within the data structure 310, where the parent-child relationships between nodes 311 at different layers 320 of the data structure represent address range containment relationships between the nodes 311. The management logic 226 may also encode corresponding sibling relationships within the data structure 310, where nodes 311 having the same corresponding parent node 311 in an upper layer 320 of the data structure 310 represent subsets of the same corresponding larger upper-layer address range represented by the corresponding parent node 311. Sibling nodes 311 of the same parent node 311 may be organized within a sub-structure 312, where the sibling nodes 311 are indexed by a sub-tag value (e.g., by the content of the node tag 314). As disclosed herein, the management logic 226 may also be configured to implement the set of address ranges defined by the data structure 310 within the data set 210 including access metadata entries 211.

[0162] At 1004, the update logic 224 of the adaptive tracking engine 110 captures and / or maintains access metadata 112 within a respective entry 211 of the data set 210. Each entry 211 of the data set 210 is associated with a respective node 311 of the data structure 310 and covers the address range represented by the associated node 311. The update logic 224 may be configured to update the access metadata 112 in response to a command 201 related to an address 202 of the address space. At 1004, the command 201 is received, and in response, the update logic 224 maps the address 202 related to the command 201 to an entry 211 of the data set 210 and updates the access metadata of the entry 211 accordingly. At 1004, the adaptive tracking engine 110 may also be configured to provide the access metadata 112 related to a specified address range to a consumer 115 (such as a cache, a cache memory, cache control logic, cache prefetch logic, prefetch logic, a prefetchor, etc.). The consumer 115 may use the access metadata 112 to implement a prefetch operation within the specified address range and provide feedback related to the prefetch performance and / or utility within the specified address range. As disclosed herein, this feedback may be used to determine a prefetch utility metric (utility metric 213) for respective access metadata entries 211 of the data set 210.

[0163] At 1006, the management logic 226 modifies the data structure 310 based at least in part on the prefetch utility metrics of the access metadata entries 211, the nodes 311, and / or the corresponding address ranges of the data set 210. The management logic 226 may implement the modification to: modify the size of one or more address ranges, increase the size of one or more address ranges, upgrade one or more entries 211 to a higher level 320 of the data structure, downgrade one or more entries 211 to a lower level 320 of the data structure, merge one or more entries 211 (and / or corresponding nodes 311), split one or more entries 211 (and / or corresponding nodes 311), and so on. The modification to the data structure 310 may be adapted to improve prefetch performance. The modification may include reducing the size of an entry 211 having a utility metric 213 below a reduction threshold, increasing the size of an entry 211 having a utility metric 213 above an increase threshold, combining sibling entries 211 having a utility metric 213 within a proximity threshold, etc. The management logic 226 may implement the modification of 1006 in particular by manipulating the nodes 311 of the data structure 310. These manipulations may be implemented according to the hierarchical address inclusion relationship of the data structure 310 such that the set of modified address ranges defined by the modified data structure 310 are different from each other.

[0164] At 1008, the management logic 226 updates the address ranges covered by at least one of the entries 211 in the data set 210 in response to modifying the data structure 310. The management logic 226 can be configured to propagate the modifications implemented within the data structure 310 at 1006 within the access metadata entries 211 of the data set 210. More specifically, the management logic 226 can link the entries 211 of the data set 210 to the occupied or leaf nodes 311 of the data structure 310, and configure the entries 211 to cover the address ranges defined by the associated nodes 311 after the modification.

[0165] Figure 11 A further example of a method for implementing an apparatus for adaptive address tracking is illustrated in flowchart 1100. At 1102, the management logic 226 maintains a data set 210 that includes access metadata entries 211, each entry 211 being configured to cover an address range of a set of address ranges defined by the data structure 310. The management logic 226 can be configured to build the data structure 310 and the corresponding data set 210 from an initial state in which the data structure 310 and the data set 210 are substantially empty. The management logic 226 can also be configured to add nodes 311 to the data structure 310 and corresponding entries 211 to the data set 210 in response to a tracking miss (e.g., in response to command 201 and / or a request for access metadata 112 related to an address 202 not covered by an entry 211 of the accessed data set 210). In some embodiments, the accessed data set 210 is maintained in a first memory 608, and the data structure 310 is maintained in a second memory 618 that is separate from and / or independent of the first memory 608.

[0166] At 1104, the update logic 224 of the adaptive tracking engine 110 captures the access metadata 112 within an entry 211 of the data set 210. The access metadata 112 can be captured in response to a command 201 related to an address 202 of the address space. At 1104, the corresponding entry 211 of the data set 210 is updated in response to a command 201 related to an address 202 within the address range covered by the corresponding entry 211.

[0167] At 1106, the interface 222 of the adaptive tracking engine 110 provides access metadata 112 (and / or portions thereof) to the prefetch logic 515. The prefetch logic 515 can utilize the access metadata 112 to notify of prefetch operations within the address range covered by the access metadata 112. The prefetch logic 515 can implement prefetch operations within the address range covered by the corresponding entry 211 based on and / or by using the access metadata 112 of the entry 211. The prefetch logic 515 can also be configured to return feedback 204 related to the prefetch utility of the corresponding address range, which can be used to determine, update, and / or modify the utility metric 213 of the corresponding entry 211 of the data set 210.

[0168] At 1108, the update logic 224 evaluates the prefetch utility of the individual access metadata entries 211 of the data set 210. The prefetch utility of the entry 211 can indicate whether the size of the address range covered by the entry 211 is suitable for capturing access metadata 112 from which access patterns can be derived. A low prefetch utility can indicate that the size of the address range is inappropriate and / or should be downgraded to a smaller size, while a high prefetch utility can indicate that the size of the address range is appropriate and / or should be upgraded to a larger size.

[0169] At 1110, the management logic 226 (or its adaptation logic 726) determines whether to modify the set of address ranges defined by the data structure 310 (and implemented by the entries 211 of the data set 210). At 1110, the prefetch utility (e.g., the utility metric 213) of the entry 211 can be compared with one or more thresholds: entries 211 having a utility metric 213 below the first threshold can be selected for downgrading, entries 211 having a utility metric 213 above the second threshold can be selected for upgrading, related nodes 311 having a utility metric 213 within the threshold can be selected for a merge operation, and so on. In some embodiments, the adaptation logic 726 evaluates an adaptation function (e.g., the objective function of an optimization model) to determine, in particular, whether to modify the set of address ranges covered by the access metadata 112. The evaluation can include determining a fitness metric configured to balance the prefetch performance provided by the access metadata 112 captured within the set of address ranges and the cost associated with the access metadata 112. The cost can be quantified in terms of overhead, resource consumption, prefetch cost, etc. The evaluation can include determining a modification to the set of address ranges according to an optimization algorithm such as gradient descent and the like.

[0170] If the determination at 1110 is to modify the address range set, the process continues at 1112; otherwise, the process continues at 1102. At 1112, the management logic 226 adjusts the data structure 310 to define the modified address range set. The management logic 226 can define the modified address range set by implementing one or more manipulation operations within the data structure 310, and the manipulation operations can include but are not limited to: merge operations, inter-layer merge operations, intra-layer merge operations, split operations, inter-layer split operations, intra-layer split operations, removal operations, upgrade operations, inter-layer upgrade operations, intra-layer upgrade operations, downgrade operations, inter-layer downgrade operations, intra-layer downgrade operations, etc. The manipulation operations can be configured to improve the prefetch utility of accessing the data set 210 by downgrading the entries 211 with relatively low utility metrics 213 and upgrading the entries 211 with relatively high utility metrics 213.

[0171] At 1114, the management logic 226 reconfigures the access metadata entries 211 of the data set 210 to cover the modified address range set defined by the data structure 310, and the process can continue at 1102. In some embodiments, the portion from 1108 to 1114 can be implemented in a background operation. The background operation can be implemented during idle cycles and / or by using idle resources available to the adaptive tracking engine 110. As disclosed herein, when resources are needed to implement a foreground operation, the management logic 226 can suspend, pause, and / or terminate the background operation.

[0172] Figure 12 - 1 An example of a method for increasing the size of one or more address ranges covered by the access metadata entries 211 of the data set 210 (e.g., upgrading the entries 211 of the data set 210) as disclosed herein is illustrated in the flowchart 1200. At 1202, an access metadata entry 211 of the data set 210 is selected for upgrading. The entry 211 can be selected for upgrading based on the utility metric 213 of the entry 211, which can indicate relatively high prefetch performance within the address range covered by the entry 211. The entry 211 can be selected in response to determining that the utility metric 213 of the entry 211 exceeds one or more thresholds.

[0173] At 1204, the management logic 226 of the adaptive tracking engine 110 determines whether the node 311 associated with the selected entry 211 has a parent node within a higher level of the data structure 310. The management logic 226 can determine whether the node 311 is set within the last, highest level 320-N of the data structure 310 or within a lower level 320 of the data structure (e.g., within one of levels 320-N-1 to 320-1). If the selected entry 211 is associated with a node 311 within the highest level 320 of the data structure 310, the process continues at 1206; otherwise, the process continues at 1208. At 1206, the current address range of the selected entry 211 can be retained (unchanged). Alternatively, the address range of the selected entry 211 can be extended by an in-layer upgrade operation (in combination with Figure 12 - 2 an example of the in-layer upgrade operation disclosed in more detail).

[0174] At 1208, the management logic 226 configures the specified entry 211 of the data set 210 to cover the address range defined by the upper-level node 311 identified at 1204 (the parent node of the node 311 associated with the selected entry 1202). The specified entry 211 can be configured to cover an address space larger than the address space covered by the selected entry 211. The address space covered by the specified entry 211 can include the address space covered by the selected entry 211.

[0175] At 1210, the access metadata 112 of the selected entry 211 and the access metadata 112 of the sibling entries 211 of the selected entry 211 (if any) are used to populate the access metadata 112 of the specified entry 211. The sibling entries 211 can be identified as the entries 211 associated with sibling nodes 311 within the node 311 associated with the selected entry. The management logic 226 can merge the selected entry 211 and the sibling entries 211 (if any) into the specified entry 211 associated with the higher-level node 311 (e.g., effectively upgrading the lower-level address range covered by the selected entry 211 to a larger higher-level address range).

[0176] At 1212, the management logic 226 removes the child nodes of the upper-level node 311 from the data structure 310. At 1214, the management logic 226 invalidates and / or removes the entries associated with the child nodes 311 from the data set 210.

[0177] Figure 12 - 2A further example of a method for increasing the size of one or more address ranges covered by access metadata entries 211 of a data set 210 (e.g., upgrading entry 211) is illustrated in flow chart 1201. At 1202, an access metadata entry 211 of data set 210 is selected for upgrading as disclosed herein. At 1207, management logic 226 configures a composite node 311 that combines the node 311 associated with the selected entry 211 with one or more sibling nodes 311 in the same layer 320 as the node 311 within data structure 310. The composite node 311 can be configured to cover an address range corresponding to multiple sub-label values of the layer. Thus, the node label 314 of the composite node 311 can contain multiple sub-label values (as opposed to a single sub-label value of a non-composite node 311). In some embodiments, management logic 226 assigns consecutive sub-label values to the composite node 311.

[0178] At 1209, management logic 226 configures the selected entry 211 to cover the address range defined by the composite node 311. At 1211, management logic 226 merges the access metadata (if any) of the entries associated with the sibling nodes 311 merged into the composite node 311 at 1207 into the access metadata 112 of the selected entry 211. At 1213, the child nodes of the sibling nodes 311 (if any) are removed from the data structure. At 1215, the entries 211 associated with the sibling nodes 311 (if any) are invalidated and / or removed from the data set 210.

[0179] Figure 13 - 1 An example of a method for reducing the size of an address range covered by access metadata 112 is illustrated in flow chart 1300. Figure 13 - 1 An example of an inter-set downgrade or split operation is illustrated. At 1302, an access metadata entry 211 of data set 210 is selected for downgrading. The entry 211 can be selected for downgrading based on a utility metric 213 of the entry 211, which can indicate poor prefetch performance within the address range covered by the entry 211. In response to determining that the utility metric 213 of the entry fails to meet one or more thresholds, the entry 211 can be selected for downgrading.

[0180] At 1304, the management logic 226 determines whether the identified node 311 currently associated with the selected entry 211 is set within the first or lowest layer 320-1 of the data structure 310. If so, the process continues at 1306; otherwise, the process continues at 1308. At 1306, the identified node 311 is removed from the data structure 310, and the corresponding entry 211 is invalidated and / or removed from the data set 210. At 1306, the management logic 226 may also be configured to designate the address range covered by the entry 211 as an untracked address range, which may prevent the adaptive tracking engine 110 from tracking the address range in response to a subsequent tracking miss. The untracked designation may be included in the access metadata 112 provided to a consumer 115, such as the prefetch logic 515, which may prevent the prefetch logic 515 from attempting to perform a prefetch operation within the address range.

[0181] At 1308, the management logic 226 performs a manipulation operation to reduce the size of the covered address range. In Figure 13 - 1 the illustrated example, the management logic 226 implements an inter-layer demotion operation that includes splitting the identified node 311 into a group of one or more nodes 311 (child nodes 311) within the lower layer 320 of the data structure 310 at 1310, each node in the group being configured to cover a corresponding subset of the address range covered by the identified node 311. In some embodiments, the node group 311 is configured to cover the address range of the selected entry 211. Alternatively, the node group 311 may be configured to cover a selected portion of the address range, particularly based on the access metadata of the selected entry 211. The node group 311 may be configured to cover the portion of the address range that is determined to be relatively more active than other portions of the address range and / or corresponds to a relatively higher utility metric 213. The node group 311 may be organized into a sub-structure 312 referenced by the identified node 311. Thus, the identified node 311 can transition from being occupied to open.

[0182] At 1312, the management logic 226 configures the access metadata entry 211 of the data set 210 to cover the address ranges defined by the respective nodes 311 of the node group 311 (and associates the configured entry 211 with the corresponding nodes 311 of the group). At 1314, the management logic 226 populates the access metadata 112 of the configured entry 211 with the access metadata 112 of the selected entry 211. At 1316, the selected entry 211 is invalidated and / or removed from the data set 210.

[0183] Figure 13 - 2 An example of a method for reducing the size of the address range covered by an access metadata entry 211 associated with a composite node 311 of a data structure 310 is illustrated in flowchart 1301. More specifically, Figure 13 - 2Illustrates an example of an in - set demotion or split operation. At 1302, as disclosed herein, an access metadata entry 211 of the data set 210 is selected for demotion. At 1303, the management logic 226 determines whether the selected entry 211 is associated with a composite node 311. If not, the process continues at 1305 where an inter - layer demotion is implemented; otherwise, the process continues at 1311.

[0184] At 1311, the management logic 226 splits the address range covered by the composite node 311 into a first group and a second group. The first group contains a subset of the address range to be covered by the access metadata 112, and the second group contains a subset of the address range to be excluded from the coverage within the access metadata 112. The first group and the second group can be distinguished at least in part based on the access metadata of the selected entry 211. The first group can contain address ranges with a relatively high activity level and / or associated with a relatively high utility metric 213 compared to the second - group address ranges. The management logic 226 can also be configured to create a node 311, which is configured to represent the corresponding address range of the first group within the same layer 320 of the data structure 310 as the composite node 311.

[0185] At 1313, the management logic 226 configures the entry 211 of the data set 210 to cover the corresponding address range of the first - group address range (and the corresponding node 311). At 1315, the configured entry 211 is filled with the access metadata of the selected entry 211. At 1317, the management logic 226 invalidates the entry 211 corresponding to the second - group address range and / or removes it from the data set 210. The management logic 226 can also be configured to remove the composite node 311 from the data structure 310, and invalidate and / or remove the selected entry 211 from its data set 210.

[0186] Figure 14 Illustrates an example flowchart describing operations for merging related access metadata entries of an adaptive tracking engine. At 1402, the management logic 226 of the adaptive tracking engine 110 identifies related entries 211 of the data set 210 suitable for merging. As disclosed herein, related entries 211 refer to entries 211 that are sibling nodes. More specifically, sibling or related entries 211 include entries 211 associated with a node 311 that a) are set within the same layer 320 of the data structure 310 and b) have the same upper - level parent node 311. Related entries 211 suitable for merging refer to related entries 211 having similar utility metrics 213 with each other (e.g., having utility metrics 213 that differ by less than a threshold). Related entries 211 can be identified during a background scan operation, as disclosed herein.

[0187] At 1404, the management logic 226 configures the destination entry 211 to override the address range defined by the upper-level parent node 311 of the identified entry 211. At 1406, the access metadata of the related entry 211 is merged into the access metadata of the destination entry 211 (e.g., by averaging, aggregating, and / or otherwise combining the access metadata of the related entry 211 into the destination entry 211). At 1408, the management logic 226 removes the child nodes of the upper-level parent node 311 from the data structure 310, including the node 311 associated with the related entry 211 identified at 1402 (and the child nodes of the related entry 211, if any). At 1410, the entry 211 associated with the child nodes of the upper-level parent node 311 is invalidated and / or removed from the data set 210 as disclosed herein.

[0188] Figure 15 A further example of a method for implementing an apparatus for adaptive address tracking is illustrated in flowchart 1500. At 1502, a first logic 624 of the adaptive tracking engine 110 configures a first memory 608 to store access metadata 112 related to an address space within an entry 211 of the data set 210.

[0189] At 1504, the first logic 624 updates the access metadata of the corresponding entry 211 of the data set 210 in response to a command 201 related to an address covered by the address range of the corresponding entry 211. In response to the command 201 related to the address 202, the first logic 624 may utilize search logic 625 to locate the access metadata entry 211. The search logic 625 may be implemented in hardware and is capable of comparing the address 202 (and / or portions thereof) with multiple entries 211 of the data set 210 at least partially in parallel. At 1504, the first logic 624 may also be configured to provide the access metadata 112 and / or portions thereof to a consumer 115 such as a prefetch logic 515. The prefetch logic 515 may utilize the access metadata 112 to notify prefetch operations within the address range covered by the access metadata 112 and return a feedback 204 indicating the utility of the prefetch operations performed within the corresponding address range.

[0190] At 1506, a second logic 626 of the adaptive tracking engine 110 maintains a data structure 310 within a second memory 618, the data structure 310 being configured to define a set of address ranges covered by the entries 211 of the data set 210 held within the first memory 608, each entry 211 of the data set 210 being associated with a corresponding node 311 of the data structure 310 that defines the address range covered by accessing the entry 211 within the data set 210.

[0191] At 1508, the second logic 626 modifies the set of address ranges covered by the access data set 210 maintained within the first memory 608, at least in part, based on the utility metric of the corresponding entry 211 of the data set 210. The second logic 626 can include management logic 226 that changes the data structure 310 within the second memory 618 to, in particular, modify the address ranges defined thereby and propagates the modification to the access data set 210 maintained within the first memory 608. The management logic 226 can reconfigure the access metadata entries 211 of the data set 210 to cover the corresponding address ranges of the modified set of address ranges defined by the changed data structure 310. The process can continue with the first logic 624 updating the access metadata 211 (at 1504) in response to a command 201 related to an address 202 covered by the corresponding address ranges of the modified set of address ranges, and the interface 222 providing the access metadata 112 (and / or portions thereof) to a consumer 115, such as a prefetch logic 515, which utilizes the access metadata 112 to effectuate a prefetch operation within the address ranges covered by the respective access metadata entries 211 and provides feedback related to the prefetch utility of the corresponding entries 211.

[0192] Figure 16The operation of adapting the size of the address range covered by access metadata is illustrated in the flowchart 1600 through an example implementation of the adaptive tracking engine 110. Adjusting the size of the address range may include adjusting the set of address ranges covered by the access metadata 112 (and / or the corresponding entries 211 of the data set 210). At 1602, as disclosed herein, the adaptive tracking engine 110 implements address tracking. At 1602, the update logic 224 of the adaptive tracking engine 110 captures, updates, and / or otherwise maintains the access metadata 112 within the corresponding entry of the data set 210 in particular response to a command 201 related to the address 202 covered by the corresponding entry 211. As disclosed herein, the set of address ranges covered by the access metadata entry 211 may be defined by the data structure 310. At 1602, the management logic 226 of the adaptive tracking engine 110 creates a node 311 within the data structure 310 in response to a tracking miss, and encodes the relationships between the corresponding nodes 311 to represent the relationships between the address ranges covered by the corresponding nodes 311. In some embodiments, the utility metric 213 of the corresponding entry 211 of the data set 210 (and / or the corresponding node 311 of the data structure 310) is determined, updated, and / or modified at least in part based on feedback 204 related to prefetch performance within the address range covered by the corresponding entry 211. Thus, at 1602, the adaptive tracking engine 110 may develop an access metadata configuration 725 that in particular defines the set of address ranges covered by the access metadata 112 captured and / or maintained thereby. In some embodiments, the data structure 310 and the data set 210 are maintained in separate structures and / or memory components. In some instances, the access metadata entries 211 of the data set 210 are maintained in a first memory 608, while the data structure 310 is maintained in a second memory 618.

[0193] At 1604, the management logic 226 (and / or the adaptive logic 726) of the adaptive tracking engine 110 determines whether to evaluate the access metadata configuration 725. The determination may be based on whether the adaptive tracking engine 110 can implement one or more background operations in particular based on the availability of idle resources, whether the adaptive tracking engine 110 has received and / or is implementing one or more foreground operations, etc. Alternatively or additionally, the determination may be based on a time interval and / or other criteria (e.g., the operation of evaluating and / or adjusting the access metadata configuration 725 may be implemented periodically, even not in a background operation). In some embodiments, the adaptation logic 726 may determine at 1604 whether to implement an iteration of the optimization process, which may be based on whether one or more termination criteria of the optimization process have been met, as disclosed herein. If the determination at 1604 is to evaluate the access metadata configuration 725 (e.g., implement an optimization operation), the process continues at 1606; otherwise, the process continues at 1602.

[0194] At 1606, the adaptive logic 726 quantifies the utility of the access metadata configuration 725 of the adaptive tracking engine 110. The utility of the access metadata configuration 725 can be quantified by and / or within the utility metadata 723, as disclosed herein. The utility metadata 723 can incorporate the utility measures 213 of the respective access metadata entries 211 of the data set 210 (and / or the corresponding nodes 311 of the data structure 310). In some embodiments, the utility measures 213 can be weighted and / or adjusted based on one or more criteria such as address range size, activity level, etc.

[0195] At 1608, the adaptive logic 726 determines whether to modify the access metadata configuration 725 implemented by the adaptive tracking engine 110. The adaptation logic 726 can determine whether to modify the access metadata configuration 725 based on and / or by using an adaptation strategy. As disclosed herein, the adaptation strategy can define the conditions that trigger a modification to one or more address ranges covered by the access metadata 112. In some embodiments, while the access metadata 112 is configured to cover a first set of address ranges defined by the data structure 310, a first measure 213 is monitored, and after the access metadata 112 is adapted to cover a second set of address ranges different from the first set of address ranges (e.g., after modifying the data structure 310 to define a second address set), a second measure 213 is monitored, and based at least in part on the first measure 213 and the second measure 213, 1608 can include one of the following: adjusting the set of address ranges covered by the access metadata 112 such that the access metadata 112 reverts to covering the first set of address ranges (e.g., modifying the data structure 310 to revert to defining the first set of address ranges), continuing to operate with the access metadata 112 configured to cover the second set of address ranges, or adjusting the set of address ranges covered by the access metadata 112 such that the access metadata 112 covers a third set of address ranges different from the first set of address ranges and the second set of address ranges (e.g., modifying the data structure 310 to define a third set of address ranges).

[0196] Alternatively or additionally, the determination at 1608 can be based on an optimization model defined by and / or within the configuration data 524 of the adaptive tracking engine 110. The optimization model can implement an optimization algorithm or technique that is configured to balance the utility of each access metadata configuration 725 with the corresponding cost, which can be quantified in terms of resource utilization as disclosed herein. The optimization model can be configured to iteratively converge to an optimal access metadata configuration 725 (and / or a local or approximate optimal access metadata configuration 725) that produces the best utility at the lowest cost. The adaptation logic 726 can be configured to iteratively modify the access metadata configuration 725 via the optimization model (based on the determinations at 1604 and 1608) until an optimal access metadata configuration 725 is obtained or other termination criteria of the optimization process are satisfied. If the determination at 1608 is to modify the access metadata configuration 725, the process continues at 1610; otherwise, the process returns at 1602 and continues.

[0197] At 1610, the adaptation logic 726 modifies the access metadata configuration 725 (determined at 1608) according to the optimization model. The modification may include but is not limited to: upgrading one or more access metadata entries 211 (extending the address range covered by the extended entry 221), downgrading one or more entries 211 (narrowing the address range covered by the entry 211), removing one or more entries 211, and so on. The management logic 226 implements the modification determined by the adaptation logic 726 within the data structure 310, which may include modifying the set of address ranges defined by the data structure 310. Upgrading the address range of the selected entry 211 may include an inter-level merge operation, in which: a) the entry 211 of the data set 210 is configured to cover the address range defined by the upper parent node 311 of the selected entry 211 (the destination entry 211 for the inter-level merge), b) the access metadata of the entry 211 associated with the child node 311 of the upper parent node 311 that includes the selected entry 211 is merged into the destination entry 211, c) the child node 311 is removed from the data structure 310, and d) the entry 211 associated with the child node 311 is invalidated and / or removed from the data set 210. Alternatively or additionally, upgrading the address range of the selected entry 211 may include an intra-level merge operation, in which a) the node 311 associated with the selected entry 211 is converted into a composite node 311 that combines one or more sibling nodes 311 and / or address ranges within the same level 320 of the data structure, b) the selected entry 211 is configured to cover the extended address range defined by the composite node 311, c) the sibling node 311 is removed from the data structure 310, and d) the entry 211 associated with the sibling node 311 is invalidated and / or removed from the data set 210. Downgrading the address range of the selected entry 211 may include an inter-level split operation, in which: a) one or more child nodes 311 of the node 311 associated with the selected entry 211 are created within the next lower level 320 of the data structure 310, b) the entry 211 of the data set 210 is configured to cover the address range defined by the child node 311, c) the access metadata 112 of the selected entry 211 is copied into the entry 211 associated with the child node 311, and d) the selected entry 211 is invalidated and / or removed from the data set 210. Downgrading the address range of the selected entry 211 in an intra-level split operation may include: a) splitting the composite node 311 associated with the selected entry 211 into one or more non-composite nodes 311 within the same level 320 of the data structure 310 as the composite node 311, b) importing the access metadata 112 of the selected entry 211 into the entry 211 associated with the non-composite node 311, c) removing the composite node 311 from the data structure 310, and d) invalidating and / or removing the selected entry 211 from the data set 210.The address range of the selected entry 211 associated with the lowest layer 320-1 of the degradation and data structure 310 and the non-composite node 311 may include: a) removing the node 311 from the data structure 310, and b) invalidating the selected entry 211 and / or removing it from the data set 210. In some embodiments, the degradation address range also includes designating the address range as untracked within the access metadata 112, which may prevent the adaptive tracking engine 110 from tracking the address range in response to subsequent tracking misses and / or prevent the prefetch logic 515 from attempting to perform prefetch operations within the untracked address range. After implementing the modification at 1610, the process may continue at 1602, where the adaptive tracking engine 110 may perform address tracking operations according to the modified access metadata configuration 725.

[0198] Example System for Adaptive Address Tracking

[0199] Figure 17 An example system 1700 for implementing adaptive address tracking is illustrated. The system 1700 includes a device 1710, which may include an adaptive tracking engine 110 and / or components for implementing the adaptive tracking engine 110, as disclosed herein. Figure 17 The description relates to the above aspects, such as the adaptive tracking engine 110, which is depicted in a number of other figures (e.g., Figures 1 - 1 to 5 - 1 and FIGS. 6 through 8). The system 1700 may include an interface 1722, particularly for receiving a command 201 and / or an indication of the command 201 to access data corresponding to an address 202 of a memory address space. The interface 1722 may include circuitry, logic circuitry, interface circuitry, interface logic, switching circuitry, switching logic, routing circuitry, routing logic, interconnect circuitry, interconnect logic, I / O circuitry, analog circuitry, digital circuitry, logic gates, registers, switches, multiplexers, ALUs, state machines, microprocessors, embedded processors, PIM circuitry, logic 220, interface 222, first logic 624, interconnect 105, etc.

[0200] The system 1700 may also include a memory 1708, which may include, but is not limited to: memory, memory devices, memory components, memory circuits, memory arrays, semiconductor memory, memory banks, memory chips, volatile memory, RAM, DRAM, SRAM, SDRAM, DDR memory, non-volatile memory, solid state memory, memory 208, first memory 608, second memory 618, etc.

[0201] In some aspects, system 1700 includes a first component 1720 for storing access metadata 112 in memory 1708 in response to command 201. The access metadata 112 may be stored in an entry 211 of data set 210, and each entry 211 of data set 210 is configured to cover a corresponding address range of a set of address ranges and includes access metadata 112 related to addresses 202 within the covered address range. The first component 1720 may include, but is not limited to: circuitry, logic circuitry, memory interface circuitry, memory interface logic, switching circuitry, switching logic, routing circuitry, routing logic, memory interconnect circuitry, memory interconnect logic, I / O circuitry, analog circuitry, digital circuitry, logic gates, registers, switches, multiplexers, ALUs, state machines, microprocessors, embedded processors, PIM circuitry, logic 220, update logic 224, first logic 624, search logic 625, hardware search logic, hardware search engines, etc.

[0202] In some embodiments, the first component 1720 includes and / or is coupled to a second component 1730 for determining, adjusting, tuning, and / or otherwise managing the set of address ranges covered by the access metadata 112. The second component 1730 may adjust the size of the address range covered by at least one of the entries 211 of data set 210 at least in part based on one or more metrics 213 indicating prefetch performance within one or more of the address ranges of the set of address ranges. The second component 1730 may write one or more bits to memory 1708 to adjust the size of the address range covered by the entry 211 of data set 211 (e.g., one or more bits may be written within the range metadata 214 of entry 211). The second component 1730 may include, but is not limited to: circuitry, logic circuitry, memory interface circuitry, memory interface logic, switching circuitry, switching logic, routing circuitry, routing logic, memory interconnect circuitry, memory interconnect logic, I / O circuitry, analog circuitry, digital circuitry, logic gates, registers, switches, multiplexers, ALUs, state machines, microprocessors, embedded processors, PIM circuitry, logic 220, management logic 226, second logic 626, adaptation logic 726, etc.

[0203] In some aspects, system 1700 includes a prefetcher 1740 that is configured to determine an access pattern within an address range covered by a respective entry 211 of dataset 210 based at least in part on the access metadata 112 of the respective entry 211. The prefetcher 1740 may also be configured to prefetch data based at least in part on the determined access pattern. The prefetcher 1740 may be configured to predict the address 202 of an upcoming command 201 and prefetch the data corresponding to the predicted address 202. The prefetcher 1740 may include, but is not limited to: circuitry, logic circuitry, memory interface circuitry, memory interface logic, switching circuitry, switching logic, routing circuitry, routing logic, memory interconnect circuitry, memory interconnect logic, I / O circuitry, analog circuitry, digital circuitry, logic gates, registers, switches, multiplexers, ALUs, state machines, microprocessors, embedded processors, PIM circuitry, hardware prefetcher, prefetch circuitry, prefetch logic, cache logic, stride prefetcher, correlation prefetcher, ML prefetcher, LSTM prefetcher, logic 220, etc.

[0204] The first component 1720 may be configured to provide the access metadata 112 of the entry 211 of the dataset 210 to a consumer 115 such as the prefetcher 1740. A metric 213 associated with the entry 211 and / or the address range covered by the entry 211 may be set, determined, and / or monitored based at least in part on the prefetch performance within the address range covered by the entry 211. In some embodiments, the second component 1730 sets, determines, and / or monitors a metric 213 indicative of the prefetch performance within the address range covered by the access metadata 112 held within the respective entry 211 of the dataset 210. The metric 213 may be based at least in part on feedback 204 from one or more consumers 115 of the access metadata 112 such as the prefetcher 1740, etc.

[0205] The second component 1730 may be configured to adjust the size of the address range covered by the entry 211 of the dataset 210 based at least in part on the prefetch performance within the address range. The second component 1730 may increase the size of the address range covered by the first entry 211 of the dataset 210 in response to the metric 213 of the first entry 211 exceeding a first threshold. Conversely, the second component 1730 may decrease the size of the address range covered by the first entry 211 of the dataset 210 in response to the metric 213 of the first entry 211 falling below a second threshold.

[0206] In some embodiments, the second component 1730 is configured to modify the set of address ranges covered by an entry 211 of the data set 210, particularly by manipulating a node 311 associated with the entry 211 within the data structure 310. The second component 1730 may be configured to combine a first entry 211 of the data set 210 with a second entry 211 of the data set 210 in response to determining that a metric 213 of the first entry 211 is within a threshold of a metric 213 of the second entry 211. The second component 1730 may be configured to split a selected entry 211 of the data set 210 into two or more entries 211, each of the two or more entries 211 covering an address range smaller than the address range covered by the selected entry 211, in response to determining that a metric 213 of the selected entry 211 is below the threshold. Alternatively or additionally, the second component 1730 may invalidate an entry 211 of the data set 210 in response to the metric 213 of the entry 211 failing to meet the threshold.

[0207] In some aspects, the data structure 310 includes multiple levels 320, each level 320 corresponding to a respective range size among a plurality of range sizes. The data structure 310 may include a first level 320-1 corresponding to entries 211 having a first range size and a second level 320-2 corresponding to entries 211 having a second range size greater than the first range size. The first component 1720 (and / or the second component 1730) may be configured to map an address 202 to an entry 211 that covers the address 202 via the data structure 310. The second component 1730 may map an address 202 to an entry 211 (and / or a node 311 of the data structure 310) via the multiple levels 320 of the data structure 310, e.g., from a top level 320-N to the bottommost level 320-1. The data structure 310 may include one or more of a lookup table, a mapping table, a multi-level mapping table, a trie, a tree, a prefix tree, or a radix tree.

[0208] In some embodiments, the entry 211 of the data set 210 is maintained within the node 311 of the data structure 310. Each node 311 within the first layer 320-1 of the data structure 310 may contain entries 211 of a first range size. Each node 311 in the second layer 320-2 may include: a) entries 211 of a second range size, or b) a reference to a sub-structure 312 that includes one or more nodes 311 within the first layer 320-1 of the data structure 310. The interface 1722 may be configured to receive an indication of the command 201 related to the address 202, and in response, the first component 1720 (and / or the second component 1730) may search the second layer 320-2 of the data structure 310 to select a node 311 of the second layer 320-2 having second tag data that matches the address 202. If the selected node 311 contains an entry 211 of the data set 210, the access metadata 122 of the entry 211 may be updated in response to the command 201. Alternatively, if the selected node 311 references a sub-structure 312, the sub-structure 312 may be searched to identify a node 311 of the first layer 320-1 having first tag data that matches the address 202.

[0209] The second component 1730 may determine that the specified address 202 is outside the address range covered by the data set 210, and in response, map a first node 311 of the first layer 320-1 of the data structure 310 to a first tag corresponding to a first portion of the specified address 202, the first node 311 defining a first address range of the first range size that covers the specified address. A second node 311 of the second layer 320-2 of the data structure 310 may be mapped to a second tag corresponding to a second portion of the specified address 202, the second node 311 referencing the first node 311. The second component may associate the specified entry 211 of the data set 210 with the first node 311 and configure the specified entry 211 to cover the first address range defined by the first node 311.

[0210] In some embodiments, the second component 1730 is also configured to combine or merge groups of entries 211 of the data set 210. The second component 1730 may select entries 211 of a first range size having a metric 213 that meets a threshold. The selected entries 211 may be associated with a first node 311 within a first layer 320-1 of the data structure 310, and the first node 311 has the same parent node 311 within a second layer 320-2 (second node 311) of the data structure 310. Combining the selected entries 211 may include associating the second node 311 with a designated entry 211 of the data set 210, configuring the designated entry 211 to cover the address range defined by the second node 311, merging the access metadata 112 of the selected entries 211 into the access metadata 112 of the designated entry 211, removing the first node 311 from the data structure 310, and / or invalidating the selected entries 211.

[0211] The second component 1730 may also be configured to identify entries 211 of the data set 210 having a metric 213 below the threshold, where the identified entries 211 cover an address range of a second range size and are referenced by a designated node 311 within a second layer 320-2 of the data structure 310. In response, the second component 1730 may create a set of nodes 311 within a first layer 320 of the data structure 310, where each node 311 of the set covers a respective portion of the address range covered by the designated node 311, copy the access metadata 112 of the identified entries 211 within entries 211 corresponding to the respective nodes 311 of the set, and / or configure the designated node 311 to reference the set of nodes 311 created within the first layer 320 of the data structure 310. Alternatively or additionally, the second component 1730 may identify entries 211 of the data set 210 that have a metric 213 below the threshold and cover an address range defined by a node 311 within a first layer 320 of the data structure 310. In response, the second component 1730 may be configured to invalidate the identified entries 211 and / or remove the corresponding node 311 from the data structure 310.

[0212] In some embodiments, the first component 1720 stores access metadata 112 (e.g., data set 210) in a first memory 608, while the second component 1730 maintains the data structure 310 in a second memory 618. The first memory 608 may be different and / or separate from the second memory 618. Alternatively, the access metadata 112 (e.g., data set 210) and the data structure 310 may be maintained in the same memory (such as Figure 2 the memory 208 shown). In some aspects, the data set 210 may be stored with and / or within the data structure 310. For example, entries 211 of the data set 210 may be maintained in respective nodes 311 of the data structure 310.

[0213] Figure 18 An example system 1800 for implementing adaptive address tracking is illustrated. As disclosed herein, system 1800 may include a device 1810, which may include an adaptive tracking engine 110 and / or components for implementing the adaptive tracking engine 110. Figure 18 The description relates to the above aspects, such as the adaptive tracking engine 110, which is depicted in a number of other figures (e.g., Figures 1 - 1 to 5 - 1 5 and 6 to 8). System 1800 may include a component 1812 configured to represent an address range of a memory address space through nodes 311 within multiple levels 320 of a data structure 310, each of the multiple levels 320 of the data structure 310 corresponding to an address range size among a plurality of address range sizes. The component 1812 may maintain access metadata 112 within an entry 211 of a data set 210, each entry 211 of the data set 210 being associated with a corresponding node 311 of the data structure 310 and covering the address range represented by the associated node 311. In some aspects, the component 1812 is further configured to modify the data structure 310 at least in part based on a metric 213 related to prefetch performance and to update at least one address range covered by at least one of the entries 211 of the data set 210 in response to modifying the data structure 310. The component 1812 may include, but is not limited to: circuits, logic circuits, memory interface circuits, memory interface logic, switch circuits, switch logic, routing circuits, routing logic, memory interconnect circuits, memory interconnect logic, I / O circuits, analog circuits, digital circuits, logic gates, registers, switches, multiplexers, ALUs, state machines, microprocessors, embedded processors, PIM circuits, logic 220, update logic 224, management logic 226, first logic 624, second logic 626, search logic 625, hardware search logic, hardware search circuits, hardware search engines, adaptation logic 726, memories 208, memory 1708, first memory 608, second memory 618, etc.

[0214] In some aspects, system 1800 includes interface 1722 for receiving information about command 201 (and / or an indication of command 201) associated with a memory address space, providing access metadata 112 to one or more consumers 115 (such as prefetcher 1740), and / or receiving feedback 204 related to prefetch performance within an address range covered by the provided access metadata 112, as disclosed herein. Component 1812 may also be configured to determine a metric 213 related to prefetch performance based at least in part on feedback 204. In some embodiments, component 1812 sets, determines, and / or monitors a metric 213 related to prefetch performance within an address range represented by a corresponding node 311 of data structure 310 (and / or within an address range covered by a corresponding entry 211 of data set 210).

[0215] In some embodiments, component 1812 includes and / or is coupled to a first component 1820 for storing, updating, and / or maintaining data set 210 including access metadata 112 in a first memory 608. The first component 1820 may be configured to store and / or update the access metadata 112 of a corresponding entry 211 of data set 210 in response to command 201 related to an address 202 within an address range covered by the corresponding entry 211 (and / or in response to an indication and / or information related to command 201). The first component 1820 may also be configured to map address 202 to an entry 211 of data set 210 (e.g., a lookup entry 211 of data set 210 corresponding to the specified address 202). The first component 1820 may include, but is not limited to: circuitry, logic circuitry, memory interface circuitry, memory interface logic, switching circuitry, switching logic, routing circuitry, routing logic, memory interconnect circuitry, memory interconnect logic, I / O circuitry, analog circuitry, digital circuitry, logic gates, registers, switches, multiplexers, ALUs, state machines, microprocessors, embedded processors, PIM circuitry, logic 220, update logic 224, first logic 624, search logic 625, hardware search logic, hardware search circuitry, hardware search engines, etc.

[0216] In some aspects, component 1812 includes and / or is coupled to a second component 1830 for maintaining a data structure 310 within a second memory 618, modifying a set of address ranges represented by nodes 311 of the data structure 310, and / or configuring entries 211 of a data set 210 stored within a first memory 608 to cover the modified set of address ranges represented by nodes 311 of the data structure 310. The second component 1830 may be configured to modify the set of address ranges at least in part based on a metric 213 related to prefetch performance. The second component 1830 may be configured to determine and / or monitor a metric 213 related to prefetch performance within an address range represented by a respective node 311 of the data structure 310 (and / or covered by access metadata 112 held within a respective entry 211 of the data set 210), and modify the set of address ranges at least in part based on the metric 213 of one or more address ranges. The second component 1830 may include, but is not limited to: circuitry, logic circuitry, memory interface circuitry, memory interface logic, switching circuitry, switching logic, routing circuitry, routing logic, memory interconnect circuitry, memory interconnect logic, I / O circuitry, analog circuitry, digital circuitry, logic gates, registers, switches, multiplexers, ALUs, state machines, microprocessors, embedded processors, PIM circuitry, logic 220, management logic 226, second logic 626, adaptation logic 726, etc.

[0217] In some aspects, component 1812 (and / or component 1830) is configured to merge selected nodes 311 of the data structure 310. Merging the selected nodes 311 may include configuring a target node 311 of the data structure 310 to represent an address range spanning the address ranges represented by each of the selected nodes 311, configuring entries 211 of the data set 210 to cover the address range represented by the target node 311, and / or invalidating entries 211 associated with the selected nodes 311 within the data set 210. In some embodiments, the access metadata 112 of entries 211 associated with the selected nodes 311 may be combined into the access metadata 112 of the entry 211 associated with the target node 311.

[0218] In some instances, component 1812 (and / or component 1830) incorporates selected node 311 within the first layer 320-1 of data structure 310. Node 311 can be selected based at least in part on prefetch performance within the address range covered by the selected node 311. The selected node 311 can be incorporated into a parent node 311 within the second layer 320-2 of data structure 310, where the second layer 320-2 is higher in the hierarchy defined by data structure 310 than the first layer 320-1. Incorporating the selected node 311 can include configuring entry 211 of dataset 210 associated with the parent node 311 to cover the address range represented by the parent node 311, incorporating access metadata 112 of entry 211 associated with the selected node 311 into the configured entry 211, and / or invalidating entry 211 of dataset 210 associated with a child node 311 of the parent node 311 within data structure 310.

[0219] Component 1812 (and / or component 1830) can also be configured to split a node 311 of data structure 310 into a group of two or more nodes 311. Node 311 can be selected based at least in part on prefetch performance within the address range represented by the node 311. Splitting the selected node 311 can include configuring a group of two or more nodes 311 to represent respective subsets of the address range represented by the selected node, configuring entry 211 of dataset 210 to cover the address range represented by each node 311 within the group of two or more nodes 311, and / or invalidating entry 211 associated with the selected node 311 within dataset 210. Additionally, access metadata 112 of entry 211 associated with the selected node 311 can be replicated within entry 211 associated with each node 311 within the group of two or more nodes 311. In some embodiments, a group of two or more nodes 311 can be created within a sub-structure 312 set within the lower layer 320 of data structure 310, where the lower layer 320 corresponds to an address range size smaller than the address range size of the upper layer 320 of data structure 310 that includes the selected node 310. The selected node 311 can be designated as the parent node 311 of each node 311 within the group of two or more nodes 311 within data structure 310. Alternatively, a group of two or more nodes 311 can be created within the same layer 320 of data structure 310 as the selected node 311, and the parent node 311 of the selected node 311 can be designated as the parent node 311 of each node 311 within the group of two or more nodes 311 within data structure 310.

[0220] In some aspects, component 1812 (and / or second component 1830) is further configured to remove selected node 311 from data structure 310 at least in part based on prefetch performance within the address range represented by selected node 311. Removing the selected node 311 may include invalidating entry 211 of data set 310 associated with the selected node 311. In some embodiments, removing the selected node 311 also includes associating the address range represented by the selected node 311 with a no-track indicator configured to prevent subsequent creation of one or more nodes 311 representing an address range within data structure 310 (and / or prevent creation of entry 211 including access metadata 112 covering the address range within data set 210).

[0221] In some embodiments, component 1812 (and / or second component 1830) is configured to add node 311 to the first layer 320-1 of data structure 310 in response to determining that a specified address 202 is not covered by entry 211 of data set 210. Node 311 may be configured to represent an address range that includes the specified address 202. Adding node 311 may also include configuring the first entry 211 of data set 210 to cover the address range represented by node 311. Adding node 311 may also include establishing one or more parent-child relationships between node 311 and one or more parent nodes 311 within at least one upper layer 320 of data structure 310. Data structure 310 may be configured to establish parent-child relationships between nodes 310 within the respective layers 320 of data structure 310. The parent-child relationships between nodes 311 may define and / or correspond to relationships between the address ranges represented by nodes 311. In some aspects, each child node 311 of a parent node 311 may be configured to represent a respective subset of the address range represented by the parent node 311. Adding node 311 to the first layer 320-1 of data structure 310 may include establishing a parent-child relationship between node 311 and a parent node 311 (designated node 311) within the second layer 320-2 of data structure 310. In the hierarchy defined by data structure 320, the second layer 320-2 may be adjacent to the first layer 320-1. The second layer 320-2 may correspond to an address range size that is larger than the address range size of the first layer 320-1. The address range represented by node 311 may be a subset of the address range represented by the designated node 311.

[0222] In some aspects, component 1812 (and / or second component 1830) is also configured to upgrade node 311 from the first level 320-1 of data structure 310 to the second level 320-1. Node 311 may be selected for upgrade based at least in part on prefetch performance within the address range represented by node 311. Upgrading node 311 may include configuring entry 211 of data set 210 to cover the address range represented by the specified node 311 and / or associating entry 211 with the parent node of the specified node 311 (node 311 within the second level 320-2 of data structure 310). In some embodiments, upgrading node 311 includes modifying first entry 211 to cover a larger address range represented by the specified node 311. Alternatively, second entry 211 of data set 210 may be configured to cover the address range represented by the specified node 311. Upgrading node 311 may also include merging access metadata 112 of first entry 211 into access metadata 112 of second entry 211 and / or invalidating first entry 211 within data set 210.

[0223] Conclusion

[0224] Although embodiments for adaptive address tracking are described in language specific to certain features and / or methods, the subject matter of the appended claims need not be limited to the specific features or methods described. Rather, specific features and methods are disclosed as example embodiments for adaptive address tracking.

Claims

1. A method, comprising: representing an address range of a memory address space by nodes within multiple levels of a data structure, each of the multiple levels of the data structure corresponding to an address range size among multiple address range sizes; maintaining access metadata within entries of a data set, each entry of the data set being associated with a corresponding node of the data structure and covering the address range represented by the associated corresponding node; modifying the data structure at least in part based on one or more metrics related to prefetch performance, including updating references to at least one node of the data structure that references the corresponding entry of the data set; responsive to modifying the data structure, updating at least one address range covered by at least one of the entries of the data set, the at least one of the entries including the corresponding entry of the data set; removing the selected node from the data structure at least in part based on at least one metric related to prefetch performance within the address range represented by the selected node; invalidating the entry of the data set associated with the selected node; and associating the address range represented by the selected node with a no-tracking indicator configured to prevent subsequent creation of one or more nodes representing the address range within the data structure.

2. The method of claim 1, further comprising: responsive to determining that a specified address is not covered by the entries of the data set, adding a node to a first level of the multiple levels of the data structure, the node being configured to represent an address range that includes the specified address; and configuring a first entry of the data set to cover the address range represented by the node.

3. The method of claim 2, further comprising establishing one or more parent-child relationships between the node and one or more parent nodes within at least one upper level of the data structure, including a relationship between the node and a specified node within a second level of the data structure adjacent to the first level, the second level corresponding to an address range size larger than the address range size of the first level, such that the address range represented by the node is a subset of the address range represented by the specified node.

4. The method of claim 3, further comprising: upgrading the node from the first level of the data structure to the second level at least in part based on a metric related to prefetch performance within the address range represented by the node; configuring a second entry of the data set to cover the address range represented by the specified node; and removing the node from the data structure.

5. The method of claim 4, further comprising: merging the access metadata of the first entry into the access metadata of the second entry; and invalidating the first entry.

6. The method of claim 1, further comprising: accessing metrics related to prefetch performance within the address range represented by a corresponding node of the data structure during a background scan operation; and Select one or more nodes of the data structure for modification based at least in part on accessed metrics.

7. The method according to claim 1, further comprising: Merging the selected nodes of the data structure into a target node of the data structure, the target node representing an address range spanning the address ranges represented by each of the selected nodes; Configuring entries of the data set to cover the address range represented by the target node; And Invalidating the entries associated with the selected nodes in the data set.

8. The method according to claim 7, further comprising combining access metadata of the entries associated with the selected nodes into access metadata of the entries configured to cover the address range represented by the target node.

9. The method according to claim 1, further comprising: Selecting nodes within a first layer of the data structure, at least in part based on metrics related to prefetch performance within the address range represented by the selected nodes; Merging the selected nodes into a parent node within a second layer of the data structure, the second layer being higher in the hierarchy defined by the data structure than the first layer; Configuring entries of the data set associated with the parent node to cover the address range represented by the parent node; Merging access metadata of the entries associated with the selected nodes into the configured entries; And Invalidating the entries of the data set associated with child nodes of the parent node within the data structure.

10. The method according to claim 1, further comprising: Splitting the selected node into a group of two or more nodes, at least in part based on at least one metric related to prefetch performance within the address range represented by the selected node, each of the two or more nodes in the group being configured to represent a respective subset of the address range represented by the selected node; Invalidating the entries associated with the selected node in the data set; And Configuring entries of the data set to cover the address ranges represented by the nodes in the group of two or more nodes of the data structure.

11. The method according to claim 10, further comprising replicating access metadata of the entries of the data set associated with the selected node within the entries of the data set associated with the group of two or more nodes.

12. The method according to claim 10, further comprising: Arranging the group of two or more nodes within a sub-structure disposed within a lower layer of the data structure, the lower layer corresponding to an address range size smaller than the address range size of the upper layer of the data structure including the selected node; And Designating the selected node as the parent node of the group of two or more nodes within the data structure.

13. The method according to claim 10, further comprising: Creating the group of two or more nodes within the first layer of the data structure; Configure each node in the group of the two or more nodes to represent a corresponding subset of the address range represented by the selected node; and Designate the parent node of the selected node as the parent node of each node in the group of the two or more nodes within the data structure.

14. The method according to claim 1, further comprising maintaining the no-tracking indicator within the data structure.

15. An apparatus comprising: a memory; an interface configured to receive an indication of a command involving an address of a memory address space; and logic coupled to the memory and the interface, the logic configured to: Maintain a data structure within the memory, the data structure configured to represent an address range of the memory address space by nodes within a plurality of levels of the data structure, each of the plurality of levels corresponding to an address range size among a plurality of address range sizes; Store access metadata in the memory in response to the indication, the access metadata stored within an entry of a data set, each entry of the data set being associated with a corresponding node of the data structure and covering the address range represented by the associated corresponding node; Modify the data structure at least in part based on at least one metric related to prefetch performance within one or more of the address ranges represented by the data structure, including by updating a reference of at least one node of the data structure that references the corresponding entry of the data set; Update at least one address range covered by at least one of the entries of the data set in response to the modification of the data structure, the at least one of the entries including the corresponding entry of the data set; Remove the selected node from the data structure at least in part based on a metric related to prefetch performance within the address range represented by the selected node; Invalidate the entry of the data set associated with the selected node; and Associate the address range represented by the selected node with a no-tracking indicator configured to prevent subsequent creation of one or more nodes representing the address range within the data structure.

16. The apparatus according to claim 15, wherein the logic is further configured to determine the at least one metric related to prefetch performance at least in part based on feedback received from a consumer of the access metadata, the consumer including one or more of a cache, a cache memory, cache control logic, cache prefetch logic, prefetch logic, or a prefetcher.

17. The apparatus according to claim 15, wherein the logic is further configured to: Implement a prefetch operation within one or more address ranges of the memory address space at least in part based on the access metadata; and Determine the at least one metric related to prefetch performance at least in part based on the prefetch operation implemented within the one or more address ranges.

18. The apparatus according to claim 15, wherein the logic includes: A first logic configured to store the access metadata of a particular entry of the data set in a first memory; and A second logic configured to hold a particular node of the data structure in a second memory, the second memory being different from the first memory, the particular entry of the data set being associated with the particular node of the data structure.

19. The apparatus according to claim 18, wherein the second logic is further configured to: Access one or more metrics related to prefetch performance within an address range represented by a corresponding node of the data structure; Modify, at least in part based on the one or more accessed metrics, the set of address ranges represented by the data structure; and Configure the entries of the data set to cover the modified set of address ranges represented by the data structure.

20. The apparatus according to claim 15, wherein the logic is further configured to: Merge a selected node of the data structure into a target node of the data structure, the target node representing an address range spanning the address ranges represented by each of the selected nodes; Configure a designated entry of the data set to cover the address range represented by the target node; Combine the access metadata of the entries of the data set associated with the selected node into the access metadata of the designated entry; and Invalidate the entries of the data set associated with the selected node.

21. The apparatus according to claim 15, wherein the logic is further configured to: Select a node within a first layer of the data structure, at least in part based on one or more metrics related to prefetch performance within an address range represented by the selected node; Merge the selected node into a parent node within a second layer of the data structure, the second layer being higher in the hierarchy defined by the data structure than the first layer; Configure the entry of the data set associated with the parent node to cover the address range represented by the parent node; Merge the access metadata of the entry associated with the selected node into the configured entry; and Invalidate the entries of the data set associated with the child nodes of the parent node within the data structure.

22. The apparatus according to claim 15, wherein the logic is further configured to: Split the selected node of the data structure into a group of two or more nodes, at least in part based on prefetch performance within an address range represented by the selected node, each of the two or more nodes of the group being configured to represent a corresponding subset of the address range represented by the selected node; Invalidate the entries of the data set associated with the selected node; and Configure the entries of the data set to cover the address ranges represented by the nodes within the group of two or more nodes of the data structure.

23. The apparatus according to claim 22, wherein the logic is further configured to replicate, within access metadata of an entry of the data set associated with a group of the two or more nodes, the access metadata of the entry of the data set associated with the selected node.

24. The apparatus according to claim 22, wherein the logic is further configured to: arrange the group of the two or more nodes within a sub-structure in a lower layer of the data structure, the lower layer corresponding to an address range size smaller than an address range size of an upper layer of the data structure that includes the selected node; and designate the selected node as a parent node of the group of the two or more nodes within the data structure.

25. The apparatus according to claim 22, wherein the logic is further configured to: create a group of the two or more nodes within a first layer of the data structure; configure each node within the group of the two or more nodes to represent a respective subset of the address range represented by the selected node; and designate a parent node of the selected node as a parent node of each node within the group of the two or more nodes within the data structure.

26. The apparatus according to claim 15, wherein the logic is further configured to maintain the no-track indicator within the data structure.

27. A system, comprising: means for representing an address range of a memory address space by nodes within a plurality of layers of a data structure maintained in a memory, each of the plurality of layers of the data structure corresponding to an address range size among a plurality of address range sizes; means for maintaining access metadata in the memory, the access metadata being maintained within an entry of a data set, each entry of the data set being associated with a respective node of the data structure and covering an address range represented by the associated respective node; means for modifying the data structure at least in part based on at least one metric related to prefetch performance, the modification including updating a reference to at least one node of the data structure that references the respective entry of the data set; and means for updating at least one address range covered by at least one of the entries of the data set in response to the modification of the data structure, the at least one of the entries including the respective entry of the data set, means for: removing the selected node from the data structure at least in part based on a metric related to prefetch performance within an address range represented by the selected node; invalidating an entry of the data set associated with the selected node; and associating the address range represented by the selected node with a no-track indicator configured to prevent subsequent creation of one or more nodes representing the address range within the data structure.

28. The system according to claim 27, further comprising: means for storing the data set including the access metadata in a first memory; A component for holding the data structure in a second memory different from the first memory; A component for modifying a set of address ranges represented by the nodes of the data structure at least in part based on at least one metric related to prefetch performance; And A component for configuring entries of the data set stored in the first memory to cover the modified set of address ranges represented by the nodes of the data structure.

29. The system according to claim 27, further comprising a component for: Merging a selected node of the data structure into a target node of the data structure, the target node representing an address range spanning the address range represented by the selected node; Configuring entries of the data set to cover the address range represented by the target node; and Invalidating entries of the data set associated with the selected node.

30. The system according to claim 27, further comprising a component for: Splitting the selected node into a group of two or more nodes at least in part based on a metric related to prefetch performance within the address range represented by the selected node, each node in the group of two or more nodes being configured to represent a corresponding subset of the address range represented by the selected node within the data structure; Configuring entries of the data set to cover the address ranges represented by the nodes in the group of two or more nodes; Merging access metadata of the entries of the data set associated with the selected node into the configured entries; And Invalidating the entries of the data set associated with the selected node.

31. The system according to claim 27, further comprising a component for holding the untracked indicator in at least one of the data set or the data structure.

Images