Display device

Abstract

A display device includes a pixel, wherein the pixel includes a light emitting element, a first transistor connected to a first power supply line and the light emitting element, and controlled by a voltage of a first node, a second transistor connected to a data line and the first transistor, and controlled by an i-th scan signal, a third-first transistor connected to the first transistor and a second node, and controlled by a first control signal, a third transistor connected to the second node and the first node, and controlled by a second control signal, and a dummy transistor including a first electrode receiving a reference voltage, a second electrode connected to the second node, and a control electrode connected to an emission line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0086866, filed on July 14, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display device capable of reducing leakage current. Background Technology

[0004] Typically, electronic devices such as smartphones, digital cameras, laptops, navigation devices, or smart TVs include a display device for displaying images. The display device generates images, and the user views the generated images through the display screen of the display device.

[0005] The display device includes a plurality of pixels for generating an image and a driver for driving the pixels. Each of the pixels may include a light-emitting element, one or more transistors connected to the light-emitting element, and at least one capacitor connected to the transistor.

[0006] Leakage current can be generated by parasitic capacitors that affect the driving light-emitting elements. Therefore, leakage current may degrade the display quality of the display device. Summary of the Invention

[0007] This disclosure provides a display device capable of reducing leakage current.

[0008] According to an embodiment of the present invention, a display device includes: a pixel, wherein the pixel includes: a light-emitting element; a first transistor including a first electrode connected to a first power line, a second electrode connected to the light-emitting element, and a control electrode connected to a first node; a second transistor including a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to an i-th scan line, wherein i is a natural number greater than 1; a third transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to a second node, and a control electrode receiving a first control signal; a fourth transistor including a first electrode connected to a second node, a second electrode connected to the first node, and a control electrode receiving a second control signal; and a dummy transistor including a first electrode receiving a reference voltage, a second electrode connected to a second node, and a control electrode connected to an emission line.

[0009] The reference voltage can be set to the average voltage value of the data voltages supplied to multiple pixels.

[0010] The reference voltage can correspond to the value obtained by subtracting the threshold voltage of the first transistor from the data voltage applied to the data line.

[0011] The reference voltage can be set to the data voltage applied to the data line.

[0012] The second amplitude corresponding to the second difference between the second high level and the second low level of the second control signal can be smaller than the first amplitude corresponding to the first difference between the first high level and the first low level of the first control signal.

[0013] The second amplitude of the second control signal, corresponding to the second difference between the second high level and the second low level of the second control signal, can be smaller than the first amplitude of the transmit signal applied to the transmit line and the third amplitude of the i-th scan signal applied to the i-th scan line. The first amplitude of the transmit signal can correspond to the first difference between the first high level and the first low level of the transmit signal, and the third amplitude of the i-th scan signal can correspond to the third difference between the third high level and the third low level of the i-th scan signal.

[0014] The first control signal and the second control signal can have the same timing as the i-th scan signal applied to the i-th scan line.

[0015] The pixel may further include: a fourth transistor, including a first electrode connected to a first node, a second electrode receiving an initialization voltage, and a control electrode connected to the (i-1)th scan line; a fifth transistor, including a first electrode connected to a first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the emission line; and a sixth transistor, including a first electrode connected to the second electrode of the first transistor, a second electrode connected to a light-emitting element, and a control electrode connected to the emission line.

[0016] The first control signal can be the same as the second control signal.

[0017] The pixel may further include: a fourth transistor, including a first electrode connected to the second node, a second electrode receiving an initialization voltage, and a control electrode connected to the (i-1)th scan line; a fifth transistor, including a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the emission line; and a sixth transistor, including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the light-emitting element, and a control electrode connected to the emission line.

[0018] The first control signal can be the i-th scan signal applied to the i-th scan line.

[0019] The first control signal can be the same as the second control signal.

[0020] The first activation period of the second control signal can be longer than the second activation period of the (i-1)th scan signal applied to the (i-1)th scan line and the third activation period of the i-th scan signal applied to the i-th scan line. The third activation period of the i-th scan signal and the second activation period of the (i-1)th scan signal can be arranged within the first activation period of the second control signal.

[0021] According to another embodiment of the present invention, a display device includes: a pixel, wherein the pixel includes: a light-emitting element; a first transistor including a first electrode connected to a first power line, a second electrode connected to the light-emitting element, and a control electrode connected to a first node; a second transistor including a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to an i-th scan line, wherein i is a natural number greater than 1; a third transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to a second node, and a control electrode for receiving a control signal; a fourth transistor including a first electrode connected to the second node, a second electrode connected to the first node, and a control electrode for receiving a control signal; and a dummy capacitor including a first electrode for receiving a reference voltage and a second electrode connected to the second node.

[0022] The pixel may further include: a fourth transistor, including a first electrode connected to the second node, a second electrode receiving an initialization voltage, and a control electrode connected to the (i-1)th scan line; a fifth transistor, including a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the emission line; and a sixth transistor, including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the light-emitting element, and a control electrode connected to the emission line.

[0023] The first activation period of the control signal can be longer than the second activation period of the (i-1)th scan signal applied to the (i-1)th scan line and the third activation period of the i-th scan signal applied to the i-th scan line. The third activation period of the i-th scan signal and the second activation period of the (i-1)th scan signal can be arranged within the first activation period of the control signal.

[0024] The control signal may include: a first control signal applied to the control electrode of the third transistor; and a second control signal applied to the control electrode of the third transistor. The second amplitude of the second control signal, corresponding to the second difference between the second high level and the second low level of the second control signal, may be less than the first amplitude of the first control signal, corresponding to the first difference between the first high level and the first low level of the first control signal.

[0025] The pixel may further include: a first connection electrode disposed on and connected to the sixth transistor; a second connection electrode disposed on and connected to the first connection electrode and the light-emitting element; and a dummy electrode disposed in a layer above the first transistor.

[0026] The first electrode of the dummy capacitor may be formed of the same material as the active region of the first transistor, and may be arranged in the same layer as the active region of the first transistor. The second electrode of the dummy capacitor may be formed of the same material as one of the dummy electrode, the first connection electrode, and the second connection electrode, and may be arranged in the same layer as one of the dummy electrode, the first connection electrode, and the second connection electrode.

[0027] The first electrode of the dummy capacitor may be formed of the same material as the control electrode of the first transistor, and may be arranged in the same layer as the control electrode of the first transistor. The second electrode of the dummy capacitor may be formed of the same material as one of the dummy electrode, the first connection electrode, and the second connection electrode, and may be arranged in the same layer as one of the dummy electrode, the first connection electrode, and the second connection electrode. Attached Figure Description

[0028] The accompanying drawings are intended to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0029] Figure 1 This is a perspective view of a display device according to an embodiment of the concept of the present invention;

[0030] Figure 2 yes Figure 1 Block diagram of the display device shown;

[0031] Figure 3 Illustration Figure 2 The equivalent circuit of the pixel shown;

[0032] Figure 4 It is used for driving Figure 3 The timing diagram of the signals of the pixels shown in the figure;

[0033] Figure 5 The figure illustrates the equivalent circuit of a pixel according to another embodiment of the concept of the present invention;

[0034] Figure 6 The figure illustrates the equivalent circuit of a pixel according to another embodiment of the concept of the present invention;

[0035] Figure 7 It is used for driving Figure 6The timing diagram of the signals of the pixels shown in the figure;

[0036] Figure 8 The figure illustrates the equivalent circuit of a pixel according to another embodiment of the concept of the present invention;

[0037] Figure 9 The figure illustrates the equivalent circuit of a pixel according to another embodiment of the concept of the present invention;

[0038] Figure 10 Illustration Figure 9 The parasitic capacitor and the dummy capacitor are illustrated in the figure.

[0039] Figure 11 The figure illustrates the equivalent circuit of a pixel according to another embodiment of the concept of the present invention;

[0040] Figure 12 It is used for driving Figure 11 The timing diagram of the signals of the pixels shown in the figure;

[0041] Figure 13 Exemplary maps include Figure 3 The diagram shows a cross-sectional view of the pixels of the light-emitting element, the first transistor, and the sixth transistor; and

[0042] Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 The illustrations are exemplary cross-sectional views of pixels according to various embodiments of the present invention. Detailed Implementation

[0043] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to that other element or layer, or one or more intermediate elements or layers may exist between them.

[0044] The same reference numerals in the accompanying drawings refer to the same elements. Additionally, the thickness, proportions, and dimensions of the elements are exaggerated in the drawings for the purpose of effective description and technical illustration.

[0045] The term “and / or” includes any and all combinations of one or more related items.

[0046] Terms such as "first" and "second" may be used to describe various components, elements, regions, layers, and / or sections, but these components, elements, regions, layers, and / or sections should not be limited by the terms. These terms are used only to distinguish one component, element, region, layer, and / or section from another component, element, region, layer, and / or section. For example, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component, without departing from the scope of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms such as "a" and "the" may be intended to include the plural forms.

[0047] Additionally, spatial relative terms such as “below,” “lower,” “above,” and “upper” are used to explain the association of items as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the apparatus in use or operation.

[0048] Unless otherwise specified, the terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, it will be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] It will be further understood that, when used in this disclosure, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0050] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention.

[0052] Reference Figure 1 The display device DD may have a rectangular shape, which includes a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the display device DD is not limited to this and may have various other shapes such as circular and polygonal shapes.

[0053] In the following text, the direction that intersects substantially perpendicularly and is perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is referred to as the third direction DR3. Furthermore, in this disclosure, the expression "when viewed in a plan view" refers to the state viewed from the third direction DR3.

[0054] The top surface of the display device DD can also be referred to as the display surface DS extending in the first direction DR1 and the second direction DR2. The image IM generated in the display device DD can be provided to the user through the display surface DS of the display device DD.

[0055] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. An image IM may be displayed in the display area DA, but may not be displayed in the non-display area NDA. The non-display area NDA may define the boundary of the display device DD. The boundary of the display device DD may have a specified color.

[0056] The display device DD can be used in large electronic devices such as televisions, monitors, and outdoor billboards. Alternatively, the display device DD can be a small to medium-sized electronic device such as a personal computer (PC), laptop computer, personal digital assistant (PDA), vehicle navigator, game console, smartphone, tablet computer, or camera. However, these are presented only as embodiments of this disclosure and can be used in other electronic devices without departing from this disclosure.

[0057] Figure 2 yes Figure 1 The block diagram of the display device DD shown is shown.

[0058] Reference Figure 2 The display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a transmit driver EDV, and a timing controller T-CON. The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, and multiple transmit lines EL1 to ELm. Here, m and n are natural numbers.

[0059] Scan lines SL1 to SLm can extend in the second direction DR2 and connect pixel PX and scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 and connect pixel PX and data driver DDV. Transmit lines EL1 to ELm can extend in the second direction DR2 and connect pixel PX and transmit driver EDV.

[0060] A first voltage ELVDD and a second voltage ELVSS can be applied to the display panel DP. The second voltage ELVSS can have a voltage level lower than that of the first voltage ELVDD. The first voltage ELVDD and the second voltage ELVSS can be applied to the pixel PX. The display device DD may further include a voltage generator (not shown) for generating the first voltage ELVDD and the second voltage ELVSS.

[0061] The timing controller T-CON can receive image signals (RGB) and control signals (CS) from an external source (e.g., a system board). The timing controller T-CON can convert the RGB data format of the image signals into another data format compatible with the interface specification of the data driver DDV, and generate image data. The timing controller T-CON can then provide the image data to the data driver DDV.

[0062] In response to an externally provided control signal CS, the timing controller T-CON can generate and output a first control signal CS1, a second control signal CS2, and a third control signal CS3. The first control signal CS1 may include a scan control signal, the second control signal CS2 may include a data control signal, and the third control signal CS3 may include a transmit control signal. The first control signal CS1 may be provided to the scan driver SDV, the second control signal CS2 may be provided to the data driver DDV, and the third control signal CS3 may be provided to the transmit driver EDV.

[0063] The scan driver SDV generates multiple scan signals in response to the first control signal CS1. These scan signals can be applied to pixel PX via scan lines SL1 to SLm. The data driver DDV generates multiple data voltages corresponding to image data DATA in response to the second control signal CS2. These data voltages can be applied to pixel PX via data lines DL1 to DLn. The transmit driver EDV generates multiple transmit signals in response to the third control signal CS3. These transmit signals can be applied to pixel PX via transmit lines EL1 to ELm.

[0064] A pixel (PX) can receive data voltage in response to a scan signal. A pixel (PX) can display an image by emitting light of a brightness corresponding to the data voltage in response to a transmission signal. The emission time of a pixel (PX) can be controlled by the transmission signal.

[0065] Figure 3 Illustration Figure 2 The equivalent circuit of pixel PX shown. Figure 4 It is used for driving Figure 3 The timing diagram of the signal for pixel PX is shown in the figure.

[0066] exist Figure 3The diagram illustrates, for example, a pixel PX (also referred to as PXij) connected to the i-th scan line SLi, the i-th emission line ELi, and the j-th data line DLj. Here, i is a natural number greater than 1 and j is a natural number.

[0067] Reference Figure 3 Pixel PXij may include an OLED light-emitting element, multiple transistors including T1, T2, T3, T3-1, T4, T4-1, T5, T6, T7, and a DMT, and a capacitor CP. The transistors and capacitor CP can control the amount of current flowing through the OLED corresponding to the data voltage Vd received via data line DLj. The OLED can generate light with a specified brightness corresponding to the amount of current.

[0068] Each of the transistors may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience, in this disclosure, either the input electrode or the output electrode is referred to as the first electrode, and the other is referred to as the second electrode.

[0069] The first transistor T1 can be called the driving transistor, and the second transistor T2 can be called the switching transistor. The third transistor T3 and the third-first transistor T3-1 can be collectively referred to as the compensation transistors.

[0070] The fourth transistor T4 and the fourth-to-one transistor T4-1 can be collectively referred to as the first initialization transistor, and the seventh transistor T7 can be referred to as the second initialization transistor. The fifth transistor T5 can be referred to as the emitter control transistor.

[0071] According to one embodiment, the light-emitting element (OLED) can be an organic light-emitting element. The OLED can include an anode (AE) and a cathode (CE). The anode (AE) can be connected to a first power line (PL1) via a sixth transistor (T6), a first transistor (T1), and a fifth transistor (T5). The cathode (CE) can be connected to a second power line (PL2). A first voltage (ELVDD) can be applied to the first power line (PL1), and a second voltage (ELVSS) can be applied to the second power line (PL2). The first power line (PL1) and the second power line (PL2) can be configured in a display panel (DP).

[0072] The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a first electrode connected to the first power line PL1 via the fifth transistor T5, a second electrode connected to the anode AE ​​of the light-emitting element OLED via the sixth transistor T6, and a control electrode connected to the first node N1.

[0073] The first electrode of the first transistor T1 can receive a first voltage ELVDD through the fifth transistor T5. The first transistor T1 can control the amount of current flowing through the light-emitting element OLED according to the voltage applied to the control electrode of the first transistor T1.

[0074] The second transistor T2 can be connected between the data line DLj and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th scan line SL1.

[0075] The second transistor T2 can be turned on by the i-th scan signal received through the i-th scan line SLi, and is electrically connected to the data line DLj and the first electrode of the first transistor T1. The second transistor T2 can perform a switching operation to provide the data voltage Vd received through the data line DLj to the first electrode of the first transistor T1.

[0076] The third transistor T3 and the third-first transistor T3-1 (collectively referred to as the compensation transistor) can be connected between the second electrode of the first transistor T1 and the first node N1. The third-first transistor T3-1 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second node N2, and a control electrode connected to the i-th first control line GCHi. The control electrode of the third-first transistor T3-1 can receive the i-th first control signal through the i-th first control line GCHi.

[0077] The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the first node N1, and a control electrode connected to the i-th second control line GCLi. The third transistor T3 can receive the i-th second control signal through the i-th second control line GCLi.

[0078] The third transistor T3-1 and the third transistor T3 can be turned on in response to the i-th first control signal and the i-th second control signal, respectively, and are electrically connected to the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3-1 and the third transistor T3 are turned on, the first transistor T1 can be connected through the diode of the turned-on third transistor T3-1 and the third transistor T3.

[0079] Despite Figure 3 Not shown, but the i-th first control line GCHi and the i-th second control line GCLi can be connected to the transmit driver EDV. The transmit driver EDV can generate the i-th first control signal and the i-th second control signal, and apply them to the third transistor T3-1 and the third transistor T3 respectively through the i-th first control line GCHi and the i-th second control line GCLi.

[0080] Compensation transistors designed as a dual-gate structure comprising two transistors, T3 and T3-1, can suppress leakage current during off-state. In the dual-gate structure, the two gate electrodes (two control electrodes) can be connected to each other to have the same potential, and their channel length can be extended compared to a single-gate structure. The extended channel length of the compensation transistor may increase resistance, and during off-state, leakage current can be reduced to ensure operational stability.

[0081] The fourth transistor T4 and the fourth-one transistor T4-1 (collectively referred to as the first initialization transistor) can be connected between the first node N1 and the initialization line ITL. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the initialization line ITL via the fourth-one transistor T4-1, and a control electrode connected to the (i-1)th scan line SLi-1. The fourth-one transistor T4-1 may include a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the initialization line ITL, and a control electrode connected to the (i-1)th scan line SLi-1. The initialization line ITL can be set in the display panel DP.

[0082] An initialization voltage Vint can be applied to the initialization line ITL. A voltage generator can generate the initialization voltage Vint. The fourth transistor T4 and the fourth-to-first transistor T4-1 can be turned on by the (i-1)th scan signal received through the (i-1)th scan line SLi-1, and provide the initialization voltage Vint to the first node N1. The first initialization transistor, designed as a dual-gate structure including two transistors T4 and T4-1, can suppress leakage current when turned off.

[0083] The fifth transistor T5 can be connected between the first power line PL1 and the first transistor T1. The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th emitter line ELi.

[0084] The sixth transistor T6 can be connected between the first transistor T1 and the light-emitting element OLED. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE ​​of the light-emitting element OLED, and a control electrode connected to the i-th emission line ELi.

[0085] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th transmitted signal ESi received through the i-th transmitted line ELi. The first voltage ELVDD can be provided to the light-emitting element OLED through the turned-on fifth transistor T5 and sixth transistor T6, and a driving current can flow through the light-emitting element OLED. The light-emitting element OLED emits light according to the driving current.

[0086] The seventh transistor T7 (also referred to as the second initialization transistor) can be connected between the initialization line ITL and the anode AE ​​of the light-emitting element OLED. The seventh transistor T7 may include a first electrode connected to the anode AE ​​of the light-emitting element OLED, a second electrode connected to the initialization line ITL, and a control electrode connected to the i-th scan line SLi. However, embodiments of this disclosure are not limited thereto, and the control electrode of the seventh transistor T7 may be connected to the (i-1)-th scan line SLi-1 or the (i+1)-th scan line SLi+1.

[0087] The seventh transistor T7 can be turned on by the i-th scan signal received through the i-th scan line SLi, and provides the initialization voltage Vint to the anode AE ​​of the light-emitting element OLED. In another embodiment, the seventh transistor T7 can be omitted.

[0088] The seventh transistor T7 can improve the black level performance of pixel PX. When the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the OLED light-emitting element can be discharged. Therefore, the OLED light-emitting element can achieve appropriate black brightness without emitting light due to leakage current from the first transistor T1, and thus improve the black level performance.

[0089] A capacitor CP can be connected between the first power line PL1 and the first node N1. The capacitor CP may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, current can flow through the first transistor T1 based on the voltage stored in the capacitor CP at the first node N1. The current flowing through the first transistor T1 can be determined by the data voltage Vd received through the data line DLj.

[0090] A dummy transistor (DMT) may include a first electrode for receiving a reference voltage Vref1, a second electrode connected to a second node N2, and a control electrode connected to the i-th emitter line ELi. A voltage generator can generate the reference voltage Vref1 with a direct current (DC) voltage.

[0091] exist Figure 3The illustration shows a transistor based on a positive-channel metal-oxide-semiconductor (PMOS), but embodiments of the present invention are not limited thereto. In another embodiment of the present invention, the transistor may be formed based on a negative-channel metal-oxide-semiconductor (NMOS).

[0092] In the following text, reference will be made to Figure 4 The timing diagram in the diagram details the operation of pixel PXij, and each low-level signal is called an activation signal.

[0093] Reference Figure 3 and Figure 4 The i-th transmitted signal ESi, applied to pixel PXij via the i-th transmitted line ELi, can have a high level E-VGH and a low level E-VGL below the high level E-VGH. The period during which the i-th transmitted signal ESi has a low level E-VGL can be referred to as the transmitted period or active period of the i-th transmitted signal ESi. The period during which the i-th transmitted signal ESi has a high level E-VGH can be referred to as the non-transmitted period or inactive period of the i-th transmitted signal ESi.

[0094] The difference between the high level E-VGH and the low level E-VGL can be called the first amplitude ΔV1. The first amplitude ΔV1 can also be called the amplitude of the i-th transmitted signal ESi.

[0095] The (i-1)th scan signal SSi-1 and the ith scan signal SSi applied to pixel PXij via the (i-1)th scan line SLi-1 and the ith scan line SLi can have a high level S-VGH and a low level S-VGL (below the high level S-VGH), respectively. The period during which the (i-1)th scan signal SSi-1 and the ith scan signal SSi have a low level S-VGL can be referred to as the emission period or activation period of the ith scan signal SSi.

[0096] The difference between the high level S-VGH and the low level S-VGL can be called the second amplitude ΔV2. The second amplitude ΔV2 can also be called the amplitude of the (i-1)th scan signal SSi-1 and the amplitude of the i-th scan signal SSi.

[0097] The i-th first control signal GSHi applied to pixel PXij via the i-th first control line GCHi can have a first high level VGH1 and a first low level VGL1 below the first high level VGH1. The period during which the i-th first control signal GSHi has the first low level VGL1 can be referred to as the activation period of the i-th first control signal GSHi.

[0098] The difference between the first high level VGH1 and the first low level VGL1 can be referred to as the third amplitude ΔV3. The third amplitude ΔV3 can also be referred to as the amplitude of the i-th first control signal GSHi.

[0099] The i-th second control signal GSLi, applied to pixel PXij via the i-th second control line GCLi, can have a second high level VGH2 and a second low level VGL2 below the second high level VGH2. The period during which the i-th second control signal GSLi has the second low level VGL2 can be referred to as the activation period of the i-th second control signal GSLi.

[0100] The difference between the second high level VGH2 and the second low level VGL2 can be referred to as the fourth amplitude ΔV4. The fourth amplitude ΔV4 can also be referred to as the amplitude of the i-th second control signal GSLi.

[0101] According to one embodiment, the fourth amplitude ΔV4 can be less than the third amplitude ΔV3. Additionally, the fourth amplitude ΔV4 can be less than the first amplitude ΔV1 and the second amplitude ΔV2. The third amplitude ΔV3 can be the same as either the first amplitude ΔV1 or the second amplitude ΔV2.

[0102] After the (i-1)th scan signal SSi-1 is activated, the ith scan signal SSi can be activated. The ith first control signal GSHi and the ith second control signal GSLi can have the same activation timing as the ith scan signal SSi. For example, the activation periods of the ith first control signal GSHi and the ith second control signal GSLi can overlap with the activation period of the ith scan signal SSi.

[0103] The activated i-th scan signal SSi, i-1-th scan signal SSi-1, i-th first control signal GSHi, and i-th second control signal GSLi can be applied to pixel PXij during the non-emission period. In the following, the operation of applying each signal to the corresponding transistor can indicate the operation of applying the corresponding activated signal to the transistor.

[0104] The (i-1)th scan signal SSi-1 can be applied to turn on the first initialization transistor (i.e., the fourth transistor T4 and the fourth-to-first transistor T4-1). The initialization voltage Vint can be applied to the first node N1 through the fourth transistor T4 and the fourth-to-first transistor T4-1. Therefore, the initialization voltage Vint can be applied to the control electrode of the first transistor T1, and the first transistor T1 can be initialized by the initialization voltage Vint.

[0105] Then, the i-th scan signal SSi can be applied to the second transistor T2 to turn on the second transistor T2. In addition, the i-th first control signal GSHi and the i-th second control signal GSLi can be applied to turn on the third transistor T3-1 and the third transistor T3, respectively.

[0106] Therefore, the first transistor T1 can be connected via the conducting third transistor T3-1 and the diode of the third transistor T3. In this case, a compensation voltage Vd-Vth, obtained by subtracting the threshold voltage Vth of the first transistor T1 from the data voltage Vd supplied through the data line DLj, can be applied to the control electrode of the first transistor T1.

[0107] A first voltage ELVDD and a compensation voltage Vd-Vth can be applied to the first and second electrodes of capacitor CP, respectively. The charge corresponding to the voltage difference between the first and second electrodes can be stored in capacitor CP.

[0108] Then, during the emission period, the i-th emission signal ESi can be applied to the fifth transistor T5 and the sixth transistor T6 through the i-th emission line ELi, and the fifth transistor T5 and the sixth transistor T6 can be turned on. In this case, a drive current Id corresponding to the difference between the first voltage ELVDD and the voltage of the control electrode of the first transistor T1 can be generated. The drive current Id can be provided to the light-emitting element OLED through the sixth transistor T6.

[0109] During the emission period, the gate-source voltage Vgs of the first transistor T1 can correspond to the difference between the first voltage ELVDD and the compensation voltage Vd-Vth, which is expressed as the following equation (1).

[0110] Vgs=ELVDD-(Vd-Vth)…………(1)

[0111] The relationship between the current and voltage of the first transistor T1 can be expressed as the following equation (2). Equation (2) represents the relationship between the current and voltage of a typical transistor.

[0112] Id=(1 / 2)μCox(W / L)(Vgs-Vth) 2 …………(2)

[0113] When equation (1) is substituted into equation (2), the threshold voltage Vth is removed, and the drive current Id can be the square of the value obtained by subtracting the data voltage Vd from the first voltage ELVDD (ELVDD-Vd). 2 Proportional. Therefore, the drive current Id can be determined regardless of the threshold voltage Vth of the first transistor T1. Such an operation can be called threshold voltage compensation operation.

[0114] During non-transmission periods, the voltage of the second node N2 can vary according to the i-th second control signal GSLi. The third transistor T3 may have a parasitic capacitor. When the i-th second control signal GSLi is applied to the third transistor T3, the voltage level of the second node N2 may change at the rising edge Reg of the i-th second control signal GSLi due to the parasitic capacitor of the third transistor T3. This phenomenon can be called capacitor coupling. The rising edge Reg can indicate the time point when the signal changes from a low level to a high level.

[0115] The leakage current in the off state of the third transistor T3 is proportional to the drain-source voltage Vds. When the voltage level of the second node N2 changes, the drain-source voltage Vds of the third transistor T3 may increase, and therefore, the leakage current due to the third transistor T3 may also increase. If the voltage of the second node N2 can be uniformly maintained at a level similar to that of the first node N1, the leakage current can be reduced.

[0116] In an embodiment of the present invention, during the transmission period, the i-th transmission signal ESi is applied through the i-th transmission line ELi to turn on the dummy transistor DMT. The reference voltage Vref1 can be applied to the second node N2 through the dummy transistor DMT that is turned on during the transmission period.

[0117] The reference voltage Vref1 can have a level higher than the initialization voltage Vint, and can be set to various DC voltages with specified levels. For example, the reference voltage Vref1 can be set to the average voltage value of the data voltage supplied to pixel PX. When the data voltage output from the data driver DDV is 2V to 4V, the reference voltage Vref1 can be set to an average voltage value of 3V.

[0118] The compensation voltage Vd-Vth applied to the control electrode of the first transistor T1 can correspond to the voltage at the first node N1. The reference voltage Vref1 can be set to the average value of the data voltage, and the voltage at the second node N2 can be similar to the voltage at the first node N1. In this case, the drain-source voltage Vds of the third transistor T3 becomes smaller, and the leakage current caused by the third transistor T3 can be reduced.

[0119] As described above, according to one embodiment, the reference voltage Vref1 may have the average voltage value of the data voltage, but this disclosure is not limited thereto. In some embodiments, the data voltage Vd may be provided to the dummy transistor DMT as the reference voltage Vref1. In this case, the first electrode of the dummy transistor DMT may be connected to the i-th data line DLj. Alternatively, the reference voltage Vref1 may be set to the same voltage as the voltage of the first node N1. For example, the reference voltage Vref1 may be set to a compensation voltage Vd-Vth.

[0120] The leakage current of the third transistor T3 can be proportional to the gate-source voltage Vgs. The fourth amplitude ΔV4 of the second control signal GSLi applied to the control electrode of the third transistor T3 can be smaller than the first amplitude ΔV1, the second amplitude ΔV2, and the third amplitude ΔV3. Therefore, the gate-source voltage Vgs of the third transistor T3 becomes smaller, and the leakage current caused by the third transistor T3 can be further reduced.

[0121] In the following description, the circuit structure of the pixel PX according to various embodiments of the present invention will be described, with emphasis on... Figure 3 The differences in the circuit structure of pixel PXij shown.

[0122] Figure 5 The figure illustrates the equivalent circuit of pixel PXij according to another embodiment of the concept of the present invention.

[0123] Reference Figure 5 The connection structure of the transistor and capacitor CP of pixel PXij can be with Figure 3 The connection structures of the transistor and capacitor CP of the pixel PXij shown are basically the same. The control electrode of the third transistor T3 and the control electrode of the third-first transistor T3-1 can be connected together to the i-th second control line GCLi to receive the i-th second control signal GSLi.

[0124] and Figure 3 The structure shown is different. In pixel PXij, the i-th second control signal GSLi can be used as the i-th first control signal applied to the third transistor T3-1. In other words, the i-th first control signal applied to the third transistor T3-1 can be the same signal as the i-th second control signal GSLi applied to the third transistor T3.

[0125] Figure 6 The figure illustrates the equivalent circuit of pixel PXij according to another embodiment of the concept of the present invention. Figure 7 It is used for driving Figure 6 The timing diagram of the signal of pixel PXij is shown in the figure.

[0126] Reference Figure 6 The fourth transistor T4 of pixel PXij may include a first electrode connected to the second node N2, a second electrode connected to the initialization line ITL, and a control electrode connected to the (i-1)th control line SLi-1. Figure 6 In the pixel PXij shown, except for the fourth transistor T4 which is connected to the second node N2 and is omitted... Figure 3 Apart from the fourth transistor T4-1 shown, the connection structure of other components can be... Figure 3 The connection structures shown are basically the same.

[0127] The control electrode of the third transistor T3-1 can be connected to the i-th scan line SLi to receive the i-th scan signal SSi. Figure 3 The structure shown is different; the i-th scan signal SSi can be used as the i-th first control signal applied to the third transistor T3-1.

[0128] Reference Figure 6 and Figure 7 The i-th second control signal GSLi' can be applied to the third transistor T3 through the i-th second control line GCLi. Similar to... Figure 4 The i-th second control signal GSLi and the i-th second control signal GSLi' shown can have a fourth amplitude ΔV4, but the activation period of the i-th second control signal GSLi' can be longer than... Figure 4 The activation period of the i-th second control signal GSLi shown is long.

[0129] During the non-transmission period, the i-th second control signal GSLi' can be activated, and subsequently, the (i-1)-th scan signal SSi-1 and the i-th scan signal SSi can be activated. The activation period of the i-th second control signal GSLi' can be longer than the activation periods of the (i-1)-th scan signal SSi-1 and the i-th scan signal SSi. The activation periods of the (i-1)-th scan signal SSi-1 and the i-th scan signal SSi can be set within the activation period of the i-th second control signal GSLi'. In other words, the (i-1)-th scan signal SSi-1 and the i-th scan signal SSi can be deactivated before the deactivation of the i-th second control signal GSLi'.

[0130] The third transistor T3 can be turned on by the i-th second control signal GSLi', and when the third transistor T3 is turned on, the (i-1)-th scan signal SSi-1 can be applied to the fourth transistor T4 to turn on the fourth transistor T4. The initialization voltage Vint can be applied to the first node N1 through the turned-on third transistor T3 and fourth transistor T4.

[0131] The second transistor T2 and the third transistor T3-1 can be turned on by the i-th scan signal SSi. The first transistor T1 can be connected via the turned-on third transistor T3-1 and the diode of the third transistor T3. Other operations of pixel PXij can be related to... Figure 3 The other operations of the pixel PXij shown are essentially the same, and therefore, their description will be omitted.

[0132] Reference Figure 3 The third transistor T3 and the third-first transistor T3-1 connected to each other in pixel PXij can be referred to as the first dual-gate structure, and the fourth transistor T4 and the fourth-first transistor T4-1 connected to each other can be referred to as the second dual-gate structure.

[0133] Reference Figure 6 In pixel PXij, the third transistor T3 and the third-first transistor T3-1, which are connected to each other, can be referred to as a first dual-gate structure, and the third transistor T3 and the fourth transistor T4, which are connected to each other, can be referred to as a second dual-gate structure. In other words, it can be designed by sharing a single transistor (i.e., the third transistor T3). Figure 6 The first and second double-gate structures are shown. Therefore, with Figure 3 Compared to the pixel PXij shown, it can reduce the amount of pixels in the image. Figure 6 The number of transistors used in the pixel PXij.

[0134] Figure 8 The figure illustrates the equivalent circuit of pixel PXij according to another embodiment of the concept of the present invention.

[0135] Applied to Figure 8 The timing of the signal of pixel PXij shown Figure 7 The timing of the signals in these sequences is basically the same, and therefore, it can be referenced. Figure 7 The timing of the signals shown is used to describe Figure 8 The operation of pixel PXij is shown.

[0136] Reference Figure 7 and Figure 8 The connection structure of the transistor and capacitor CP of pixel PXij can be with Figure 6 The connection structures of the transistor and capacitor CP of the pixel PXij shown are basically the same. The control electrode of the third transistor T3 and the control electrode of the third-first transistor T3-1 can be connected together to the i-th second control line GCLi to receive the i-th second control signal GSLi'.

[0137] exist Figure 8In the pixel PXij shown, the i-th second control signal GSLi' can be used as the i-th first control signal applied to the third transistor T3-1. In other words, the i-th first control signal applied to the third transistor T3-1 can be the same signal as the i-th second control signal GSLi'. The third transistor T3 and the third transistor T3-1 can be turned on by the i-th second control signal GSLi' received through the i-th second control line GCLi.

[0138] Figure 9 The figure illustrates the equivalent circuit of pixel PXij according to another embodiment of the concept of the present invention. Figure 10 Illustration Figure 9 The diagram shows parasitic capacitors and dummy capacitors.

[0139] Applied to Figure 9 The timing of the signal of pixel PXij shown Figure 7 The timing of the signals in these sequences is basically the same, and therefore, it can be referenced. Figure 7 The timing of the signals shown is used to describe Figure 9 The operation of pixel PXij is shown.

[0140] Reference Figure 9 The connection structure of the fourth transistor T4-1 and the fourth transistor T4-2 of pixel PXij can be with Figure 3 The connection structure of the fourth transistor T4 and the fourth-to-first transistor T4-1 of pixel PXij shown is the same. Furthermore, the connection structures of the other transistors T1, T2, T3, T3-1, T5, T6, and T7, as well as the capacitor CP, can be the same as... Figure 6 The connection structure of the pixel PXij shown is the same.

[0141] exist Figure 9 In the pixel PXij shown, the fourth transistor T4-1 can be connected to the fourth transistor T4-2, but the embodiments of the present invention are not limited thereto. Similar to... Figure 6 In some embodiments, the fourth transistor T4-1 may be omitted from the pixel PXij shown.

[0142] Figure 9 The pixel PXij shown may further include a dummy capacitor DCP connected to the second node N2. The dummy capacitor DCP may include a first electrode for receiving a reference voltage Vref2 and a second electrode connected to the second node N2. The reference voltage Vref2 may have a level higher than the initialization voltage Vint and may be set to various DC voltages with specified levels.

[0143] Reference Figure 9 and Figure 10A parasitic capacitor Cps can exist in the third transistor T3. A dummy capacitor DCP can have a capacitance larger than the parasitic capacitor Cps. The dummy capacitor DCP and the parasitic capacitor Cps can be connected to each other, with a second node N2 placed between them.

[0144] Reference Figure 7 , Figure 9 and Figure 10 When the i-th second control line GSLi' is applied to the third transistor T3, the voltage level of the second node N2 may vary due to the parasitic capacitor Cps. However, since the dummy capacitor DCP, which has a larger capacitance, is connected to the second node N2, the variation in the voltage level of the second node N2 can be suppressed. The dummy capacitor DCP, with its larger capacitance, can suppress the voltage level of the second node N2, which might vary due to the parasitic capacitor Cps, which has a smaller capacitance.

[0145] As mentioned earlier, the voltage level variation of the second node N2 can be suppressed, and the drain-source voltage Vds of the third transistor T3 can be made smaller. Therefore, the leakage current caused by the third transistor T3 can be reduced.

[0146] Figure 11 The figure illustrates the equivalent circuit of pixel PXij according to another embodiment of the concept of the present invention. Figure 12 It is used for driving Figure 11 The timing diagram of the signal of pixel PXij is shown in the figure.

[0147] Apart from Figure 12 In addition to the first control signal GSHi' in the i-th part, Figure 12 The timing of the other signals shown can be compared with... Figure 7 The timing of the other signals shown is the same.

[0148] Reference Figure 11 and Figure 12 The connection structure of the transistor, capacitor CP, and dummy capacitor DCP of pixel PXij can be related to... Figure 9 The connection structure of the transistor, capacitor CP, and dummy capacitor DCP of the pixel PXij shown is basically the same.

[0149] The control electrode of the third transistor T3-1 can be connected to the i-th first control line GCHi to receive the i-th first control signal GSHi'. The control electrode of the third transistor T3 can be connected to the i-th second control line GCLi to receive the i-th second control signal GSLi'.

[0150] Similar to Figure 4The i-th first control signal GSHi shown can have a third amplitude ΔV3. Therefore, the amplitude of the i-th second control signal GSLi' can be smaller than the amplitude of the i-th first control signal GSHi'. The activation period of the i-th first control signal GSHi' can be longer than... Figure 4 The activation period of the i-th first control signal GSHi shown is long. The activation period of the i-th first control signal GSHi' can be the same as the activation period of the i-th second control signal GSLi'.

[0151] During non-transmission periods, the i-th first control signal GSHi' and the i-th second control signal GSLi' can be activated, and when the i-th first control signal GSHi' and the i-th second control signal GSLi' are activated, the (i-1)-th scan signal SSi-1 and the i-th scan signal SSi can be activated. The i-th first control signal GSHi' and the i-th second control signal GSLi' can have the same activation timing.

[0152] The i-th first control signal GSHi' and the i-th second control signal GSLi' can be applied to turn on the third transistor T3-1 and the third transistor T3, respectively. Subsequently, the fourth transistor T4-1 and the fourth transistor T4-2 can be turned on by the (i-1)-th scan signal SSi-1. The initialization voltage Vint can be applied to the first node N1 through the turned-on third transistor T3, fourth transistor T4-1, and fourth transistor T4-2.

[0153] The i-th scan signal SSi can be applied to turn on the second transistor T2. The first transistor T1 can be connected via a turned-on third transistor T3-1 and a diode. Other operations of pixel PXij are similar to... Figure 3 The other operations of the pixel PXij shown are essentially the same, and therefore their description will be omitted.

[0154] Figure 13 Exemplary maps include Figure 3 The diagram shows a cross-sectional view of the OLED light-emitting element, the first transistor T1, and the sixth transistor T6, and the pixel PXij.

[0155] Reference Figure 13 An OLED light-emitting element may include a first electrode (also referred to herein as the anode AE), a second electrode (also referred to herein as the cathode CE), a hole control layer HCL, an electron control layer ECL, and a light-emitting layer EML.

[0156] The first transistor T1, the sixth transistor T6, and the light-emitting element OLED can be disposed on the substrate SUB. The display area DA corresponding to the pixel PXij can include a light-emitting area PA and a non-light-emitting area NPA surrounding the light-emitting area PA. The light-emitting element OLED can be disposed in the light-emitting area PA of the pixel PXij.

[0157] A buffer layer (BFL) can be disposed on a substrate (SUB). The buffer layer (BFL) may include an inorganic layer. A semiconductor pattern may be disposed on the buffer layer (BFL). The semiconductor pattern may include polycrystalline silicon. However, embodiments of this disclosure are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

[0158] The electrical properties of a semiconductor pattern can vary depending on the type of dopant material. A semiconductor pattern can include doped and undoped regions. Doped regions can be doped with N-type or P-type dopant. The conductivity of doped regions can be greater than that of undoped regions, and the doped regions can essentially function as the source and drain electrodes of a transistor. Undoped regions can essentially correspond to the active region (or channel) of a transistor.

[0159] The source electrode S1, active region A1, and drain electrode D1 of the first transistor T1, and the source electrode S6, active region A6, and drain electrode D6 of the sixth transistor T6 can be formed by a semiconductor pattern. A first insulating layer INS1 can be disposed on the semiconductor pattern. The gate electrode (or control electrode) G1 of the first transistor T1 and the gate electrode G6 of the sixth transistor T6 can be disposed on the first insulating layer INS1.

[0160] The second insulating layer INS2 can be disposed on the gate electrodes G1 and G6. The dummy electrode DME can be disposed on the second insulating layer INS2. The dummy electrode DME can be disposed in a layer higher than the first transistor T1 and the sixth transistor T6. The third insulating layer INS3 can be disposed on the dummy electrode DME.

[0161] A connecting electrode CNE can be disposed between the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE can connect the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1. The first connecting electrode CNE1 can be disposed on the sixth transistor T6 to connect to the sixth transistor T6. The second connecting electrode CNE2 can be disposed between the first connecting electrode CNE1 and the first electrode AE ​​of the light-emitting element OLED to connect them.

[0162] The first connecting electrode CNE1 can be disposed on the third insulating layer INS3 and connected to the drain electrode D6 through a first contact hole CH1 that penetrates from the first insulating layer INS1 to the third insulating layer INS3. A fourth insulating layer INS4 can be disposed on the first connecting electrode CNE1. A fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4. The second connecting electrode CNE2 can be disposed on the fifth insulating layer INS5. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through a second contact hole CH2 that penetrates both the fourth and fifth insulating layers INS4 and INS5.

[0163] The sixth insulating layer INS6 can be disposed on the second connection electrode CNE2. The layers from the buffer layer BFL to the sixth insulating layer INS6 can be collectively referred to as the circuit element layers. The first insulating layer INS1 to the sixth insulating layer INS6 may include inorganic layers and / or organic layers.

[0164] The first electrode AE ​​of the OLED light-emitting element can be disposed on the sixth insulating layer INS6. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the third contact hole CH3 penetrating the sixth insulating layer INS6. A pixel defining layer PDL for exposing a portion of the first electrode AE ​​can be disposed on the first electrode AE ​​and the sixth insulating layer INS6. In the pixel defining layer PDL, the opening portion PX_OP can expose this portion of the first electrode AE ​​of the OLED light-emitting element.

[0165] A hole control layer (HCL) can be disposed on the first electrode (AE) and the pixel definition layer (PDL). The HCL can also be disposed together in the light-emitting region (PA) and the non-light-emitting region (NPA). The HCL may include a hole transport layer and / or a hole injection layer.

[0166] The luminescent layer (EML) can be disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening portion (PX_OP). The EML can comprise organic and / or inorganic materials. The EML can generate light in one of the following colors: red, green, and blue.

[0167] An electronic control layer (ECL) can be disposed on the light-emitting layer (EML) and the hole control layer (HCL). The ECL can also be disposed together in the light-emitting region (PA) and the non-light-emitting region (NPA). The ECL may include an electron transport layer and / or an electron injection layer.

[0168] The second electrode (CE) can be disposed on the electronic control layer (ECL). The second electrode (CE) can be disposed together in multiple pixel layers (PX). The thin-film encapsulation layer (TFE) can be disposed on the light-emitting element (OLED).

[0169] A first voltage, ELVDD, can be applied to the first electrode, AE, and a second voltage, ELVSS, can be applied to the second electrode, CE. Holes and electrons injected into the light-emitting layer, EML, can combine to form excitons, and when the excitons transition to the ground state, the OLED emits light. The OLED emits light to display an image.

[0170] A dummy capacitor DCP can be disposed on a substrate SUB. The first electrode E1 of the dummy capacitor DCP can be formed of the same material as the active regions A1 and A6, and can be disposed in the same layer as the active regions A1 and A6. The second electrode E2 of the dummy capacitor DCP can be formed of the same material as the dummy electrode DME, and can be disposed in the same layer as the dummy electrode DME.

[0171] Figures 14 to 18 The illustration shows a cross-sectional view of a pixel PXij according to various embodiments of the present invention.

[0172] Figures 14 to 18 As illustrated in the example, with Figure 13 The cross-section of the corresponding pixel PXij. Figures 14 to 18 The configuration of the light-emitting element OLED and the first transistor T1 and the sixth transistor T6 shown can be related to... Figure 13 The configuration of the light-emitting element OLED and the first transistor T1 and the sixth transistor T6 is basically the same, and the configuration of the dummy capacitors DCP_1 to DCP_5 will be described below.

[0173] Reference Figure 14 The first electrode E1 of the dummy capacitor DCP_1 can be formed of the same material as the active regions A1 and A6, and can be disposed in the same layer as the active regions A1 and A6. The second electrode E2 of the dummy capacitor DCP_1 can be formed of the same material as the first connecting electrode CNE1, and can be disposed in the same layer as the first connecting electrode CNE1.

[0174] Reference Figure 15 The first electrode E1 of the dummy capacitor DCP_2 can be formed of the same material as the active regions A1 and A6, and can be disposed in the same layer as the active regions A1 and A6. The second electrode E2 of the dummy capacitor DCP_2 can be formed of the same material as the second connecting electrode CNE2, and can be disposed in the same layer as the second connecting electrode CNE2.

[0175] Reference Figure 16The first electrode E1 of the dummy capacitor DCP_3 can be formed of the same material as the gate electrodes G1 and G6, and can be disposed in the same layer as the gate electrodes G1 and G6. The second electrode E2 of the dummy capacitor DCP_3 can be formed of the same material as the dummy electrode DME, and can be disposed in the same layer as the dummy electrode DME.

[0176] Reference Figure 17 The first electrode E1 of the dummy capacitor DCP_4 can be formed of the same material as the gate electrodes G1 and G6, and can be disposed in the same layer as the gate electrodes G1 and G6. The second electrode E2 of the dummy capacitor DCP_4 can be formed of the same material as the first connection electrode CNE1, and can be disposed in the same layer as the first connection electrode CNE1.

[0177] Reference Figure 18 The first electrode E1 of the dummy capacitor DCP_5 can be formed of the same material as the gate electrodes G1 and G6, and can be disposed in the same layer as the gate electrodes G1 and G6. The second electrode E2 of the dummy capacitor DCP_5 can be formed of the same material as the second connection electrode CNE2, and can be disposed in the same layer as the second connection electrode CNE2.

[0178] According to an embodiment of the present invention, a DC level reference voltage (e.g., reference voltage Vref1) can be applied to a node (e.g., second node N2) between the third transistor T3 and the third-first transistor T3-1 to reduce leakage current.

[0179] Although embodiments of the present disclosure have been described, it is to be understood that the present disclosure should not be limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the present disclosure. Furthermore, the embodiments disclosed herein are not intended to limit the technical spirit of the inventive concept, and the scope of the present disclosure should be interpreted on a holistic basis, including the appended claims, and it should be understood that all technical spirit included within its equivalent scope is included within the scope of this disclosure.

Claims

1. A display device, comprising: Pixels The pixels include: Light-emitting elements; The first transistor includes a first electrode connected to a first power line, a second electrode connected to the light-emitting element, and a control electrode connected to a first node; The second transistor includes a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the i-th scan line, where i is a natural number greater than 1. The third transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the second node, and a control electrode that receives the first control signal; The third transistor includes a first electrode connected to the second node, a second electrode connected to the first node, and a control electrode for receiving a second control signal; and... The dummy transistor includes a first electrode that receives a reference voltage, a second electrode connected to the second node, and a control electrode connected to the emitter line. The amplitude of the second control signal is less than the amplitude of the i-th scan signal applied to the i-th scan line.

2. The display device according to claim 1, wherein The reference voltage is set to the average voltage value of the data voltages provided to multiple pixels.

3. The display device according to claim 1, wherein The reference voltage corresponds to a value obtained by subtracting the threshold voltage of the first transistor from the data voltage applied to the data line.

4. The display device according to claim 1, wherein The reference voltage is set to the data voltage applied to the data line.

5. The display device according to claim 1, wherein The amplitude of the second control signal corresponds to the second difference between the second high level and the second low level of the second control signal, and the amplitude of the second control signal is less than the amplitude of the first control signal. The amplitude of the first control signal corresponds to the first difference between the first high level and the first low level of the first control signal.

6. The display device according to claim 1, wherein The amplitude of the second control signal corresponds to the second difference between the second high level and the second low level of the second control signal, and the amplitude of the second control signal is less than the amplitude of the transmitted signal applied to the transmit line. The amplitude of the transmitted signal corresponds to a first difference between the first high level and the first low level of the transmitted signal, and the amplitude of the i-th scan signal corresponds to a third difference between the third high level and the third low level of the i-th scan signal.

7. The display device according to claim 1, wherein, The first control signal and the second control signal have the same timing as the i-th scan signal applied to the i-th scan line.

8. The display device according to claim 1, wherein, The pixel further includes: The fourth transistor includes a first electrode connected to the first node, a second electrode receiving an initialization voltage, and a control electrode connected to the (i-1)th scan line; The fifth transistor includes a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the emitter line; and The sixth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the light-emitting element, and a control electrode connected to the emission line.

9. The display device of claim 8, wherein, The first control signal is the same as the second control signal.

10. The display device according to claim 1, wherein The pixel further includes: The fourth transistor includes a first electrode connected to the second node, a second electrode receiving an initialization voltage, and a control electrode connected to the (i-1)th scan line; The fifth transistor includes a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the emitter line; and The sixth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the light-emitting element, and a control electrode connected to the emission line.

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