Memory system, memory device, and method of operating a memory device

Abstract

Embodiments of the present disclosure relate to a memory system, a memory device, and a method for operating the memory device. According to embodiments of the present disclosure, the memory device may, in response to receiving a suspend command from a memory controller to suspend a program operation being executed, perform a first verification operation and a second verification operation on a memory cell, may store a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation in a first data latch, and may perform a third verification operation, and restore the result value of the first verification operation and the result value of the second verification operation based on the result value of the third verification operation and the temporary value stored in the first data latch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0079073, filed on Jun. 29, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Technologies and embodiments disclosed in this patent document relate to memory systems, memory devices, and methods of operating memory devices. Background Art

[0004] A storage device refers to an electronic component for storing data permanently or temporarily. Each storage device may include one or more storage media to store data and operate based on a request from a host. Examples of hosts include computers, mobile terminals (e.g., smartphones or tablets), or various other electronic devices. Storage devices can be classified based on the type of storage medium. For example, a hard disk drive (HDD) uses a magnetic disk as a storage medium, and a solid-state drive (SSD), a universal flash memory device (UFS), or an embedded MMC (eMMC) device uses a semiconductor device such as a volatile memory device and a non-volatile memory device as a storage medium.

[0005] The memory system may further include a memory controller for controlling the memory device. The memory controller may receive a command from the host, and may perform or control an operation for reading, writing, or erasing data in a volatile memory or a nonvolatile memory included in the memory system based on the received command. The memory controller may drive firmware for performing logic operations for controlling such operations.

[0006] The memory system includes a memory cell used as a digital storage device. The memory cell is programmed to one of a plurality of states by performing a programming operation (or referred to as a write operation) to program or write data on the memory cell. However, in some cases, the programming operation being performed on the memory cell may be suspended. For example, the programming operation is suspended, and a read operation is performed while the programming operation is suspended. After receiving a resume command, the suspended programming operation may be resumed. The operation of the memory system including the suspension of the programming operation and the resumption of the programming operation may improve the quality of service (QoS) to the host. Summary of the invention

[0007] Embodiments of the disclosed technology may provide a memory system, a memory device, and a method of operating a memory device, which are capable of restoring a verification result after a program operation is resumed so that the restored verification result is the same as the verification result obtained before the program operation is suspended.

[0008] Furthermore, some embodiments of the disclosed technology may provide a memory system, a memory device, and a method of operating a memory device, which are capable of preventing abnormal execution of a program operation caused by a change in a threshold voltage distribution in a case where the program operation is suspended.

[0009] In one aspect of the present disclosure, an embodiment of the present disclosure may provide a memory system comprising: a memory device including a memory cell array including memory cells programmable in multiple states; and a memory controller communicating with the memory device and configured to control the memory device.

[0010] A memory device may include a memory cell and a first data latch storing information about a state of the memory cell.

[0011] The memory device may perform first and second verification operations on the memory cells in response to receiving a suspend command from the memory controller to suspend a program operation being performed on the memory cells. The first and second verification operations may be performed using verification voltages to determine states of the memory cells.

[0012] The memory device may store a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation in the first data latch.

[0013] The storage device may perform a third verification operation in response to receiving a resume command to resume the programming operation from the memory controller, and may restore result values ​​of the first verification operation and the second verification operation based on result values ​​of the third verification operation and a temporary value stored in the first data latch.

[0014] In this case, a verification voltage for the first verification operation is higher than verification voltages for the second and third verification operations. The verification voltage for the second verification operation may be the same as the verification voltage for the third verification operation.

[0015] The memory device may set the temporary value to the first value when both the result value of the first verification operation and the result value of the second verification operation are the first value, and may set the temporary value to the second value when either the result value of the first verification operation or the result value of the second verification operation is the second value.

[0016] The memory device may further include a second data latch configured to be used during a read operation performed between receiving the suspend command and receiving the resume command.

[0017] The memory device may store the temporary value stored in the first data latch in the second data latch in response to receiving the restore command, and may store a result value of the third verification operation in the first data latch.

[0018] When the temporary value stored in the second data latch is the first value, the memory device can set the value of the first data latch to the first value, and when the temporary value stored in the second data latch and the result value of the third verification operation stored in the first data latch are both second values, the value of the second data latch can be set to the first value.

[0019] In another aspect of the present disclosure, embodiments of the present disclosure may provide a memory device communicating with a memory controller.

[0020] The memory device may include a memory cell programmable between multiple states and a first data latch storing information about the state of the memory cell.

[0021] The memory device may perform first and second verification operations on the memory cells in response to receiving a suspend command from the memory controller to suspend a program operation being performed on the memory cells. The first and second verification operations may be performed using different verification voltages to verify the states of the memory cells.

[0022] The memory device may store a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation in the first data latch.

[0023] The memory device may perform a third verification operation in response to receiving a resume command to resume the programming operation from the memory controller, and may restore result values ​​of the first verification operation and the second verification operation based on result values ​​of the third verification operation and a temporary value stored in the first data latch.

[0024] In another aspect of the present disclosure, embodiments of the present disclosure may provide a method of operating a memory device.

[0025] The method of operating a memory device may include receiving a suspend command from a memory controller to suspend a program operation being performed on a memory cell, the memory cell being in the memory device and being programmable in a plurality of states.

[0026] The method of operating a memory device may include an operation of performing a first verification operation and a second verification operation on a memory cell using a verification voltage to determine a state of the memory cell.

[0027] The method of operating a memory device may include an operation of storing a temporary value obtained based on a result value of a first verification operation and a result value of a second verification operation in a first data latch.

[0028] The method of operating a memory device may include an operation of receiving a resume command to resume a program operation from a memory controller.

[0029] The method of operating a memory device may include: when a resume command associated with a suspended program operation is received, performing a third verification operation, and restoring result values ​​of the first verification operation and result values ​​of the second verification operation based on the result values ​​of the third verification operation and a temporary value stored in a first data latch.

[0030] In this case, a verification voltage for the first verification operation may be higher than verification voltages for the second and third verification operations. The verification voltage for the second verification operation and the verification voltage for the third verification operation may be the same.

[0031] When the result value of the first verification operation and the result value of the second verification operation are both first values, the temporary value is the first value, and when the result value of the first verification operation or the result value of the second verification operation is the second value, the temporary value is the second value.

[0032] Restoring the result value of the first verification operation and the result value of the second verification operation may include storing the temporary value stored in the first data latch in the second data latch, and storing the result value of the third verification operation in the first data latch.

[0033] Restoring the result value of the first verification operation and the result value of the second verification operation may include: when the temporary value stored in the second data latch is the first value, setting the value of the first data latch to the first value, and when the temporary value stored in the second data latch and the result value of the third verification operation stored in the first data latch are both the second value, setting the value of the second data latch to the first value.

[0034] According to an embodiment of the disclosed technology, when a suspended program operation is resumed, a verification result may be restored to be the same as a verification result obtained before the program operation was suspended.

[0035] Furthermore, according to an embodiment of the disclosed technology, it is possible to prevent abnormal execution of a program operation that may be caused by a change in threshold voltage distribution when the program operation is suspended. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other aspects, features and advantages of the disclosed technology will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1 is a schematic diagram showing the configuration of a memory system based on some embodiments of the disclosed technology.

[0038] Figure 2 is a block diagram schematically illustrating a memory device according to some embodiments of the disclosed technology.

[0039] Figure 3 is a diagram showing the structure of word lines and bit lines of a memory device based on some embodiments of the disclosed technology.

[0040] Figure 4 is a schematic diagram illustrating a memory system based on some embodiments of the disclosed technology.

[0041] Figure 5 is a flow chart illustrating the operation of a memory controller and a memory device according to some embodiments of the disclosed technology.

[0042] Figure 6 is a diagram illustrating results of a first verification operation and a second verification operation when a program operation is performed.

[0043] Figure 7 is a diagram illustrating a value stored in a first data latch when a program operation is suspended.

[0044] Figure 8 is a diagram illustrating states of the first data latch and the second data latch when a read operation is performed after a program operation is suspended.

[0045] Fig. 9 is a diagram illustrating an example of changes in threshold voltage distribution of memory cells on which programming is performed when a program operation is suspended.

[0046] Fig.10 is a diagram illustrating a result of a third verification operation when a program operation is resumed.

[0047] Fig.11 is a diagram illustrating an example of a value stored in the first data latch when a program operation is resumed.

[0048] Fig.12 is a diagram showing an example of a value stored in the second data latch when a program operation is resumed.

[0049] Fig.13 is a flow chart illustrating a method of operating a memory device according to some embodiments of the disclosed technology.

[0050] Fig.14 is a diagram showing the configuration of a computing system based on some embodiments of the disclosed technology. DETAILED DESCRIPTION

[0051] Hereinafter, embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0052] When a resume command is received, the memory system performs a verification operation to verify the state of the memory cell. In the process of resuming the suspended programming operation, the verification point of the data written to the memory cell may change, or a portion of the verification data obtained before the write operation was suspended may be lost. Therefore, in the process of writing data to the memory device, the verification of determining the state of the memory cell may be abnormally performed, and the threshold voltage distribution of the memory cell in which the data is written may be degraded, which is a disadvantage. Recognizing this, the disclosed technology provides various embodiments that enable the result of the verification operation to be obtained without being affected by undesirable situations during the recovery operation.

[0053] Figure 1 is a diagram showing a schematic configuration of a memory system 100 according to an embodiment of the disclosed technology.

[0054] Reference Figure 1 , the memory system 100 may include a memory device 110 configured to store data and a memory controller 120 configured to control the memory device 110 .

[0055] The memory device 110 may include a plurality of memory blocks. The memory device 110 may be configured to operate in response to control signals received from the memory controller 120. The operation of the memory device 110 may include, for example, a read operation, a program operation (also referred to as a "write operation"), an erase operation, etc.

[0056] The memory device 110 may include a memory cell array including a plurality of memory cells (also referred to as "cells") configured to store data. In some embodiments, each of the memory cells may be constructed or operated to store a single bit or more bits of information. The memory cell array may be organized into different blocks and pages for memory operations. The cells of the memory cell array may be organized to include a plurality of memory blocks. Each memory block may include a plurality of pages, and each page corresponds to a plurality of memory cells.

[0057] For example, the memory device 110 may be implemented as various types such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate fourth generation (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0058] The memory device 110 may be implemented in a three-dimensional array structure. In some embodiments, the embodiments of the disclosed technology are applicable to a flash memory device having a charge storage layer configured as a conductive floating gate. In some other embodiments, the embodiments of the disclosed technology are applied to a flash memory device having a charge trap flash memory (CTF) having a charge storage layer configured as an insulating film.

[0059] By providing a command / address signal to the memory controller 120, the memory controller 120 may access the memory device 110 based on a request from a user / host. In some embodiments, the memory device 110 may be configured to receive a command and an address to execute or run the command from the memory controller, and access an area in the memory cell array selected using the address. For example, the memory device 110 may perform an operation corresponding to the received command in a memory area of ​​the memory device having a physical address corresponding to the address received from the memory controller 120.

[0060] For example, the memory device 110 may perform a programming operation, a read operation, an erase operation, or other operations. During a programming operation, the memory device 110 may program data in an area selected by an address. During a read operation, the memory device 110 may read data from an area selected by an address. During an erase operation, the memory device 110 may erase data stored in an area selected by the address.

[0061] The memory controller 120 may control a write operation (programming operation), a read operation, an erase operation, or a background operation with respect to the memory device 110. The background operation may include, for example, at least one of a garbage collection (GC) operation, a wear leveling (WL) operation, and a bad block management (BBM) operation. The term "garbage collection" as used herein may refer to a form of memory management in which a garbage collector attempts to reclaim memory (garbage) occupied by objects that are no longer used. Wear leveling refers to a technique for extending the life of an erasable storage device.

[0062] Memory controller 120 may control the operation of memory device 110 at the request of the host. Alternatively, memory controller 120 may control the operation of memory device 110 without a corresponding request from the host, for example, when memory controller 120 performs one or more background operations of the memory device.

[0063] The memory controller 120 and the host may be separate devices. In some cases, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, the memory controller 120 and the host are separate devices.

[0064] Reference Figure 1 , the memory controller 120 may include a memory interface 122 , a control circuit 123 , and a host interface 121 .

[0065] The host interface 121 may be configured to provide an interface for communicating with a host.

[0066] When receiving a command from the host HOST, the control circuit 123 may receive the command through the host interface 121 and may perform an operation of processing the received command.

[0067] The memory interface 122 may be connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 may be configured to provide an interface to the memory device 110 and the memory controller 120 in response to the control of the control circuit 123.

[0068] The control circuit 123 may be configured to control the operation of the memory device 110 by performing operations for overall control of the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126 and the like.

[0069] The processor 124 may control the overall operation of the memory controller 120 . The processor 124 may perform logic operations. The processor 124 may communicate with the host HOST through the host interface 121 . The processor 124 may communicate with the memory device 110 through the memory interface 122 .

[0070] The processor 124 may perform the function of a flash translation layer (FTL). The processor 124 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and convert the LBA into the PBA by using a mapping table.

[0071] According to the mapping unit, FTL can adopt various address mapping methods. Typical address mapping methods can include page mapping method, block mapping method and hybrid mapping method.

[0072] The processor 124 may be configured to randomize the data received from the host. For example, the processor 124 may randomize the data received from the host by using a randomization seed. The randomized data is provided to the memory device 110 as data to be stored and is programmed in the memory cell array.

[0073] The processor 124 may be configured to derandomize data received from the memory device 110 during a read operation. For example, the processor 124 may derandomize data received from the memory device 110 by using a derandomization seed. The derandomized data may be output to the host HOST.

[0074] The processor 124 may execute firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 may control the overall operation of the memory controller 120, and may execute (drive) the firmware loaded into the working memory 125 during booting in order to perform logical operations.

[0075] The firmware refers to a program running inside the memory system 100 and may include various functional layers.

[0076] For example, the firmware may include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer (FTL) is configured to convert between a logical address provided by the host HOST requesting the memory system 100 and a physical address of the memory device 110, the host interface layer (HIL) is configured to interpret a command issued by the host HOST to the memory system 100 (storage device) and pass the command to the FTL, and the flash interface layer (FIL) is configured to pass the command issued by the FTL to the memory device 110.

[0077] For example, the firmware may be stored in the memory device 110 and then loaded into the working memory 125 .

[0078] The working memory 125 may store firmware, program codes, commands or data necessary to drive the memory controller 120. The working memory 125 may include at least one of, for example, static RAM (SRAM), dynamic RAM (DRAM) and synchronous RAM (SDRAM) as volatile memories.

[0079] The error detection / correction circuit 126 may be configured to detect error bits of the inspection target data by using an error correction code and correct the detected error bits. For example, the inspection target data may be data stored in the working memory 125, data retrieved from the memory device 110, or the like.

[0080] The error detection / correction circuit 126 can be implemented to decode the data by using an error correction code. The error detection / correction circuit 126 can be implemented by using various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0081] For example, the error detection / correction circuit 126 can detect error bits sector by sector for each read data. Each read data may include multiple sectors. As used herein, a sector may refer to a data unit that is smaller than a read unit (page) of a flash memory. The sectors constituting each read data may correspond to each other via addresses.

[0082] The error detection / correction circuit 126 may calculate a bit error rate (BER) and determine whether correction is possible on a sector-by-sector basis. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 may determine that the corresponding sector is uncorrectable or "failed." If the BER is lower than or equal to the reference value, the error detection / correction circuit 126 may determine that the corresponding sector is correctable or "passed."

[0083] The error detection / correction circuit 126 can continuously perform error detection and correction operations on all read data strips. When a sector included in the read data is correctable, the error detection / correction circuit 126 can omit the error detection and correction operation related to the corresponding sector for the next read data. After completing the error detection and correction operation on all read data strips in this way, the error detection / correction circuit 126 can detect a sector that is considered to be ultimately uncorrectable. There may be one or more sectors that are considered to be uncorrectable. The error detection / correction circuit 126 can pass information (e.g., address information) about the sector that is considered to be uncorrectable to the processor 124.

[0084] The bus 127 may be configured to provide a channel between the constituent elements 121, 122, 124, 125, and 126 (i.e., the host interface 121, the memory interface 122, the processor 124, the working memory 125, and the error detection / correction circuit 126) of the memory controller 120. The bus 127 may include, for example, a control bus for transferring various types of control signals and commands, and a data bus for transferring various types of data.

[0085] The above-mentioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are provided only as examples. Note that some of the above-mentioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be omitted, or some of the above-mentioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. In addition, in some cases, in addition to the above-mentioned constituent elements of the memory controller 120, one or more other constituent elements may be added.

[0086] In the following, reference will be made to Figure 2 The memory device 110 is described in more detail.

[0087] Figure 2 is a block diagram schematically illustrating a memory device 110 according to an embodiment of the disclosed technology.

[0088] Reference Figure 2 , the memory device 110 may include a memory cell array 210 , an address decoder 220 , a read / write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0089] The memory cell array 210 may include a plurality of memory blocks BLK1 -BLKz, where z is a natural number equal to or greater than 2.

[0090] In the plurality of memory blocks BLK1 -BLKz, a plurality of word lines WL and a plurality of bit lines BL may be provided in rows and columns, and a plurality of memory cells MC may be arranged.

[0091] The plurality of memory blocks BLK1-BLKz may be connected to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1-BLKz may be connected to the read / write circuit 230 through a plurality of bit lines BL.

[0092] Each of the plurality of memory blocks BLK1-BLKz may include a plurality of memory cells. For example, the plurality of memory cells are nonvolatile memory cells. In some embodiments, the nonvolatile memory cells have a vertical channel structure.

[0093] The memory cell array 210 may include a memory cell array having a two-dimensional structure or a memory cell array having a three-dimensional structure.

[0094] Each of the plurality of memory cells included in the memory cell array 210 may store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-layer cell (SLC) configured to store one bit of data per memory cell. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-layer cell (MLC) configured to store two bits of data per memory cell. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-layer cell (TLC) configured to store three bits of data per memory cell. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-layer cell (QLC) configured to store four bits of data per memory cell. In another example, the memory cell array 210 may include a plurality of memory cells, each of the plurality of memory cells may be configured to store at least five bits of data per memory cell.

[0095] Reference Figure 2 , the address decoder 220 , the read / write circuit 230 , the control logic 240 , and the voltage generation circuit 250 may operate as a peripheral circuit configured to drive the memory cell array 210 .

[0096] The address decoder 220 may be connected to the memory cell array 210 through a plurality of word lines WL.

[0097] The address decoder 220 may be configured to operate in response to commands and control signals from the control logic 240 .

[0098] The address decoder 220 may receive an address through an input / output buffer inside the memory device 110. The address decoder 220 may be configured to decode a block address among the received addresses. The address decoder 220 may select at least one memory block based on the decoded block address.

[0099] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0100] When a read voltage is applied during a read operation, the address decoder 220 may apply the read voltage Vread to a selected word line WL inside a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0101] During a program verification operation, the address decoder 220 may apply a verification voltage generated by the voltage generation circuit 250 to a selected word line WL inside a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0102] The address decoder 220 may be configured to decode a column address among the received addresses. The address decoder 220 may transmit the decoded column address to the read / write circuit 230.

[0103] The memory device 110 may perform read operations and programming operations based on pages. In some embodiments, the memory cell array may include a memory block, and each memory block may include a plurality of pages, each page corresponding to a plurality of memory cells. The address received when requesting a read operation and a programming operation may include at least one of a block address, a row address, and a column address.

[0104] The address decoder 220 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read / write circuit 230.

[0105] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0106] The read / write circuit 230 may include a plurality of page buffers PB. The read / write circuit 230 may operate as a “read circuit” when the memory cell array 210 performs a read operation, and may operate as a “write circuit” when the memory cell array 210 performs a write operation.

[0107] The above-mentioned read / write circuit 230 is also called a page buffer circuit including a plurality of page buffers PB, or a data register circuit. The read / write circuit 230 may include a data buffer capable of holding data for data processing, and in some embodiments, may further include a cache buffer for data caching.

[0108] A plurality of page buffers PB may be connected to the memory cell array 210 through a plurality of bit lines BL. In order to detect or sense a threshold voltage Vth of a memory cell during a read operation and a program verification operation, the plurality of page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cell to detect an electrical change proportional to the current based on a programming state of the corresponding memory cell at a sensing node, and may latch a corresponding voltage as sensing data.

[0109] The read / write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0110] During a read operation, the read / write circuit 230 senses a voltage value of a memory cell and reads the voltage value as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to an input / output buffer of the memory device 110. In an embodiment, the read / write circuit 230 may include a column selection circuit in addition to the page buffer PB or the page register.

[0111] The control logic 240 may be connected to the address decoder 220, the read / write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory device 110.

[0112] The control logic 240 may be configured to control the overall operation of the memory device 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting the voltage level of the sensing nodes of the plurality of page buffers PB to a precharge voltage level.

[0113] The control logic 240 may control the read / write circuit 230 to perform a read operation in the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used during a read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0114] A memory block BLK included in the memory device 110 may include a plurality of pages PG and a plurality of strings. The plurality of pages PG correspond to a plurality of word lines WL, and the plurality of strings STR correspond to a plurality of bit lines BL.

[0115] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged crosswise. For example, each of the plurality of word lines WL may be arranged along a row direction, and each of the plurality of bit lines BL may be arranged along a column direction. In another example, each of the plurality of word lines WL may be arranged along a column direction, and each of the plurality of bit lines BL may be arranged along a row direction.

[0116] A plurality of word lines WL and a plurality of bit lines BL may cross each other, thereby defining a plurality of memory cells MC. Each memory cell MC may have a transistor TR disposed therein.

[0117] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected to the corresponding bit line BL directly or via another transistor TR. The source (or drain) of the transistor TR may be connected to the source line (which may be grounded) directly or via another transistor TR. The gate of the transistor TR may include a floating gate (FG) and a control gate (CG), wherein the floating gate (FG) is surrounded by an insulator, and a gate voltage is applied to the control gate CG from the word line WL.

[0118] In each of the multiple memory blocks BLK1-BLKz, a first selection line (also called a source selection line or a drain selection line) may be additionally arranged outside a first outermost word line that is closer to the read / write circuit 230 among the two outermost word lines, and a second selection line (also called a drain selection line or a source selection line) may be additionally arranged outside another second outermost word line.

[0119] In some cases, at least one dummy word line may be additionally disposed between the first outermost word line and the first selection line. In addition, at least one dummy word line may also be additionally disposed between the second outermost word line and the second selection line.

[0120] A read operation and a program operation (write operation) of a memory block may be performed in units of pages, and an erase operation may be performed in units of memory blocks.

[0121] Figure 3 is a diagram showing the structure of word lines WL and bit lines BL of a memory device 110 according to an embodiment of the disclosed technology.

[0122] Reference Figure 3 The memory device 110 has a core region in which memory cells MC are concentrated, and an auxiliary region corresponding to a remaining region outside the core region. The auxiliary region includes circuits for supporting the operation of the memory cell array 210.

[0123] The core region may include a page PG and a string STR. In some embodiments, a plurality of word lines WL1 to WL9 and a plurality of bit lines BL are cross-arranged.

[0124] The word lines WL1 to WL9 may be connected to the row decoder 310. The bit lines BL may be connected to the column decoder 320. Figure 2 The data register 330 of the read / write circuit 230 may exist between the plurality of bit lines BL and the column decoder 320 .

[0125] The plurality of word lines WL1 to WL9 may correspond to a plurality of pages PG.

[0126] For example, Figure 3As shown, each of the plurality of word lines WL1 to WL9 may correspond to one page PG. When the size of each of the plurality of word lines WL1 to WL9 is large, each of the plurality of word lines WL1 to WL9 may correspond to at least two (e.g., two or four) page PGs. Each page PG is the minimum unit associated with performing a programming operation and a reading operation, and when performing a programming operation and a reading operation, all memory cells MC within the same page PG may perform the operation simultaneously.

[0127] The plurality of bit lines BL may be connected to the column decoder 320. In some embodiments, the plurality of bit lines BL may be divided into odd-numbered bit lines BL and even-numbered bit lines BL such that a pair of odd-numbered bit lines BL and even-numbered bit lines BL are commonly coupled to the column decoder 320.

[0128] The address can be used to access one or more memory cells MC in the core area. The address can be provided to the row decoder 310 and the column decoder 320 through the input / output terminal to select the corresponding target memory cell. In some embodiments, the target memory cell may refer to one of the memory cells MC as a target accessed from the memory controller or the user, and in some embodiments, the memory cell MC may be located at the intersection between the word lines WL1 to WL9 connected to the row decoder 310 and the bit lines BL connected to the column decoder 320.

[0129] In some embodiments, the data register 330 is functional because all data processing by the memory device 110, including programming operations and read operations, occurs via the data register 330. If the data processing of the data register 330 is delayed, all other regions need to wait until the data register 330 completes the data processing, which degrades the overall performance of the memory device 110.

[0130] Reference Figure 3 In the example shown in , in one string STR, a plurality of transistors TR1 to TR9 may be connected to a plurality of word lines WL1 to WL9, respectively. In some embodiments, the plurality of transistors TR1 to TR9 correspond to memory cells MC. In this example, the plurality of transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0131] The plurality of word lines WL1 to WL9 include two outermost word lines WL1 and WL9. A first selection line DSL may be additionally arranged outside the first outermost word line WL1, which is closer to the data register 330 and has a shorter signal path than the other outermost word line WL9. A second selection line SSL may be additionally arranged outside the other second outermost word line WL9.

[0132] The first selection transistor D-TR turned on / off by the first selection line DSL has a gate electrode connected to the first selection line DSL but does not include a floating gate FG. The second selection transistor S-TR turned on / off by the second selection line SSL has a gate electrode connected to the second selection line SSL but does not include a floating gate FG.

[0133] The first selection transistor D-TR is used as a switch circuit to connect the corresponding string STR to the data register 330. The second selection transistor S-TR is used as a switch circuit to connect the corresponding string STR to the source line SL. Therefore, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding string STR and pass / block the signal.

[0134] During a programming operation, the memory system 100 fills the target memory cell MC of the bit line BL to be programmed with electrons. Therefore, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

[0135] The memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR during a read operation or a verification operation. Therefore, during a read operation or a verification operation, a current may flow through the corresponding string STR and out to the source line SL corresponding to the ground voltage, so that the voltage level of the bit line BL can be measured. However, during a read operation, there may be a time difference in the on / off time between the first selection transistor D-TR and the second selection transistor S-TR.

[0136] During the erase operation, the memory system 100 may apply a predetermined voltage (e.g., +20V) to the substrate through the source line SL. During the erase operation, the memory system 100 applies a certain voltage to float both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, the applied erase voltage may remove charge from the floating gate FG of the selected memory cell.

[0137] Figure 4 is a schematic diagram illustrating a memory system 100 according to various embodiments of the disclosed technology.

[0138] Reference Figure 4 The memory controller 120 of the memory system 100 may transmit a command to perform an operation (eg, a program operation, a read operation, or a delete operation) on the memory device 110 in order to process a request from a host (HOST). The memory device 110 may perform an operation based on the command received from the memory controller 120.

[0139] The memory device 110 may include a first data latch (DL_1). The memory device 110 may additionally include a second data latch (DL_2). The first data latch (DL_1) and the second data latch (DL_2) may be circuits or include circuits, each capable of storing 1 bit of data, and used to store programming state information of a memory cell to be programmed during a programming operation. Each of the first data latch (DL_1) and the second data latch (DL_2) may be implemented as, for example, a flip-flop circuit, a register, etc.

[0140] While the memory device 110 is performing a program operation in response to a program command received from the memory controller 120, the memory controller 120 may transmit a suspend command instructing to suspend the program operation currently being performed to the memory device 110. The memory controller 120 may transmit a suspend command to the memory device 110 when the memory controller 120 receives a separate suspend command from a host (HOST) or receives a read request from the host while the program operation is being performed.

[0141] The memory device 110 may suspend a currently executed program operation after receiving the suspend command from the memory controller 120, and may subsequently execute another command (e.g., a read command) received from the memory controller 120. The memory device 110 may receive a resume command from the memory controller instructing the memory device to resume the suspended program operation, and may resume the suspended program operation.

[0142] In the following, reference will be made to Figure 5 Operations of the memory controller 120 and the memory device 110 when a program operation is suspended and resumed are described.

[0143] Figure 5 is a flowchart illustrating operations of the memory controller 120 and the memory device 110 according to an embodiment of the disclosed technology.

[0144] Reference Figure 5 , the memory controller 120 may transmit a suspend command to the memory device 110 to suspend a program operation currently being executed.

[0145] When the memory device 110 receives a suspend command while performing a program operation on memory cells, the memory device 110 may perform a first verification operation and a second verification operation on corresponding memory cells.

[0146] Each of the first verification operation and the second verification operation may be an operation of applying a verification voltage to a memory cell in order to verify a programming state of the corresponding memory cell. In some embodiments, the verification voltage may be pre-set. In this case, the value of the verification voltage for the first verification operation may be higher than the value of the verification voltage for the second verification operation.

[0147] Subsequently, the memory device 110 may store a temporary value generated or obtained based on the result values ​​of the first and second verification operations in the first data latch (DL_1) included in the memory device 110. Subsequently, the memory device 110 may enter a state in which a program operation is suspended.

[0148] Subsequently, the memory controller 120 may transmit a read command to the memory device 110 in order to process a read operation requested by the host (HOST) in a state where the program operation is suspended. After receiving the read command, the memory device 110 may perform a read operation indicated by the corresponding read command.

[0149] Subsequently, the memory controller 120 may transmit a resume command to the memory device 110 in order to resume the suspended program operation.

[0150] After receiving the resume command, the memory device 110 may perform a third verification operation on the memory cells whose program operation is suspended. In the third verification operation, the memory device 110 may verify the program states of the corresponding memory cells using the same verification voltage as that used for the second verification operation.

[0151] Based on the result value of the third verification operation and the temporary value stored in the first data latch ( DL_1 ), the memory device 110 may restore the result values ​​of the first verification operation and the second verification operation obtained before the program operation is suspended.

[0152] Hereinafter, embodiments of the above-described operation of the memory device 110 will be described in detail with reference to the accompanying drawings.

[0153] Figure 6 2 is a diagram illustrating a result of a first verification operation and a result of a second verification operation when a program operation is performed.

[0154] like Figure 5 As shown, the memory device 110 may perform a first verification operation and a second verification operation on the memory cells in order to verify the programming states of the memory cells.

[0155] In the first verification operation, the memory device 110 may apply a first verification voltage (VER_1) to the memory cell. In the second verification operation, the memory device 110 may apply a second verification voltage (VER_2) to the memory cell. In this case, Figure 6 As shown, a first verification voltage (VER_1) applied to the memory cell when the first verification operation is performed is higher than a second verification voltage (VER_2) applied to the memory cell when the second verification operation is performed.

[0156] In this case, a program state of the memory cell may be classified into a first state (ST_1), a second state (ST_2), or a third state (ST_3) based on a threshold voltage of the memory cell, a first verification voltage (VER_1), and a second verification voltage (VER_2).

[0157] If the threshold voltage of the memory cell is less than the second verification voltage (VER_2), the memory device 110 may determine that the programming state of the corresponding memory cell is the first state (ST_1). The memory device 110 may input a programming pulse corresponding to a first pulse (e.g., 15V) to the corresponding memory cell to complete the programming operation of the memory cell in the first state (ST_1).

[0158] If the threshold voltage of the memory cell is greater than or equal to the second verification voltage (VER_2) and less than the first verification voltage (VER_1), the memory device 110 may determine that the programming state of the corresponding memory cell is the second state (ST_2). The memory device 110 may input a programming pulse corresponding to a second pulse (e.g., 12V) to the corresponding memory cell so as to program data in the memory cell in the second state (ST_2). In this case, the amplitude of the second pulse is smaller than the amplitude of the first pulse.

[0159] If the threshold voltage of the memory cell is greater than or equal to the first verification voltage (VER_1), the memory device 110 may determine that the program state of the corresponding memory cell is the third state (ST_3). In the third state (ST_3), the memory device 110 may not input an additional program pulse to the memory cell.

[0160] The memory device 110 may use a first value (set value) and a second value (reset value) to set a result value of a first verification operation and a result value of a second verification operation, respectively. In addition, the setting of the result value of the first verification operation and the result value of the second verification operation may be performed in consideration of the programming state of the memory cell. Hereinafter, an embodiment of the disclosed technology will be described with reference to an example in which the first value is 1 and the second value is 0.

[0161] For example, in the case of the first state (ST_1), the memory device 110 may set the result value of the first verification operation to 1, and may set the result value of the second verification operation to 0. In the case of the second state (ST_2), the memory device 110 may set the result value of the first verification operation to 1, and may set the result value of the second verification operation to 1. In the case of the third state (ST_3), the memory device 110 may set the result value of the first verification operation to 0, and may set the result value of the second verification operation to 1. Hereinafter, according to various embodiments, description will be made with reference to the case where the result value of the first verification operation and the result value of the second verification operation are set as described above.

[0162] If the programming operation is not suspended, the memory device 110 may store the result value of the first verification operation in one of the first data latch (DL_1) and the second data latch (DL_2), and may store the result value of the second verification operation in the remaining data latch. Therefore, the memory device 110 may determine the programming state of the memory cell based on the result value of the first verification operation stored in the first data latch (DL_1) and the result value of the second verification operation stored in the second data latch (DL_2).

[0163] Before resuming the suspended programming operation, the value stored in the first data latch (DL_1) or the second data latch (DL_2) may be changed by another operation (e.g., a read operation). The reason for this is that when reading data in a memory cell in a state where the programming operation is suspended, the first data latch (DL_1) or the second data latch (DL_2) may be used. In this case, the value stored in the first data latch (DL_1) or the second data latch (DL_2) before the programming operation is suspended may be lost.

[0164] Therefore, the memory device 110 may not be able to determine the programming state that the memory cell had before the programming operation was suspended based on the value stored in the first data latch (DL_1) and the value stored in the second data latch (DL_2). Therefore, in the process of resuming the suspended programming operation, the memory device 110 may need to generate the result value of the first verification operation and the result value of the second verification operation in order to accurately determine the programming state of the memory cell.

[0165] Hereinafter, a detailed embodiment will be described in conjunction with an operation in which the memory device 110 generates a result value of a first verification operation and a result value of a second verification operation when resuming a suspended program operation.

[0166] Figure 7is a diagram showing a value stored in the first data latch (DL_1) when a program operation is suspended.

[0167] When the program operation is suspended, the memory device 110 may store a temporary value in the first data latch (DL_1), the temporary value being obtained by performing an AND operation on the result value of the first verification operation and the result value of the second verification operation. In this case, when both result values ​​are first values, the value obtained by performing an AND operation on the two result values ​​is the first value; otherwise, the value obtained by performing the AND operation is the second value.

[0168] Reference Figure 7 , when the memory cell on which programming is performed is in the first state (ST_1), the memory device 110 can store a value 0 (=1AND 0) obtained by performing an AND operation on a result value 1 of the first verification operation and a result value 0 of the second verification operation in the first data latch (DL_1).

[0169] If the memory cell on which programming is performed is in the second state (ST_2), the memory device 110 can store 1 corresponding to the output of the AND operation of 1 (which is the result value of the first verification operation) and 1 (which is the result value of the second verification operation) in the first data latch (DL_1).

[0170] If the memory cell on which programming is performed is in the third state (ST_3), the memory device 110 can store 0 corresponding to the output of the AND operation of 0 (which is the result value of the first verification operation) and 1 (which is the result value of the second verification operation) in the first data latch (DL_1).

[0171] Figure 8 is a diagram illustrating a state of a first data latch and a state of a second data latch when a read operation is performed after a program operation is suspended.

[0172] Reference Figure 8 , when a read operation is performed after the program operation is suspended, the memory device 110 may use the second data latch (DL_2) for the read operation.

[0173] In this case, the first data latch (DL_1) stores a temporary value obtained by performing an AND operation on the result value of the first verification operation and the result value of the second verification operation, so the memory device 110 may not use the first data latch (DL_1) for the read operation. Therefore, information associated with the result value of the first verification operation and the result value of the second verification operation obtained before the program operation is suspended can be retained in the first data latch (DL_1).

[0174] Fig. 9 is a diagram illustrating an example of changes in threshold voltage distribution of memory cells on which programming is performed when a program operation is suspended.

[0175] Reference Fig. 9 In the process of resuming the suspended program operation, the threshold voltage distribution of the memory cells on which programming is performed may change. For example, when the program operation is suspended, there may be memory cells with reduced threshold voltages due to the carryover effect.

[0176] In this case, a memory cell having a threshold voltage greater than or equal to the second verification voltage (VER_2) before the program operation is suspended may have a threshold voltage less than the second verification voltage (VER_2) after the program operation is suspended. In this case, if a program pulse is provided to the memory cell without considering a program state obtained before the program operation is suspended, the program operation may not be performed correctly and an abnormal result may be obtained.

[0177] Therefore, the memory device 110 needs to identify the program state that the memory cell had before the program operation was suspended, so as to be able to correctly perform the program operation on the memory cell.

[0178] In some embodiments, the memory device 110 may be configured to identify the programming state of the memory cell before the programming operation is suspended based on the temporary value stored in the first data latch (DL_1) and the result value of the third verification operation. The third verification operation may be performed after the programming operation is resumed. This will be described in detail below.

[0179] Fig.10 is a diagram illustrating a result of a third verification operation when a program operation is resumed.

[0180] like Figure 5 As described in , when resuming the suspended program operation, the memory device 110 may perform a third verification operation.

[0181] If the program state of the memory cell is the first state (ST_1) before the program operation is suspended, the result of the first verification operation performed on the memory cell is 1, and the result of the second verification operation is 0.

[0182] In this case, the programming state of the memory cell after the program operation is resumed is also the first state (ST_1). The reason is that even if the threshold voltage is reduced due to the retention effect, the threshold voltage of the memory cell less than the second verification voltage (VER_2) is still less than the second verification voltage (VER_2). Therefore, the result of the third verification operation is also 0.

[0183] If the program state of the memory cell is the second state (ST_2) before the program operation is suspended, a result of the first verification operation performed on the memory cell is 1, and a result of the second verification operation is 1.

[0184] In this case, the programming state of the corresponding memory cell after the program operation is resumed may be one of a 2-1st state (ST_2-1) and a 2-2nd state (ST_2-2) that are different from each other. The 2-1st state (ST_2-1) is a state in which the threshold voltage of the corresponding memory cell is lowered below the second verification voltage (VER_2) after the program operation is resumed, and the 2-2nd state (ST_2-2) is a state in which the threshold voltage of the corresponding memory cell is greater than or equal to the second verification voltage (VER_2) after the program operation is resumed.

[0185] In the 2-1 state (ST_2-1), the threshold voltage of the memory cell is less than the second verification voltage (VER_2), so the result of the third verification operation is 0. In the 2-2 state (ST_2-2), the threshold voltage of the memory cell is greater than or equal to the second verification voltage (VER_2), so the result of the third verification operation is 1.

[0186] If the program state of the memory cell is the third state (ST_3) before the program operation is suspended, a result of the first verification operation performed on the memory cell is 0, and a result of the second verification operation is 1.

[0187] In this case, the threshold voltage of the memory cell after the program operation is resumed is greater than the verification voltage used in the third verification operation. Therefore, the result of the third verification operation is also 1.

[0188] As described above, when the programming operation is suspended, the first data latch (DL_1) stores a temporary value obtained by performing an AND operation on the result value of the first verification operation and the result value of the second verification operation. When the memory cell is in the first state (ST_1), the temporary value stored in the first data latch (DL_1) is 0, when the memory cell is in the second state (ST_2), the temporary value is 1, and when the memory cell is in the third state (ST_3), the temporary value is 0.

[0189] After the program operation resumes, the memory device 110 may store the temporary value stored in the first data latch ( DL_1 ) in the second data latch ( DL_2 ), and may store the result value of the third verification operation in the first data latch ( DL_1 ).

[0190] Hereinafter, a detailed embodiment will be described in conjunction with an operation for generating a result of a first verification operation and a result of a second verification operation that are the same as the result value obtained before the program operation is suspended based on the temporary value stored in the second data latch (DL_2) and the result value of the third verification operation stored in the first data latch (DL_1). The description will be made with reference to the case where the first value is 1 and the second value is 0.

[0191] Fig.11 is a diagram showing an example of a value stored in the first data latch ( DL_1 ) when a program operation resumes.

[0192] When generating or restoring the results of the first verification operation and the second verification operation that are the same as the results obtained before the programming operation was suspended, if the temporary value stored in the second data latch (DL_2) is the first value, the memory device 110 may set the value of the first data latch (DL_1) to the first value.

[0193] Reference Fig.11 , if the state of the memory cell is the second state (ST_2) before the program operation is suspended, the temporary value stored in the second data latch (DL_2) may be 1 when the program operation is resumed.

[0194] Therefore, if the state of the memory cell is the second state (ST_2) before the program operation is suspended, the value of the first data latch (DL_1) is set to 1 when the program operation is resumed. This is regardless of whether the state of the corresponding memory cell is the 2-1st state (ST_2-1) or the 2-2nd state (ST_2-2) after the program operation is resumed.

[0195] Fig.12 is a diagram illustrating an example of a value stored in the second data latch (DL_2) when a program operation resumes.

[0196] In the process of generating or restoring the result of the first verification operation and the result of the second verification operation that are the same as the result obtained before the programming operation is suspended, if the temporary value stored in the second data latch (DL_2) is the second value and the result value of the third verification operation stored in the first data latch (DL_1) is the second value, the memory device 110 may set the value of the second data latch (DL_2) to the first value.

[0197] Reference Fig.12, when the state of the memory cell is the first state (ST_1) before the programming operation is suspended, the result value of the third verification operation stored in the first data latch (DL_1) is 0, and the temporary value stored in the second data latch (DL_2) is 0, therefore, the value of the second data latch (DL_2) is set to 1 after the programming operation is resumed.

[0198] Therefore, if the state of the memory cell before the program operation is suspended is the first state (ST_1), the value of the first data latch (DL_1) after the program operation is resumed is 0. If the state of the memory cell before the program operation is suspended is the second state (ST_2), the value of the first data latch (DL_1) after the program operation is resumed is 1. If the state of the memory cell before the program operation is suspended is the third state (ST_3), the value of the first data latch (DL_1) after the program operation is resumed is 1. Therefore, the value of the first data latch (DL_1) after the program operation is resumed is the same as the result of the second verification operation obtained before the program operation was suspended.

[0199] If the state of the memory cell before the program operation is suspended is the first state (ST_1), the value of the second data latch (DL_2) after the program operation is resumed is 1. If the state of the memory cell before the program operation is suspended is the second state (ST_2), the value of the second data latch (DL_2) after the program operation is resumed is 1. If the state of the memory cell before the program operation is suspended is the third state (ST_3), the value of the second data latch (DL_2) after the program operation is resumed is 0. Therefore, the value of the second data latch (DL_2) after the program operation is resumed is the same as the result of the first verification operation obtained before the program operation was suspended.

[0200] Therefore, the memory device 110 can use the value of the first data latch (DL_1) to generate or restore the result value of the second verification operation that is the same as the result value obtained before the programming operation is suspended, and can use the second data latch (DL_2) to generate or restore the result value of the first verification operation that is the same as the result value obtained before the programming operation is suspended.

[0201] Fig.13 is a flowchart illustrating a method of operating the memory device 110 according to an embodiment of the disclosed technology.

[0202] The method of operating the memory device 110 may include, in operation S1310, when a suspend command associated with a program operation is received from the memory controller 120 while a program operation is performed on the memory cells, performing first and second verification operations on the memory cells.

[0203] The method of operating the memory device 110 may include an operation of storing a temporary value generated based on result values ​​of the first and second verification operations performed in operation S1310 in the first data latch ( DL_1 ) in operation S1320 .

[0204] The method of operating the memory device 110 may include: in operation S1330, when a resume command associated with a suspended programming operation is received, performing a third verification operation, and based on the result value of the third verification operation and a temporary value stored in the first data latch (DL_1), restoring the result value of the first verification operation and the result value of the second verification operation identically.

[0205] In this case, a verification voltage for the first verification operation may be higher than verification voltages for the second and third verification operations. The verification voltage for the second verification operation and the verification voltage for the third verification operation may be the same.

[0206] When the result value of the first verification operation and the result value of the second verification operation are both first values, the temporary value may be the first value, and when the result value of the first verification operation or the result value of the second verification operation is the second value, the temporary value may be the second value.

[0207] In operation S1330, when a resume command associated with a program operation is received, the temporary value stored in the first data latch (DL_1) is stored in the second data latch (DL_2), and a result value of the third verification operation is stored in the first data latch (DL_1).

[0208] In operation S1330, if the temporary value stored in the second data latch (DL_2) is the first value, the value of the first data latch (DL_1) is set to the first value, and if the temporary value stored in the second data latch (DL_2) and the result value of the third verification operation stored in the first data latch (DL_1) are both second values, the value of the second data latch (DL_2) is set to the first value.

[0209] Fig.14 is a diagram showing a configuration of a computing system 1400 according to an embodiment of the disclosed technology.

[0210] Reference Fig.14, a computing system 1400 according to an embodiment of the disclosed technology may include: a memory system 1400, electrically connected to a system bus 1460; a CPU 1410, configured to control the overall operation of the computing system 1400; a RAM 1420, configured to store data and information related to the operation of the computing system 1400; a user interface / user experience (UI / UX) module 1430, configured to provide a user environment to a user; a communication module 1440, configured to communicate with an external device in a wired and / or wireless manner; and a power management module 1450, configured to manage the power used by the computing system 1400.

[0211] The computing system 1400 may be a personal computer (PC) or may include a mobile terminal such as a smartphone, a tablet computer, or various electronic devices.

[0212] The computing system 1400 may further include a battery for supplying an operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and a DRAM. Other elements will be apparent to those skilled in the art.

[0213] The memory system 100 may include not only a device configured to store data in a disk, such as a hard disk drive (HDD), but also a device configured to store data in a non-volatile memory, such as a solid state drive (SSD), a universal flash memory device, or an embedded MMC (eMMC) device. The non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. In addition, the memory system 100 may be implemented as various types of storage devices and may be installed inside various electronic devices.

[0214] According to the embodiments of the above disclosed technology, the operation delay time of the memory system can be minimized. In addition, according to the embodiments of the disclosed technology, the overhead generated in the process of calling a specific function can be minimized. Although various embodiments of the disclosed technology have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions can be made based on the disclosure of this document.

Claims

1. A memory system, comprising: A memory device comprising a memory cell array including memory cells programmable in multiple states; as well as a memory controller communicating with the memory device and controlling the memory device, wherein the memory device further comprises a first data latch storing information about a state of the memory cell, and: In response to receiving a suspend command from the memory controller to suspend a program operation being performed on the memory cell, performing a first verification operation and a second verification operation on the memory cell, wherein the first verification operation and the second verification operation are performed using a verification voltage to determine a state of the memory cell; storing a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation in the first data latch; and In response to receiving a resume command to resume the programming operation from the memory controller, a third verification operation is performed, and result values ​​of the first verification operation and the second verification operation are restored based on result values ​​of the third verification operation and the temporary value stored in the first data latch. 2 . The memory system of claim 1 , wherein a verification voltage for the first verification operation is higher than verification voltages for the second verification operation and the third verification operation. 3 . The memory system of claim 2 , wherein a verification voltage used for the second verification operation and a verification voltage used for the third verification operation are the same.

4. The memory system according to claim 1, wherein the memory device: when a result value of the first verification operation and a result value of the second verification operation are both first values, sets the temporary value to the first value; and when a result value of the first verification operation or a result value of the second verification operation is a second value, sets the temporary value to the second value. 5 . The memory system of claim 4 , wherein the memory device further comprises a second data latch used during a read operation performed between receiving the suspend command and receiving the resume command.

6. The memory system of claim 5 , wherein the memory device further: in response to receiving the resume command, stores the temporary value stored in the first data latch in the second data latch; and stores a result value of the third verification operation in the first data latch.

7. The memory system of claim 6, wherein the memory device further: When the temporary value stored in the second data latch is the first value, setting the value of the first data latch to the first value; and When the temporary value stored in the second data latch and the result value of the third verification operation stored in the first data latch are both the second value, the value of the second data latch is set to the first value.

8. A memory device in communication with a memory controller, the memory device comprising: Memory cells, programmable in multiple states; a first data latch storing information about a state of the memory cell, and wherein the memory device further: In response to receiving a suspend command from the memory controller to suspend a program operation being performed on the memory cell, performing a first verification operation and a second verification operation on the memory cell, wherein the first verification operation and the second verification operation are performed using different verification voltages to verify a state of the memory cell; storing a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation in the first data latch; and In response to receiving a resume command to resume the programming operation from the memory controller, a third verification operation is performed, and result values ​​of the first verification operation and the second verification operation are restored based on result values ​​of the third verification operation and the temporary value stored in the first data latch. 9 . The memory device of claim 8 , wherein a verification voltage for the first verification operation is higher than verification voltages for the second and third verification operations. 10 . The memory device of claim 9 , wherein a verification voltage for the second verification operation is the same as a verification voltage for the third verification operation.

11. The memory device of claim 8 , wherein when a result value of the first verification operation and a result value of the second verification operation are both first values, the temporary value is set to the first value; and when a result value of the first verification operation or a result value of the second verification operation is a second value, the temporary value is set to the second value.

12. The memory device of claim 11 , further comprising: The second data latch is used during a read operation performed between receiving the suspend command and receiving the resume command.

13. The memory device of claim 12, wherein the memory device further: in response to receiving the resume command, stores the temporary value stored in the first data latch in the second data latch; and stores a result value of the third verification operation in the first data latch.

14. The memory device of claim 13, wherein the memory device further, in response to receiving the restore command: when the temporary value stored in the second data latch is the first value, sets the value of the first data latch to the first value; and When the temporary value stored in the second data latch and the result value of the third verification operation stored in the first data latch are both the second value, the value of the second data latch is set to the first value.

15. A method of operating a memory device, the memory device communicating with a memory controller, the method comprising: receiving a suspend command from the memory controller to suspend a programming operation being performed on a memory cell, the memory cell being included in the memory device and being programmable in a plurality of states; performing a first verification operation and a second verification operation on the memory cell using a verification voltage to determine a state of the memory cell; storing a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation in a first data latch of the memory device; receiving a resume command from the memory controller to resume the programming operation; as well as A third verification operation is performed, and a result value of the first verification operation and a result value of the second verification operation are restored based on a result value of the third verification operation and the temporary value stored in the first data latch.

16. The method according to claim 15, wherein when the result value of the first verification operation and the result value of the second verification operation are both first values, the temporary value is the first value, and when the result value of the first verification operation or the result value of the second verification operation is a second value, the temporary value is the second value.

17. The method according to claim 16, wherein restoring the result value of the first verification operation and the result value of the second verification operation comprises: The temporary value stored in the first data latch is stored in the second data latch, and a result value of the third verification operation is stored in the first data latch.

18. The method according to claim 17, wherein restoring the result value of the first verification operation and the result value of the second verification operation comprises: When the temporary value stored in the second data latch is the first value, setting the value of the first data latch to the first value, and When the temporary value stored in the second data latch and the result value of the third verification operation stored in the first data latch are both the second value, the value of the second data latch is set to the first value.

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