Stacked capacitor, semiconductor memory device, and method of manufacture

Abstract

The application relates to the technical field of semiconductors, in particular to a capacitor, which comprises a bottom electrode, a dielectric layer formed on the bottom electrode, and a top electrode assembly formed on the dielectric layer, wherein the top electrode assembly comprises a first top electrode, a second top electrode and a third top electrode which are sequentially stacked from one side of the dielectric layer; the first top electrode is a metal layer, the second top electrode is a carbon and boron doped silicon germanium layer, and the third top electrode is a boron doped silicon germanium layer. By forming the carbon and boron doped silicon germanium layer between the first top electrode and the third top electrode, a double structure of the carbon and boron doped silicon germanium layer and the boron doped silicon germanium layer is formed on the first top electrode, the resistance increase is greatly reduced, the residual stress of the boron doped silicon germanium layer is also reduced, the mechanical stress generated by the boron doped silicon germanium layer on the dielectric layer of the capacitor is lowered, and the dielectric leakage problem of the dielectric layer is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a stacked capacitor, a semiconductor memory device and a preparation method. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, which is composed of many repeated DRAM memory units, each of which includes a single transistor and a single capacitor coupled in series with the transistor. The structure of the capacitor can be divided into trench type and stacked type. The traditional DRAM structure is shown in FIG. 1, wherein the structure of the capacitor in the DRAM is shown in FIG. 2. The capacitor is a vertical high aspect ratio cylindrical shape to increase the surface area. The top electrode (plate poly) of the capacitor is formed by the following process: forming a plate-shaped polysilicon on a TiN layer. Specifically, the plate-shaped polysilicon can be boron-doped silicon germanium (SiGe). Under certain process conditions, high-concentration boron (B) gas and high-flow Ge are reacted. During the growth of boron-doped silicon germanium, the grain size gradually increases, and finally grows into a polysilicon with a columnar structure, as shown in FIG. 3. At this time, the residual stress of the plate-shaped boron-doped silicon germanium (B-doped SiGe) crystal will generate a compressive stress of about 0.1-0.5 GPa, which will generate mechanical stress on the dielectric layer of the capacitor, induce thermalization of the capacitor, and further cause leakage. Figure 1 Figure 2 Figure 3 SUMMARY

[0003] The present application at least partially solves the above technical problems in the related art. To this end, the present application provides a stacked capacitor, a semiconductor memory device and a preparation method, which reduces the residual stress of the capacitor dielectric layer and solves the problem of capacitor leakage.

[0004] To achieve the above purpose, the first aspect of the present application provides a capacitor, comprising:

[0005] a bottom electrode;

[0006] a dielectric layer formed on the bottom electrode;

[0007] ​​​A top electrode assembly is formed on the dielectric layer, and the top electrode assembly includes a first top electrode, a second top electrode, and a third top electrode that are sequentially stacked from one side of the dielectric layer.

[0008] The first top electrode is a metal layer, the second top electrode is a silicon-germanium layer doped with carbon and boron, and the third top electrode is a silicon-germanium layer doped with boron.

[0009] A second aspect of this application provides a semiconductor device including the capacitor described above.

[0010] A third aspect of this application provides an electronic device, including the semiconductor device described above.

[0011] The fourth aspect of this application provides a method for manufacturing a capacitor, comprising the following steps:

[0012] Deposit a bottom electrode on a semiconductor substrate;

[0013] A dielectric layer is deposited over the bottom electrode to cover the bottom electrode;

[0014] A top electrode assembly is deposited over the dielectric layer to cover the dielectric layer;

[0015] Depositing a top electrode assembly above the dielectric layer includes the following steps:

[0016] A first top electrode, a second top electrode, and a third top electrode are sequentially deposited on top of the dielectric layer. The first top electrode is a metal layer, the second top electrode is a silicon-germanium layer doped with carbon and boron, and the third top electrode is a silicon-germanium layer doped with boron. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Figure 1 This is a schematic SEM image of a partial cross-section of a DRAM in the prior art;

[0019] Figure 2 for Figure 1 A magnified view of a section at point A in the middle;

[0020] Figure 3 for Figure 2 A magnified view of a section at point B in the middle;

[0021] Figure 4A cross-sectional view of a stacked capacitor according to some embodiments of the present application;

[0022] Figure 5 A cross-sectional view of a top electrode assembly according to some embodiments of the present application; Figure 4 A SEM image at C;

[0023] Figure 6 A SEM image of a cross-sectional view of a top electrode assembly according to some embodiments of the present application;

[0024] Figure 7 A graph of XRD data of second top electrodes with different carbon contents according to some embodiments of the present application;

[0025] Figure 8 A graph of crystalline grain size versus tension and pressure according to some embodiments of the present application;

[0026] Figure 9 A graph of the effect of carbon doping on the performance of a stacked capacitor, where A represents a conventional stacked capacitor and B represents a stacked capacitor according to some embodiments of the present application. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present disclosure, and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid obscuring the concept of the present disclosure.

[0028] In the drawings, various structural diagrams according to embodiments of the present disclosure are illustrated. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary, and can be varied in actuality due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0029] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0030] Referring to Figures 4-6 A first aspect of the present application provides a cylindrical capacitor 100, the capacitor 100 comprising:

[0031] a bottom electrode 10;

[0032] The dielectric layer 11 is formed on the bottom electrode 10;

[0033] The top electrode assembly 12 is formed on the dielectric layer 11, and the top electrode assembly 12 comprises a first top electrode 120, a second top electrode 121 and a third top electrode 122 which are sequentially stacked from one side of the dielectric layer 11;

[0034] The first top electrode 120 is a metal layer, the second top electrode 121 is a carbon and boron doped silicon germanium layer, and the third top electrode 122 is a boron doped silicon germanium layer.

[0035] That is, the bottom electrode 10, the dielectric layer 11 and the top electrode assembly 12 are sequentially stacked on the interlayer dielectric layer.

[0036] It is worth mentioning that, as shown in Figures 5-9 When the boron doped silicon germanium layer is doped with carbon to form the carbon and boron doped silicon germanium layer, the particle size of the boron doped silicon germanium layer is sharply reduced, and the crystal structure is changed from columnar structure to random structure, as shown in Figure 8 The residual stress is also changed from compressive stress 0.1-0.5 GPa to close to 0. In addition, during the carbon doping process, the efficiency of doping activation is reduced, and the resistance is increased. At this time, when the capacitor 100 is carbon doped with a thickness of 5002, the residual stress can be reduced, and when the thickness is more than 10002, it becomes a double structure of the boron doped silicon germanium layer without carbon doping. Through the double structure, the resistance increase can be minimized, and the capacitor leakage problem is solved.

[0037] In the embodiment, the material of the bottom electrode 10 and the first top electrode 120 is selected from any one of copper, aluminum, titanium nitride, titanium, platinum, iridium or ruthenium. Specifically, the bottom electrode 10 and the first top electrode 120 can comprise a copper metal layer, and the first top electrode 120 can specifically be a copper metal layer. If the bottom electrode 10 and the first top electrode 120 comprise a copper metal layer, the copper metal layer can be formed by a damascene process. According to the damascene process, the insulating layer is partially etched by a photo-etching process to form a trench, and a copper seed layer is deposited on the insulating layer so that the copper seed layer fills the trench. Then, the copper seed layer is planarized by a chemical mechanical polishing process, thereby forming a copper interconnection.

[0038] In addition, the bottom electrode 10 and the first top electrode 120 can comprise an aluminum metal layer. If the bottom electrode 10 and the first top electrode 120 comprise an aluminum metal layer, the aluminum layer is formed on the insulating layer, and then the aluminum layer is patterned by a photo-etching process.

[0039] Note that the material for the bottom electrode 10 and the first top electrode 120 is not limited to copper or aluminum, and various conductive materials can be used in accordance with the metal interconnection for a semiconductor device. The capacitor of the present application can be formed between the metal interconnection layers. In this case, the electrodes of the capacitor can include the metal interconnection. Further, the first top electrode 120 can include a metal layer having a Ti and TiN laminated structure, and in the metal layer, Ta can be used instead of Ti.

[0040] Further, the weight percentage of germanium in the third top electrode 122 is greater than 40%, and the weight percentage of carbon is 2-7%.

[0041] Specifically, in the present embodiment, the thickness of the second top electrode 121 is 2002-8002, and the thickness of the third top electrode 122 is greater than 10002.

[0042] Further, in the present embodiment, the dielectric layer 11 has a split structure, and the dielectric layer 11 includes a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 stacked in order from the bottom electrode. The first dielectric layer 110 and the third dielectric layer 112 are each made of zirconium oxide, and the second dielectric layer 111 is made of aluminum oxide.

[0043] Note that the band gap of the first dielectric layer 110 and the third dielectric layer 112 can be greater than the band gap of the second dielectric layer 111. The band gap of the second dielectric layer 111 can be about 5.7 eV. If the thickness of the second dielectric layer 112 is less than a predetermined thickness, the characteristics of the second dielectric layer (e.g., the leakage current characteristics) can be reduced. However, since the first dielectric layer 110 and the third dielectric layer 112 having a relatively high band gap are formed below the lower surface and above the upper surface of the second dielectric layer 111, the leakage current characteristics and the breakdown voltage characteristics are improved.

[0044] Further, the dielectric constant of the second dielectric layer 111 can be higher than the dielectric constant of the first dielectric layer 110 and the third dielectric layer 112.

[0045] Note that the dielectric layer 11 can also have a monolithic structure, and specifically, the dielectric layer 11 is made of any one of zirconium oxide, hafnium oxide, and tantalum oxide.

[0046] The manufacturing method of the capacitor in the present embodiment will be described below.

[0047] Specifically, the manufacturing method of the capacitor 100 includes the following steps:

[0048] forming the bottom electrode 10 on the semiconductor substrate;

[0049] A dielectric layer 11 is formed over the bottom electrode 10 to cover the bottom electrode 10;

[0050] A top electrode assembly 12 is formed over the dielectric layer 11 to cover the dielectric layer 11;

[0051] The forming of the top electrode assembly 12 over the dielectric layer 11 includes the following steps:

[0052] The first top electrode 110, the second top electrode 111 and the third top electrode 112 are sequentially stacked over the dielectric layer 11, the first top electrode 110 is a metal layer, the second top electrode 111 is a carbon-doped and boron-doped silicon germanium layer, and the third top electrode 112 is a boron-doped silicon germanium layer.

[0053] It should be noted that the upper surface of the semiconductor substrate has already formed an insulating layer with aluminum metal interconnection.

[0054] The semiconductor substrate with the bottom electrode 10 is placed in an ALD (atomic layer deposition) device, so that the first to third dielectric layers 110, 111 and 112 are sequentially deposited on the bottom electrode 10. If the ALD method is used, the dielectric layer 11 with a thickness of 1 nm needs to be deposited for one cycle. Then, the dielectric layer 11 with the desired thickness can be deposited by repeating the number of cycles, specifically, the ALD process can be carried out at a processing temperature of about 300-400°C.

[0055] First, the first dielectric layer 110 can be deposited on the semiconductor substrate with the bottom electrode 10. The first dielectric layer 110 can include zirconium oxide (ZrO2). The first dielectric layer 110 can be formed by reacting TEMAHf (tetra[ethylmethylamino]hafnium) as a precursor with ozone (O3).

[0056] When the first dielectric layer 110 is deposited, the second dielectric layer 111 is then deposited on the first dielectric layer 110. The second dielectric layer 111 can include aluminum trioxide (Al2O3), and the second dielectric layer 111 can be formed by reacting TMA (trimethylaluminum) as a precursor with ozone (O3).

[0057] When the second dielectric layer 111 is deposited, the third dielectric layer 112 is then deposited on the second dielectric layer 111. The third dielectric layer 112 can include zirconium oxide (ZrO2). The third dielectric layer 112 can be formed by reacting TEMAHf (tetra[ethylmethylamino]hafnium) as a precursor with ozone (O3).

[0058] It is worth mentioning that, since the band gap of the first dielectric layer 110 and the third dielectric layer 112 is larger than that of the second dielectric layer 111, the leakage current characteristics and the breakdown voltage characteristics of the dielectric layer 11 can be improved. In addition, since the second dielectric layer 111 has a high dielectric constant, the dielectric layer 11 can have a high capacitance.

[0059] Further, the structure obtained by forming the first top electrode 110 above the dielectric layer 11 is placed in a chemical vapor deposition furnace tube;

[0060] The source gas of germanium, the source gas of boron and the source gas of silicon are simultaneously introduced into the chemical vapor deposition furnace tube to react to form the third top electrode 112. In the process of growing the third top electrode 112, the source gas of carbon is introduced to form carbon in the third top electrode 112 in an in-situ doping manner to form the second top electrode 111 between the third top electrode 112 and the first top electrode 110.

[0061] Specifically, the process conditions for forming the second top electrode 111 are: the reaction temperature is 400-430℃, the concentration of the source gas of boron is greater than 1E21cm -3 , the proportion of the source gas of germanium in the total flow of the reaction gas is greater than 40%, and the source gas of carbon accounts for 2-7% of the total flow of the reaction gas.

[0062] Further, the source gas of germanium can include GeH4 or Ge2H6, the source gas of carbon can include C2H4 or SiH3CH3, the source gas of boron can include BCl3 or B2H6, and the source gas of silicon can include SiH4 or Si2H6.

[0063] Figure 5 A chart showing the characteristic parameter values of the capacitor provided in the embodiments of the present application.

[0064] After the source gas of germanium, the source gas of boron and the source gas of silicon, a boron-doped silicon germanium layer, i.e. the third top electrode 112, is formed, and then the source gas of carbon is introduced to dope carbon in the boron-doped silicon germanium layer. At this time, the particle size of the boron-doped silicon germanium layer is sharply reduced, and the crystal structure is changed from columnar structure to random structure, as shown in Figure 8 , and further a carbon and boron-doped silicon germanium layer is formed, and the residual stress of the carbon and boron-doped silicon germanium layer is also changed from compressive stress 0.1-0.5GPa to close to 0. In addition, in the process of carbon doping, the efficiency of doping activation is reduced, and further the resistance is increased. At this time, in the capacitor 100 with a thickness of 500a, carbon doping can reduce the residual stress, and in the thickness of 1000a or more, a double structure of the boron-doped silicon germanium layer without carbon doping is formed. Through the double structure, the increase of resistance can be maximally reduced, so that the electrical stability and the leakage current characteristics can be improved.

[0065] The capacitor in the embodiment can be used in a semiconductor device, so that the capacitor has an advantage in the development of high-tech DRAM and CMDS devices.

[0066] It should be noted that when the capacitor is used in DRAM, Flash and Logic, transistors (not shown) coupled with the capacitor in series can be formed by known manufacturing processes to complete the manufacture of DRAM.

[0067] Further, the DRAM, Flash and Logic with the capacitor in the embodiment can be used in various chips.

[0068] Further, the chip with the capacitor can be used in various electronic devices, and specifically, the electronic device can be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, a mobile power supply, etc.

[0069] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the above-described methods in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0070] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. A capacitor, characterized in that, include: Bottom electrode; A dielectric layer is formed on the bottom electrode; A top electrode assembly is formed on the dielectric layer, and the top electrode assembly includes a first top electrode, a second top electrode, and a third top electrode that are sequentially stacked from one side of the dielectric layer. The first top electrode is a metal layer, the second top electrode is a silicon-germanium layer doped with carbon and boron, and the third top electrode is a silicon-germanium layer doped with boron. The process conditions for forming the second top electrode are: a reaction temperature of 400-430℃ and a boron source gas concentration greater than 1E21cm⁻¹. -3 The flow rate of germanium source gas accounts for more than 40% of the total flow rate of reactant gas, while carbon source gas accounts for 2-7% of the total flow rate of reactant gas.

2. The capacitor according to claim 1, characterized in that, The metal layer is made of any one of copper, aluminum, titanium nitride, titanium, platinum, iridium, or ruthenium.

3. The capacitor according to claim 1, characterized in that, The dielectric layer has a split structure, and the dielectric layer includes a zirconium oxide layer, an aluminum oxide layer and a zirconium oxide layer stacked sequentially on the bottom electrode.

4. The capacitor according to claim 1, characterized in that, The dielectric layer has an integral structure, and the material of the dielectric layer is selected from any one of zirconium oxide, hafnium oxide, and tantalum oxide.

5. The capacitor according to claim 1, characterized in that, The material of the bottom electrode is selected from any one of copper, aluminum, titanium nitride, titanium, platinum, iridium or ruthenium.

6. A semiconductor device, characterized in that, The capacitor includes any one of claims 1 to 5.

7. An electronic device, characterized in that, Includes the semiconductor device as described in claim 6.

8. The electronic device according to claim 7, characterized in that, The electronic devices include smartphones, computers, wearable smart devices, artificial intelligence devices, and power banks.

9. A method for manufacturing a capacitor, comprising the following steps: A bottom electrode is formed on a semiconductor substrate; A dielectric layer is formed above the bottom electrode to cover the bottom electrode; A top electrode assembly is formed above the dielectric layer to cover the dielectric layer; The process of forming a top electrode assembly above the dielectric layer includes the following steps: A first top electrode, a second top electrode, and a third top electrode are sequentially stacked on top of the dielectric layer. The first top electrode is a metal layer, the second top electrode is a silicon-germanium layer doped with carbon and boron, and the third top electrode is a silicon-germanium layer doped with boron. The process conditions for forming the second top electrode are: a reaction temperature of 400-430℃ and a boron source gas concentration greater than 1E21cm⁻¹. -3 The flow rate of germanium source gas accounts for more than 40% of the total flow rate of reactant gas, while carbon source gas accounts for 2-7% of the total flow rate of reactant gas.

10. The method for manufacturing a capacitor according to claim 9, characterized in that, The steps of forming the second top electrode and the third top electrode include: Simultaneously, germanium source gas, boron source gas, and silicon source gas are introduced to react and form a third top electrode. During the growth of the third top electrode, carbon source gas is introduced to form carbon in part of the third top electrode in an in-situ doping manner, so as to form a second top electrode between the third top electrode and the first top electrode.

11. The method for preparing a capacitor according to claim 10, characterized in that, The germanium source gas includes GeH4 or Ge2H6, the carbon source gas includes C2H4 or SiH3CH3, the boron source gas includes BCl3 or B2H6, and the silicon source gas includes SiH4 or Si2H6.

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