A filtering circuit design method, device, storage medium and electronic device

Abstract

This application relates to the technical field of filters, and specifically relates to a method and device for designing a filter circuit, a storage medium, and an electronic device, which can flexibly select the topological structure and related parameters of a filter circuit that conforms to the inverter structure, and suppress electromagnetic interference generated by the inverter or surrounding devices with the most reasonable filter circuit. The method includes: obtaining the source impedance and load impedance of the inverter; determining the topological structure of the filter circuit according to the source impedance and the load impedance; determining the insertion loss that the filter circuit needs to compensate; calculating the cut-off frequency of the filter circuit by using the cut-off frequency calculation formula; obtaining at least one capacitor corresponding to the topological structure; and determining the inductor corresponding to the filter circuit according to at least one of the capacitors and the filter transfer function corresponding to the topological structure.

Description

Technical Field

[0001] The present application relates to the technical field of filters, and particularly to a method and device for designing a filter circuit, a storage medium, and an electronic device. Background Art

[0002] Due to the increasing use of photovoltaic power generation systems, when developing photovoltaic inverter devices, the electromagnetic interference filtering circuits on the input and output sides become very important. This filtering circuit can not only prevent the high-frequency electromagnetic interference generated by the inverter itself from interfering with the surrounding sensitive electromechanical devices, but also prevent the inverter itself from being interfered by the high-frequency harmonics on the grid side and the photovoltaic panel side.

[0003] Currently, the traditional design method is to directly specify the filter topology, and the design is relatively rigid. Also, due to safety regulations requirements, the capacitance values of the capacitors used in the filter topology are all relatively small. Therefore, the order of magnitude differences of the inductance values in different filter topologies calculated by backstepping are very large. And in the design and manufacture of inductors, the difference in order of magnitude is almost equivalent to the huge difference in volume. So, in devices with requirements for space and volume, the practicality is relatively low. Summary of the Invention

[0004] The present application provides a method and device for designing a filter circuit, a storage medium, and an electronic device, which flexibly select the topology structure and its related parameters of the filter circuit that conforms to the inverter structure, and suppress the electromagnetic interference generated by the inverter or surrounding devices with the most reasonable filter circuit.

[0005] In a first aspect, the present application provides a method for designing a filter circuit, the method comprising:

[0006] Obtain the source impedance and load impedance of the inverter;

[0007] Determine the topology structure of the filter circuit according to the source impedance and the load impedance;

[0008] Determine the insertion loss that the filter circuit needs to compensate;

[0009] Calculate the cut-off frequency of the filter circuit by using the cut-off frequency calculation formula;

[0010] Obtain at least one capacitor corresponding to the topology structure;

[0011] Determine the inductor corresponding to the filter circuit according to at least one of the capacitors and the filter transfer function corresponding to the topology structure.

[0012] According to an embodiment of the present application, optionally, in the above filter circuit design method, determining the topology structure of the filter circuit according to the source impedance and the load impedance includes:

[0013] Obtain a topology correspondence table, where the topology correspondence table includes the correspondence relationships among multiple source impedances, multiple load impedances, and multiple topologies;

[0014] Search for the topology corresponding to the source impedance and load impedance of the inverter in the topology correspondence table.

[0015] According to an embodiment of the present application, optionally, in the above filter circuit design method, determining the insertion loss that the filter circuit needs to compensate includes:

[0016] Obtain a preset curve and the conducted emission interference curve of the inverter, where the preset curve is a relationship curve between a frequency band and the standard noise corresponding to the frequency band;

[0017] Take the maximum difference between the preset curve and the conducted emission interference curve as the insertion loss that the filter circuit needs to compensate.

[0018] According to an embodiment of the present application, optionally, in the above filter circuit design method, the cut-off frequency calculation formula is:

[0019] loss×lg(F / F 0 )=D;

[0020] where loss is the fixed loss corresponding to the topology of the filter circuit, F is the interference frequency, F 0 is the cut-off frequency, and D is the insertion loss that the filter circuit needs to compensate.

[0021] According to an embodiment of the present application, optionally, in the above filter circuit design method, obtaining at least one capacitor corresponding to the topology includes:

[0022] Search for at least one capacitor corresponding to the topology in the capacitor correspondence table, where the capacitor correspondence table includes multiple preset topologies, the number of preset capacitors corresponding to each topology, and the capacitance values corresponding to each preset capacitor.

[0023] According to an embodiment of the present application, optionally, in the above filter circuit design method, when the topology includes a common-mode filter topology, obtaining at least one capacitor corresponding to the topology includes a first common-mode capacitor and a second common-mode capacitor, the inductor is a common-mode inductor, and the filter transfer function is:

[0024]

[0025] where F 0 is the cut-off frequency, L cm is the common-mode inductor, and C cm is the first common-mode capacitor or the second common-mode capacitor.

[0026] According to an embodiment of the present application, optionally, in the above filtering circuit design method, when the topological structure includes a differential-mode filtering topological structure, obtaining at least one capacitor corresponding to the topological structure includes a first differential-mode capacitor and a second differential-mode capacitor, the inductor is a differential-mode inductor, and the filter transfer function is:

[0027]

[0028] where F 0 is the cut-off frequency, L dm is the differential-mode inductor, C dm1 is the first differential-mode capacitor, C dm2 is the second differential-mode capacitor, R 2 is the load resistance.

[0029] In a second aspect, the present application provides a filtering circuit design device, which includes:

[0030] A first acquisition module, configured to acquire the source impedance and the load impedance of an inverter;

[0031] A first determination module, configured to determine the topological structure of the filtering circuit according to the source impedance and the load impedance;

[0032] A second determination module, configured to determine the insertion loss that the filtering circuit needs to compensate;

[0033] A calculation module, configured to calculate the cut-off frequency of the filtering circuit by using the cut-off frequency calculation formula;

[0034] A second acquisition module, configured to acquire at least one capacitor corresponding to the topological structure;

[0035] A third determination module, configured to determine the inductor corresponding to the filtering circuit according to at least one of the capacitors and the filter transfer function corresponding to the topological structure.

[0036] In a third aspect, the present application provides a storage medium, which stores a computer program. When the computer program is executed by one or more processors, the filtering circuit design method described in any item of the first aspect above is implemented.

[0037] In a fourth aspect, the present application provides an electronic device, including a memory and a processor. A computer program is stored on the memory. When the computer program is executed by the processor, the filtering circuit design method described in any item of the first aspect above is implemented.

[0038] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0039] A filter circuit design method, device, storage medium and electronic device provided by the present application. The method includes: obtaining the source impedance and load impedance of an inverter; determining the topological structure of the filter circuit according to the source impedance and the load impedance; determining the insertion loss that the filter circuit needs to compensate; calculating the cut-off frequency of the filter circuit by using the cut-off frequency calculation formula; obtaining at least one capacitor corresponding to the topological structure; and determining the inductor corresponding to the filter circuit according to at least one of the capacitors and the filter transfer function corresponding to the topological structure. The topological structure and its related parameters of the filter circuit that conforms to the inverter structure are flexibly selected to suppress the electromagnetic interference generated by the inverter or surrounding devices with the most reasonable filter circuit. Description of the Drawings

[0040] In the following, the present application will be described in more detail based on embodiments and with reference to the drawings.

[0041] Figure 1 It is a schematic flow chart of a filter circuit design method provided in Embodiment 1 of the present application.

[0042] Figure 2 It is a schematic structural diagram of a filter circuit with a common-mode filter topology structure provided in Embodiment 1 of the present application.

[0043] Figure 3 It is a schematic structural diagram of a filter circuit with a differential-mode filter topology structure provided in Embodiment 1 of the present application. Detailed Embodiments

[0044] The following will combine the drawings and embodiments to detail the implementation manners of the present application, so as to fully understand how the present application uses technical means to solve technical problems and the implementation process of achieving corresponding technical effects and implement accordingly. Each feature in the embodiments of the present application and in the embodiments can be combined with each other on the premise of not conflicting, and the formed technical solutions are all within the protection scope of the present application.

[0045] Example 1

[0046] Please refer to Figure 1 , the present application provides a filter circuit design method applicable to electronic devices such as mobile phones, computers or tablet computers. When the filter circuit design method is applied to the electronic device, steps S110 to S160 are executed.

[0047] Step S110: Obtain the source impedance and load impedance of the inverter.

[0048] In this embodiment, the source impedance and load impedance of the inverter can be measured according to the actual situation.

[0049] It should be noted that, according to circuit principles, when the source impedance of a circuit matches the load impedance of the circuit, the energy transfer efficiency of the circuit is the highest. On the contrary, when the source impedance of the circuit and the load impedance of the circuit are unbalanced (i.e., mismatched), the energy transfer efficiency of the circuit will decrease. Therefore, when wanting to filter out the energy of a certain frequency, the principle of impedance mismatch can be utilized to reduce the energy transfer efficiency of the circuit, and different filter structures will achieve the mismatch between the source impedance and the load impedance of the circuit. In the embodiment, the inverter is a photovoltaic inverter.

[0050] Step S120: Determine the topological structure of the filter circuit according to the source impedance and the load impedance.

[0051] In practical applications, the topological structures include π-type (e.g., common-mode filter), LC-type (e.g., differential-mode filter), etc. The circuit structures of different topological structures are different, and the components (e.g., capacitors) that make up the circuit structure are different.

[0052] In this embodiment, determining the topological structure of the filter circuit corresponding to the inverter specifically includes: obtaining a topological structure correspondence table, and searching in the topological structure correspondence table for the topological structure corresponding to the source impedance and the load impedance of the inverter. Wherein, the topological structure correspondence table includes the corresponding relationships between multiple source impedances, multiple load impedances, and multiple topological structures.

[0053] In some embodiments, the topological structure correspondence table is shown in the following table:

[0054]

[0055] It should be understood that the above topological structure correspondence table may also include other forms, which can be specifically set according to actual needs. This embodiment does not make any limitation thereto.

[0056] Step S130: Determine the insertion loss that the filter circuit needs to compensate.

[0057] In this embodiment, the ability of the filter to suppress interference noise can be measured by insertion loss. Determining the insertion loss that the filter circuit needs to compensate specifically includes:

[0058] First, obtain a preset curve and the conducted emission interference curve of the inverter. Wherein, the preset curve is a relationship curve between a frequency band and the standard noise corresponding to the frequency band. This frequency band can be 0.15 MHz - 30 MHz (this frequency band is the frequency band for electromagnetic interference testing), and in this frequency band, each frequency corresponds to a noise voltage. The conducted emission interference curve can be obtained by detecting the inverter with a special detector.

[0059] Then, the maximum difference between the preset curve and the conducted emission interference curve is taken as the insertion loss that the filter circuit needs to compensate. Generally, at the same abscissa (frequency), the preset curve and the conducted emission interference curve respectively correspond to an ordinate (i.e., noise voltage), and the difference between the ordinates of the two curves at the same abscissa is determined. When determining the insertion loss that the filter circuit needs to compensate, generally the maximum difference between the preset curve and the conducted emission interference curve (i.e., the maximum difference between the ordinates of the two curves at the same abscissa) is taken as the compensation value (i.e., insertion loss). And since the curves of the inverter in the above frequency band are basically parallel to each other up and down, after compensating at the frequency corresponding to the maximum difference, there is no need to compensate other frequency points.

[0060] It should be noted that when there is a situation where the conducted emission interference curve is higher than the preset curve (i.e., the current noise of the inverter is higher than the standard noise), it indicates that a filter circuit needs to be inserted to compensate for the part where the conducted emission interference curve is higher than the preset curve.

[0061] Step S140: Calculate the cut-off frequency of the filter circuit by using the cut-off frequency calculation formula.

[0062] In this embodiment, the cut-off frequency calculation formula is:

[0063] loss×lg(F / F 0 )=D (1);

[0064] In formula (1), loss is the fixed loss corresponding to the topological structure of the filter circuit, F is the interference frequency, F 0 is the cut-off frequency, and D is the insertion loss that the filter circuit needs to compensate.

[0065] In the above formula, F is the noise frequency that needs to be compensated, that is, the frequency corresponding to the maximum difference mentioned above. Different topological structures have different fixed losses. For example, the π-type filter topology circuit has an insertion loss of 60 dB, and the LC-type filter topology circuit has an insertion loss of 40 dB.

[0066] Step S150: Obtain at least one capacitor corresponding to the topological structure.

[0067] In this embodiment, the number and capacitance value of the capacitors corresponding to different topological structures are different. By presetting a capacitor correspondence table, after determining the topological structure of the filter circuit, the number and capacitance value of the capacitors corresponding to this topological structure can be determined according to this table. Among them, the capacitor correspondence table specifically includes various preset topological structures, the number of preset capacitors corresponding to each topological structure, and the capacitance value corresponding to each preset capacitor.

[0068] It should be noted that when setting the capacitance correspondence table, the number and value of capacitors need to be set according to the actual application situation. Generally, the value of the capacitor can be determined according to the specifications of the inverter for the capacitor.

[0069] In this embodiment, the common-mode capacitor in the filter circuit of the common-mode filtering topology structure is generally selected as 86 nF, and the differential-mode capacitor in the filter circuit of the differential-mode filtering topology structure is generally selected as 3.3 μF.

[0070] Step S160: Determine the inductor corresponding to the filter circuit according to at least one of the capacitors and the filter transfer function corresponding to the topology structure.

[0071] In this embodiment, the filter transfer functions corresponding to different topology structures are different. After determining the topology structure of the filter circuit and the parameters related to the capacitor, the filter transfer function corresponding to the actual circuit structure can be deduced according to the circuit principle of the actual circuit.

[0072] Please refer to Figure 2 , such as Figure 2 shown in the schematic diagram of the filter circuit structure of a common-mode filtering topology structure. The source impedance of this filter circuit is selected as a low impedance, and the load impedance is selected as a high impedance. According to the circuit principle of the filter circuit of this common-mode filtering topology structure, the total impedance of this filter circuit is:

[0073]

[0074] In Equation (2), Z 1 is the total impedance corresponding to the filter circuit of the common-mode filtering topology structure, ω is the angular frequency, L cm is the common-mode inductor, C cm can be either the first common-mode capacitor or the second common-mode capacitor, and the values of the first common-mode capacitor and the second common-mode capacitor are equal, and R 1 is the load resistor of the filter circuit of the common-mode filtering topology structure.

[0075] Then the ratio of the output voltage U O1 and the input voltage U I1 of this filter circuit is:

[0076]

[0077] In the high-frequency band, the low-order terms of the angular frequency can be ignored. Therefore, the above Equation (3) can be transformed into:

[0078]

[0079] Also, since the cut-off frequency of this filter circuit is similar to its resonant frequency, when there is no attenuation of the input voltage and the output voltage, it is the resonant point, that is:

[0080]

[0081] Also, since ω = 2πf 1 , f 1 is the cut-off frequency of the filter circuit of the common-mode filter topology (i.e., F 0 ), combining the above formula (5), we can obtain:

[0082]

[0083] It should be noted that R 1 is the load resistance of the filter circuit of the common-mode filter topology, generally 50 ohms. Therefore, after the values of each common-mode capacitor and the cut-off frequency are determined, the value of the common-mode inductor can be calculated according to the above calculation.

[0084] Please refer to Figure 3 , as Figure 3 shown in the schematic diagram of the filter circuit structure of a differential-mode filter topology. The source impedance of this filter circuit is selected as a high impedance, and the load impedance is a high impedance. According to the circuit principle of the filter circuit of this differential-mode filter topology, the total impedance of this filter circuit is:

[0085]

[0086] In the above formula (7), Z 2 is the total impedance corresponding to the filter circuit of the differential-mode filter topology, ω is the angular frequency, L dm is the differential-mode inductor, C dm1 is the first differential-mode capacitor, C dm2 is the second differential-mode capacitor, and R 2 is the load resistance of the filter circuit of the differential-mode filter topology.

[0087] Then the ratio of the output voltage U O2 and the input voltage U I2 is:

[0088]

[0089] In the high-frequency band, the low-order terms of the angular frequency can be ignored. Therefore, the above formula (8) can be transformed into:

[0090]

[0091] Also, since the cut-off frequency of this filter circuit is similar to its resonant frequency, so when there is no attenuation of the input voltage and the output voltage, it is its resonant point, that is:

[0092]

[0093] Also, since ω = 2πf2 ,f 2 is the cut-off frequency (i.e., F) of the filter circuit with a differential-mode filter topology. Combining the above formula (10), we can obtain:

[0094]

[0095] It should be noted that R 2 is the load resistance of the filter circuit with a differential-mode filter topology, generally 50 ohms. Therefore, after the values of the first differential-mode capacitor, the second differential-mode capacitor, and the cut-off frequency are determined, the value of the common-mode inductor can be calculated according to the above method.

[0096] Therefore, combining the above examples, the filter transfer function corresponding to the topology of each filter circuit can be obtained according to the circuit principle of the filter circuit, and then the inductor value can be calculated according to the filter transfer function corresponding to the determined filter topology.

[0097] Figure 2 and Figure 3 represent the topologies of two different filter circuits. Due to their different structures, the filter transfer functions obtained according to the circuit principle are also different. Also, since the values of the capacitors in both filter circuits are relatively small, the difference in the inductors corresponding to the two different filter circuit topologies is relatively large. In the design and manufacture of inductors, the difference in order of magnitude is almost equivalent to the huge difference in volume. Therefore, the present application can determine the topology of the filter circuit according to the actual source impedance and load impedance of the inverter, and determine the other parameters of the filter circuit with the smallest space. In equipment with requirements for space and volume, the present application has high practicability.

[0098] It should be noted that the above examples of the common-mode filter topology and the differential-mode filter topology do not impose any limitations on the present application. Those skilled in the art should understand that in actual applications, other forms of filter circuit topologies can be designed according to the inverter, and then the values of other parameters in this structure can be obtained according to this topology.

[0099] In this embodiment, after obtaining the designed filter circuit according to each inductor value, each capacitor value, and the topology of the filter circuit, the designed filter circuit is added to the inverter, and the electromagnetic interference conducted emission spectrum of the inverter is measured again, and compared with the standard electromagnetic interference conducted emission spectrum to verify the effect of the filter circuit in suppressing electromagnetic interference.

[0100] Example 2

[0101] This embodiment provides a filter circuit design device, which includes a first acquisition module, a first determination module, a second determination module, a calculation module, a second acquisition module, and a third determination module.

[0102] In this embodiment, a first acquisition module is configured to acquire the source impedance and the load impedance of an inverter; a first determination module is configured to determine the topology of a filter circuit according to the source impedance and the load impedance; a second determination module is configured to determine the insertion loss to be compensated by the filter circuit; a calculation module is configured to calculate the cut-off frequency of the filter circuit by using a cut-off frequency calculation formula; a second acquisition module is configured to acquire at least one capacitor corresponding to the topology; and a third determination module is configured to determine the inductor corresponding to the filter circuit according to the at least one capacitor and the filter transfer function corresponding to the topology.

[0103] Among them, the implementation process of the first acquisition module can refer to the implementation process of step S110 in the first embodiment above, the implementation process of the first determination module can refer to the implementation process of step S120 in the first embodiment above, the implementation process of the second determination module can refer to the implementation process of step S130 in the first embodiment above, the implementation process of the calculation module can refer to the implementation process of step S140 in the first embodiment above, the implementation process of the second acquisition module can refer to the implementation process of step S150 in the first embodiment above, and the implementation process of the third determination module can refer to the implementation process of step S160 in the first embodiment above. For this, this embodiment will not be elaborated.

[0104] Example 3

[0105] This embodiment further provides a computer-readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (such as an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disc, a server, an App application store, etc., on which a computer program is stored. When the computer program is executed by a processor, all or part of the steps of the filter circuit design method in the first embodiment can be implemented. The specific implementation process of the above-mentioned all or part of the steps of the filter circuit design method can refer to the first embodiment, and this embodiment will not be repeated here.

[0106] Example 4

[0107] This application embodiment provides an electronic device, which can be a mobile phone, a computer, a tablet computer, etc., including a memory and a processor. A calculator program is stored on the memory, and when the computer program is executed by the processor, the filter circuit design method described in the first embodiment is implemented.

[0108] Among them, the processor is used to execute all or part of the steps in the filtering circuit design method in the first embodiment. The memory is used to store various types of data, which may include, for example, instructions of any application or method in the electronic device, as well as application-related data.

[0109] The processor may be implemented by an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor or other electronic components, and is used to execute the filtering circuit design method in the first embodiment above.

[0110] The memory may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk or an optical disk.

[0111] In summary, a filter circuit design method, apparatus, storage medium, and electronic device provided by the present application, the method includes: obtaining the source impedance and load impedance of an inverter; determining the topological structure of the filter circuit according to the source impedance and the load impedance; determining the insertion loss to be compensated by the filter circuit; calculating the cut-off frequency of the filter circuit by using the cut-off frequency calculation formula; obtaining at least one capacitor corresponding to the topological structure; and determining the inductor corresponding to the filter circuit according to at least one of the capacitors and the filter transfer function corresponding to the topological structure. The topological structure and its related parameters of the filter circuit that conforms to the inverter structure are flexibly selected to suppress the electromagnetic interference generated by the inverter or surrounding devices with the most reasonable filter circuit.

[0112] In several embodiments provided by the embodiments of the present application, it should be understood that the disclosed systems and methods can also be implemented in other ways. The above-described system and method embodiments are merely illustrative.

[0113] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0114] Although the disclosed embodiments of the present application are as above, the content described above is only an embodiment adopted for the convenience of understanding the present application and is not used to limit the present application. Any person skilled in the art within the technical field to which the present application pertains may make any modifications and changes in the form of implementation and details without departing from the spirit and scope disclosed by the present application. However, the scope of patent protection of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A method for designing a filtering circuit, characterized in that, the method includes: Obtaining the source impedance and load impedance of the inverter; Determining the topological structure of the filtering circuit according to the source impedance and the load impedance; Determining the insertion loss that the filtering circuit needs to compensate; Calculating the cut-off frequency of the filtering circuit by using the cut-off frequency calculation formula; Obtaining at least one capacitor corresponding to the topological structure; Determining the inductor corresponding to the filtering circuit according to at least one of the capacitors and the filter transfer function corresponding to the topological structure.

2. The method according to claim 1, characterized in that, Determining the topological structure of the filtering circuit according to the source impedance and the load impedance includes: Obtaining a topological structure correspondence table, wherein the topological structure correspondence table includes the correspondence relationships of various source impedances, various load impedances and various topological structures; Searching in the topological structure correspondence table for the topological structure corresponding to the source impedance and the load impedance of the inverter.

3. The method according to claim 1, characterized in that, Determining the insertion loss that the filtering circuit needs to compensate includes: Obtaining a preset curve and the conducted emission interference curve of the inverter, wherein the preset curve is a relationship curve between a frequency band and a standard noise corresponding to the frequency band; Taking the maximum difference between the preset curve and the conducted emission interference curve as the insertion loss that the filtering circuit needs to compensate.

4. The method according to claim 1, characterized in that, The cut-off frequency calculation formula is: loss×lg(F / F 0 ) = D; where loss is the fixed loss corresponding to the topological structure of the filtering circuit, F is the interference frequency, F 0 is the cut-off frequency, and D is the insertion loss that the filtering circuit needs to compensate for.

5. The method according to claim 1, characterized in that, Obtaining at least one capacitor corresponding to the topological structure includes: Searching in the capacitor correspondence table for at least one capacitor corresponding to the topological structure, wherein the capacitor correspondence table includes various preset topological structures, the number of preset capacitors corresponding to each topological structure, and the capacitance values corresponding to each preset capacitor.

6. The method according to claim 1, characterized in that, When the topological structure includes a common-mode filtering topological structure, obtaining at least one capacitor corresponding to the topological structure includes a first common-mode capacitor and a second common-mode capacitor, the inductor is a common-mode inductor, and the filter transfer function is: Among them, F 0 is the cut-off frequency, L cm is the common-mode inductor, and C cm is the first common-mode capacitor or the second common-mode capacitor.

7. The method according to claim 1, characterized in that, When the topological structure includes a differential-mode filtering topological structure, obtaining at least one capacitor corresponding to the topological structure includes a first differential-mode capacitor and a second differential-mode capacitor, the inductor is a differential-mode inductor, and the filter transfer function is: Among them, F 0 is the cut-off frequency, L dm is the differential-mode inductor, C dm1 is the first differential-mode capacitor, C dm2 is the second differential-mode capacitor, R 2 is the load resistor.

8. A filtering circuit design device, characterized in that, the device includes: A first obtaining module, configured to obtain the source impedance and load impedance of the inverter; A first determining module, configured to determine the topological structure of the filtering circuit according to the source impedance and the load impedance; A second determining module, configured to determine the insertion loss that the filtering circuit needs to compensate; A calculation module, configured to calculate the cut-off frequency of the filtering circuit by using the cut-off frequency calculation formula; A second obtaining module, configured to obtain at least one capacitor corresponding to the topological structure; A third determination module, configured to determine an inductor corresponding to the filter circuit according to at least one of the capacitors and a filter transfer function corresponding to the topology.

9. A storage medium, characterized in that the storage medium stores a computer program, and when the computer program is executed by one or more processors, the filter circuit design method according to any one of claims 1-7 is implemented.

10. An electronic device, characterized in that it includes a memory and a processor, a computer program is stored on the memory, and when the computer program is executed by the processor, the filter circuit design method according to any one of claims 1-7 is implemented.

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