A method and system for inter-process communication

Abstract

A method and system for inter-process communication, the system includes: a processor core, IPC engine hardware and a memory, the processor core is used to configure part of the memory space of the memory as a shared memory space when the IPC engine hardware is initialized to store the data to be transferred required for the inter-process communication, and to establish a page table; run the client process, send a call instruction to the IPC engine hardware, the call instruction includes the identifier of the server process and the virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space; the IPC engine hardware is used to instruct the processor core to run the server process; the processor core runs the server process, and the server process queries the page table according to the virtual address of the data to be transferred to obtain the data to be transferred to perform the service; and send a return instruction to the IPC engine hardware; the IPC engine hardware is used to instruct the processor core to resume running the client process. In this way, the IPC delay can be reduced, the data transmission efficiency can be improved, and the performance can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, related equipment and system for inter-process communication. Background Art

[0002] Software systems, such as Linux, allocate and manage resources in units of processes. In user space, a process cannot directly access the resources of another process. However, in practical applications, multiple processes are usually needed to complete a task together, which requires a communication mechanism between processes, namely inter-process communication (IPC). IPC is a technology for transmitting data or signals between at least two processes. A process is a unit for allocating resources to a computing device, and a process can run on the same computing device or on different computing devices connected to the network. Each process corresponds to a part of independent system resources and is isolated from each other. The IPC mechanism allows different processes to access resources from each other and coordinate work.

[0003] Traditionally, IPC mechanisms based on Linux include pipe communication, signal communication, message queue, socket, etc. Android provides a further optimized IPC mechanism based on the Linux kernel: IPCbinder. Binder is a communication mechanism based on the client-server (CS) model. All clients obtain the services of the server through the centralized binder driver.

[0004] The performance of IPC is a key factor affecting the overall performance of computing devices. For example, for Android, user space processes need to frequently interact with a large number of user space services. The latency performance of IPC also directly affects the user experience.

[0005] See for example Figure 1The core of the existing Binder mechanism is to run the Binder driver at the kernel layer. Since the kernel space in the system can share resources, the Binder driver has a strong cross-process access capability. The Binder driver assumes the role of a medium for IPC communication between the client process (caller) and the server process (callee). The user-state caller process requests the kernel service through the system call function "call()". The caller process falls into the kernel state to complete the context switch, that is, it is necessary to switch from the user state to the kernel state. Next, the IPC message data is copied from the client's user space to the kernel space. The server, as the data receiving end, shares data with the kernel, so there is no need to copy the data again. Therefore, the entire IPC process only needs one memory copy to pass the message data to the callee. Then, the kernel switches to the context of the user-state callee to complete the service response, and finally returns by calling the function "reply()". The kernel then restores the state of the caller process.

[0006] In the above-mentioned Binder mechanism, on the one hand, the kernel needs to allocate execution time to complete the switching between the kernel state and the user state of the process and the saving / restoring process of the process context, so that the CPU cycle occupied by the IPC process can be as long as 00 cycles, and the latency overhead is large. On the other hand, a copy process is inevitably required in the message data transmission, which affects the data transmission efficiency. When some existing solutions try to overcome the above defects, they often need to change the address access process of the memory management unit (MMU) in the existing standards, which is difficult to promote and apply in products that follow the existing standards. Summary of the invention

[0007] The present application provides a method, related equipment and system for inter-process communication, which can reduce IPC latency, improve data transmission efficiency and enhance performance.

[0008] In the first aspect, the present application provides a hardware system for inter-process communication (IPC), the system comprising: a processor core, IPC engine hardware and a memory, wherein: the processor core is used to, when the IPC engine hardware is initialized, configure a portion of the memory space in the memory as a shared memory space of the process, the shared memory space being used to store the data to be transferred required for inter-process communication; a page table is established according to the starting address and length of the shared memory space, the page table containing a mapping relationship from a virtual address to a physical address of the shared memory space; the processor core is also used to run a client process (e.g., a caller), and when the client process needs to call a service of a server process (e.g., callee), send a first processor instruction (e.g., the ipccall described in the specification) to the IPC engine hardware, the first processor instruction being the client The process calls the service, the calling instruction including the identifier of the server process and the virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space; the IPC engine hardware is used to instruct the processor core to run the server process according to the identifier, and send the virtual address of the data to be transferred to the server process; the processor core is also used to run the server process, the server process queries the page table according to the virtual address of the data to be transferred to obtain the data to be transferred to execute the service; and send a second processor instruction (such as ipcret described in the specification) to the IPC engine hardware, the second processor instruction is the return instruction of the server process; the IPC engine hardware is also used to instruct the processor core to resume running the client process according to the second processor instruction.

[0009] The attributes of the client process and the server process may be processes or threads.

[0010] It can be seen that the present application embodiment can transfer the context information preservation, context switching and recovery, data transmission, etc. in the user state to a new physical entity (i.e., IPC engine) in time and space. As the medium of IPC, the IPC engine provides corresponding user state instructions ipccall and ipcret, so that caller and callee can complete context switching in user state without switching to kernel state, thereby satisfying the service call of caller and the callback of callee, realizing the interaction of process in user state level, and the IPC engine can work in parallel with kernel software, greatly reducing the overall delay of IPC process. In addition, in the present application embodiment, the data access right can be transmitted by the IPC engine, and only the virtual address of the data needs to be transmitted to the callee, without the need to transmit the data itself, thereby avoiding the copy of the data (copy), further reducing the delay of the data copy, and improving the data transmission efficiency.

[0011] In addition, when the system is initialized (IPC engine is initialized), the operating system running on the processor core reserves (or configures) a portion of memory in the physical memory as the shared memory of the caller and callee. That is to say, in the embodiment of the present application, the shared memory is fixedly reserved and allocated when the IPC engine is initialized, and this portion of the shared memory is not in the page management page table of the kernel (such as the kernel). This portion of the shared memory can be directly accessed by the IPC engine. The shared memory can be used to save data that needs to be transferred between processes during the IPC communication process. By reserving the shared memory, a dedicated page table (the page table contains the mapping relationship between the virtual address and the physical address) can be established to ensure that the data to be transferred always has a corresponding physical page, thereby avoiding page faults and improving system performance.

[0012] After the shared memory is allocated, when the callee is registered with the IPC engine, the callee can establish a page table for the current process and add it to the MMU based on the starting address and length (size) of the shared memory. The page table globally defines the mapping relationship between the virtual address (VA) and the physical address (PA) of the shared memory segment. By implementing the solution of the embodiment of the present application, it is also possible to achieve that after the IPC engine is initialized, the operating system allocates shared memory, and the callee initiates registration to establish a page table for the current process, which is managed by the MMU. Thus, the purpose of caller and callee sharing memory is achieved, and changes to the existing MMU workflow are avoided, page fault errors are avoided, and the stability and security of IPC communication are guaranteed.

[0013] Based on the first aspect, in a possible embodiment, the processor core is further used to configure a portion of the memory space in the shared memory space to the client process to store the data to be transferred when the client process needs to call the service of the server process.

[0014] In implementing the embodiment of the present application, when the caller needs to call the callee service, the operating system allocates memory to the caller based on the shared memory, that is, allocates a portion of the memory space in the shared memory to the caller to store the data to be transferred (msg), that is, the operating system allocates a memory segment in the shared memory to the caller to store the data (msg) to be transferred, and the mapping relationship between the virtual address and the physical address of the msg in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU. Therefore, in the subsequent IPC communication, after the msg VA is transferred from the caller to the callee through the IPC engine, the callee can access the page table according to the VA to obtain the data, thereby achieving the purpose of sharing memory between the caller and the callee, avoiding changes to the existing MMU workflow, avoiding the occurrence of page faults, and ensuring the stability and security of the IPC communication.

[0015] Based on the first aspect, in a possible embodiment, before running the client process, the processor core is also used to send registration information of the server process to the IPC engine hardware, and the registration information includes the identifier; the IPC engine hardware is also used to: receive the registration information; save the identifier and the entry address of the server process in the IPC engine hardware in response to the registration information; the IPC engine hardware is specifically used to: find the entry address according to the identifier; set the entry address to the program counter (PC) in the processor core; the processor core is also used to run the server process according to the entry address set in the PC.

[0016] Wherein, the IPC engine hardware may include a callee register set, and the callee register set includes a set of registers for recording indication information of the context information of the callee. The callee register set is specifically used to record the entry addresses (callee entry address) of multiple callees, and each callee entry address corresponds to the context information of a callee. In one embodiment, the callee entry address includes an address pointer of a service function of a callee, and the service function can be a callback function (Callback function). The IPC engine can set the program counter (ProgramCounter, PC) in the CPU to the callee entry address, so that the CPU starts to execute the callee process context and runs the callee to execute the corresponding service.

[0017] Furthermore, the callee register set further includes a first address register and a count register, wherein the first address register is used to store the first address of the callee list, specifically, it can be the first callee entry address in the callee list. The count register is used to record the number of callee entry addresses (entry list size), specifically, each time a list entry (i.e., a callee entry address) is added to the callee list, the number recorded in the count register is increased by 1. In this way, the callee register set can record the entry addresses (callee entry addresses) of multiple callees to the callee list according to the registration status of multiple callees. In a specific implementation, each list entry of the callee list can be configured to correspond to an index identifier (ID). The index ID can be the process ID of the callee (i.e., the callee ID), or the index ID can be mapped one-to-one with the process ID, and the index ID can be determined after the callee is registered with the IPC engine. In this way, it is convenient for the client process (caller) to perform IPC with one or more callees.

[0018] It can be seen that the IPC engine of the embodiment of the present application can realize context information preservation, context switching, or data transfer in user mode, and the kernel is not aware of these processes (that is, the IPC process does not require the participation of the kernel), avoiding the disadvantages of frequent switching between user mode and kernel mode in existing IPC mechanisms (such as the binder mechanism), and separating the IPC process of the process from the kernel, thereby releasing a large amount of CPU software execution time, thereby greatly reducing the overall latency of the IPC process.

[0019] Based on the first aspect, in a possible embodiment, the IPC engine hardware is also used to, after receiving the call instruction, query the status register in the processor core to obtain the call stack address of the client process, and save the call stack address of the client process in the IPC engine hardware; the IPC engine hardware is specifically used to call out the call stack address according to the second processor instruction, and instruct the processor core to resume running the client process according to the call stack address.

[0020] Specifically, the IPC engine hardware may include a link register, and the link register is used to save the entry address of the current caller, and the entry address of the caller corresponds to the context information of the caller. Specifically, the link register can save the call stack address of the current caller to record the call behavior of the current triggerer, and the call stack address is associated with the context information of the caller. After the caller initiates the call instruction (ipccall), the IPC logic circuit of the IPC engine queries the status register in the CPU, and by querying the latest caller state saved in the status register, it is possible to know which caller initiates the call, so that the call stack address of the caller can be saved to the link register. After the callee completes the execution of the service, the link register can pop up the record of the current caller, realize process switching (i.e., CPU switches from the context of the callee to the context of the caller), to restore the process of the caller. The callee register set and the link register provided by the embodiment of the present application can realize the context switching process of the process in hardware, thereby releasing the software execution time of the CPU and reducing the delay of the IPC process.

[0021] Based on the first aspect, in a possible embodiment, the IPC engine hardware is specifically used to check whether the client process and the server meet the requirements of inter-process communication, and when the client process and the server meet the requirements of inter-process communication, instruct the processor core to run the server process according to the identifier. Execution of this embodiment makes the IPC engine hardware provided by this application more secure and reliable.

[0022] For example, the IPC engine may perform at least one of the following condition checks through the IPC logic circuit:

[0023] 1) Check if caller and callee are in different execution levels.

[0024] 2) Check whether the caller and callee are in the same processor core. The IPC logic circuit can decide whether to migrate the process context information based on whether the processes are in the same core.

[0025] 3) Check the caller's security permissions to determine whether the caller has the authority to call the callee's service.

[0026] 4) Check whether the relevant parameters carried by the call instruction meet the length requirements.

[0027] Based on the first aspect, in a possible embodiment, the call instruction and the return instruction are both user-mode instructions. This satisfies the service call of the caller and the callback of the callee, realizes the interaction of processes at the user-mode level, avoids the drawback of frequent switching between user mode and kernel mode in the existing IPC mechanism (such as the binder mechanism), and realizes that the software does not switch to the kernel mode, and the IPC engine and CPU work in parallel on the hardware.

[0028] Based on the first aspect, in a possible embodiment, when the caller needs to initiate an ipccall to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates a portion of the memory space in the shared memory to the caller to store the data to be transmitted (msg), and indicates the virtual address (VA) of the data to the caller, and sets the access rights to be read and write by the caller, and non-readable and non-writable by other processes / threads. When the ipccall instruction is executed, after the permission check passes, the IPC engine sets the portion of the shared memory to be readable by the callee according to the information of the callee entry, and non-readable and non-writable by other processes / threads.

[0029] In the second aspect, an embodiment of the present application provides a method for inter-process communication (IPC), and the method of this embodiment is a method executed in the system described in the first aspect above. The method includes: when the IPC engine hardware is initialized, the processor core configures a part of the memory space in the memory as the shared memory space of the process, and the shared memory space is used to store the data to be transferred required for inter-process communication; a page table is established according to the starting address and length of the shared memory space, and the page table contains the mapping relationship from the virtual address of the shared memory space to the physical address; the processor core runs the client process, and when the client process needs to call the service of the server process, the processor core sends a first processor instruction to the IPC engine hardware, and the first processor instruction is a call instruction of the client process to the service, and the call instruction includes the identifier of the server process and the virtual address of the data to be transferred. The virtual address of the data to be transferred is located in the shared memory space; the IPC engine hardware instructs the processor core to run the server process according to the identifier, and sends the virtual address of the data to be transferred to the server process; the processor core runs the server process, and obtains the data to be transferred by querying the page table according to the virtual address of the data to be transferred by the server process to execute the service; the processor core sends a second processor instruction to the IPC engine hardware, and the second processor instruction is a return instruction of the server process; the IPC engine hardware instructs the processor core to resume running the client process according to the second processor instruction.

[0030] Based on the second aspect, in a possible embodiment, when the client process needs to call a service of the server process, the processor core configures a portion of the memory space in the shared memory space to the client process to store the data to be transferred.

[0031] Based on the second aspect, in a possible embodiment, before the processor core runs the client process, the method also includes: the processor core sends registration information of the server process to the IPC engine hardware, the registration information including the identifier; the IPC engine hardware receives the registration information; in response to the registration information, saves the identifier and the entry address of the server process in the IPC engine hardware; accordingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier, including: the IPC engine finds the entry address according to the identifier; sets the entry address to the program counter (PC) in the processor core; the processor core runs the server process according to the entry address set in the PC.

[0032] Based on the second aspect, in a possible embodiment, after the processor core sends a first processor instruction to the IPC engine hardware, the method further includes: the IPC engine hardware queries a status register in the processor core to obtain a call stack address of the client process, and saves the call stack address of the client process in the IPC engine hardware; accordingly, the IPC engine hardware instructs the processor core to resume running the client process according to the second processor instruction, including: the IPC engine hardware calls out the call stack address according to the second processor instruction, and instructs the processor core to resume running the client process according to the call stack address.

[0033] Based on the second aspect, in a possible embodiment, before the IPC engine hardware instructs the processor core to run the server process according to the identifier, the method also includes: the IPC engine hardware checks whether the client process and the server meet the requirements of inter-process communication; accordingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier specifically includes: when the client process and the server meet the requirements of inter-process communication, the IPC engine hardware instructs the processor core to run the server process according to the identifier.

[0034] Based on the second aspect, in a possible embodiment, the calling instruction and the return instruction are both user mode instructions.

[0035] In a third aspect, the present application provides a method for inter-process communication (IPC), which is applied to an IPC engine in a physical entity form (i.e., IPC engine hardware); when the IPC engine hardware is initialized, the processor core configures a portion of the memory space in the memory as a shared memory space of the process, and the shared memory space is used to store data to be transferred required for inter-process communication; a page table is established according to the starting address and length of the shared memory space, and the page table contains a mapping relationship from a virtual address of the shared memory space to a physical address;

[0036] The method comprises: the IPC engine receives a call instruction from a client process; the call instruction is used to request a service of a server process, and the call instruction comprises an identifier of the server process and a virtual address of data to be transferred; the IPC engine activates the server process according to the identifier of the server process, so that the server process queries the page table according to the virtual address of the data to be transferred to obtain the data to be transferred to perform the service; the physical address of the data to be transferred is located in the shared memory space; the IPC engine receives a return instruction from the server process, and the return instruction comprises an execution result; wherein the call instruction and the return instruction are both processor instructions in user mode; the IPC engine restores the client process according to the return instruction.

[0037] Based on the third aspect, in a possible embodiment, when the client process needs to call a service of the server process, the processor core configures a portion of the memory space in the shared memory space to the client process to store the data to be transferred.

[0038] Based on the third aspect, in a possible embodiment, the length of the data to be transmitted is greater than a preset threshold.

[0039] Based on the third aspect, in a possible embodiment, before the IPC engine receives a call instruction from the client process, the method also includes: the IPC engine accepts the registration of the server process; the IPC engine records the identifier of the server process and the entry address of the server process according to the registration of the server process.

[0040] The IPC engine activates the server process according to the identifier of the server process, including: the IPC engine finds the entry address of the server process according to the identifier of the server process; the IPC engine runs the server process according to the entry address of the server process.

[0041] Based on the third aspect, in a possible embodiment, after the IPC engine receives the call instruction from the client process, it also includes: the IPC engine records the entry address of the client process; accordingly, the IPC engine restores the client process according to the return instruction, including: the IPC engine switches the operation of the server process to the operation of the client process according to the entry address of the client process.

[0042] Based on the third aspect, in a possible embodiment, before the IPC engine runs the server process according to the identifier of the server process, it also includes: the IPC engine checks whether the client process and the server meet the requirements of inter-process communication; accordingly, the IPC engine activates the server process according to the identifier of the server process, including: when the client process and the server meet the requirements of inter-process communication, the IPC engine activates the server process according to the identifier of the server process.

[0043] In the fourth aspect, the embodiment of the present application also provides IPC engine hardware for executing the method described in the third aspect, or realizing the function of the IPC engine hardware in the method described in the second aspect, the IPC engine hardware includes an IPC logic circuit (or IPC logic), a callee register set, a link register (or link reg), and a message register set. The IPC engine can be deployed in a CPU core or independently. The IPC engine hardware can be a coprocessor or an independent processing chip. In some embodiments, the IPC engine hardware can be integrated in a processor, and the IPC engine hardware runs in parallel with the CPU core. In some other embodiments, the IPC engine hardware can be independent of the processor and communicate through a communication line / interface.

[0044] In a fifth aspect, the present application provides a computer storage medium, wherein the computer storage medium is used to store a computer program, and when the computer program is executed by one or more processors, the method provided in any one of the second aspect or the third aspect is implemented.

[0045] In a sixth aspect, the present application provides a computer program product, which is used to store a computer program, and when the computer program is executed by one or more processors, implements the method provided in any one of the second aspect or the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a scenario diagram of the existing Binder mechanism;

[0047] Figure 2This is a schematic diagram of a possible application scenario for communication between a client process and a server process based on a CS mode provided in an embodiment of the present application;

[0048] Figure 3 This is a schematic diagram of another possible application scenario of communication between a client process and a server process based on the CS mode provided in an embodiment of the present application;

[0049] Figure 4A is a possible system structure block diagram of a computing device in an embodiment of the present application;

[0050] Figure 4B is an example diagram of a physical hardware system provided in an embodiment of the present application;

[0051] Figure 4C is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0052] Figure 5A It is a possible hardware architecture of an IPC engine provided in an embodiment of the present application;

[0053] Figure 5B These are some example diagrams of application scenarios of the IPC engine provided in the embodiments of the present application;

[0054] Figure 5C This is another example diagram of an application scenario of the IPC engine provided in an embodiment of the present application;

[0055] Figure 6 This is a flowchart of a method for inter-process communication provided by an embodiment of the present application;

[0056] Figure 7 This is a flowchart of another method for inter-process communication provided by an embodiment of the present application;

[0057] Figure 8 It is a scenario diagram of a shared memory solution provided in an embodiment of the present application;

[0058] Fig. 9 This is a schematic diagram of an IPC communication scenario in which the solution of the present application is applied, provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, but are not intended to limit the present application. The singular forms of "a kind of", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include a plurality of forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items. The terms "include" and "have" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or equipment are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0060] It should be understood that in the present application, "at least one" means one or more, and "plurality" means two or more. The character " / " generally indicates that the objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0061] The present application provides a new IPC mechanism, through which the latency of the IPC process can be significantly reduced and the efficiency of data transmission can be improved. In order to better understand the solution of the present application, the client-server (CS) mode involved in the embodiment of the present application is first described below. In this article, the requester of the service (service) can be referred to as the client (client), the implementer of the service is referred to as the server (server), the client process can be referred to as the client process, the client process is the process that accesses the service, and it can also be referred to as the sending process (caller) in this article. The process of the server can be referred to as the server process. The server process is the process that provides the service, and it can also be referred to as the receiving process (callee) in this article.

[0062] See also Figure 2 and Figure 3 , Figure 2 and Figure 3 The following describes a possible application scenario of the client process and the server process communicating based on the CS mode provided by the embodiment of the present application. In some possible embodiments, the two processes (client process and server process) can be located in the same computing device, that is, IPC reflects the communication between two processes in the same computing device, where the computing device can be a terminal or a server. In one example, Figure 2 As shown, the two processes can run on the same processor core of the computing device, such as the CPU core. In another example, when the computing device has multiple CPU cores, the two processes can run on different CPU cores of the computing device (such as CPU core1 and CPU core2 shown in the figure). In some other possible embodiments, the two processes can also be located in different computing devices, that is, IPC embodies the inter-process communication between two different computing devices (computing device 1 and computing device 2), wherein computing device 1 and computing device 2 can both be terminals, can both be servers, or one device can be a terminal and the other device can be a server.

[0063] Taking the example of two processes located in the same computing device, the computing operating system type may be an Android system. In the description of the following related embodiments, the inter-process communication method of the present application is applied to the Android system as an example.

[0064] In the embodiment of the present application, the system architecture of the computing device can be designed using a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture, or a cloud architecture. The following takes the Android system with a layered architecture as an example to illustrate a system architecture of a computing device. Figure 4A , Figure 4A This is a possible system structure diagram of a computing device in an embodiment of the present application. The system architecture includes the underlying physical hardware and the software architecture running on the physical hardware. The physical hardware layer provides various computing resources (such as CPU), storage resources (such as memory, disk, etc.), communication resources (such as transceiver), etc. required by the computing device. The software architecture divides the software into several layers, each with clear roles and division of labor. The layers communicate with each other through software interfaces.

[0065] In one possible implementation, the software architecture of the Android system is divided from bottom to top into: kernel layer, hardware abstraction layer (HAL), system service layer, application framework layer and application layer. Among them: the kernel layer is used to provide drivers for the Linux kernel and various hardware devices. The hardware abstraction layer is used to encapsulate the kernel layer hardware drivers and provide a unified hardware interface that can be called by the system service layer. The system service layer is used to provide system services (services) and provide interfaces that can be called by the application framework layer. The application framework layer can be understood as the Android SDK, which is used to provide four major components, drawing and other basic components used in daily development. Developers can call the interface of the application framework layer. The application layer is used to provide user-oriented applications (APP).

[0066] It should be noted that the kernel layer used by the computing device in the embodiment of the present application can be a macro kernel (Monolithic kernel) or a micro kernel (Micro kernel). Among them, the macro kernel is such as the Linux kernel. In addition to providing the most basic process, thread management, and memory management, the macro kernel also provides file systems, drivers, network protocols, etc. For the microkernel (such as SEL4, QNX, Fuchsia, LK etc.) architecture, the most basic scheduling and memory management are provided in the kernel. The driver, file system, etc. are all implemented by the user-mode daemon process, which brings better scalability, security, and fault tolerance, and is applied to more and more products (such as mobile terminals, car machines, aircraft equipment, etc.).

[0067] In the embodiment of the present application, the processing logic of IPC is set to the physical hardware layer instead of the kernel layer, and a dedicated hardware-based IPC engine (IPC Engine) is designed. The IPC engine can also be referred to as IPC engine hardware in this article. The IPC engine, as the core of process interaction, can be processed in parallel with the kernel, and the kernel can initialize, configure, control, service process registration, abnormal interrupt processing, etc. for the IPC engine. The service call (function call), context switch, data exchange (data access right transfer) and the like involved in the IPC process are completed by the IPC engine in hardware, and data or data address transfer is performed inside the IPC engine, thereby avoiding the context switch and data copy of the kernel state and user process stack in software mode, thereby releasing a large amount of CPU software execution time and reducing the overall delay.

[0068] The IPC engine can run in parallel with the software execution cycle of the CPU. In one implementation of the IPC engine, the hardware-specific logic of the IPC Engine can be added to the chip where the CPU Core is located as a coprocessor, that is, the CPU Core and IPCEngine are integrated into the same chip; in another implementation of the IPC engine, the IPC engine can be a processing chip independent of the CPU Core.

[0069] In addition, in order to realize the interaction between the IPC engine and the process, the process is provided with a processor instruction to use the IPC engine, such as the "ipccall instruction" and the "ipcret instruction". The client process (caller) in the user space can call the service of the server process (callee) through the ipccall instruction, and the server process can return through the ipcret instruction to restore the client process. The premise for the execution of the above two instructions is that the IPC engine completes the initialization (for example, including the initialization configuration of the IPC engine, memory allocation, etc.), and the initialization process can be completed by the kernel state driver.

[0070] Through the design of this application, the application framework layer in Android is open to developers in the form of SDK, and the core services in the system service layer run with the system startup, and the manager (Manager) provided by the application framework layer provides service calls for applications in real time. Each service in the system service layer runs in its own independent process space, and the application can call the service (service) in the system service layer through the IPC engine. Therefore, the process of context switching and data exchange can be realized by hardware, and the CPU realizes the soft and hard collaborative work through the IPC engine with the help of the IPC software communication mode, releasing the software execution time of the CPU. In this way, it is manifested at the level of user processes, and caller and callee realize the communication of direct IPC in user state, thereby avoiding the delay caused by the switch between kernel state and user state in the existing scheme, and the data interaction between processes can only pass the data address (data access right), thereby reducing or even eliminating the occurrence of data copy, greatly improving the data transmission efficiency, and further reducing the delay of the IPC process.

[0071] The embodiment of the present application also provides a physical hardware system, including: a central processing unit (CPU) and IPC engine hardware. The IPC engine hardware may be referred to as the IPC engine herein. In specific implementation, the IPC engine hardware may be a logic circuit or an independent logic computing chip. Wherein: the CPU includes a CPU core (CPU core). In some embodiments, the IPC engine may be integrated into the CPU, and the IPC engine and the CPU core may run in parallel. In some other embodiments, the IPC engine may be independent of the processor core.

[0072] See also Figure 4B , Figure 4BThis is an example diagram of a physical hardware system also provided in an embodiment of the present application, and the physical hardware system includes a CPU core 11, an IPC engine 12 and a DDR memory 13. Among them, some or all of the CPU core 11, the IPC engine 12 and the DDR memory 13 can be integrated together, or connected through a common communication interface, or connected through a bus. Among them: the CPU core 11 can be used to run a process (client process caller or server process callee), the IPC engine 12 can be used to implement communication between processes, and the DDR memory 13 can be used to provide the data and context information necessary for the process to run. Specifically: the CPU core can register the server process with the IPC engine in advance, and the IPC engine saves the identifier of the server process and the entry address of the server process according to the registration. The CPU core can be used to send a first processor instruction to the IPC engine when a client process needs to call a service of a server process. The first processor instruction includes a call instruction of the client process to the service (such as the ipccall described in any embodiment of the present application), and the call instruction includes an identifier of the server process and a virtual address of data to be transferred; the virtual address of the data to be transferred can be a virtual address corresponding to the location of the data to be transferred in the DDR memory.

[0073] The IPC engine can be used to save the entry address of the client process; and find the entry address of the server process according to the identification (ID) of the server process, and then instruct the CPU core to run the server process, thereby realizing the context switch of the process. In addition, the IPC engine can also establish a mapping between the address of the data to be transferred and the address of the server process in the memory space, and pass the mapping to the server process, realizing the transfer of data access rights (but not the data itself).

[0074] The CPU core is also used to run the server process to execute the service according to the data to be transmitted; the CPU core is also used to send a second processor instruction to the IPC engine, and the second processor instruction includes a return instruction of the server process (such as ipcret described in any embodiment of the present application). Among them, the first processor instruction and the second processor instruction are both user-mode processor instructions. The IPC engine is also used to find the entry address of the client process and instruct the processor core to run the client process, thereby realizing the recovery of the client process.

[0075] It can be seen that the implementation of the embodiment of the present application can realize the process of context preservation, context switching, data exchange and other processes on the IPC engine hardware. After the caller actually initiates the IPC, the IPC process can be implemented without the participation of the kernel, so that the software does not switch to the kernel state. The IPC engine and the CPU core work in parallel on the hardware. The CPU uses the IPC software communication method to realize the software and hardware collaboration through the IPC engine, thereby releasing the software execution time of the CPU core. In order to cooperate with the interaction between the hardware-shaped IPC engine and the process, user-state processor instructions (first processor instructions and second processor instructions) are also provided, thereby satisfying the caller's service call and the callee's callback, realizing the interaction of the process at the user state level, and ensuring the feasibility of the IPC process. In this way, at the user process level, the caller and the callee realize direct IPC communication in the user state, thereby avoiding the delay caused by the frequent switching between the user state and the kernel state in the existing IPC mechanism (such as the binder mechanism). Data interaction between processes can only transmit the mapping of data addresses (data access rights), thereby reducing or even eliminating the occurrence of data copying, greatly improving the data transmission efficiency, and further reducing the delay of the IPC process.

[0076] Further, see Figure 4C , Figure 4C The schematic diagram of the structure of a computing device 30 is exemplarily shown. The computing device 30 may be a terminal or a server. It should be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the computing device 30. Figure 4C As shown, computing device 30 may include: chip 310, memory 315, user interface 314. These components may communicate over one or more communication buses.

[0077] The chip 310 may be integrated to include: one or more processors 311, IPC engine hardware 312 and a power management module 313. The processor 311 may perform operations, generate operation control signals, complete the control of fetching and executing instructions, run processes (such as client process caller or server process collee), etc. The power management module 313 integrated in the chip 310 is mainly used to provide stable and high-precision voltage for the chip 310 and other components of the computing device 30. The IPC engine hardware 312 integrated in the chip 310 may be the IPC engine described in any embodiment of the present application, and implements the context saving, context switching, data exchange and other processes of the process in the IPC communication.

[0078] The IPC engine hardware 312 can be a coprocessor or an independent processing chip. In some embodiments, the IPC engine hardware 312 can be integrated in the processor 311, and the IPC engine hardware 312 runs in parallel with the CPU core. In some other embodiments, the IPC engine hardware 312 can be independent of the processor 311 and communicate through a communication line / interface. The specific functional implementation of the IPC engine hardware 312 can refer to the description of the IPC engine in any embodiment of the present application.

[0079] The processor 311 may specifically include one or more processing units with different capabilities, for example, the processor 311 may include the central processing unit (CPU), application processor (AP), modem processor, graphics processor (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural-network processing unit (NPU) described in the previous embodiments. Different processing units may be independent devices or integrated in one or more processors. Each processing unit may include one or more cores.

[0080] In some embodiments, the processor 311 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0081] The memory 315 may be connected to the processor 311 via a bus, or may be coupled to the processor 311, and is used to store various data, software programs, and / or multiple sets of instructions. In a specific implementation, the memory 315 may include a DDR memory for storing data and context information necessary for the process to run. The memory 315 may also include a high-speed random access memory (e.g., a cache memory), and the memory 315 may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

[0082] The user interface 314 may be used to connect peripheral devices in the computing device 30, such as various input / output devices (I / O devices, sensors, display screens, etc., which are not limited in the present embodiment of the present application).

[0083] The following describes a possible hardware architecture of the IPC engine in the embodiment of the present application. Figure 5A The hardware architecture may include an IPC logic circuit (or IPC logic), a callee register set (also called a second register set), a link register (or link reg), and a message register set (also called a first register set). The IPC engine can be deployed in the CPU core or independently.

[0084] As the control center of the IPC engine, the IPC logic circuit can respond to two user-mode processor instructions, ipccall and ipcret, which are instructions that a process can call in user mode; perform control processing of the IPC process, complete various condition checks for callee and caller, and so on.

[0085] The callee register set includes a set of registers for recording the indication information of the callee's context information. The registers may be, for example, 32-bit or 64-bit registers, and the present application does not limit the bit width of the registers. Specifically, the callee register set is specifically used to record the entry addresses (callee entry address) of multiple callees, and each callee entry address corresponds to the context information of a callee. Therefore, the callee entry address may also be referred to as the "indication information of the callee's context information".

[0086] In one embodiment, the callee entry address may represent a callee process in the global DDR (e.g. Figure 4BThe address of the context in the DDR memory 13 in the callee entry address. Exemplarily, the specific content of the callee entry address may be, but is not limited to, at least one of: a page table pointer, an address pointer, a virtual address, or a physical address.

[0087] In one embodiment, the callee entry address includes an address pointer of a callee's service function, which may be a callback function (Callback function), that is, the address pointer of the callee points to the address of the callback function (Callback function) registered by the callee, and the callback function is used by the callee to execute the corresponding service (service). The callback function is a kind of handler, which is a function called through a function pointer, and the call between functions is implemented through the callback function. If the pointer (address) of a function is passed as a parameter to another function, when this pointer is used to call the function it points to, this function is called a callback function. The IPC engine can set the program counter (PC) in the CPU to the callee entry address, so that the CPU starts to execute the callee process context and runs the callee to execute the corresponding service.

[0088] Each time a callee register set is used to record a callee entry address, when the callee register set records the callee entry addresses of multiple callees multiple times, these callee entry addresses can form a list, which is called a callee list. This list can be saved in memory for indexing. The callee register set can be regarded as the manager of the callee list, providing functions such as registration, editing (addition, deletion), maintenance, access, or query of the callee list.

[0089] like Figure 5AAs shown, in a possible implementation, the callee register set further includes a first address register and a count register. The first address register is used to store the first address of the callee list, specifically, the first callee entry address in the callee list. The count register is used to record the number of callee entry addresses (entry list size). Specifically, for each additional list entry (i.e., a callee entry address) in the callee list, the number recorded in the count register is increased by 1. In this way, the callee register set can record the entry addresses (callee entry addresses) of multiple callees to the callee list according to the registration status of multiple callees.

[0090] See also Figure 5B , Figure 5B (1) in FIG. 1 shows an example diagram of a scenario in which a callee is registered to a callee list with an IPC engine. In a specific implementation, each list entry in the callee list may be configured to correspond to an index identifier (ID). The index ID may be the process ID of the callee (i.e., the callee ID), or the index ID may be mapped one-to-one with the process ID, and the index ID may be determined after the callee is registered with the IPC engine. In this way, it is convenient for a client process (caller) to perform IPC with one or more callees.

[0091] The registration process of the callee to the IPC engine can be completed through a system call, for example, the user interface of the device driver CPU core corresponding to the kernel can be used to save relevant content (such as address pointer) to the first address register of the IPC engine according to the context information of the callee.

[0092] In this way, during the IPC process, the IPC engine can find the callee entryaddress based on the ID passed in by the caller. Figure 5BAs shown in (2), the call instruction (ipccall) initiated by the caller to the IPC engine carries the callee ID, so that the IPC logic circuit can search the callee list according to the callee ID, thereby indexing the callee's entry address. The IPC engine can also set the program counter (PC) in the CPU to the callee entry address to enable the callee to run and provide corresponding services. The program counter is a register that stores the address (location) of the instruction currently being executed. When each instruction is obtained, the storage address of the program counter is increased by one. After each instruction is obtained, the program counter points to the next instruction in the sequence. Therefore, the IPC engine can send the callee entry address to the PC for recording, so that the CPU executes the instruction to run the callee.

[0093] In the embodiment of the present application, when the IPC engine is deployed in the CPU core, the user interface of the CPU core can provide system calls such as adding and removing callee entry addresses, and registration and deregistration of callee services can also be implemented through this interface.

[0094] The link register is used to save the entry address of the current caller, and the entry address of the caller corresponds to the context information of the caller. Specifically, the link register can save the call stack address of the current caller to record the call behavior of the current triggerer, and the call stack address is associated with the context information of the caller. After the caller initiates the call instruction (ipccall), the IPC logic circuit of the IPC engine queries the status register in the CPU, and by querying the latest caller state saved in the status register, it is possible to know which caller initiates the call, so that the call stack address of the caller can be saved to the link register. After the callee completes the execution of the service, the link register can pop up the record of the current caller, realize process switching (i.e., CPU switches from the context of the callee to the context of the caller), to restore the process of the caller. The callee register set and the link register provided by the embodiment of the present application can realize the context switching process of the process in hardware, thereby releasing the software execution time of the CPU and reducing the delay of the IPC process.

[0095] The message register set includes a set of registers for recording the address of the data (msg) that the caller needs to pass to the callee. The register can be, for example, a 32-bit or 64-bit register, and the present application does not limit the bit width of the register. The message register set can be used to establish and save indication information (such as a pointer), which indicates the mapping relationship between the virtual address (VA) and the physical address (PA) of the data (msg) that needs to be transmitted during the IPC communication process, and the mapping relationship can be stored in the memory.

[0096] In a specific embodiment, the message register set is used to record the entry addresses (msg entryaddress) of multiple msgs. In a specific implementation, the message register set may record the address of the data passed in by the caller in the call instruction, or the data itself (for example, small data of only a few bytes). Each msg entry address indicates the address of the msg in the DDR memory (which may be referred to as the msg memory address), and the msg entry address may include at least one of the following: the base address of the virtual address (VA base), the base address of the physical address (PA base), and the length of the address space (length). It can be seen that the message register set can record the address of the data that needs to be transferred by one or more callees, thereby facilitating the caller to perform IPC with one or more callees. It should be understood that the subsequent embodiments are introduced using memory as an example, but are not used to limit it and can be extended to other types of memory.

[0097] A caller may pass in one or more msg addresses through a call instruction (ipccall). In one embodiment, the address of the msg passed in may be the virtual address (VA) of the msg. One or more msg entry addresses may be recorded each time through a message register set. After the message register set records the msg entryaddress multiple times, these msg entry addresses may form a list, which may be called a msg list (msglist). This list may be stored in memory for indexing. The message register set may be regarded as the manager of the msg list, providing external functions such as editing (addition, deletion), maintenance, access, or query of the msg list.

[0098] In some embodiments of the present application, in order to avoid the copy (copy) of the data to be transferred during the IPC process, in the IPC engine, the data itself may not be directly transferred, but the data transfer may be indirectly realized by transferring the mapping (memory mapping) of the data, without the need to copy the data. Specifically, a mapping mechanism of the msg address space may be added to the IPC engine, and a portion of the memory may be configured in advance in the DDR global memory as a shared memory, which may be shared and accessed by the caller and callee. In other words, the caller and callee share a section of memory space, which is referred to as the shared memory herein), and the physical address (PA) of the data msg to be transferred is the position of the msg in the section of memory space. The shared memory is used to store the data (msg) that needs to be transmitted during the service call process, so that the msg is only mapped between the caller and the callee.

[0099] For details, see Figure 8 In the embodiment of the present application, when the system is initialized (IPC engine is initialized), the operating system running on the processor core reserves (or configures) a part of the memory in the physical memory as the shared memory of the caller and callee. In order to improve the security of data access, the memory access rights can also be initialized. At the same time, the logic of accessing this part of the shared memory can be unified into the access logic of the existing memory management unit (memory management unit, MMU) to avoid changes to the existing MMU execution process and avoid page faults. That is to say, in the embodiment of the present application, the shared memory is fixedly reserved and allocated when the IPC engine is initialized, and this part of the shared memory is not in the page management page table of the kernel (such as kernel). This part of the shared memory can be directly accessed by the IPC engine. The shared memory can be used to save data that needs to be transferred between processes during the IPC communication process. By reserving the shared memory, a dedicated page table (the page table contains the mapping relationship between the virtual address and the physical address) can be established to ensure that the data to be transferred always has a corresponding physical page, thereby avoiding page faults.

[0100] After the shared memory is allocated, a mapping relationship between the virtual address (VA) and the physical address (PA) is formed globally in the shared memory. Each msg involved in the IPC communication is stored in the shared memory, thereby forming a large number of mapping relationships (such as mapping tables) between the virtual address (VA) and the physical address (PA) of the msg. The IPC engine can access such mapping tables. When the caller needs to call the callee service, the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to store the data to be transmitted (msg), and indicates the virtual address (VA) of the data to the caller, so that the caller can initiate the call instruction ipccall.

[0101] Later, when the caller sends a call instruction to the IPC engine, the IPC logic circuit of the IPC engine can maintain the msg list by searching the mapping table.

[0102] See also Figure 5C , Figure 5C The following diagram shows an example of a scenario in which the IPC engine maintains a msg list according to the call instruction (ipccall) of the caller. Figure 5CAs shown, in a possible implementation, the message register set further includes a msg register and a counting register. The msg register can also be exemplarily a first address register for storing the first address of the msg list, specifically, the first msg entry address in the msg list. The counting register is used to record the number of msg entry addresses. Specifically, for each additional list entry (i.e., a msg entry address) in the msg list, the number recorded in the counting register is increased by 1. In this way, one or more msg entry addresses can be recorded to the calleelist through the message register set. Among them, each list entry (i.e., a msg entry address) can be specifically represented as the physical address (PA) of the msg in the shared memory. In a specific implementation, the caller's ipccall can carry a msg VA (such as VA1 shown in the figure), and the IPC logic circuit of the IPC engine can search the mapping table corresponding to the shared memory based on the msg VA, thereby determining the PA corresponding to the msg VA (such as PA1 shown in the figure), and the PA is used as the msg entry address, and the msg entryaddress is recorded to the msg list through the message register set. It can be understood that when the caller passes in multiple msg VAs, multiple msg entry addresses can be recorded in the msg list through the message register set.

[0103] In the specific implementation, in order to facilitate data search, each list entry (PA) of the msg list can be configured to correspond to a virtual address (VA). That is, a mapping relationship from msg VA to PA is formed. In this way, only the msg VA needs to be transferred to the callee later without transferring the msg itself, avoiding the disadvantages of data duplication and improving transmission efficiency.

[0104] In some embodiments, during the IPC communication process, the callee can use the VA to query the msg list maintained by the IPC engine to obtain data. The query process includes, for example: the callee uses the msg VA to request the corresponding PA from the IPC engine, and the IPC logic circuit of the IPC engine finds the corresponding PA in the VA based on the mapping relationship and then sends it to the callee.

[0105] In some other embodiments, after the shared memory is allocated, when the callee is registered with the IPC engine, the callee can also establish the page table of the process according to the starting address and length (size) of the shared memory and add it to the MMU. The page table globally defines the mapping relationship between the virtual address (VA) and the physical address (PA) of the shared memory segment. The callee can access the page table according to the VA to directly obtain the PA corresponding to the VA, that is, the callee can use the VA to directly access the data (msg) in the shared memory, thereby unifying the address access logic to the MMU and avoiding changes to the existing MMU process, thereby further improving the feasibility of the solution. In this embodiment, the msg list maintained by the IPC engine can be used to verify the correctness of the data, that is, after the msg list is established, when the caller initiates the call of the service again, the IPC engine verifies whether the PA corresponding to the VA is in the shared memory through the msglist (that is, whether the msg list records the mapping relationship between the VA and the PA located in the shared memory).

[0106] Further, in order to achieve the security and accuracy of data access, the IPC logic circuit of the IPC engine can control the access rights of msg by setting the query rights of callee to the msg list maintained by the IPC engine. For example, when the caller needs to initiate an ipccall to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to save the data to be transmitted (msg), and indicates the virtual address (VA) of the data to the caller, and sets the access rights to caller readable and writable, and the rest of the processes / threads cannot read and write. For the callee corresponding to the callee ID passed in when the caller calls the service, the IPC engine can enable the search permission in the context information of the callee, that is, allow the callee corresponding to the callee ID to use VA to query the msglist maintained by the IPC engine, set the memory where the data is located to be readable by the callee, and other processes / threads cannot read and write, thereby achieving access to msg. For other callees, the default search permission is closed, so other callees cannot query the msglist, which avoids other callees from illegally accessing data and improves the security and accuracy of data access.

[0107] In addition, during the IPC logic circuit execution cycle, different CPU cores can be prohibited from accessing resources on the IPC engine at the same time to resist possible malicious attack programs and improve the security of the IPC process.

[0108] It can be seen that through shared memory, data (msg) can be mapped between caller and callee, and the IPC engine maintains the mapping relationship between msg VA and PA. The IPC engine can set the access rights of msg according to the ipccall initiated by the caller, and only needs to pass the msg VA to the callee later. Thereby, the data transfer is indirectly completed without relying on the kernel and without data copying, and the transfer process is invisible to the outside. It can also be understood that in the embodiment of the present application, the data transfer form of the current caller can be the transfer of access rights to the data (rather than the data itself), and the access rights are obtained from the call chain of the caller, such as caller->callee, thereby saving transmission resources and improving data transfer efficiency.

[0109] It should be noted that in this article, the so-called "process context information" can be regarded as various variables, data and the environment when the process is executed related to the state of the process, including all register variables related to the process, files opened by the process, or memory information, etc. When process scheduling occurs, the process switch is the process context switch, and the context information mentioned above needs to be switched before the newly scheduled process can run. For example, when it is necessary to switch from the client process to the server process, all the states of the client process need to be saved, and at the same time, the state of the server process needs to be loaded. In this way, when the service ends, the state of the interrupted client process can be restored according to the context information of the client process.

[0110] It can be seen that the embodiment of the present application designs a dedicated hardware-based IPC engine, and the IPC engine can be used as a coprocessor or a separate execution unit, and can run in parallel without the software execution cycle of the CPU. The IPC engine further provides an IPC logic circuit and multiple registers to establish a new IPC mechanism. In order to cooperate with the interaction between the hardware-based IPC engine and the process, the embodiment of the present application also designs user-mode processor instructions for caller and callee: ipccall and ipcret, respectively, to facilitate the calling interface, thereby satisfying the caller's service call and the callee's callback, and ensuring the feasibility of the IPC process. The premise for the execution of the above two instructions is that the IPC engine completes initialization, and the initialization process can be completed by the kernel state driver, including the initialization configuration of the IPC engine, memory allocation, etc.

[0111] The IPC engine can be used to save context information, switch contexts, or transfer data in user mode. The kernel is not aware of these processes (that is, the IPC process does not require kernel participation), avoiding the drawbacks of frequent switching between user mode and kernel mode in existing IPC mechanisms (such as the binder mechanism). The IPC process of the process is separated from the kernel, thereby releasing a large amount of CPU software execution time, thereby greatly reducing the overall latency of the IPC process.

[0112] In addition, the IPC engine in the embodiment of the present application maps the data memory and only needs to pass the virtual address of the data to the callee without passing the data itself, thereby avoiding copying the data, reducing the delay of data copying, and improving data transmission efficiency.

[0113] In addition, the scheme of the embodiment of the present application can also be implemented to achieve that after the IPC engine is initialized, the operating system allocates shared memory, and the callee initiates registration to establish the page table of the process, which is managed by the MMU. When the caller needs to call a service, the operating system allocates a memory segment in the shared memory to the caller to store the data (msg) to be transferred on behalf of the caller. The mapping relationship between the virtual address and the physical address of the msg in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU. Therefore, in the subsequent IPC communication, after the msg VA is transferred from the caller to the callee through the IPC engine, the callee can access the page table according to the VA to obtain the data, thereby achieving the purpose of the caller and the callee sharing memory, avoiding the change of the existing MMU workflow, avoiding the occurrence of page faults, and ensuring the stability and security of the IPC communication.

[0114] Need to understand, Figure 5A The IPC engine can be implemented in pure hardware, including a large number of logic circuits, algorithm circuits or registers, and can also include various interfaces or analog circuits, etc., which are not limited in this embodiment. When the IPC engine is a coprocessor, it can be implemented in pure hardware without executing software, or it can be partially implemented in the form of a coprocessor that can run software. That is, the function of the IPC engine is realized by running the necessary software. Figure 5A The corresponding components can run necessary software modules to implement the technical solution. At this time, the IPC engine is still a hardware accelerator independent of the CPU, but it needs necessary software to drive its work, which is not specifically expanded in this embodiment.

[0115] For the sake of convenience, the various method embodiments described below are expressed as a combination of a series of action steps, but those skilled in the art should be aware that the specific implementation of the technical solution of the present application is not limited by the order of the described series of action steps.

[0116] Based on the system architecture and IPC engine described above, the following describes a method flow of inter-process communication (IPC) provided by an embodiment of the present application, see Figure 6 , the method is described from the perspective of the IPC engine side, including but not limited to the following steps:

[0117] S100. When the IPC engine hardware is initialized, the operating system running on the processor core configures a portion of the memory space in the memory as a shared memory space of the process, and the shared memory space is used to store the data to be transmitted required for inter-process communication. The memory can be a memory, such as a DDR memory, such as DDR SDRAM (Double Data Rate SDRAM).

[0118] In the embodiment of the present application, when the system is initialized (IPC engine is initialized), the operating system reserves a fixed portion of memory in the physical memory as shared memory for caller and callee. The shared memory can be used to store data that needs to be transferred between processes during IPC communication.

[0119] In some embodiments, before running the callee process, callee can establish a page table based on the starting address and length (size) of the shared memory space. The page table is managed by the MMU and contains a mapping relationship from the virtual address of the shared memory space to the physical address, so that callee can obtain the delegated data based on VA search in the page table in subsequent IPC communications.

[0120] In some further embodiments, indication information (pointer) is saved in a register of the IPC engine, and the indication information indicates a mapping relationship between a virtual address of the data to be transferred and a physical address of the data to be transferred, so that a subsequent callee can query the IPC engine based on VA to obtain the transferred data in subsequent IPC communications.

[0121] When the caller needs to initiate an ipccall to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates a memory segment in the shared memory to the caller to store the data to be transferred (msg), and indicates the virtual address (VA) of the data to the caller. The mapping relationship between the virtual address and the physical address of msg in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU.

[0122] For the relevant implementation contents of the above embodiments, please refer to the relevant description above and will not be repeated here.

[0123] S101. The IPC engine receives a call instruction from a client process, the call instruction may be the ipccall described herein, the call instruction is used to request a service of a server process, and the call instruction includes an identifier of the server process and an address of data to be transferred, the address may be a virtual address.

[0124] In the embodiment of the present application, the server (Server) as the owner of many services (Service), before it can provide services to the client (Client), can first register its own services with the IPC engine through the server process (callee). In one implementation, when the callee is started, the registration process can be completed with the assistance of the kernel driver, where the kernel can be a macro kernel or a micro kernel, which is not limited in the present application.

[0125] The server may register one or more services with the IPC engine. The IPC engine records the callee's ID and the callee's entry address according to the callee's registration. The callee's entry address corresponds to the callee's context information.

[0126] Since the information of various services has been pre-registered in the IPC engine, the caller can learn from the IPC engine which services are available. As a user of services, when the client needs to use one or more callee services, it can apply for one or more services from the IPC engine through the client process (caller). At this time, the client's caller can use the call instruction (ipccall) at the user layer to request the IPC engine service.

[0127] The call request may include information such as the command to call the service, the ID of the callee, and the address of the parameter msg.

[0128] S102. The IPC engine activates the server process according to the identification (ID) of the server process, so that the server process executes the service according to the data to be transmitted.

[0129] On the one hand, the IPC engine can search the local storage to find the entry address of the server process according to the identifier of the server process; then, the IPC engine can set the program counter (PC) to the callee entry address and start executing the callee process context, thereby running the server process.

[0130] On the other hand, in order to avoid copying the data to be transferred during the IPC process, in the IPC engine, the data itself can be transferred indirectly by transferring the mapping (memory mapping) of the data to the callee without copying the data. Specifically, the address of the data to be transferred can be the msg VA. The IPC engine can establish a mapping relationship from msg VA to PA based on the shared memory mechanism, grant the callee the right to query the mapping relationship, and pass the VA to the callee. Or the callee can query the page table in the MMU according to the VA to obtain the PA corresponding to the VA, thereby achieving access to the msg. In this way, the subsequent callee can query the IPC engine according to the VA to achieve access to the msg, and execute the services required by the client according to the msg.

[0131] S103. The IPC engine receives a return instruction (ipcret) from the server process, wherein the return instruction includes an execution result.

[0132] The ipccall and ipcret in this application are both user-mode processor instructions, so the caller and callee implement instruction interaction in the user mode during the IPC process to avoid falling into the kernel mode.

[0133] S104. The IPC engine resumes the client process according to the return instruction.

[0134] In an embodiment of the present application, after the IPC engine receives the ipccall from the caller, the entry address of the caller may also be recorded. The entry address of the caller corresponds to the context information of the caller. In this way, when the IPC engine receives the ipcret of the callee, the operation of the callee can be switched to the operation of the caller according to the entry address of the caller, that is, the process switching is realized. Specifically, after the callee completes the IPC processing, the ipcret can be executed. The IPC engine responds to the ipcret, pops up the current caller record, thereby switching to the caller context and restoring the state of the caller.

[0135] It can be seen that, by implementing the embodiment of the present application, the context information preservation, context switching and recovery, data transfer, etc. in the user state can be transferred to a new physical entity (i.e., IPC engine) in time and space to realize. As the medium of IPC, the IPC engine provides corresponding user state instructions ipccall and ipcret, so that caller and callee can complete context switching in user state without switching to kernel state, thereby satisfying the service call of caller and the callback of callee, realizing the interaction of process in user state level, and the IPC engine can work in parallel with kernel software, greatly reducing the overall delay of IPC process. In addition, in the embodiment of the present application, the data access right can be transmitted by the IPC engine, and only the virtual address of the data needs to be transmitted to the callee, without the need to transmit the data itself, thereby avoiding the copy of the data (copy), further reducing the delay of the data copy, and improving the data transmission efficiency.

[0136] In addition, by implementing the solution of the embodiment of the present application, it is also possible to realize that after the IPC engine is initialized, the operating system allocates shared memory, and after the callee initiates registration, the page table of the current process is established and managed by the MMU. When the caller needs to call a service, the operating system allocates a memory segment in the shared memory to the caller to store the transferred data (msg). The mapping relationship between the virtual address and the physical address of the msg in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU. Therefore, in the subsequent IPC communication, after the msg VA is passed from the caller to the callee through the IPC engine, the callee can access the page table according to the VA to obtain the data, thereby achieving the purpose of the caller and the callee sharing memory, avoiding changes to the existing MMU workflow, avoiding the occurrence of page fault errors, ensuring the stability and security of the IPC communication, and improving the feasibility of the product.

[0137] Based on the system architecture and IPC engine described above, the following describes another inter-process communication (IPC) method flow provided by an embodiment of the present application. The IPC engine can be deployed in the CPU core and interact with the outside world, such as interacting with the process, by means of the user interface of the CPU core. Figure 7 The method describes the scheme in detail from multiple perspectives, including but not limited to the following steps:

[0138] S200. When the IPC engine hardware is initialized, a portion of the memory space in the memory is configured as a shared memory space of the process, and the shared memory space is used to store the data to be transmitted required for inter-process communication. The memory may be a memory, such as a DDR memory, such as DDR SDRAM (Double Data Rate SDRAM).

[0139] The relevant memory of this step refers to the description of step S100 and will not be repeated here.

[0140] S201.callee is registered to the IPC engine after startup.

[0141] Exemplarily, callee can be registered with the IPC engine through the kernel. Of course, callee can also be registered with the IPC engine through other methods, for example, corresponding to a system with a microkernel, it can be registered with the IPC engine through a user-mode driver. This application does not specifically limit the registration method.

[0142] In the embodiment of the present application, the server, as the owner of many services, must first register its own services with the IPC engine through the server process (callee) before it can provide services to the client (Client) through IPC. The server can register one or more services with the IPC engine.

[0143] In one implementation, after the callee is started, the registration process can be completed with the assistance of the kernel driver, wherein the kernel can be a macro kernel or a micro kernel, which is not limited in this application. The kernel can drive the IPC engine to save the information registered by the callee. For example, the registration process can be completed by a system call (such as a callee list add instruction). The IPC engine forms a callee entry address through the callee register set according to the ID of the callee, and records the ID number of the callee, which is associated with the callee entry address. It can be understood that for different processes of the same server, or different processes of different clients, registration can be completed in the IPC engine. Each time a callee is registered, a callee entry address is added. All these callee entry addresses can form a list (callee list), which points to the global DDR memory. Therefore, a callee entry address can be regarded as an entry in the list. The ID number of the callee can be used as the index of the entry.

[0144] Exemplarily, the ID number of the callee may be the process ID (processID, PID) of the callee.

[0145] S202. When the caller needs the service of the callee, the caller sends a service call instruction (ipccall) to the IPC engine. The call instruction includes the ID of the callee and the address of the data to be transferred (for example, recorded as msg address information). The address can be a virtual address.

[0146] In this step, since the information of various services has been pre-registered in the IPC engine, the caller can obtain which services are available from the IPC engine. As a user of the service, when the client needs to use the services of one or more callees, it needs to apply to the IPC engine for the one or more services. At this time, the client's caller can use the call instruction (ipccall) at the user layer to request the IPC engine service, and pass the ID and related parameters of the callee corresponding to the service through the ipccall instruction. The related parameters include the address of the data to be transferred to the callee (referred to as the address of the data to be transferred). For example, the address of the data to be transferred is a virtual address (i.e., the msg VA mentioned above).

[0147] It should be noted that the ipccall in this article can support synchronous or asynchronous calling methods, and this method flow mainly uses the synchronous calling method as an example to illustrate the solution.

[0148] S203. The IPC engine performs a condition check on the IPC communication between the caller and the callee.

[0149] In this step, in response to the ipccall from the caller, the IPC engine can perform various condition checks to verify whether the requirements of the IPC communication are met. In a possible embodiment, the subsequent steps are performed only when the condition check passes. If the condition check fails, the ipccall can be rejected.

[0150] For example, the IPC engine may perform at least one of the following condition checks through the IPC logic circuit:

[0151] 1) Check if caller and callee are in different execution levels.

[0152] 2) Check whether the caller and callee are in the same processor core. The IPC logic circuit can decide whether to migrate the process context information based on whether the processes are in the same core.

[0153] 3) Check the caller's security permissions to determine whether the caller has the authority to call the callee's service.

[0154] 4) Check whether the relevant parameters carried by the call instruction meet the length requirements.

[0155] It should be noted that this step is an optional step.

[0156] S204. The IPC engine records the indication information of the caller context information in the link register (link reg), and centrally records the entry address (msg entry address) of the data to be transferred through the message register.

[0157] In this step, the IPC engine can record the caller context information in the call stack pointed to by link reg, so as to be used when the caller needs to be restored later. In addition, the IPC engine can record the msg entry address to the msg list through the message register set according to the msg address (such as msg CA) passed in by the caller. The msg address passed in by the caller in a call instruction can be one or more. It can be understood that when the caller needs to perform IPC communication with one or more callees, the caller can pass in the msg address information corresponding to different callees respectively.

[0158] It should be noted that, in a possible implementation, this step may also be performed before step S203.

[0159] S205. The IPC engine finds the callee entry address through the callee register set according to the callee ID.

[0160] S206. The IPC engine performs process context switching according to the callee entry address, thereby activating the callee.

[0161] In the embodiment of the present application, since the callee ID and the callee entry address have a clear correspondence, the IPC engine can find the callee entry address in the list (callee list) according to the ID passed in by the caller. Exemplarily, the callee entry address can be an address pointer of the callee, and the address pointer of the callee points to the callback function address registered by the callee, and the callback function is used for the callee to execute the corresponding service (service).

[0162] Then, the IPC engine can set the program counter (PC) in the CPU to the callee entry address and start executing the callee process context. At this time, the callee is activated to execute the corresponding service.

[0163] S207. The IPC engine determines the mapping relationship between the address (virtual address) of the data to be transferred and the memory address.

[0164] S208. The IPC engine passes the address (virtual address) of the data to be transferred to the callee, and transfers the access right of the data to be transferred to the callee.

[0165] In some embodiments of the present application, in order to avoid copying the data to be transferred during the IPC process, the IPC engine may not directly transfer the data itself, but indirectly transfer the data by transferring the mapping (memory mapping) of the data without copying the data. Figure 8As shown, a specific implementation scheme is: add a mapping mechanism of the msg address space in the IPC engine so that the msg data is only mapped between the caller and the callee. When the IPC engine is initialized, a part of the memory is allocated as shared memory, and a mapping table between the virtual address (VA) and the memory address (physical address) of the msg is established, and the IPC engine can access such a mapping table. When the caller initiates an ipccall to the IPC engine, the IPC engine can find the PA by searching the mapping table according to the incoming msg VA, and record the mapping relationship between the VA and the PA to maintain the msg list. In this way, on the one hand, the IPC engine only needs to pass the msg VA to the callee without passing the msg itself, avoiding the disadvantages of data duplication and improving transmission efficiency. On the other hand, the IPC logic circuit of the IPC engine can control the access rights of the msg by setting the query rights of the callee to the msg list maintained by the IPC engine. For example, when the caller needs to initiate an ipccall to the IPC engine, the operating system allocates memory to the caller based on the shared memory, that is, allocates a portion of the memory space in the shared memory to the caller to store the data to be transferred (msg), and indicates the virtual address (VA) of the data to the caller, and sets the access rights to be readable and writable by the caller, and unreadable and writable by other processes / threads. When the ipccall instruction is executed, after the permission check passes, the IPC engine sets the portion of the shared memory to be readable by the callee according to the information of the callee entry, and unreadable and writable by other processes / threads. Specifically, for the callee corresponding to the callee ID passed in when the caller calls the service, the IPC engine can enable the search permission in the context information of the callee, that is, allow the callee corresponding to the callee ID to use VA to query the msg list maintained by the IPC engine, thereby accessing the msg, or the callee can query the page table in the MMU according to the VA to obtain the PA corresponding to the VA, thereby accessing the msg. That is, the data access right is transferred from the caller to the callee. For other callees, the default search permission is closed, so other callees cannot query the msg list. This prevents other callees from illegally accessing data and improves the security and accuracy of data access.

[0166] In some other embodiments of the present application, different transmission modes may be configured for data of different lengths according to the length of the data to be transmitted, so as to improve the flexibility of data transmission.

[0167] An exemplary solution may be: configure small data (data length is less than a preset threshold, such as less than 32 bytes) to be directly transferred through the msg register copy. Configure large data (data length is greater than or equal to a preset threshold, such as greater than or equal to 32 bytes) to be transferred using a memory mapping solution, and complete the transfer process by transferring the access right of the data to the callee through the IPC engine.

[0168] Another exemplary solution may be: if the data length is less than 32 bytes, it is directly copied and transferred through the msg register during the process context switch; if the data length is greater than or equal to 32 bytes and less than the IPC cache size (IPCBUF size, which can be customized, such as 128 bytes), it can be copied and transferred through scheduling or interruption; if the data length is greater than the IPC cache size (such as greater than 128 bytes), it is transferred using a memory mapping solution, and the access rights to the data are transferred to the callee through the IPC engine to complete the transfer process.

[0169] It should be noted that the present application does not limit the specific size of the preset threshold, and the above example is only used to explain the present application scheme and is not a limitation.

[0170] It should also be noted that there is no necessary sequence between the above steps S205 - S208 .

[0171] S209.callee obtains the data to be transmitted and executes the services required by the caller.

[0172] In this step, the caller can obtain msg according to the data access rights (for example, use VA to query the msg list maintained by the IPC engine to access msg), and call related functions to complete specific services. The services in the system service layer can be provided to the application in real time through the Manager provided by the application layer framework layer. The service content can be, for example, messages, communications, cameras, or window usage, etc., which are not limited in this application.

[0173] S210.callee sends a return instruction (ipcret) to the IPC engine, and the return instruction can carry the execution result of the service.

[0174] S211. The IPC engine uses the link register to resume the execution of the caller.

[0175] In this step, when callee completes the IPC processing, ipcret can be executed. The IPC logic circuit of the IPC engine responds to ipcret and controls the link register (link reg) to pop out the last caller record, thereby switching to the caller context and restoring the caller state.

[0176] In order to better understand the specific solutions of the embodiments of the present application, Fig. 9 In the figure, the instruction interaction between caller and callee is represented by a dotted line, which is to illustrate that caller and callee can implement service calls at the user layer. There is no real direct interaction between them, but they interact through the IPC engine at the hardware layer as an intermediary to realize the IPC communication method.

[0177] The IPC communication process after using the IPC engine is as follows: After the IPC service process callee is started, it is registered with the IPC engine through the kernel driver. The caller uses the ipccall instruction in the user layer to request the IPC engine service, and passes the corresponding callee ID and the address of the relevant parameter msg to the IPC engine. The caller's context information is recorded in the call stack pointed to by the link register of the IPC engine, and will be used when the caller state needs to be restored. The msg is recorded in the continuous memory pointed to by the msg register. The IPC engine finds the callee entry address according to the ID passed by the caller, and sets the program counter (PC) in the CPU to the callee entry address, and the CPU starts to switch to the callee's process context. The IPC engine also passes the access right of msg to the callee. In this way, the callee can execute the corresponding service method. After the callee completes the IPC processing, it sends the ipcret instruction to the IPC engine, and the IPC engine controls the link register to pop up the caller record, thereby resuming the execution of the caller process. In the above IPC process, the event notification of the IPC engine can be reported to the kernel through interruption. For example, when an exception occurs in the IPC engine, it can be reported to the kernel through an interrupt. For another example, when the IPC processing is completed, the event can also be reported to the kernel through an interrupt.

[0178] It should be noted that for the parts not described in detail in the present method embodiment, reference can be made to the description of the relevant contents above, such as Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C For the sake of brevity of the specification, the above embodiments are not described here.

[0179] It can be seen that the embodiment of the present application transfers the context information preservation, context switching and recovery, data transfer, etc. in the user state to a new physical entity (i.e., the IPC engine) in terms of time and space. The kernel driver pre-assists in the registration of the collee, the initialization of the IPC engine, the memory allocation, etc. After the caller actually initiates the IPC, the IPC process does not require the participation of the kernel, avoiding the drawbacks of frequent switching between the user state and the kernel state in the existing IPC mechanism (such as the binder mechanism), and achieving no switching to the kernel state in software. The IPC engine and the CPU work in parallel in hardware, thereby releasing a large amount of CPU software execution time. In order to cooperate with the interaction between the hardware-based IPC engine and the process, user-state processor instructions: ipccall and ipcret are also provided to the caller and callee for easy calling of the interface, thereby satisfying the caller's service call and the callee's callback, realizing the interaction of processes at the user state level, and ensuring the feasibility of the IPC process, greatly reducing the overall latency of the IPC process. The implementation of the embodiments of the present application and the application test on the Android platform show that the delay of the IPC process can be reduced to 20 cycles, which significantly reduces the IPC delay compared to the prior art.

[0180] In addition, in the embodiment of the present application, data (such as small data) or data access rights can be transferred through the IPC engine. Specifically, the IPC engine maps the msg memory of the data to be transferred, and realizes the transfer of data access rights without transferring the data itself, thereby avoiding the copy of data, further reducing the delay of data copying, and improving data transmission efficiency.

[0181] In addition, by implementing the scheme of the embodiment of the present application, it is also possible to realize that after the IPC engine is initialized, the operating system allocates shared memory, and after the callee initiates registration, the page table of the current process is established and managed by the MMU. When the caller needs to call a service, the operating system allocates a memory segment in the shared memory to the caller to store the transferred data (msg). The mapping relationship between the virtual address and the physical address of the msg in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU. Therefore, in the subsequent IPC communication, after the msg VA is passed from the caller to the callee through the IPC engine, the callee can access the page table according to the VA to obtain the data, thereby achieving the purpose of the caller and the callee sharing memory, avoiding changes to the existing MMU workflow, avoiding the occurrence of page fault errors, and ensuring the stability and security of the IPC communication.

[0182] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A hardware system for inter-process communication (IPC), characterized in that: include: Processor core, IPC engine hardware and memory, including: The processor core is used to configure a portion of the memory space in the memory as a shared memory space of the process when the IPC engine hardware is initialized, and the shared memory space is used to store the data to be transferred required for inter-process communication; establish a page table according to the starting address and length of the shared memory space, and the page table contains a mapping relationship from a virtual address to a physical address of the shared memory space; The processor core is further used to run the client process, and when the client process needs to call the service of the server process, send a first processor instruction to the IPC engine hardware, wherein the first processor instruction is a call instruction of the client process to the service, and the call instruction includes an identifier of the server process and a virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space; The IPC engine hardware is used to instruct the processor core to run the server process according to the identifier, and send the virtual address of the data to be transferred to the server process; The processor core is further used to run the server process, wherein the server process queries the page table according to the virtual address of the data to be transferred to obtain the data to be transferred to perform the service; and send a second processor instruction to the IPC engine hardware, wherein the second processor instruction is a return instruction of the server process; The IPC engine hardware is further configured to, according to the second processor instruction, instruct the processor core to resume running the client process.

2. The hardware system according to claim 1, characterized in that: The processor core is also used to configure a portion of the memory space in the shared memory space to the client process to store the data to be transferred when the client process needs to call the service of the server process.

3. The hardware system according to claim 1 or 2, characterized in that: Before running the client process, the processor core is further used to send registration information of the server process to the IPC engine hardware, where the registration information includes the identifier; The IPC engine hardware is further used to: receive the registration information; save the identifier and the entry address of the server process in the IPC engine hardware in response to the registration information; The IPC engine hardware is specifically used to: find the entry address according to the identifier; set the entry address to the program counter (PC) in the processor core; The processor core is also used to run the server process according to the entry address set in the PC.

4. The hardware system according to claim 1 or 2, characterized in that: The IPC engine hardware is also used to, after receiving the call instruction, query the status register in the processor core to obtain the call stack address of the client process, and save the call stack address of the client process in the IPC engine hardware; The IPC engine hardware is specifically used to call out the call stack address according to the second processor instruction, and instruct the processor core to resume running the client process according to the call stack address.

5. The hardware system according to claim 1 or 2, characterized in that: The IPC engine hardware is specifically used to check whether the client process and the server meet the requirements of inter-process communication, and when the client process and the server meet the requirements of inter-process communication, instruct the processor core to run the server process according to the identifier.

6. The hardware system according to claim 1 or 2, characterized in that: The calling instruction and the returning instruction are both user mode instructions.

7. A method for inter-process communication (IPC), characterized in that: include: When the IPC engine hardware is initialized, the processor core configures a portion of the memory space in the memory as a shared memory space of the process, wherein the shared memory space is used to store the data to be transmitted required for inter-process communication; a page table is established according to the starting address and length of the shared memory space, wherein the page table contains a mapping relationship from a virtual address of the shared memory space to a physical address; The processor core runs the client process, and when the client process needs to call the service of the server process, sends a first processor instruction to the IPC engine hardware, wherein the first processor instruction is a call instruction of the client process to the service, and the call instruction includes an identifier of the server process and a virtual address of the data to be transferred; the physical address of the data to be transferred is located in the shared memory space; The IPC engine hardware instructs the processor core to run the server process according to the identifier, and sends the virtual address of the data to be transferred to the server process; The processor core runs the server process, and the server process queries the page table according to the virtual address of the data to be transferred to obtain the data to be transferred to execute the service; The processor core sends a second processor instruction to the IPC engine hardware, where the second processor instruction is a return instruction of the server process; The IPC engine hardware instructs the processor core to resume running the client process according to the second processor instruction.

8. The method according to claim 7, characterized in that The method further comprises: When the client process needs to call the service of the server process, the processor core configures a portion of the memory space in the shared memory space to the client process to store the data to be transferred.

9. The method according to claim 7 or 8, characterized in that: Before the processor core runs the client process, the method further includes: The processor core sends registration information of the server process to the IPC engine hardware, where the registration information includes the identifier; The IPC engine hardware receives the registration information; in response to the registration information, the IPC engine hardware stores the identifier and the entry address of the server process; Correspondingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier, including: The IPC engine finds the entry address according to the identifier; sets the entry address to a program counter (PC) in the processor core; The processor core runs the server process according to the entry address set in the PC.

10. The method according to claim 7 or 8, characterized in that: After the processor core sends the first processor instruction to the IPC engine hardware, the method further includes: The IPC engine hardware queries the status register in the processor core to obtain the call stack address of the client process, and saves the call stack address of the client process in the IPC engine hardware; Correspondingly, the IPC engine hardware instructs the processor core to resume running the client process according to the second processor instruction, including: The IPC engine hardware calls out the call stack address according to the second processor instruction, and instructs the processor core to resume running the client process according to the call stack address.

11. The method according to claim 7 or 8, characterized in that: Before the IPC engine hardware instructs the processor core to run the server process according to the identifier, the method further includes: The IPC engine hardware checks whether the client process and the server meet the requirements of inter-process communication; Correspondingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier, specifically including: When the client process and the server meet the requirements for inter-process communication, the IPC engine hardware instructs the processor core to run the server process according to the identifier.

12. The method according to claim 7 or 8, characterized in that: The calling instruction and the returning instruction are both user mode instructions.

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