Method and apparatus for bypassing sensing signals in a power converter

Abstract

Methods, apparatus, systems, and articles of manufacture for bypassing sensing signals in a power converter are disclosed. The disclosed methods, apparatus, systems, and articles of manufacture provide an apparatus for bypassing sensing signals in a power converter, the apparatus comprising: a first single-transmit circuit for generating a clock signal based on an adaptive delay during the operation time of the power converter, the adaptive delay being based on a count value of a counter (526); a pulse comparator (514) coupled to an adaptation pulse generator, the pulse comparator (514) for: comparing a first duration of the adaptation pulse with a second duration of a reference pulse during the operation time of the power converter; and adjusting the count value of the counter (526); and a readiness detector (542) coupled to the pulse comparator (514), the readiness detector (542) for transmitting the count value to a second single-transmit circuit in response to a trigger event during the operation time of the power converter.

Description

Technical Field

[0001] This disclosure generally relates to power converters, and more specifically to methods and apparatus for bypassing sensing signals in power converters. Background Technology

[0002] In recent years, automakers have developed advanced vehicles that incorporate a variety of sensors. For example, vehicles include radio detection and ranging (RADAR), light detection and ranging (LIDAR), sound navigation and ranging (SONAR), cameras, and / or other systems containing sensors suitable for applications used in the vehicle.

[0003] These systems typically require high-frequency and / or high-duty-cycle (e.g., cycling) power modules. In this high-frequency and / or high-duty-cycle application, the power module uses a power metal-oxide-semiconductor field-effect transistor (MOSFET) to provide the required power. Power MOSFETs can be used as power delivery devices to support ampere ratings up to hundreds of amperes during operation that delivers power to a load. In some instances, the load draws current in the tens of amperes range. Alternatively, the system can use a low-frequency and / or low-duty-cycle power module to provide the power required for automotive applications. Attached Figure Description

[0004] Figure 1 This is a schematic diagram of an instance control system used for an instance power converter.

[0005] Figure 2 This explains why a single pulse in an instance is too short to bypass the sensing current signal. Figure 1 Timing diagrams of various example signals in the control system.

[0006] Figure 3 This explains why when a single pulse in an instance is too long to bypass the sensing current signal... Figure 1 Timing diagrams of various example signals in the control system.

[0007] Figure 4 This explains when a single pulse is properly adjusted to bypass the sensed current signal. Figure 1 Timing diagrams of various example signals in the control system.

[0008] Figure 5A and 5B It is a display Figure 1 A schematic diagram showing further details of an example implementation of the core control circuit.

[0009] Figure 6 It is a display Figure 1 A schematic diagram showing further details of an example implementation of one of the single-shot circuits of 5.

[0010] Figure 7 It is a display Figure 6 A schematic diagram showing further details of an example implementation of the adaptive delay circuit.

[0011] Figure 8 It is an explanation and Figure 6 Timing diagrams of various instance signals associated with the first operating mode of one of the single-shot circuits to generate single-shot pulses.

[0012] Figure 9 It is an explanation and Figure 6 The timing diagrams of various instance signals associated with the second operating mode of one of the single-electrode circuits as oscillator operation.

[0013] Figure 10 It is an explanation and Figure 1 Timing diagrams of various example signals associated with the core control circuit of 5.

[0014] Figure 11 It is an explanation and Figure 1 The state diagram of the instance state associated with the core control circuit of 5.

[0015] Figure 12A and 12B This is a flowchart illustrating a process executable by machine-readable instructions, which can be executed to carry out... Figure 1 And the core control circuit of 5.

[0016] The figures are not drawn to scale. Unless otherwise indicated, connection references (e.g., attachment, coupling, connection, and link) should be interpreted broadly and may include intermediate parts between sets of elements and relative movement between elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected and have a fixed relationship with each other. Generally, the same reference numerals will be used throughout the figures and accompanying written description to refer to the same or similar parts.

[0017] In this document, descriptors such as "first," "second," "third," etc., are used to identify multiple elements or components that can be individually mentioned. Unless otherwise specified or understood based on the context of their use, such descriptors are not intended to impose any meaning of temporal priority or order, but are merely for ease of understanding of the disclosed instances as markers for individually mentioning multiple elements or components. In some instances, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be mentioned in the claims using different descriptors such as "second" or "third." In such examples, it should be understood that such descriptors are used merely for ease of mentioning multiple elements or components. Detailed Implementation

[0018] The examples disclosed herein provide an apparatus for bypassing sensing signals in a power converter, the apparatus comprising: a first single-shot circuit for generating a clock signal based on an adaptive delay during the operation time of the power converter, the adaptive delay being based on a counter count value; a pulse comparator coupled to an adaptive pulse generator, the pulse comparator being configured to: compare a first duration of the adaptive pulse with a second duration of a reference pulse during the operation time of the power converter; and adjust the counter count value; and a readiness detector coupled to the pulse comparator, the readiness detector being configured to transmit the count value to a second single-shot circuit in response to a trigger event during the operation time of the power converter. As used herein, the term "adapted" is defined as adjusted to compensate for the operating conditions of the circuit to maintain a predetermined value.

[0019] In recent years, automakers have developed advanced vehicles that incorporate a variety of sensors. For example, vehicles include radio detection and ranging (RADAR), light detection and ranging (LIDAR), sound navigation and ranging (SONAR), cameras, and / or other systems containing sensors suitable for applications used in the vehicle.

[0020] These systems typically require high-frequency and / or high-duty-cycle power modules. In this high-frequency and / or high-duty-cycle application, the power module uses a power MOSFET to provide the required power. Power MOSFETs can be used as power delivery devices to support ampere ratings up to hundreds of amperes during operation that delivers power to the load. In some instances, the load draws current in the tens of amperes range.

[0021] In applications using high-frequency and / or high-duty-cycle signals to control power MOSFETs, monitoring the current through the power MOSFET is crucial. High-frequency switching of the power MOSFET can introduce noise into the sensed signal, which represents the current. This noise causes the sensed signal to have a settling time that varies depending on the operating conditions of the power MOSFET in use. The sensed signal representing the current is unreliable during the settling time. Therefore, decisions made during the settling time to continue or stop current acquisition are also unreliable.

[0022] To reliably control the current through a power MOSFET, it is advantageous to have a sensing signal for the blanking current during the settling time. However, since power MOSFETs are controlled by high-frequency signals, the switching cycle is very short (e.g., in the range of tens of nanoseconds) and varies only slightly for both the high-side and low-side power MOSFETs (e.g., it may vary due to high frequency or duty cycle). Reliably controlling a power MOSFET without adjusting the length of the blanking period is extremely difficult. Improperly adjusting the blanking period when controlling a power MOSFET can cause problems.

[0023] For example, if the blanking period is too long, the on-time of either the high-side or low-side power MOSFET will be longer than expected, affecting the power converter's duty cycle or switching frequency and output characteristics. For example, if the on-time of either the high-side or low-side power MOSFET is longer than expected, the current may potentially rise to levels outside the performance specifications of either the high-side or low-side power MOSFET, and / or cause the power converter's output voltage to vary near the value required by the load.

[0024] Furthermore, if the blanking period is too short, the sensed current signal may cause the overcurrent protection mechanism in the power converter to disconnect the power MOSFET and stop either the high-side or low-side power MOSFET from conducting. For example, the sensed signal during the settling time may be inaccurate due to noise generated by the high-frequency switching of either the high-side or low-side power MOSFET. Therefore, an excessively short blanking period can cause the overcurrent protection mechanism to malfunction inappropriately, leading to ineffective operation of the power converter. Thus, a finely tuned blanking period corresponding to the settling time of the sensed signal is advantageous for controlling the power MOSFET.

[0025] Figure 1 This is a schematic diagram of an instance control system 100 for an instance power converter. The instance control system 100 includes an instance core control circuit 102 and an instance oscillator 104. The instance core control circuit 102 includes an instance single-shot fine-tuner 106 and an instance first single-shot circuit 108a. The instance control system 100 also includes an instance second single-shot circuit 108b, an instance third single-shot circuit 108c, an instance fourth single-shot circuit 108d, and an instance fifth single-shot circuit 108e.

[0026] exist Figure 1 In the illustrated example, the example oscillator 104 is coupled to the example single-shot tuner 106. The example single-shot tuner 106 is coupled to the example oscillator 104, the example first single-shot circuit 108a, the example second single-shot circuit 108b, the example third single-shot circuit 108c, the example fourth single-shot circuit 108d, and the example fifth single-shot circuit 108e. In this example, the example first single-shot circuit 108a is coupled to the example single-shot tuner 106.

[0027] In the illustrated example, the instance control system 100 further includes instance power converters 110a and 110b, instance current sensors 112a and 112b, instance comparators 114a and 114b, instance logic gates 116a and 116b, and instance comparators 118a and 118b. The instance control system 100 also includes instance power converter control circuits 120a and 120b, instance logic gates 121a and 121b, instance logic circuits 122a and 122b, and instance gate driver circuits 124a and 124b.

[0028] exist Figure 1 In the illustrated example, instance current sensors 112a and 112b are coupled to corresponding instance power converters 110a and 110b and corresponding instance comparators 114a and 114b. Instance comparators 114a and 114b are coupled to corresponding instance current sensors 112a and 112b and corresponding instance logic gates 116a and 116b. In this example, instance logic gate 116a is coupled to instance logic gate 121a, instance comparator 114a, and instance power converter control circuit 120a. Instance logic gate 116b is coupled to instance logic gate 121b, instance comparator 114b, and instance power converter control circuit 120b. Instance comparators 118a and 118b are coupled to corresponding instance power converter control circuits 120a and 120b, corresponding instance power converters 110a and 110b, and corresponding reference voltage source V. REF_1 V REF_2 These correspond to the desired output voltages of example power converters 110a and 110b, respectively.

[0029] exist Figure 1 In the examples described herein, example power converter 110a further includes example high-side switch 126a, example low-side switch 128a, example inductor 130a, example capacitor 132a, and example load 134a. In the examples, example power converter 110b includes example high-side switch 126b, example low-side switch 128b, example inductor 130b, example capacitor 132b, and example load 134b.

[0030] In this example, the instance power converter control circuit 120a is coupled to instance logic gate 116a, instance comparator 118a, instance second single-shot circuit 108b, and instance third single-shot circuit 108c. The instance power converter control circuit 120b is coupled to instance logic gate 116b, instance comparator 118b, instance fourth single-shot circuit 108d, and instance fifth single-shot circuit 108e. The instance second single-shot circuit 108b is coupled to the instance single-shot trimmer 106, instance power converter control circuit 120a, instance logic circuit 122a's instance set input, and logic gate 121a. The instance third single-shot circuit 108c is coupled to the instance single-shot trimmer 106, instance power converter control circuit 120a, instance logic circuit 122a's instance reset input, and logic gate 121a. Example 4 single-shot circuit 108d is coupled to example single-shot fine-tuner 106, example power converter control circuit 120b, example logic circuit 122b, example set input, and logic gate 121b. Example 5 single-shot circuit 108e is coupled to example single-shot fine-tuner 106, example power converter control circuit 120b, example logic circuit 122b, example reset input, and logic gate 121b.

[0031] In the illustrated example, example logic circuit 122a is coupled to example second single-transmitter circuit 108b, example third single-transmitter circuit 108c, example logic gate 121a, and example gate driver circuit 124a. Example logic circuit 122b is coupled to example fourth single-transmitter circuit 108d, example fifth single-transmitter circuit 108e, example logic circuit 121b, and example gate driver circuit 124b. Example gate driver circuits 124a and 124b are coupled to corresponding example logic circuits 122a and 122b and corresponding example power converters 110a and 110b.

[0032] exist Figure 1 In the illustrated examples, example power converters 110a and 110b include example input voltage node V. IN_1 V IN_2 They refer to the example ground node GND. Example high-side switches 126a and 126b include connections to the corresponding input voltage node V. IN_1 V IN_2 The corresponding drain. In Figure 1In the example, the high-side switches 126a and 126b include corresponding sources coupled to the corresponding switching nodes SW1 and SW2. The corresponding switching nodes SW1 and SW2 are coupled to the corresponding drains of the low-side switches 128a and 128b. The sources of the corresponding low-side switches 128a and 128b are coupled to the ground node GND. The corresponding switching nodes SW1 and SW2 are coupled to the corresponding inductors 130a and 130b, and the corresponding inductors 130a and 130b are coupled to the corresponding positive terminals of the corresponding capacitors 132a and 132b. The negative terminals of the corresponding capacitors 132a and 132b are coupled to the ground node GND. The corresponding current flowing through the corresponding switching nodes SW1 and SW2 is current I. SW_1 I SW_2 .

[0033] exist Figure 1 In the illustrated example, each of the example current sensors 112a and 112b senses the corresponding current I in the corresponding power converters 110a and 110b. SW_1 I SW_2 The device. In the illustrated example, each of the example current sensors 112a and 112b is a combination of a shunt resistor and a voltage source. The example shunt resistor measures the corresponding current I flowing through the corresponding power converters 110a and 110b. SW_1 I SW_2 And output the corresponding current I SW_1 I SW_2 The corresponding voltage. Additionally, each of the example current sensors 112a and 112b includes an example voltage source to output a voltage corresponding to the current I. SW_1 I SW_2 The corresponding reference voltage is limited by the corresponding current.

[0034] exist Figure 1 In the illustrated examples, each of the example comparators 114a and 114b compares the current I. SW_1 I SW_2 The corresponding voltage and the corresponding current I SW_1 I SW_2 The device limits the corresponding reference voltage for the example current and outputs corresponding overcurrent protection (OCP) signals OCP1 and OCP2. When the current I... SW_1 I SW_2 The corresponding voltage is greater than the corresponding current I SW_1 I SW_2When the instance current limit is equal to the corresponding reference voltage, each of instance comparators 114a and 114b outputs a logic high value (e.g., binary '1'). Otherwise, each of instance comparators 114a and 114b outputs a logic low value (e.g., binary '0'). In this instance, each of instance comparators 114a and 114b is an analog comparator. In other instances, each of instance comparators 114a and 114b may be a digital comparator, one or more logic gates, or any combination thereof suitable for the application.

[0035] exist Figure 1 In the illustrated example, each of the example logic gates 116a and 116b is a device for comparing the corresponding OCP signals OCP1 and OCP2 with the corresponding outputs of the corresponding logic gates 121a and 121b. In the example, each of the corresponding logic gates 116a and 116b is a terminal-inverting AND logic gate. Example logic gate 116a outputs the OCP_blanked_1 signal based on the OCP1 signal and the output of logic gate 121a. Example logic gate 116b outputs the OCP_blanked_2 signal based on the OCP2 signal and the output of logic gate 121b. In the example, when the OCP1 signal is high and the output of logic gate 121a is low, then example logic gate 116a outputs a logic high value as the OCP_blanked_1 signal. In the example, when the OCP2 signal is high and the output of logic gate 121b is low, then example logic gate 116b outputs a logic high value as the OCP_blanked_2 signal. Otherwise, each of the instance logic gates 116a and 116b outputs a logic low value as the OCP_blanked_1 signal and the OCP_blanked_2 signal, respectively. In other instances, each of the instance logic gates 116a and 116b may be an analog comparator, a digital comparator, one or more logic gates, or any combination thereof suitable for the application.

[0036] exist Figure 1 In the illustrated example, each of the example comparators 118a and 118b compares the corresponding voltage across loads 134a and 134b with a corresponding reference voltage V corresponding to the corresponding desired voltage across loads 134a and 134b. REF_1 V REF_2 A comparison device. In this example, each of comparators 118a and 118b is an analog comparator. In this example, comparator 118a is based on the voltage across load 134a and a reference voltage V corresponding to the desired voltage across load 134a. REF_1 The output signal is loop_comp_1. In this example, the reference voltage V corresponds to the desired output voltage across the load 134a. REF_1When the voltage is higher than that across load 134a, the instance comparator 118a outputs a logic high value as the loop_comp_1 signal. Otherwise, the instance comparator 118a outputs a logic low value as the loop_comp_1 signal. In this instance, comparator 118b is based on the voltage across load 134b and a reference voltage V corresponding to the desired voltage across load 134b. REF_2 The output signal is loop_comp_2. In this example, the reference voltage V corresponds to the desired output voltage across load 134b. REF_2 When the voltage is higher than that across load 134b, instance comparator 118b outputs a logic high value as the loop_comp_2 signal. Otherwise, instance comparator 118b outputs a logic low value as the loop_comp_2 signal. In other instances, each of instance comparators 118a and 118b may be a digital comparator, one or more logic gates, or any combination thereof suitable for the application.

[0037] exist Figure 1 In the illustrated examples, each of the example power converter control circuits 120a and 120b is a device for controlling the corresponding power converters 110a and 110b. In the illustrated examples, each of the example power converter control circuits 120a and 120b is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that determines when to enable and / or disable the gates of the corresponding high-side switches 126a and 126b and the gates of the corresponding low-side switches 128a and 128b. In the example, example power converter control circuit 120a outputs trigger_hs_1 and trigger_ls_1 based on the ocp_blanked_1 and loop_comp_1 signals. In the example, example power converter control circuit 120b outputs trigger_hs_2 and trigger_ls_2 based on the ocp_blanked_2 and loop_comp_2 signals. In other instances, each of the example power converter control circuits 120a and 120b may be one or more controllers, one or more application-specific integrated circuits (ASICs), one or more processors that execute machine-readable instructions, or any combination thereof suitable for the application.

[0038] exist Figure 1In the illustrated example, the second single-shot circuit 108b is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that generates a single_shot_hs_1 signal based on the trigger_hs_1 signal and one or more signals from the single-shot tuner 106. In other examples, the second single-shot circuit 108b may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The second single-shot circuit 108b may be a semiconductor-based (e.g., silicon-based) device. In a further example, the second single-shot circuit 108b may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0039] exist Figure 1 In the illustrated example, the third single-shot circuit 108c is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that generates the single_shot_ls_1 signal based on the trigger_ls_1 signal and one or more signals from the single-shot tuner 106. In other examples, the third single-shot circuit 108c may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The third single-shot circuit 108c may be a semiconductor-based (e.g., silicon-based) device. In further examples, the third single-shot circuit 108c may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0040] exist Figure 1 In the illustrated example, the fourth single-shot circuit 108d is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that generates the single_shot_hs_2 signal based on the trigger_hs_2 signal and one or more signals from the example single-shot tuner 106. In other examples, the fourth single-shot circuit 108d may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The fourth single-shot circuit 108d may be a semiconductor-based (e.g., silicon-based) device. In a further example, the fourth single-shot circuit 108d may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0041] exist Figure 1In the illustrated example, the fifth single-shot circuit 108e is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that generates the single_shot_ls_2 signal based on the trigger_ls_2 signal and one or more signals from the single-shot tuner 106. In other examples, the fifth single-shot circuit 108e may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The fifth single-shot circuit 108e may be a semiconductor-based (e.g., silicon-based) device. In further examples, the fifth single-shot circuit 108e may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0042] exist Figure 1 In the illustrated example, each of the logic circuits 121a and 121b is an OR gate. In this example, logic gate 121a receives the single_shot_hs_1 signal and the single_shot_ls_1 signal, and performs a logical OR on the signals. In this way, logic gate 121a outputs a logical high value when either the single_shot_ls_1 signal or the single_shot_ls_2 signal is a logical high value.

[0043] exist Figure 1In the illustrated examples, each of the example logic circuits 122a and 122b is an SR latch. In this example, example logic circuit 122a outputs the hs_active_1 signal based on the single_shot_hs_1 and single_shot_ls_1 signals. In this example, example logic circuit 122a outputs a logic high value as the hs_active_1 signal when the single_shot_hs_1 signal is at a logic high value, and outputs a logic low value as the hs_active_1 signal when the single_shot_ls_1 signal is at a logic high value. When both the single_shot_hs_1 and single_shot_ls_1 signals are at a logic low value, example logic circuit 122a outputs its previous state. In this example, example logic circuit 122b outputs the hs_active_2 signal based on the single_shot_hs_2 and single_shot_ls_2 signals. In this example, when the single_shot_hs_2 signal is at a logic high value, instance logic circuit 122b outputs a logic high value as the hs_active_2 signal, and when the single_shot_ls_2 signal is at a logic high value, it outputs a logic low value as the hs_active_2 signal. When both the single_shot_hs_2 and single_shot_ls_2 signals are at a logic low value, instance logic circuit 122b outputs the previous state it was in. In other examples, each of instance logic circuits 122a and 122b may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0044] exist Figure 1In the illustrated example, each of the example gate driver circuits 124a and 124b is a means of driving the corresponding gate of the high-side switches 126a and 126b and the corresponding gate of the low-side switches 128a and 128b. Furthermore, the example gate driver circuits 124a and 124b synchronously drive the corresponding gates of the high-side switches 126a and 126b and the corresponding gates of the low-side switches 128a and 128b. In this manner, the example gate driver circuits 124a and 124b enable the corresponding gates of the high-side switches 126a and 126b while disabling the corresponding gates of the low-side switches 128a and 128b. Similarly, in this manner, the example gate driver circuits 124a and 124b enable the corresponding gates of the low-side switches 128a and 128b while disabling the corresponding gates of the high-side switches 126a and 126b. Furthermore, the example gate driver circuits 124a and 124b ensure that the corresponding high-side switches 126a and 126b and the corresponding low-side switches 128a and 128b are not simultaneously enabled. In the illustrated example, each of the example gate driver circuits 124a and 124b is one or more combinational logic circuits. In other examples, each of the example gate driver circuits 124a and 124b is one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0045] exist Figure 1 In the illustrated example, each of the example high-side switches 126a and 126b is an example first negative-channel (N-channel) MOSFET, and each of the example low-side switches 128a and 128b is an example second N-channel MOSFET. In the example, the corresponding high-side switches 126a and 126b and the corresponding low-side switches 128a and 128b control the corresponding current I in the corresponding power converters 110a and 110b. SW_1 I SW_2 The flow. In other examples, each of the example high-side switches 126a, 126b and each of the corresponding low-side switches 128a, 128b is a positive-channel (P-channel) MOSFET, an insulated-gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), a junction-gate field-effect transistor (JFET), or any combination thereof suitable for the application.

[0046] exist Figure 1 In the illustrated examples, each of the example inductors 130a and 130b is a discrete inductor. In the illustrated examples, example inductors 130a and 130b temporarily store energy to facilitate power conversion. In other examples, each of the corresponding inductors 130a and 130b is one or more inductive elements that can be used to temporarily store energy to facilitate power conversion. Figure 1In the illustrated examples, each of the example capacitors 132a and 132b is a discrete capacitor. In the illustrated examples, the example capacitors 132a and 132b temporarily store energy to facilitate power conversion. In other examples, each of the example capacitors 132a and 132b is one or more capacitive elements that can be used to temporarily store energy to facilitate power conversion.

[0047] exist Figure 1 In the illustrated examples, each of the example loads 134a and 134b is an automotive subsystem. In this example, the corresponding loads 134a and 134b are devices to which the corresponding power converters 110a and 110b supply power. For example, each of the corresponding loads 134a and 134b is an automotive subsystem containing an application processor. For example, an automotive subsystem is a radio, display, dashboard, or other device providing information and / or entertainment in a vehicle. In another example, each of the example loads 134a and 134b is a RADAR subsystem in a vehicle. In other examples, each of the loads 134a and 134b may be a LIDAR subsystem, a SONAR subsystem, one or more camera subsystems, and / or any other suitable sensor subsystem for the application. In a further example, each of the instance loads 134a and 134b may be a power steering subsystem, a headlight or other lighting subsystem, a windshield wiper subsystem, a defroster subsystem, a starter subsystem, an alternator subsystem, or any other electrical component or subsystem in a vehicle. In a further example, each of the instance loads 134a and 134b may be a personal electronic device. For example, each of the corresponding power converters 110a and 110b may be implemented in a personal electronic device (e.g., a cellular phone, tablet computer, laptop computer, etc.). In a further example, each of the corresponding loads 134a and 134b is an industrial subsystem, such as a sensor, test equipment, display, application processor, or field-programmable gate array (FPGA).

[0048] exist Figure 1In the illustrated examples, each of the example power converters 110a and 110b is a DC-DC buck converter. In other examples, each of the example power converters 110a and 110b may be a boost converter, buck-boost converter, flyback converter, forward converter, rectifier, or any other power converter suitable for the application. A DC power converter operates by temporarily storing input energy in electronic components (e.g., inductors, capacitors, inductive elements, capacitive elements, etc.) and then releasing said energy at a different voltage at the output load. In power converters 110a and 110b, when the corresponding high-side switches 126a and 126b are turned on and the corresponding low-side switches 128a and 128b are turned off, the corresponding current flows from the corresponding input voltage node V. IN_1 V In_2 The current flows to the corresponding inductors 130a and 130b, which charge at a linear rate. When the corresponding inductors 130a and 130b are charging, they store energy in the corresponding current I flowing through them. SW_1 I SW_2 In the corresponding magnetic field generated. Additionally, when the corresponding high-side switches 126a and 126b are turned on and the corresponding low-side switches 128a and 128b are turned off, the corresponding capacitors 132a and 132b are also charged to the corresponding desired output voltage level, and the corresponding loads 134a and 134b are charged from the corresponding input voltage node V. IN_1 V In_2 The supplied current. When the corresponding high-side switches 126a and 126b are open, the corresponding low-side switches 128a and 128b are turned on, causing the corresponding current I to be supplied. SW_1 I SW_2 The energy can continue to flow to the corresponding loads 134a and 134b. The energy stored in the corresponding magnetic fields of the corresponding inductors 130a and 130b is dissipated, and as it dissipates, a corresponding current (e.g., I0) is generated. SW_1 I SW_2 The current flows through the corresponding power converters 110a and 110b and to the corresponding loads 134a and 134b. When the corresponding high-side switches 126a and 126b are open, the corresponding current I flowing through the corresponding power converters 110a and 110b... SW_1 I SW_2The magnitude will be equal to the corresponding current flowing through the corresponding low-side switches 128a and 128b. The corresponding current from the corresponding inductors 130a and 130b flows to the corresponding capacitors 132a and 132b and the corresponding loads 134a and 134b, while the corresponding capacitors 132a and 132b maintain the corresponding desired output voltage of the corresponding power converters 110a and 110b, and the corresponding loads 134a and 134b (e.g., automotive subsystems) receive power. The corresponding current returns to the corresponding inductors 130a and 130b by flowing through the ground node GND and the corresponding low-side switches 128a and 128b. This switching mode allows continuous current to flow into the corresponding loads 134a and 134b of the corresponding power converters 110a and 110b.

[0049] exist Figure 1 In the illustrated examples, the instance core control circuit 102 is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits. In other examples, the instance core control circuit 102 may be implemented by one or more integrated circuits, logic circuits, microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), or controllers from any desired family or manufacturer. The core control circuit 102 may be a semiconductor-based (e.g., silicon-based) device. In further examples, the instance core control circuit 102 may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application. The instance core control circuit 102 is a device for controlling one or more operating conditions of one or more power converters (e.g., power converters 110a, 110b) in an application.

[0050] exist Figure 1 In the illustrated example, oscillator 104 is a device for controlling the operating frequency of the core control circuit 102. In the illustrated example, oscillator 104 is a resistor-capacitor (RC) oscillator. In other examples, oscillator 104 is a ring oscillator, crystal oscillator, phase-locked loop oscillator, or any other suitable oscillator for the application. Oscillator 104 generates a system clock signal (e.g., the CLK_SYS signal) at a desired frequency (e.g., 100 MHz).

[0051] exist Figure 1In the illustrated example, the instance core control circuit 102 includes an instance single-shot fine-tuner 106. The instance single-shot fine-tuner 106 is a means of fine-tuning a single-shot signal generated by a single-shot circuit (e.g., instance first single-shot circuit 108a) according to the operating conditions of the power converter. In this example, the instance single-shot fine-tuner 106 is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits. In other examples, the instance single-shot fine-tuner 106 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The single-shot fine-tuner 106 may be a semiconductor-based (e.g., silicon-based) device. In a further example, the instance single-shot fine-tuner 106 may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0052] exist Figure 1 In the illustrated example, the instance core control circuit 102 includes an instance first single-shot circuit 108a. The instance first single-shot circuit 108a is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that generates a single-shot pulse based on one or more signals from the instance single-shot tuner 106. In other examples, the instance first single-shot circuit 108a may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The first single-shot circuit 108a may be a semiconductor-based (e.g., silicon-based) device. In a further example, the instance first single-shot circuit 108a may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0053] exist Figure 1 In the illustrated example, the example single-shot trimmer 106 fine-tunes the single-shot signal generated by the example first single-shot circuit 108a based on the operating conditions of the respective power converters 110a and 110b (e.g., die temperature, input voltage variations, etc.). For example, as the temperature of the silicon die on which the example high-side switch 126a and example low-side switch 128a are fabricated increases, the corresponding on-time and off-time of the example high-side switch 126a and example low-side switch 128a may vary. In this example, due to variations in temperature, duty cycle, and other factors, the duration of the blanking period (e.g., 30 nanoseconds (ns)) will similarly vary (e.g., from 18 ns to 42 ns). Without compensating for this variation, the circuitry generating the blanking period cannot properly bypass the sensing signal in the control system 100. Figure 1The illustrated example single-shot tuner 106 adjusts the duration of the blanking period across small time intervals (e.g., 1 millisecond (ms)) to maintain a predetermined duration of the blanking period (e.g., 30 ns) regardless of changes in temperature or other operating conditions. The predetermined duration corresponds to the worst-case scenario for the blanking period, thus allowing reliable current sensing under all conditions. The tuned single-shot tuner 106 transmits the adjusted blanking period to the example second single-shot circuit 108b, example third single-shot circuit 108c, example fourth single-shot circuit 108d, and example fifth single-shot circuit 108e. The adjusted blanking period allows the example second single-shot circuit 108b, example third single-shot circuit 108c, example fourth single-shot circuit 108d, and example fifth single-shot circuit 108e to accurately bypass the sensing signal in the example control system 100, regardless of the operating conditions of the control system 100. This adjusted blanking period is beneficial to the load (e.g., each of loads 134a, 134b). For example, an improperly adjusted blanking period (e.g., too short or too long) can lead to incorrect signal sensing, output voltage disturbances, limited output current capability, damage to power converters (e.g., power converters 110a, 110b), erroneous interruption signals disrupting power delivery to the load, duty cycle limitations, switching frequency limitations, higher ripple voltage on the output voltage, and additional noise in the control system (e.g., control system 100). For instance, in a RADAR subsystem in an automotive vehicle, a very high switching frequency is used in the power converter to supply power to the RADAR subsystem to generate a RADAR signal. In this example, the RADAR subsystem operates more advantageously for the user if the input voltage source has a low ripple voltage. Advantageously, a blanking period suitable for the operating conditions of the power converter allows for stable switching at high frequencies, which reduces ripple voltage on the power converter output. Additionally, if the input switching frequency is outside the normal radio bandwidth (e.g., amplitude modulation (AM) frequency, frequency modulation (FM) frequency, etc.), the example RADAR subsystem operates more advantageously for the user. A sufficiently high switching frequency cannot be achieved with an improperly adjusted blanking period (e.g., inappropriately adjusted for the operating conditions of the power converter); however, a high switching frequency that is beneficial to the user can be achieved with an properly adjusted blanking period. Furthermore, a higher switching frequency allows for smaller inductor values ​​(e.g., inductor values ​​<220nH), which are physically smaller than other inductors used in power converters. Smaller values ​​improve load transient performance, and smaller dimensions reduce the inductor's footprint on the printed circuit board (PCB) or other circuitry.

[0054] Figure 2 This explains why a single pulse is too short (e.g., shorter than the predetermined duration) to bypass the sensed current signal. Figure 1The timing diagram 200 shows various example signals in the control system 100. Example timing diagram 200 includes example first curve 202, example second curve 204, example third curve 206, example fourth curve 208, example fifth curve 210, example sixth curve 212, example first time 214 (T0), and example second time 216 (T1). Example timing diagram 200 includes an amplitude axis and a time axis.

[0055] exist Figure 2 In the illustrated example, curve 202 in the first example represents the passage... Figure 1 Example: Current I of inductor 130A SW_1 Example 2, curve 204, represents the result of... Figure 1 The third single-shot circuit 108c generates a single-shot pulse (e.g., a single_shot_ls_1 signal). Example third curve 206 represents the signal generated by... Figure 1 The current I of the low-side switch 128a SW_1 The current level associated with the current level. Example fourth curve 208 represents the current level associated with current I. SW_1 The example current limit corresponds to the current limit (e.g., -3 Amperes). Example fifth curve 210 represents the current limit... Figure 1 The example comparator 114a generates the example OCP1 signal. Example curve 212 represents the signal generated by... Figure 1 The instance OCP_blanked_1 signal is generated by instance logic gate 116a.

[0056] exist Figure 2 In the illustrated example, prior to instance time 214, instance high-side switch 126a is enabled and instance low-side switch 128a is disabled. Prior to instance time 214, instance first curve 202 increases at a linear rate, instance second curve 204 is at a logic low value, instance third curve 206 is at a value of 0 amps, instance fourth curve 208 is at a value of -3 amps, instance fifth curve 210 is at a logic low value, and instance sixth curve 212 is at a logic low value.

[0057] exist Figure 2In the illustrated example, at instance first time 214, instance gate driver circuit 124a controls instance high-side switch 126a and instance low-side switch 128a to enable low-side switch 128a and disable high-side switch 126a, while ensuring that instance high-side switch 126a and instance low-side switch 128a are not enabled simultaneously. At first time 214, first curve 202 transitions from increasing at a linear rate to decreasing at a linear rate, second curve 204 transitions from a logic low value to a logic high value, third curve 206 starts decreasing from a value of 0 amps, instance fourth curve 208 is at a value of -3 amps, instance fifth curve 210 is at a logic low value, and sixth curve 212 is at a logic low value.

[0058] exist Figure 2 In the illustrated example, between the first instance time 214 and the second instance time 216, the first instance curve 202 decreases at a linear rate, the second instance curve 204 is at a logic high value, the third instance curve 206 oscillates (e.g., is stable) between 0 amps and -5 amps, the fourth instance curve 208 is at -3 amps, the fifth instance curve 210 starts from a logic low value, and the sixth instance curve 212 starts from a logic low value. Between the first instance time 214 and the second instance time 216, when the magnitude of the third instance curve 206 exceeds the magnitude of the fourth instance curve 208, the fifth instance curve 210 transitions from a logic low value to a logic high value and remains at a logic high value until the magnitude of the third instance curve 206 is less than the magnitude of the fourth instance curve 208. Between the first instance time 214 and the second instance time 216, the sixth instance curve 212 remains at a logic low value because the second instance curve 204 is at a logic high value.

[0059] exist Figure 2 In the example described, at time 216 in the second instance, Figure 1 Example gate driver circuit 124a disables example low-side switch 128a and enables example high-side switch 126a due to the single pulse being too short. At the second time 216, the first curve 202 transitions from decreasing at a linear rate to increasing at a linear rate, the second curve 204 transitions from a logic high value to a logic low value, the third curve 206 transitions from a value of -5 amps to a value of -2 amps, the fourth curve 208 is at a value of -3 amps, the fifth curve 210 is at a logic high value, and the sixth curve 212 transitions from a logic low value to a logic high value.

[0060] exist Figure 2In the illustrated examples, after the second time point 216, the first curve 202 increases at a linear rate, the second curve 204 is at a logic low value, the third curve 206 transitions from a value of -5 amps to a value of 0 amps, the fourth curve 208 is at a value of -3 amps, the fifth curve 210 starts from a logic high value and then transitions to a logic low value, and the sixth curve 212 starts from a logic high value and then transitions to a logic low value. In other examples disclosed herein, the values ​​of the first curve 202, the second curve 204, the third curve 206, the fourth curve 208, the fifth curve 210, and the sixth curve 212 can be any suitable values ​​(e.g., the value of the fourth curve 208 can be in the range of -0.0003A to -3A), depending on the design of the power converter system in which the third single-electrode circuit 108c is implemented.

[0061] Figure 3 This explains why a single pulse in an instance is too long (e.g., longer than the predetermined duration) to bypass the sensed current signal. Figure 1 The timing diagram 300 shows various example signals in the control system 100. Example timing diagram 300 includes example first curve 202, example second curve 204, example third curve 206, example fourth curve 208, example fifth curve 210, example sixth curve 212, example first time 214 (T0), example third time 302 (T2), and example fourth time 304 (T3). Example timing diagram 300 includes an amplitude axis and a time axis.

[0062] exist Figure 3 In the illustrated example, curve 202 in the first example represents the passage... Figure 1 Example: Current I of inductor 130A SW_1 Example 2, curve 204, represents the result of... Figure 1 The third single-shot circuit 108c generates a single-shot pulse (e.g., a single_shot_ls_1 signal). Example third curve 206 represents the signal generated by... Figure 1 The current I of the low-side switch 128a SW_1 The current level associated with the current level. Example fourth curve 208 represents the current level associated with current I. SW_1 The example current limit corresponds to the current limit (e.g., -3 Amperes). Example fifth curve 210 represents the current limit... Figure 1 The example comparator 114a generates the example OCP1 signal. Example curve 212 represents the signal generated by... Figure 1 The instance OCP_blanked_1 signal is generated by instance logic gate 116a.

[0063] exist Figure 3In the illustrated example, prior to instance time 214, instance high-side switch 126a is enabled and instance low-side switch 128a is disabled. Prior to instance time 214, instance first curve 202 increases at a linear rate, instance second curve 204 is at a logic low value, instance third curve 206 is at a value of 0 amps, instance fourth curve 208 is at a value of -3 amps, instance fifth curve 210 is at a logic low value, and instance sixth curve 212 is at a logic low value.

[0064] exist Figure 3 In the illustrated example, at instance first time 214, instance gate driver circuit 124a controls instance high-side switch 126a and instance low-side switch 128a to enable low-side switch 128a and disable high-side switch 126a, while ensuring that instance high-side switch 126a and instance low-side switch 128a are not enabled simultaneously. At first time 214, first curve 202 transitions from increasing at a linear rate to decreasing at a linear rate, second curve 204 transitions from a logic low value to a logic high value, third curve 206 starts decreasing from a value of 0 amps, instance fourth curve 208 is at a value of -3 amps, instance fifth curve 210 is at a logic low value, and sixth curve 212 is at a logic low value.

[0065] exist Figure 3 In the illustrated examples, between the first instance time 214 and the fourth instance time 304, the first instance curve 202 decreases at a linear rate, the second instance curve 204 is at a logic high value, the third instance curve 206 oscillates (e.g., stabilizes) between 0 amps and -5 amps until it stabilizes at -2 amps, the fourth instance curve 208 is at -3 amps, the fifth instance curve 210 starts from a logic low value, and the sixth instance curve 212 starts from a logic low value. Between the first instance time 214 and the fourth instance time 304, when the magnitude of the third instance curve 206 exceeds the magnitude of the fourth instance curve 208, the fifth instance curve 210 transitions from a logic low value to a logic high value and remains at a logic high value until the magnitude of the third instance curve 206 is less than the magnitude of the fourth instance curve 208. Between the first instance time 214 and the fourth instance time 304, the sixth instance curve 212 remains at a logic low value because the second instance curve 204 is at a logic high value.

[0066] exist Figure 3In the illustrated example, instance third time 302 represents the time when instance gate driver circuit 124a disables instance low-side switch 128a and enables instance high-side switch 126a. However, because the single_shot_ls_1 pulse on instance second curve 204 is too long, the time to enable instance low-side switch 128a and disable instance high-side switch 126a is longer than the time required by the application. The length of the additional time to enable instance low-side switch 128a and disable instance high-side switch 126a is the time between instance third time 302 and instance fourth time 304.

[0067] exist Figure 3 In the illustrated example, at time 304 in instance four, Figure 1 Example gate driver circuit 124a disables example low-side switch 128a and enables example high-side switch 126a. At the fourth time 304, the first curve 202 transitions from decreasing at a linear rate to increasing at a linear rate, the second curve 204 transitions from a logic high value to a logic low value, the third curve 206 transitions from a value of -2 amps to a value of 0 amps, the fourth curve 208 is at a value of -3 amps, the fifth curve 210 is at a logic low value, and the sixth curve 212 is at a logic low value.

[0068] exist Figure 3 In the illustrated examples, after time 304 in example four, curve 202 in example one increases at a linear rate, curve 204 in example two is at a logic low value, curve 206 in example three transitions from a value of -2 amps to a value of 0 amps, curve 208 in example four is at a value of -3 amps, curve 210 in example five is at a logic low value, and curve 212 in example six is ​​at a logic low value. In other examples disclosed herein, the values ​​of curves 202, 204, 206, 208, 210, and 212 can be any suitable values ​​(e.g., the value of curve 208 can be in the range of -0.0003A to -3A), depending on the design of the power converter system in which the single-electrode circuit 108c of example three is implemented.

[0069] Figure 4 This explains when a single pulse is properly adjusted (e.g., matched to a predetermined duration) to bypass the sensed current signal. Figure 1 The timing diagram 400 shows various example signals in the control system 100. Example timing diagram 400 includes example first curve 202, example second curve 204, example third curve 206, example fourth curve 208, example fifth curve 210, example sixth curve 212, example first time 214 (T0), and example fifth time 402 (T4). Example timing diagram 400 includes an amplitude axis and a time axis.

[0070] exist Figure 4 In the illustrated example, curve 202 in the first example represents the passage... Figure 1 Example: Current I of inductor 130A SW_1 Example 2, curve 204, represents the result of... Figure 1 The third single-shot circuit 108c generates a single-shot pulse (e.g., a single_shot_ls_1 signal). Example third curve 206 represents the signal generated by... Figure 1 The current I of the low-side switch 128a SW_1 The current level associated with the current level. Example fourth curve 208 represents the current level associated with current I. SW_1 The example current limit corresponds to the current limit (e.g., -3 Amperes). Example fifth curve 210 represents the current limit... Figure 1 The example comparator 114a generates the example OCP1 signal. Example curve 212 represents the signal generated by... Figure 1 The instance OCP_blanked_1 signal is generated by instance logic gate 116a.

[0071] exist Figure 4 In the illustrated example, prior to instance time 214, instance high-side switch 126a is enabled and instance low-side switch 128a is disabled. Prior to instance time 214, instance first curve 202 increases at a linear rate, instance second curve 204 is at a logic low value, instance third curve 206 is at a value of 0 amps, instance fourth curve 208 is at a value of -3 amps, instance fifth curve 210 is at a logic low value, and instance sixth curve 212 is at a logic low value.

[0072] exist Figure 4 In the illustrated example, at instance first time 214, instance gate driver circuit 124a controls instance high-side switch 126a and instance low-side switch 128a to enable low-side switch 128a and disable high-side switch 126a, while ensuring that instance high-side switch 126a and instance low-side switch 128a are not enabled simultaneously. At first time 214, first curve 202 transitions from increasing at a linear rate to decreasing at a linear rate, second curve 204 transitions from a logic low value to a logic high value, third curve 206 decreases from a value of 0 amperes, fourth curve 208 is at a value of -3 amperes, fifth curve 210 is at a logic low value, and sixth curve 212 is at a logic low value.

[0073] exist Figure 4In the illustrated example, between the first instance time 214 and the fifth instance time 402, the first instance curve 202 decreases at a linear rate, the second instance curve 204 is at a logic high value, the third instance curve 206 oscillates (e.g., stabilizes) between 0 amps and -5 amps until it stabilizes at -2 amps, the fourth instance curve 208 is at -3 amps, the fifth instance curve 210 starts from a logic low value, and the sixth instance curve 212 is at a logic low value. Between the first instance time 214 and the fifth instance time 402, when the magnitude of the third instance curve 206 exceeds the magnitude of the fourth instance curve 208, the fifth instance curve 210 transitions from a logic low value to a logic high value and remains at a logic high value until the magnitude of the third instance curve 206 is less than the magnitude of the fourth instance curve 208. Between the first instance time 214 and the fifth instance time 402, the sixth instance curve 212 remains at a logic low value because the second instance curve 204 is at a logic high value.

[0074] exist Figure 4In the illustrated example, after instance time 402, instance low-side switch 128a remains enabled, while instance high-side switch 126a remains disabled. After instance time 402, instance first curve 202 continues to decrease at a linear rate, instance second curve 204 starts at a logic high value, instance third curve 206 stabilizes at a value of -2 amps, instance fourth curve 208 is at a value of -3 amps, instance fifth curve 210 is at a logic low value, and instance sixth curve 212 is at a logic low value. After instance time 402, instance second curve 204 remains at a logic high value for a short period to ensure that instance third curve 206 has stabilized at a steady-state value (e.g., -2 amps). Then, instance second curve 204 transitions from a logic high value to a logic low value. Between instance first time 214 and instance fifth time 402, instance sixth curve 212 remains at a logic low value and does not transition from a logic low value to a logic high value. This is because the single_shot_ls_1 pulse on instance second curve 204 is finely tuned to be long enough to compensate for the oscillation on instance third curve 206, but not so long as to increase the duty cycle of low-side switch 128a. Furthermore, instance single pulses (e.g., single_shot_ls_1 pulses) are appropriately adapted (e.g., adjusted to match a predetermined duration) to suit the operating conditions of power converter 110a, and proper and beneficial operation of power converter 110a is possible. In other examples disclosed herein, the values ​​of the first curve 202, the second curve 204, the third curve 206, the fourth curve 208, the fifth curve 210, and the sixth curve 212 may be any suitable values ​​(e.g., the value of the fourth curve 208 may be in the range of -0.0003A to -3A), depending on the design of the power converter system of the third single-electrode circuit 108c in which the embodiment of example three is implemented.

[0075] Figure 5A and 5B It is a display Figure 1 A schematic diagram showing further details of an example implementation of the core control circuit 102. Figure 1 The instance core control circuit 102 includes an instance single-shot fine-tuner 106 and an instance first single-shot circuit 108a. The instance single-shot fine-tuner 106 includes an instance refresh pulse generator 500, an instance start detector 502, an instance sequencer 504, an instance reference pulse generator 506, an instance pulse comparator 514, an instance counter 526, an instance fine-tuning distributor 536, an instance ready detector 542, an instance adaptation pulse generator 544, an instance single-shot counter 552, and a logic gate 554.

[0076] exist Figure 5A and 5BIn the illustrated examples, the example reference pulse generator 506 includes example logic gate 508, example logic circuit 510, and example logic circuit 512. The example pulse comparator 514 includes example logic gate 516, example logic circuit 518, example logic circuit 520, example logic circuit 522, and example logic circuit 524. The example counter 526 includes example logic circuit 528, example adder 530, example logic circuit 532, and example logic circuit 534. The example fine-tuning distributor 536 includes example logic circuit 538 and example logic circuit 540. The example adjusting pulse generator 544 includes example logic gate 546, example logic circuit 548, and example logic circuit 550.

[0077] exist Figure 5A and 5B In the illustrated example, the instance refresh pulse generator 500 is coupled to the instance start detector 502. In the illustrated example, the instance start detector 502 is coupled to the instance refresh pulse generator 500, the instance sequencer 504, the instance oscillator 104, and the instance ready detector 542. In the example, the instance sequencer 504 is coupled to the instance start detector 502, the instance reference pulse generator 506, the instance pulse comparator 514, the instance counter 526, the instance ready detector 542, and one or more single-shot circuits. In the example, the instance reference pulse generator 506 is coupled to the instance sequencer 504, the instance pulse comparator 514, the instance single-shot counter 552, the instance logic gate 554, and the instance oscillator 104. In the example, the instance pulse comparator 514 is coupled to the instance sequencer 504, the instance reference pulse generator 506, the instance adaptation pulse generator 544, the instance counter 526, the instance ready detector 542, and the instance oscillator 104.

[0078] exist Figure 5A and 5BIn the illustrated example, instance counter 526 is coupled to instance pulse comparator 514, instance sequencer 504, instance fine-tuning distributor 536, and instance oscillator 104. In the illustrated example, instance fine-tuning distributor 536 is coupled to instance counter 526, instance ready detector 542, instance oscillator 104, and one or more single-shot circuits. In the illustrated example, instance ready detector 542 is coupled to instance start detector 502, instance sequencer 504, instance pulse comparator 514, instance fine-tuning distributor 536, and instance oscillator 104. In the illustrated example, instance adaptation pulse generator 544 is coupled to instance single-shot counter 552, instance pulse comparator 514, instance logic gate 554, and instance first single-shot circuit 108a. In the illustrated example, instance single-shot counter 552 is coupled to instance reference pulse generator 506, instance adaptation pulse generator 544, and instance first single-shot circuit 108a. In the illustrated example, instance logic gate 554 is coupled to instance reference pulse generator 506, instance tuning pulse generator 544, and instance first single-shot circuit 108a. In the illustrated example, instance first single-shot circuit 108a is coupled to instance logic gate 554, instance single-shot counter 552, instance tuning pulse generator 544, instance counter 526, and instance reference logic high value.

[0079] exist Figure 5A and 5B In the illustrated example, the refresh pulse generator 500 is an oscillator. For example, the refresh pulse generator 500 is a ring oscillator, crystal oscillator, RC oscillator, or any other suitable oscillator for the application. In this example, the refresh pulse generator 500 generates pulses at a preset frequency (e.g., 1 kHz). The pulses generated by the refresh pulse generator 500 are signals used to trigger the adjustment of the single pulse length to match a predetermined duration.

[0080] exist Figure 5A and 5B In the illustrated example, the instance start detector 502 is a device that detects the rising edge of a pulse generated by the instance refresh pulse generator 500. When the instance start detector 502 detects the rising edge of an instance pulse generated by the instance refresh pulse generator 500, the instance start detector 502 outputs a pulse (e.g., a start_adaptation signal) to the instance sequencer 504. The instance pulse (e.g., the start_adaptation signal) causes the instance sequencer 504 to begin the process of adjusting the length of a single pulse to a predetermined duration. In this example, the instance start detector 502 operates at the frequency of the instance oscillator 104.

[0081] exist Figure 5A and 5BIn the illustrated example, instance sequencer 504 is a means of counting a predefined number of clock cycles to control the length of instance reference pulses generated by instance reference pulse generator 506. For example, instance sequencer 504 is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits. In other examples, instance sequencer 504 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. Sequencer 504 may be a semiconductor-based (e.g., silicon-based) device. In further examples, sequencer 504 may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0082] During operation (e.g., during runtime), instance sequencer 504 initiates the generation of reference pulses generated by instance reference pulse generator 506 using the instance start_adapt_cycle signal. The on-time length (e.g., logic high value) of the reference pulses generated by instance reference pulse generator 506 is based on the ref_pulse_done signal. For example, instance sequencer 504 generates a pulse as the start_adapt_cycle signal. In this instance, the reference pulses generated by instance reference pulse generator 506 remain at a logic high value until instance sequencer 504 generates the ref_pulse_done signal. For example, sequencer 504 generates the ref_pulse_done signal after a predefined number of clock cycles have been detected. Furthermore, in this instance, instance sequencer 504 generates the ref_cntr_done signal to notify instance counter 526 and instance ready detector 542 that reference pulses have been generated by instance reference pulse generator 506. Instance sequencer 504 also generates the start_adapt_cycle signal when generating the ref_cntr_done signal. The instance sequencer 504 continues this process until it detects the adaptation_ready signal generated by the instance ready detector 542. In an instance, the instance sequencer 504 outputs the allow_trim_sync signal to one or more single-shot circuits.

[0083] exist Figure 5A and 5BIn the illustrated example, the instance reference pulse generator 506 is a means of generating an instance reference_pulse signal based on the instance start_adapt_cycle and ref_pulse_done signals generated by the instance sequencer 504. The instance reference pulse generator 506 includes instance logic gate 508, instance logic circuit 510, and instance logic circuit 512. Instance logic gate 508 is coupled to the instance sequencer 504 and instance logic circuit 510, and instance logic circuit 510 is coupled to instance logic circuit 512 and instance logic gate 508. Instance logic circuit 512 is coupled to instance logic circuit 510, instance oscillator 104, and instance pulse comparator 514 (e.g., coupled to pulse comparator 514). Figure 5A and 5B In the examples described, example logic gate 508 is an example OR gate. In the example, example logic circuit 510 is a 2-to-1 multiplexer. In the example, logic circuit 512 is an example D flip-flop.

[0084] During operation (e.g., during runtime), instance logic gate 508 receives the instance start_adapt_cycle signal and the instance ref_pulse_done signal. Instance logic gate 508 calculates a logical OR of the start_adapt_cycle and ref_pulse_done signals. Instance logic circuit 510 receives the start_adapt_cycle signal and the output of instance logic circuit 512. Based on the output of instance logic gate 508, instance logic circuit 512 outputs either the start_adapt_cycle signal or its own output to its input. Instance logic circuit 512 outputs the signal received from the output of instance logic circuit 510. The output of instance logic circuit 512 is updated based on the CLK_SYS signal.

[0085] exist Figure 5A and 5BIn the illustrated example, instance pulse comparator 514 is a device for comparing the reference_pulse signal and the adaptation_pulse signal and adjusting the counter 526. For example, instance pulse comparator 514 includes instance logic gate 516, instance logic circuit 518, instance logic circuit 520, instance logic circuit 522, and instance logic circuit 524. Instance logic gate 516 is coupled to instance logic circuit 512, instance adaptation pulse generator 544, and instance logic circuit 520. Instance logic circuit 518 is coupled to instance logic circuit 520, instance sequencer 504, and reference logic low value. Instance logic circuit 520 is coupled to instance logic gate 516, instance logic circuit 518, instance logic circuit 522, and oscillator 104. Instance logic circuit 522 is coupled to instance logic circuit 520, instance logic circuit 524, and instance oscillator 104. Example logic circuit 524 is coupled to example logic circuit 522, example counter 526, example ready detector 542, and example oscillator 104. In this example, example logic gate 516 is an AND logic gate with one of its terminals inverted. In this example, example logic circuit 518 is a 2-to-1 multiplexer. In this example, example logic circuit 520 is a D flip-flop containing a set input. In this example, example logic circuit 522 is a D flip-flop, and example logic circuit 524 is a D flip-flop.

[0086] During operation (e.g., during runtime), instance logic gate 516 receives an instance reference_pulse signal from instance logic circuit 512 and an instance adaptation_pulse signal from instance adaptation pulse generator 544. When the reference_pulse signal is logic low and the adaptation_pulse signal is logic high, instance logic gate 516 outputs a logic high value. Otherwise, instance logic gate 516 outputs a logic low value. During operation (e.g., during runtime), instance logic circuit 518 receives a reference logic low value and the output of instance logic circuit 520. Instance logic circuit 518 outputs either a reference logic low value or the output of instance logic circuit 520 based on the logic value of the start_adapt_cycle signal. When the start_adapt_cycle signal is logic high, instance logic circuit 518 outputs a reference logic low value. When the instance start_adapt_cycle signal is logic low, instance logic circuit 518 outputs the output of instance logic circuit 520.

[0087] During operation (e.g., during runtime), instance logic circuit 520 receives the output of instance logic gate 516, the output of instance logic circuit 518, and the CLK_SYS signal. The output of instance logic circuit 520 is based on the inputs from instance logic circuit 518 and instance logic gate 516. The output of instance logic circuit 520 is updated at the frequency of the CLK_SYS signal. More specifically, at each rising edge of the CLK_SYS signal, logic circuit 520 is updated based on the logic values ​​at the outputs of logic circuit 518 and logic gate 516. For example, if the output of logic gate 516 is a logic low value, then at each rising edge of the CLK_SYS signal, the output of logic circuit 520 is set to the logic value at the output of logic circuit 518. In this example, when the output of logic gate 516 is a logic high value, then the output of logic circuit 520 is set to a logic high value, regardless of the logic value at the output of logic circuit 518 and the rising and / or falling edges of the CLK_SYS signal. In this way, the output of logic circuit 520 is asynchronously set by logic gate 516.

[0088] During operation (e.g., during runtime), instance logic circuit 522 receives the output of instance logic circuit 520. The output of instance logic circuit 522 is updated based on the inputs to instance logic circuit 522 and at the frequency of the CLK_SYS signal. During operation (e.g., during runtime), instance logic circuit 524 receives the output of instance logic circuit 522. The output of instance logic circuit 524 (e.g., the ss_too_long signal) is updated based on the inputs to instance logic circuit 524 and at the frequency of the CLK_SYS signal.

[0089] exist Figure 5A and 5B In the illustrated example, instance counter 526 includes instance logic circuit 528, instance adder 530, instance logic circuit 532, and instance logic circuit 534. Instance logic circuit 528 is coupled to instance logic circuit 524, instance logic value corresponding to decimal 1, instance logic value corresponding to decimal negative 1, and instance adder 530. Instance adder 530 is coupled to instance logic circuit 528, instance logic circuit 532, and instance logic circuit 534. Instance logic circuit 532 is coupled to instance adder 530, instance logic circuit 534, and instance sequencer 504. Instance logic circuit 534 is coupled to instance logic circuit 532, instance fine-tuning distributor 536, instance adder 530, instance first single-shot circuit 108a, and instance oscillator 104. In the examples, example logic circuit 528 is a 2-to-1 multiplexer, example adder 530 is a full adder, example logic circuit 532 is a 2-to-1 multiplexer, and example logic circuit 534 is a D flip-flop.

[0090] During operation (e.g., during runtime), instance logic circuit 528 receives a logic value corresponding to 1, a logic value corresponding to -1, and an ss_too_long signal. If the instance ss_too_long signal is a low logic value, then logic circuit 528 outputs a logic value corresponding to 1. If the instance ss_too_long signal is a high logic value, then logic circuit 528 outputs a logic value corresponding to -1. During operation (e.g., during runtime), instance adder 530 adds the output of instance logic circuit 528 to the output of instance logic circuit 534. Instance logic circuit 532 receives the output of instance adder 530, the output of instance logic circuit 534, and a ref_cntr_done signal. If ref_cntr_done is a high logic value, then instance logic circuit 532 outputs the output of instance adder 530. If ref_cntr_done is a low logic value, then instance logic circuit 532 outputs the output of instance logic circuit 534. During operation (e.g., during runtime), instance logic circuit 534 receives the output of instance logic circuit 532. The output of instance logic circuit 534 (e.g., the trim_adaptation signal) is updated based on the inputs to instance logic circuit 534 and at the frequency of the CLK_SYS signal. In this instance, the instance trim_adaptation signal is a 5-bit signal.

[0091] exist Figure 5A and 5B In the illustrated example, instance fine-tuning distributor 536 includes instance logic circuitry 538 and instance logic circuitry 540. Instance logic circuitry 538 is coupled to instance logic circuitry 534, instance logic circuitry 540, and instance readiness detector 542. In the example, instance logic circuitry 540 is coupled to instance logic circuitry 538, instance oscillator 104, and one or more single-shot circuits.

[0092] During operation (e.g., during runtime), instance logic circuit 538 receives the outputs of instance logic circuit 534, instance logic circuit 540, and instance readiness detector 542 (e.g., the adaptation_ready signal). If the adaptation_ready signal is a logic high value, instance logic circuit 538 outputs the trim_adaptation signal. If the adaptation_ready signal is a logic low value, instance logic circuit 538 outputs the output of instance logic circuit 540. During operation (e.g., during runtime), instance logic circuit 540 receives the outputs of instance logic circuit 538. The output of instance logic circuit 540 (e.g., a trim signal) is updated based on the inputs to instance logic circuit 540 and at the frequency of the CLK_SYS signal. In this instance, the instance trim signal is a 5-bit signal.

[0093] exist Figure 5A and 5B In the illustrated example, instance readiness detector 542 is a means of detecting whether an instance single pulse is properly tuned (e.g., matched to a predetermined duration). In this example, instance readiness detector 542 is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits. In other examples, readiness detector 542 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. Readiness detector 542 may be a semiconductor-based (e.g., silicon-based) device. In further examples, readiness detector 542 may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0094] During operation (e.g., during runtime), instance readiness detector 542 receives a start_adaptation signal, which indicates that readiness detector 542 will monitor the length of a single pulse. Instance readiness detector 542 also receives a start_adapt_cycle signal, which indicates that reference pulse generator 506 is generating a reference_pulse signal.

[0095] The instance readiness detector 542 also receives the ss_too_long signal, which indicates whether the pulse comparator 514 has indicated that the reference_pulse signal is longer than the adaptation_pulse signal. The instance readiness detector 542 receives the ref_cntr_done signal, which indicates that the reference_pulse signal has been generated by the instance reference pulse generator 506. The instance readiness detector 542 operates at the frequency of the CLK_SYS signal.

[0096] During operation (e.g., during runtime), instance readiness detector 542 monitors the instance ss_too_long signal in response to a triggering event. In an instance, a triggering event corresponds to an alternating sequence of logical values ​​on the ss_too_long signal followed by the next logical high value. For example, instance readiness detector 542 determines the logical value on the ss_too_long signal when the ref_cntr_done signal is at a logical high value. When readiness detector 542 detects a logical high value on the ref_cntr_done signal, the logical high value indicates that readiness detector 542 will monitor logical values ​​on the ss_too_long signal. If instance readiness detector 542 detects a logical low value followed by a logical high value, which is then followed by a sequence of logical low values ​​(e.g., 010) or a logical high value followed by a logical low value, which is then followed by a sequence of logical high values ​​(e.g., 101), then instance readiness detector 542 monitors the ss_too_long signal for the next logical high value. In one instance, the trigger event corresponds to an alternating sequence of logic values ​​(e.g., 101, 010) followed by a logic high value (e.g., 1011, 0101) for the next sample of the ss_too_long signal. For example, the trigger event could correspond to an alternating sequence of four identical logic low, logic high, and low values ​​(e.g., 0000101). In another instance, the trigger event corresponds to six logic high values ​​followed by an alternating sequence of logic low and logic high values ​​(e.g., 1111110101). If the readiness detector 542 detects the trigger event, then the instance readiness detector 542 generates an instance adaptation_ready signal. The trigger event indicates to the instance readiness detector 542 that the duration of the adaptation_pulse signal is slightly longer than that of the reference_pulse signal, because the ss_too_long signal oscillates near both too short and too long.

[0097] exist Figure 5A and 5B In the illustrated example, the instance adaptation pulse generator 544 is a device for generating an adaptation_pulse signal based on the output of the instance single-shot counter 552. The instance adaptation pulse generator 544 includes instance logic gate 546, instance logic circuit 548, and instance logic circuit 550. In this example, instance logic gate 546 is coupled to the instance single-shot counter 552 and instance logic circuit 548. Instance logic circuit 548 is coupled to instance logic circuit 546 and instance logic circuit 550. Instance logic circuit 550 is coupled to instance logic gate 516, instance logic circuit 554, and instance first single-shot circuit 108a. Figure 5A and 5BIn the examples described, example logic gate 546 is an example OR gate. In the example, example logic circuit 548 is a 2-to-1 multiplexer. In the example, logic circuit 550 is an example D flip-flop.

[0098] During operation (e.g., during runtime), instance logic gate 546 receives the instance start_adaptation_pulse signal and the instance ss_cntr_done signal. Instance logic gate 546 calculates a logical OR of the start_adaptation_pulse and ss_cntr_done signals. Instance logic circuit 548 receives the start_adaptation_pulse signal and the output of instance logic circuit 550. Based on the output of instance logic gate 546, instance logic circuit 550 outputs either the start_adaptation_pulse signal or its own output to its input. Instance logic circuit 550 outputs the signal received from the output of instance logic circuit 548. The output of instance logic circuit 550 is updated based on the clk_single_shot signal.

[0099] exist Figure 5A and 5B In the illustrated examples, instance single-shot counter 552 is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that counts a predefined number of clock cycles to control the length of the instance adaptation_pulse generated by instance adaptation pulse generator 544. For example, instance single-shot counter 552 is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits. In other examples, instance single-shot counter 552 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. Single-shot counter 552 may be a semiconductor-based (e.g., silicon-based) device. In further examples, single-shot counter 552 may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0100] exist Figure 5A and 5BIn the illustrated examples, the first single-pulse circuit 108a is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that generates a single pulse based on the reference_pulse signal, the adaptation_pulse signal, and the trim_adaptation signal. In other examples, the first single-pulse circuit 108a may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The first single-pulse circuit 108a may be a semiconductor-based (e.g., silicon-based) device. In further examples, the first single-pulse circuit 108a may be one or more controllers, one or more ASICs, one or more processors executing machine-readable instructions, or any combination thereof suitable for the application.

[0101] During operation (e.g., during runtime), instance single-shot counter 552 counts clock cycles generated by instance first single-shot circuit 108a. When instance single-shot counter 552 detects a rising edge on the instance reference_pulse signal, instance single-shot counter 552 outputs a pulse as the instance start_adaptation_pulse signal. The pulse causes instance adaptation pulse generator 544 to begin generating the adaptation_pulse signal. The on-time length of the adaptation_pulse signal (e.g., a logic high value) is based on the ss_cntr_done signal. During operation (e.g., during runtime), instance single-shot counter 552 generates a pulse as the start_adaptation_pulse signal. In this instance, the adaptation_pulse signal generated by instance adaptation pulse generator 544 remains at a logic high value until instance single-shot counter 552 generates the ss_cntr_done signal. For example, single-shot counter 552 generates the ss_cntr_done signal after a predefined number of clock cycles have been detected from instance first single-shot circuit 108a.

[0102] During operation (e.g., during runtime), instance logic gate 554 receives the instance reference_pulse signal and the instance adaptation_pulse signal. Instance logic gate 554 performs a logical OR on the reference_pulse signal and the adaptation_pulse signal. In this way, instance logic gate 554 outputs a logic high value when either the reference_pulse signal or the adaptation_pulse signal is a logic high value. During operation (e.g., during runtime), instance first single-shot circuit 108a receives the output of instance logic gate 554, the trim_adaptation signal, and the reference logic high value. The reference logic high value sets instance first single-shot circuit 108a to a first operating mode. Instance first single-shot circuit 108a generates a clock signal based on the trigger signal and the trim_adaptation signal. Instance adaptation pulse generator 544 generates the adaptation_pulse signal based on the start_adaptation_pulse signal generated by instance single-shot counter 552 and the ss_cntr_done signal.

[0103] exist Figure 5A and 5B In the illustrated example, instance reference pulse generator 506 generates a reference_pulse signal based on the start_adapt_cycle and ref_pulse_done signals generated by instance sequencer 504. Instance sequencer 504 counts clock cycles on the instance CLK_SYS signal (e.g., generated by instance oscillator 104). When a first predetermined number of clock cycles is detected, instance sequencer 504 outputs a logic high value on the ref_pulse_done signal. The logic high value on the ref_pulse_done signal causes instance reference pulse generator 506 to transition the reference pulse from a logic high value to a logic low value. When a second predetermined number of clock cycles is detected, instance sequencer 504 outputs a logic high value on the ref_cntr_done signal. The logic high value on the ref_cntr_done signal notifies instance counter 526 and instance ready detector 542 that instance reference pulse generator 506 has completed the generation of the reference_pulse signal within one cycle. When a logic high value is generated on the ref_cntr_done signal, the instance sequencer 504 generates a logic high value on the start_adapt_cycle signal, and the instance reference pulse generator 506 restarts generating the reference_pulse signal.

[0104] exist Figure 5A and 5BIn the illustrated example, when the reference_pulse signal is generated, the instance first single-shot circuit 108a is triggered to generate the clk_single_shot signal. In this way, the instance clk_single_shot signal is generated synchronously based on the reference_pulse signal. The instance first single-shot circuit 108a generates the clk_single_shot signal based on the trim_adaptation signal. In response to the reference_pulse signal, the instance single-shot counter 552 generates a pulse as the start_adaptation_pulse signal, causing the instance adaptation pulse generator 544 to generate the adaptation_pulse signal. The instance single-shot counter 552 counts clock cycles on the clk_single_shot signal. When a third predetermined number of clock cycles is detected, the instance single-shot counter 552 outputs a logic high value on the ss_cntr_done signal. The logic high value on the ss_cntr_done signal causes the instance adaptation pulse generator 544 to transition the adaptation_pulse signal from a logic high value to a logic low value.

[0105] exist Figure 5A and 5B In the illustrated example, instance pulse comparator 514 compares an adaptation pulse (e.g., an adaptation_pulse signal) with a reference pulse (e.g., a reference_pulse signal). For example, pulse comparator 514 sets the logic value of the ss_too_long signal, which is adjusted to the input signal of counter 526. Adjusting the input signal of counter 526 does not change the output of counter 526 until the ref_cntr_done signal reaches a logic high value. When instance pulse comparator 514 detects a falling edge on the reference_pulse signal and a logic high value on the adaptation_pulse signal, instance pulse comparator 514 adjusts the count value of counter 526, which is output to the trimmer distributor 536. Instance pulse comparator 514 adjusts the count value of instance counter 526 by setting the ss_too_long signal to a logic high value. A logic high value on the ss_too_long signal causes counter 526 to subtract a logic value corresponding to negative 1 from the count value.

[0106] Otherwise, if the adaptation_pulse signal is logic low at the falling edge of the reference_pulse signal, the instance pulse comparator 514 adjusts the count value of the instance counter 526 by holding the ss_too_long signal at a logic low value. Furthermore, the output of the instance pulse comparator 514 is updated after three rising edges of the clk_sys signal, so the counter 526 changes the clk_sys signal for three cycles after the rising edge of the start_adapt_cycle signal. A logic low value on the ss_too_long signal causes the counter 526 to increment its count value by a logic value corresponding to 1. In this way, the instance pulse comparator 514 adjusts the count value of the instance counter 526 based on whether a first duration associated with the adaptation pulse (e.g., the adaptation_pulse signal) exceeds a second duration associated with the reference pulse (e.g., the reference_pulse signal). To precisely adjust the count value of the counter 526, the output of the pulse comparator 514 (e.g., the ss_too_long signal) is reset to a logic low value at each rising edge of the start_adapt_cycle signal. For example, when there is a rising edge on the start_adapt_cycle signal, logic circuits 520, 522 and 524 set the logic value to low at the rising edge of the clk_sys signal.

[0107] exist Figure 5A and 5BIn the illustrated example, when the instance counter 526 is adjusted via the instance pulse comparator 514, the value of the trim_adaptation signal is also adjusted. In this way, the duration of the adaptation_pulse signal is appropriately suited to the application. The readiness detector 542 monitors the ss_too_long signal and determines whether a triggering event has occurred. For example, the instance readiness detector 542 monitors both the ss_too_long and ref_cntr_done signals. In this example, the readiness detector 542 detects a logic value on the ss_too_long signal when it detects a high logic value on the ref_cntr_done signal. The instance readiness detector 542 monitors the ss_too_long signal in response to triggering events. For example, the instance readiness detector 542 monitors the ss_too_long signal for sequences of logic low followed by logic high followed by logic low, or vice versa. After detecting this sequence, instance-ready detector 542 monitors the logic high value of the ss_too_long signal when taking the next sample of the ss_too_long signal. When instance-ready detector 542 detects a logic high value after an alternating sequence of logic values, instance-ready detector 542 detects a trigger event. In response to the trigger event, ready detector 542 sets the adaptation_ready signal to a logic high value, causing fine-tuning distributor 536 to transmit fine-tuning signals to one or more single-shot circuits operating in the second operating mode. Instance sequencer 504 also transmits the allow_trim_sync signal to the one or more single-shot circuits operating in the second operating mode. The one or more single-shot circuits are used to generate one or more single-shot pulses based on the allow_trim_sync signal.

[0108] Figure 6 It is a display Figure 1A schematic diagram illustrating further details of an example implementation of one of the single-transmitter circuits 108a, 108b, 108c, 108d, and 108e. One of the example single-transmitter circuits 108a, 108b, 108c, 108d, and 108e includes example logic gates 600, 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, and 626. In the example, logic gate 600 is coupled to the example en_osc_mode signal input, the adaptive delay circuit 622, and logic gate 602. Example logic gate 602 is coupled to logic gates 604, 600, and 626. Example logic gate 604 is coupled to example logic gate 602, example logic circuit 606, and example trigger signal input. Example logic circuit 606 is coupled to logic gate 604, logic gate 626, logic circuit 608, delay circuit 610, logic gate 618, logic gate 624, logic circuit 616, and example single_shot signal output. Example logic circuit 608 is coupled to example logic circuit 606, example logic circuit 612, and example allow_trim_sync signal input. In some examples disclosed herein, a delay circuit and / or several delay circuits may be referred to as a delay cell and / or several delay cells, respectively.

[0109] exist Figure 6 In the illustrated examples, instance delay circuit 610 is coupled to instance logic circuits 606, 612, adaptive delay circuit 622, logic gate 618, and logic gate 626. Instance logic circuit 612 is coupled to delay circuit 610, logic circuit 608, and logic circuit 614. Instance logic circuit 614 is coupled to logic circuits 612, 616, and the instance fine-tuning signal input. Instance logic circuit 616 is coupled to logic circuits 606, 614, and the adaptive delay circuit 622. Instance logic gate 618 is coupled to delay circuit 610, 606, and logic gate 620. Instance logic gate 620 is coupled to logic gate 618, adaptive delay circuit 622, and the en_osc_mode signal input. Instance adaptive delay circuit 622 is coupled to logic circuit 616, delay circuit 610, logic gate 620, and logic gate 600. Example logic gate 624 is coupled to logic circuit 606, adaptive delay circuit 622, and logic gate 626. Example logic gate 626 is coupled to delay circuit 610, logic gate 624, logic gate 602, and logic circuit 606.

[0110] exist Figure 6In the illustrated example, logic gate 600 is an AND gate. In this example, logic gate 600 receives the en_osc_mode signal and the output of adaptive delay circuit 622 (e.g., the delay_adapt signal), and performs a logical AND on said signals. In this way, logic gate 600 outputs a logical high value when both the en_osc_mode signal and the delay_adapt signal are logically high.

[0111] exist Figure 6 In the illustrated example, logic gate 602 is an OR gate. In this example, logic gate 602 receives the output of logic gate 600 and the output of logic gate 626 (e.g., the reset_pulse signal), and performs a logical OR on said signals. In this way, logic gate 602 outputs a logical high value when either the output of logic gate 600 or the reset_pulse signal is a logical high value.

[0112] exist Figure 6 In the illustrated example, logic gate 604 is an AND gate with one terminal inverted. In this example, logic gate 604 receives the output of logic gate 602 and a trigger signal. In this way, when the trigger signal is a logic high value and the output of logic gate 602 is a logic low value, logic gate 604 outputs a logic high value.

[0113] exist Figure 6 In the illustrated example, the example logic circuit 606 is an SR latch. In this example, logic circuit 606 receives the output of logic gate 604 (e.g., the set_latch signal) and the reset_pulse signal. In this way, the output of logic circuit 606 is set to a logic high value by the logic value at the output of logic gate 604. Furthermore, when the reset input (e.g., the reset_pulse signal) is logic high, the output of logic circuit 606 is set to a logic low value. For example, logic circuit 606 will remain at the logic value set by logic gate 604 until a logic high value is received from logic gate 626.

[0114] exist Figure 6 In the illustrated example, the example logic circuit 608 is a D flip-flop. In this example, logic circuit 608 receives the allow_trim_sync signal and the output of logic circuit 606. In this way, the output of logic circuit 608 is set by the allow_trim_sync signal at the rising edge of the signal at the output of logic circuit 606. The output of logic circuit 608 is updated with the logic value on the allow_trim_sync signal at the frequency of the signal output from logic circuit 606.

[0115] exist Figure 6In the illustrated example, the example delay circuit 610 is a circuit that receives an input and outputs a signal (e.g., a delay_fixed signal) input to the circuit after a predetermined time amount (e.g., 10 nanoseconds (ns)). In this way, the delay circuit 610 receives the output of the logic circuit 606, and after the predetermined time amount, the delay circuit 610 outputs the input received from the logic circuit 606 to one or more circuits or components.

[0116] exist Figure 6 In the illustrated example, the example logic circuit 612 is a D flip-flop. In this example, logic circuit 612 receives the output of logic circuit 608 and the output of delay circuit 610. In this manner, the output of logic circuit 612 is set by the output of logic circuit 608 at the rising edge of the signal at the output of delay circuit 610. The output of logic circuit 612 is updated with the logic value at the output of logic circuit 608, using the frequency of the signal output from delay circuit 612.

[0117] exist Figure 6 In the illustrated example, example logic circuit 614 is a 2-to-1 multiplexer that receives two 5-bit signals (e.g., a trim signal and a trim_synced signal) and outputs one of the two 5-bit signals based on a 1-bit input signal (e.g., the output of logic circuit 612). Logic circuit 614 receives the trim signal, the output of logic circuit 616 (e.g., the trim_synced signal), and the output of logic circuit 612. When the output of logic circuit 612 is a logic high value, logic circuit 614 outputs the trim signal. When the output of logic circuit 612 is a logic low value, logic circuit 614 outputs the same logic value as the output of logic circuit 616. In this example, the trim_synced signal is a 5-bit signal.

[0118] exist Figure 6 In the illustrated example, example logic circuit 616 is a five-bit register containing five D flip-flops, each D flip-flop having an inverting clock terminal. Logic circuit 616 receives a 5-bit signal (e.g., the output of logic circuit 614) and outputs a 5-bit signal (e.g., the trim_synced signal) at the frequency of the inverter clock terminal (e.g., the output of logic circuit 606, the single_shot signal). In this way, the output of logic circuit 614 sets the logic value at the output of logic circuit 616 at the falling edge of the signal at the output of logic circuit 606. The output of logic circuit 616 is updated with the logic value at the output of logic circuit 614 at the frequency of the signal output from logic circuit 606 (e.g., the single_shot signal).

[0119] exist Figure 6In the illustrated example, logic gate 618 is an AND gate with one terminal inverted. Logic gate 618 receives the delay_fixed signal and the output of logic circuit 606. In this way, when the delay_fixed signal is a logic high value and the output of logic circuit 606 is a logic low value, logic gate 618 outputs a logic high value.

[0120] exist Figure 6 In the illustrated example, logic gate 620 is an AND gate with one terminal inverted. In this example, logic gate 620 receives the output of logic gate 618 and the en_osc_mode signal. In this way, when the output of logic gate 618 is a logic high value and the en_osc_mode signal is a logic low value, logic gate 620 outputs a logic high value as the clear_delay_line signal.

[0121] exist Figure 6 In the illustrated example, the adaptive delay circuit 622 is a circuit that can be controlled to adjust the amount of time between the received signal (e.g., the delay_fixed signal) and the output signal (e.g., the delay_adapt signal). In this example, the adaptive delay circuit 622 (e.g., an adaptive delay element) receives the delay_fixed signal, the trim_synced signal, and the clear_delay_line signal, and outputs the delay_adapt signal. In this way, the trim_synced signal sets the amount of time used to delay the output of the delay_fixed signal, while clear_delay_line sets the delay between the delay_fixed signal and the delay_adapt signal to zero seconds.

[0122] exist Figure 6 In the illustrated example, logic gate 624 is an OR gate with one terminal inverted. In this example, logic gate 624 receives the output of logic circuit 606 and the delay_adapt signal. Thus, when the output of logic circuit 606 is a logic low value or the delay_adapt signal is a logic high value, logic gate 624 outputs a logic high value.

[0123] exist Figure 6 In the illustrated example, logic gate 626 is an AND gate. In this example, logic gate 626 receives the output of logic gate 624 and the delay_fixed signal. In this way, when the output of logic gate 624 is a logic high value and the delay_fixed signal is a logic high value, logic gate 626 outputs a logic high value as the reset_pulse signal.

[0124] exist Figure 6In the illustrated examples, one of the single-shot circuits 108a, 108b, 108c, 108d, and 108e includes two operating modes. In the first operating mode (e.g., the en_osc_mode signal is a logic low value), one of the single-shot circuits 108a, 108b, 108c, 108d, and 108e operates as a single-shot circuit and outputs a single pulse as the single_shot signal. In the first operating mode, in response to a pulse on the trigger signal, one of the single-shot circuits 108a, 108b, 108c, 108d, and 108e outputs a single pulse as the single_shot signal, and the duration of the single pulse is set by a fine-tuning signal. In the first operating mode, the output of one of the single-shot circuits 108a, 108b, 108c, 108d, and 108e is a pulse with a duty cycle that varies based on the fine-tuning signal.

[0125] exist Figure 6 In the illustrated example, when one of the single-transmitter circuits 108a, 108b, 108c, 108d, and 108e is in a second operating mode (e.g., the en_osc_mode signal is a logic high value), one of the single-transmitter circuits 108a, 108b, 108c, 108d, and 108e operates as an oscillator. In the second operating mode, in response to a pulse as a trigger signal, one of the single-transmitter circuits 108a, 108b, 108c, 108d, and 108e outputs an oscillation signal at a defined frequency, which can be adjusted based on a fine-tuning signal. In the second operating mode, the output of one of the single-transmitter circuits 108a, 108b, 108c, 108d, and 108e is a pulse with a 50% duty cycle oscillating at the defined frequency. In the second operating mode of the example, one of the example single-transmitter circuits 108a, 108b, 108c, 108d, and 108e generates a clock signal.

[0126] Figure 7 It is a display Figure 6 A schematic diagram illustrating further details of an example implementation of the adaptive delay circuit 622. The example adaptive delay circuit 622 includes example logic gates 700, 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, 724, and a decoder 726.

[0127] exist Figure 7In the illustrated example, logic gate 700 is coupled to the delay_fixed signal input, the clear_delay_line signal input, and delay circuit 704. In the example, logic gate 702 is coupled to the delay_fixed signal input, decoder 726, and logic gate 720. In the example, delay circuit 704 is coupled to logic gates 700, 708, and 706. In the example, logic gate 706 is coupled to delay circuit 704, decoder 726, and logic gate 720. In the example, logic gate 708 is coupled to delay circuit 704, the clear_delay_line signal input, delay circuit 710, and logic gate 706. In the example, delay circuit 710 is coupled to logic gates 708, 714, and 712. In the example, logic gate 712 is coupled to logic gate 722, delay circuit 710, and decoder 726.

[0128] exist Figure 7 In the illustrated example, logic gate 714 is coupled to delay circuits 710 and 716. In the example, delay circuit 716 is coupled to logic gates 714 and 718. In the example, logic gate 718 is coupled to delay circuit 716, logic gate 722, and decoder 726. In the example, logic gate 720 is coupled to logic gates 702, 706, and 724. In the example, logic gate 722 is coupled to logic gates 712, 718, and 724. In the example, logic gate 724 is coupled to logic gates 720 and 722, and the delay_adapt signal output.

[0129] exist Figure 7 In the illustrated examples, each of the example logic gates 700, 708, and 714 is an AND gate with an inverting terminal. In the example, logic gate 700 receives the `delay_fixed` signal and the `clear_delay_line` signal. Thus, when the `delay_fixed` signal is logic high and the `clear_delay_line` signal is logic low, logic gate 700 outputs a logic high value. In the example, logic gate 708 receives the output of delay circuit 704 and the `clear_delay_line` signal. Thus, when the output of delay circuit 704 is logic high and the `clear_delay_line` signal is logic low, logic gate 708 outputs a logic high value. In the example, logic gate 714 receives the output of delay circuit 710 and the `clear_delay_line` signal. Thus, when the output of delay circuit 710 is logic high and the `clear_delay_line` signal is logic low, logic gate 714 outputs a logic high value.

[0130] exist Figure 7In the illustrated examples, each of the delay circuits 704, 710, and 716 is a circuit that receives an input and outputs a signal to the circuit after a predetermined time period (e.g., 1 ns). In one example, delay circuit 704 receives the output of logic gate 700. In this way, after the predetermined time period, delay circuit 704 outputs the input received from logic gate 700 to logic gate 708. In another example, delay circuit 710 receives the output of logic gate 708. In this way, after the predetermined time period, delay circuit 710 outputs the input received from logic gate 708 to logic gate 714. In another example, delay circuit 716 receives the output of logic gate 714. In this way, after the predetermined time period, delay circuit 716 outputs the input received from logic gate 714 to logic gate 718.

[0131] exist Figure 7 In the illustrated example, each of logic gates 702, 706, 712, and 718 is an AND gate. In the example, logic gate 702 receives the delay_fixed signal and the delay_select[0] signal from decoder 726. In this way, if the delay_fixed signal is a logic high value and the delay_select[0] signal is a logic high value, then logic gate 702 outputs a logic high value. In the example, logic gate 706 receives the output of delay circuit 704 and the delay_select[1] signal. In this way, if the output of delay circuit 704 is a logic high value and the delay_select[1] signal is a logic high value, then logic gate 706 outputs a logic high value. In the example, logic gate 712 receives the output of delay circuit 710 and the delay_select

[30] signal. In this way, if the output of delay circuit 710 is a logic high value and the delay_select

[30] signal is a logic high value, then logic gate 712 outputs a logic high value. In this example, logic gate 718 receives the output of delay circuit 716 and the delay_select

[31] signal. In this way, if the output of delay circuit 716 is a logic high value and the delay_select

[31] signal is a logic high value, then logic gate 718 outputs a logic high value.

[0132] exist Figure 7In the illustrated examples, each of logic gates 720, 722, and 724 is an OR gate. In this example, logic gate 720 receives the outputs of logic gate 702 and 706. In this way, if the output of logic gate 702 or logic gate 706 is a logic high value, then logic gate 720 outputs a logic high value. In this example, logic gate 722 receives the outputs of logic gate 712 and 718. In this way, if the output of logic gate 712 or logic gate 718 is a logic high value, then logic gate 722 outputs a logic high value. In this example, logic gate 724 receives the outputs of logic gate 720 and 722. In this way, if the output of logic gate 720 or logic gate 722 is a logic high value, then logic gate 724 outputs a logic high value as the delay_adapt signal.

[0133] exist Figure 7 In the illustrated example, the instance decoder 726 is a combination of one or more combinational logic circuits and / or one or more sequential logic circuits that converts an input signal containing n bits (e.g., a 5-bit trim_synced signal) into an input signal containing 2 bits. n The output signal is a 32-bit delay_select[31:0] signal (e.g., containing 32 bits). In this example, the instance decoder 726 is a one-hot decoder. In this example, the instance decoder 726 decodes the binary value corresponding to the input signal (e.g., the binary value 00010 on the trim_synced signal) into a binary value with only one logic high value located at the position in the binary value corresponding to the decimal equivalent of the input binary number (e.g., the binary value 00000000000000000000000000000100 on the delay_select[31:0] signal). For example, if the trim_synced signal contains a binary value corresponding to 5, then the delay_select[31:0] signal will contain all logic low values ​​except for the position of bit 5, which is the least significant bit. In other examples, the instance decoder 726 is a 1-n (1-of-n) decoder, a code transpiler decoder, and an address decoder, or any other suitable decoder for the application. In the example, decoder 726 selects one or more delayed cells based on the trim_synced signal.

[0134] exist Figure 7In the illustrated example, the example trim_synced signal selects the duration of the delay for the adaptive delay circuit 622. In this example, the delay_fixed signal is input to logic gate 700 and delayed by multiple delay circuits (e.g., delay circuits 704, 710, 716) corresponding to the decimal equivalent of the trim_synced signal. For example, the binary value 00001 on the trim_synced signal corresponds to selecting only the delay circuit 704. In this example, the delay_select[1] signal is a logic high value, and the output of the delay circuit 704 is a logic high value. The logic high value on the Delay_select[1] signal and the logic high value on the output of the delay circuit 704 cause logic gate 706 to output a logic high value. The logic high value on the output of logic gate 706 causes logic gate 720 to output a logic high value, and the logic high value on the output of logic gate 720 causes logic gate 724 to output a logic high value as the delay_adapt signal. The trim_synced signal allows the duration of the delay of the adaptive delay circuit 622 to change adaptively during circuit operation.

[0135] exist Figure 7 The illustrated example shows only three delay circuits (e.g., delay circuits 704, 710, and 716). However, the adaptive delay circuit 622 contains 31 delay circuits, each with corresponding logic gates to allow selection of the delay circuit.

[0136] Figure 8 It is an explanation and Figure 6 Timing diagram 800 is provided for various example signals associated with the first operating mode of one of the single-shot circuits 108a, 108b, 108c, 108d, and 108e to generate a single pulse. Example timing diagram 800 includes example curves 802 (seventh), 804 (eighth), 806 (ninth), 808 (tenth), 810 (eleventh), 812 (sixth time, T5), 814 (seventh time, T6), 816 (eighth time, T7), and 818 (ninth time, T8). Example timing diagram 800 includes an amplitude axis and a time axis.

[0137] exist Figure 8 In the illustrated example, curve 802 in example seven represents the result of... Figure 6 The trigger signal received by the instance logic gate 604. Instance eight curve 804 represents the signal received by... Figure 6 The single_shot signal is generated by logic circuit 606. Example, curve 806 in the ninth example, represents the signal generated by... Figure 6The delay_fixed signal generated by delay circuit 610. Example curve 808 (tenth example) represents the delay_adapt signal generated by adaptive delay circuit 622. Example curve 810 (eleventh example) represents the delay_fixed signal generated by... Figure 6 The reset_pulse signal generated by the instance logic gate 626.

[0138] exist Figure 8 In the illustrated example, Figure 6 One of the instance single-transmitter circuits 108a, 108b, 108c, 108d, and 108e is in the first operating mode. In this manner, the value of the en_osc_mode signal received by logic circuit 606 is at a logic low value (e.g., en_osc_mode = 0). For example, Figure 1 The second single-shot circuit 108b, the third single-shot circuit 108c, the fourth single-shot circuit 108d, and the fifth single-shot circuit 108e operate in the first operating mode.

[0139] exist Figure 8 In the illustrated example, prior to time 812 in instance six, each of the following curves—instance seven (802), instance eight (804), instance nine (806), instance ten (808), and instance eleven (810)—was at a logical low value. At time 812 in instance six, instance seven (802) transitioned from a logical low to a logical high value, instance eight (804) transitioned from a logical low to a logical high value, instance nine (806) remained at a logical low value, instance ten (808) remained at a logical low value, and instance eleven (810) remained at a logical low value.

[0140] exist Figure 8 In the illustrated example, between the sixth time 812 and the seventh time 814, the seventh curve 802 transitions from a logic high value to a logic low value, the eighth curve 804 remains at a logic high value, the ninth curve 806 remains at a logic low value, the tenth curve 808 remains at a logic low value, and the eleventh curve 810 remains at a logic low value. In this example, the difference between the seventh time 814 and the sixth time 812 is... Figure 6 The time delay associated with the instance delay circuit 610.

[0141] exist Figure 8 In the illustrated example, at the seventh time 814, the seventh curve 802 remains at a logic low value, the eighth curve 804 remains at a logic high value, the ninth curve 806 transitions from a logic low value to a logic high value, the tenth curve 808 remains at a logic low value, and the eleventh curve 810 remains at a logic low value.

[0142] exist Figure 8In the illustrated example, between the seventh time 814 and the eighth time 816, curve 802 in example seven remains at a logic low value, curve 804 in example eight remains at a logic high value, curve 806 in example nine remains at a logic high value, curve 808 in example ten remains at a logic low value, and curve 810 in example eleven remains at a logic low value. In this example, the difference between the eighth time 816 and the seventh time 814 is... Figure 6 The time delay associated with the example adaptive delay circuit 622.

[0143] exist Figure 8 In the illustrated example, at time 816 of example eight, curve 802 of example seven remains at a logic low value, curve 804 of example eight transitions from a logic high value to a logic low value, curve 806 of example nine remains at a logic high value, curve 808 of example ten transitions from a logic low value to a logic high value, and curve 810 of example eleven transitions from a logic low value to a logic high value.

[0144] exist Figure 8 In the illustrated example, between the ninth time 818 and the eighth time 816, the seventh curve 802 remains at a logic low value, the eighth curve 804 remains at a logic low value, the ninth curve 806 remains at a logic high value, the tenth curve 808 transitions from a logic high value to a logic low value, and the eleventh curve 810 remains at a logic high value.

[0145] exist Figure 8 In the illustrated example, at the ninth time 818, the seventh curve 802 remains at a logic low value, the eighth curve 804 remains at a logic low value, the ninth curve 806 transitions from a logic high value to a logic low value, the tenth curve 808 remains at a logic low value, and the eleventh curve 810 transitions from a logic high value to a logic low value.

[0146] exist Figure 8In the illustrated example, the instance logic high value on instance seventh curve 802 (e.g., trigger signal) at sixth time 812 sets the output of logic circuit 606 to a logic high value. The value of logic circuit 606 remains at the logic high value until a reset input (e.g., reset_pulse signal) receives the logic high value. The duration of adaptive delay circuit 622 sets the duration of the pulse (e.g., the duration of the logic high value) on instance eighth curve 804. More specifically, because the number of delay elements used to generate the duration of delay circuit 610 is fixed, the duration of adaptive delay circuit 622 sets the pulse duration based on the number of selected delay circuits (e.g., delay circuit 704, delay circuit 710, delay circuit 716, etc.). In this way, the time (e.g., duration) difference between eighth time 816 and sixth time 812 is set by adaptive delay circuit 622. Furthermore, although the durations of the delay elements in both delay circuit 610 and adaptive delay circuit 622 vary depending on operating conditions, because adaptive delay circuit 622 is adjustable and the number of delay elements can be selected based on the trim_synced signal, the difference between the eighth time 816 and the sixth time 812 is the sum of the duration of delay circuit 612 and the duration of adaptive delay circuit 622. When the output of adaptive delay circuit 622 transitions to a logic high value (e.g., at the eighth time 816), the output of logic circuit 606 is reset to a logic low value through the output of logic gate 626 (e.g., the reset_pulse signal). In the illustrated example, the eighth time 816 represents the reset of logic circuit 606 when the eleventh curve 810 transitions to a logic high value.

[0147] Figure 9 It is an explanation and Figure 6 Timing diagrams 900 are used to associate the second operating mode of one of the single-transmitter circuits 108a, 108b, 108c, 108d, and 108e with various example signals for oscillator operation. Example timing diagrams 900 include example curve 802 (seventh example), example curve 804 (eighth example), example curve 810 (eleventh example), example curve 902 (twelfth example), example time 904 (T9), and example time 906 (T11). 10 ), Example 12 Time 908 (T) 11 ) and Example Thirteen Time 910 (T 12 Example timing diagram 900 includes an amplitude axis and a time axis.

[0148] exist Figure 9 In the illustrated example, curve 802 in example seven represents the result of... Figure 6 The trigger signal received by the instance logic gate 604. Instance eight curve 804 represents the signal received by... Figure 6The single_shot signal is generated by logic circuit 606. Example 11, curve 810, represents the signal generated by... Figure 6 The reset_pulse signal generated by the example logic gate 626. Example 12, curve 902, represents... Figure 6 The output of logic gate 604 (e.g., the set_latch signal).

[0149] exist Figure 9 In the illustrated example, Figure 6 One of the instance single-transmitter circuits 108a, 108b, 108c, 108d, and 108e is in the second operating mode. In this manner, the value of the en_osc_mode signal received by logic circuit 606 is at a logic high value (e.g., en_osc_mode = 1). For example, Figure 1 The first single-transmitter circuit 108a operates in the second operating mode.

[0150] exist Figure 9 In the illustrated example, prior to the tenth time point 904, each of the following instances—the seventh curve 802, the eighth curve 804, the eleventh curve 810, and the twelfth curve 902—is at a logical low value. At the tenth time point 904, the seventh curve 802 transitions from a logical low value to a logical high value, the eighth curve 804 transitions from a logical low value to a logical high value, the eleventh curve 810 remains at a logical low value, and the twelfth curve 902 transitions from a logical low value to a logical high value.

[0151] exist Figure 9 In the illustrated example, between time 904 (tenth time) and time 906 (eleventh time), curve 802 in example seven remains at a logical high value, curve 804 in example eight remains at a logical high value, curve 810 in example eleven remains at a logical low value, and curve 902 in example twelfth remains at a logical high value. Based on Figure 6 The duration of the adaptive delay circuit 622 determines the difference between the eleventh time 906 and the tenth time 904. More specifically, because the duration of the delay circuit 610 is fixed, the duration of the adaptive delay circuit 622 is set based on the number of selected delay circuits (e.g., delay circuit 704, delay circuit 710, delay circuit 716, etc.) to determine the pulse duration. Therefore, the difference between the eleventh time 906 and the tenth time 904 depends on... Figure 6 The duration of the adaptive delay circuit 622.

[0152] exist Figure 9In the illustrated examples, at time 906 (the eleventh time), curve 802 (the seventh example) remains at a logical high value, curve 804 (the eighth example) transitions from a logical high value to a logical low value, curve 810 (the eleventh example) transitions from a logical low value to a logical high value, and curve 902 (the twelfth example) transitions from a logical high value to a logical low value. At time 906 (the eleventh time), Figure 6 The adaptive delay circuit 622 outputs a logic high value, making Figure 6 The logic gate 626 outputs a logic high value (e.g., the reset_pulse signal). A logic high value at the output of logic gate 626 also causes the set_latch signal to transition to a logic low value.

[0153] exist Figure 9 In the illustrated example, between eleventh time 906 and twelfth time 908, curve 802 in example seven remains at a logic high value, curve 804 in example eight remains at a logic low value, curve 810 in example eleven remains at a logic high value and then transitions to a logic low value, and curve 902 in example twelfth time 902 remains at a logic low value. In this example, curves 804 and 902 remain at logic low values ​​because the output of adaptive delay circuit 622 is at a logic high value (e.g., the delay_adapt signal is at a logic high value). In this way, the output of logic gate 604 (e.g., the set_latch signal) remains at a logic low value, causing the output of logic circuit 606 (e.g., the single_shot signal) to remain at a logic low value.

[0154] exist Figure 9 In the illustrated examples, at time 12 (908), curve 802 in example 7 remains at a logic high value, curve 804 in example 8 transitions from a logic low value to a logic high value, curve 810 in example 11 remains at a logic low value, and curve 902 in example 12 transitions from a logic low value to a logic high value. At time 12 (908), Figure 6 The output of the adaptive delay circuit 622 transitions from a logic high value to a logic low value. In this way, the output of logic gate 604 (e.g., the set_latch signal) transitions from a logic low value to a logic high value, causing the output of logic circuit 606 (e.g., the single_shot signal) to transition from a logic low value to a logic high value.

[0155] exist Figure 9 In the illustrated example, between the twelfth time 908 and the thirteenth time 910, curve 802 in example seven remains at a logic high value, while curve 804 in example eight... Figure 6The duration of the adaptive delay circuit 622 and the period defined by the duration of the delay circuit 610 oscillate between logic high and logic low values. Furthermore, between the twelfth time 908 and the thirteenth time 910, the duration of the pulse (e.g., the duration of the logic high value) is... Figure 6 The duration of the adaptive delay circuit 622 and Figure 6 The duration of the delay circuit 610. Furthermore, between the twelfth time 908 and the thirteenth time 910, in... Figure 6 The duration of the adaptive delay circuit 622 and Figure 6 During the duration of the delay circuit 610, the single_shot signal is at a logic low value.

[0156] exist Figure 9 In the example, between the twelfth time 908 and the thirteenth time 910, the eleventh curve 810 is... Figure 6 The duration defined by the delay circuit 610 and the adaptive delay circuit 622 oscillates between logic low and logic high values, and the twelfth curve 902 in example is... Figure 6 The adaptive delay circuit 622 oscillates between logic high and logic low values ​​at a period defined by twice the duration of its duration. In the example, between the twelfth time 908 and the thirteenth time 910, based on the... Figure 6 The trim_synced signal output by logic circuit 616 is used to adjust the duration of adaptive delay circuit 622.

[0157] exist Figure 9 In the illustrated example, at time 13 (910), curve 802 in example 7 transitions from a logic high value to a logic low value, curve 804 in example 8 remains at a logic high value, curve 810 in example 11 remains at a logic low value, and curve 902 in example 12 transitions from a logic high value to a logic low value. At time 13 (910), the reference_pulse signal and the adaptation_pulse signal are at a logic low value, causing the trigger signal to transition from a logic high value to a logic low value.

[0158] exist Figure 9 In the illustrated example, after the thirteenth time 910, the seventh example curve 802 remains at a logic low value, the eighth example curve 804 remains at a logic high value until the eleventh example curve 810 transitions from a logic low value to a logic high value, the eleventh example curve 810 remains at a logic low value until the output of the adaptive delay circuit 622 (e.g., the adapt_delay signal) transitions from a logic low value to a logic high value, and the twelfth example curve 902 remains at a logic low value.

[0159] Figure 10 It is an explanation and Figure 1 The timing diagram 1000 shows various instance signals associated with the core control circuit 102 of example 5. Example timing diagram 1000 includes example thirteenth curve 1002, example fourteenth curve 1004, example fifteenth curve 1006, example sixteenth curve 1008, example seventeenth curve 1010, example eighteenth curve 1012, example nineteenth curve 1014, example twentieth curve 1016, example twenty-first curve 1018, example twenty-second curve 1020, example twenty-third curve 1022, example twenty-fourth curve 1024, example twenty-fifth curve 1026, and example fourteenth time 1028 (T). 13 ), Example 15, time 1030 (T) 14 ), Example 16, time 1032 (T) 15 ), and Example 17, Time 1034 (T) 16 ).

[0160] exist Figure 10 In the illustrated example, curve 1002 in example thirteen represents... Figure 5A and 5B The start_adaptation signal, represented by curve 1004 in example fourteen. Figure 5A and 5B The start_adapt_cycle signal, example curve 1006 of the fifteenth example, is composed of... Figure 5A and 5B The sequencer 504 determines the value for counting, as shown in the sixteenth curve 1008 in the example. Figure 5A and 5B The reference_pulse signal, in example, curve 1010 in the seventeenth instance, represents the signal generated by... Figure 5A and 5B The count value determined by the single-shot counter 552, as shown in the eighteenth curve 1012 in the example. Figure 5A and 5B The adaptation_pulse signal, represented by curve 1014 in example nineteen. Figure 5A and 5B The ss_too_long signal, in example, curve 1016 in the twentieth case represents the signal generated by... Figure 5A and 5B The direction_changed_twice signal generated by the ready detector 542 is represented by curve 1018 in example twenty-one. Figure 5A and 5B The ref_cntr_done signal, represented by curve 1020 in example twenty-two. Figure 5A and 5B The adaptation_ready signal, represented by curve 1022 in example twenty-three. Figure 5A and 5B The trim_adaptation signal, represented by curve 1024 in example twenty-four. Figure 5A and 5B The fine-tuning signal, and curve 1026 in example twenty-five represents Figure 5A and 5B The allow_trim_sync signal.

[0161] exist Figure 10 In the illustrated example, prior to the fourteenth time 1028, each of the following examples—curve 13 (1002), curve 14 (1004), curve 15 (1006), curve 16 (1008), curve 17 (1010), curve 18 (1012), curve 19 (1014), curve 20 (1016), curve 21 (1018), and curve 22 (1020)—is at a logic low value. Prior to the fourteenth time 1028, curve 23 (1022) is at a binary count value larger than the count value associated with the single-shot counter 552 (e.g., a binary count value representing decimal 18), curve 24 (1024) is at a binary value associated with a previous iteration of the core control circuitry 102, and curve 25 (1026) is at a logic high value.

[0162] exist Figure 10 In the illustrated example, at time 1028 (the fourteenth time), the thirteenth curve 1002 transitions from a logic low to a logic high. For example, at time 1028 (the fourteenth time), Figure 5A and 5B The startup detector 502 detects by Figure 5A and 5B The pulses generated by the refresh pulse generator 500. In this example, Figure 5A and 5B The start detector 502 generates a pulse as the start_adaptation signal. In this example, at the fourteenth time 1028, the fourteenth curve 1004 transitions from a logic low value to a logic high value. For example, the instance sequencer 504 generates a pulse at the fourteenth time 1028 as the start_adapt_cycle signal to initiate the adaptive cycle. In this example, the sequencer 504 controls the reference pulse generator 506, which generates the reference_pulse signal.

[0163] exist Figure 10In the illustrated example, after the fourteenth time 1028, the eighteenth curve 1012 and the sixteenth curve 1008 oscillate between logic high and logic low values ​​with periods determined by the example adaptation pulse generator 544 and the example reference pulse generator 506, respectively. For example, the example adaptation pulse generator 544 generates the adaptation_pulse signal based on a reference pulse (e.g., the reference_pulse signal), the clk_single_shot signal, and a count value associated with the single-shot counter 552. Additionally, in this example, the reference pulse generator 506 generates the reference_pulse signal based on the start_adapt_cycle signal and the ref_pulse_done signal.

[0164] exist Figure 10 In the illustrated example, the time interval between the fourteenth time 1028 and the fifteenth time 1030 represents the reference pulse generator 506 and the adaptation pulse generator 544, which respectively generate the reference_pulse signal and the adaptation_pulse signal. In this example, the time interval between the fourteenth time 1028 and the fifteenth time 1030 represents the pulse comparator 514, which compares the adaptation pulse (e.g., the adaptation_pulse signal) and the reference pulse (e.g., the reference_pulse signal) and adjusts... Figure 5A and 5B The count value of counter 526. Figure 10 In the illustrated example, the adjustment of counter 526 is represented by the decrease in the value of curve 1022 (twenty-third). In this example, when the duration of the adaptation_pulse signal is greater than the duration of the reference_pulse signal, pulse comparator 514 decrements the count value of counter 526. The count value of counter 526 (e.g., the trim_adaptation signal) adjusts the duration of the clk_single_shot signal, affecting the amount of time elapsed while the single-shot counter 552 counts a predetermined number of clock cycles.

[0165] exist Figure 10In the illustrated example, between the fifteenth time 1030 and the sixteenth time 1032, the duration of the adaptation_pulse signal on the eighteenth curve 1012 oscillates between a duration shorter than and longer than that of the reference_pulse signal on the sixteenth curve 1008. For example, at the fifteenth time 1030, the instance pulse comparator 514 outputs a logic high value on the ss_too_long signal to the instance counter 526. In this example, when the counter 526 next updates its count value (e.g., at the next rising edge of the ref_cntr_done signal), the output of the instance pulse comparator 514 is a logic low value.

[0166] exist Figure 10 In the illustrated example, at time 1032, instance 20 curve 1016 transitions from a logic low value to a logic high value. For example, at time 1032, ready detector 542 detects a direction change or a sequence of decreasing and then increasing values ​​on instance 23 curve 1022 and outputs a logic high value on the direction_changed_twice signal. In this example, the direction_changed_twices signal is internal to instance ready detector 542 and causes instance ready detector 542 to monitor the next logic high value on the ss_too_long signal. Monitoring the next logic high value corresponds to an elapsed delay time to allow the duration of the adaptation_pulse signal on the eighteenth curve 1012 to be greater than the duration of the reference_pulse signal on the sixteenth curve 1008 by a duration associated with one of the delay circuits in adaptive delay circuit 622 (e.g., delay circuit 704, delay circuit 710, delay circuit 716, etc.). A trigger event is detected after an alternating sequence of logical values ​​on the ss_too_long signal is detected, followed by a logical high value on the ss_too_long signal.

[0167] exist Figure 10 In the illustrated example, at time 1034, the twenty-second example curve 1020 transitions from a logic low value to a logic high value. At time 1034, the twenty-fourth example curve 1024 transitions from a binary value associated with a previous iteration of the core control circuit 102 to a binary value associated with the current iteration of the core control circuit 102 (e.g., a binary value corresponding to the decimal value 12).

[0168] exist Figure 10 In the illustrated example, between the fourteenth time 1028 and the seventeenth time 1034, the twenty-fifth curve 1026 is... Figure 5A and 5B The instance sequencer 504 determines a period that oscillates between logic high and logic low values. For example, instance sequencer 504 outputs the allow_trim_sync signal on instance twenty-fifth curve 1026. In this way, instance sequencer 504 allows fine-tuning signals to be received by instance second single-transmitter circuit 108b, instance third single-transmitter circuit 108c, instance fourth single-transmitter circuit 108d, and instance fifth single-transmitter circuit 108e. Figure 10 In the illustrated example, after the seventeenth time 1034, the adjustment process continues whenever the activated detector 502 detects a pulse. In this example, this is illustrated as a pulse on the thirteenth curve 1002.

[0169] Figure 11 It is an explanation and Figure 1 The instance state diagram 1100 is associated with the core control circuit 102 of 5. The instance state diagram includes instance first state 1102, instance second state 1104, instance third state 1106, instance fourth state 1108, instance fifth state 1110, instance sixth state 1112 and instance seventh state 1114.

[0170] exist Figure 11 In the illustrated example, when in instance first state 1102, instance single-shot tuner 106 is in instance disabled mode (e.g., power off). Instance first state 1102 includes a first operating condition 1116. The first operating condition 1116 determines whether instance single-shot tuner 106 exits instance first state 1102. In instance first state 1102, logic signals in instance single-shot tuner 106 are logic low values. The first operating condition 1116 is satisfied once power is connected to single-shot tuner 106.

[0171] exist Figure 11 In the illustrated example, in response to power being connected to the single-shot tuner 106, the single-shot tuner 106 enters the second instance state 1104 with the second instance operating condition 1118. In the second instance state 1104, the single-shot tuner 106 begins an adaptation cycle and generates a reference_pulse signal and an adaptation_pulse signal. More specifically, in the second instance state 1104, the instance reference pulse generator 506 generates the reference_pulse signal, and the adaptation pulse generator 544 generates the adaptation_pulse signal. When both the reference_pulse signal and the adaptation_pulse signal have been generated, the second instance operating condition 1118 is satisfied.

[0172] exist Figure 11In the illustrated example, in response to the generation of the reference_pulse signal and the adaptation_pulse signal, the single-shot fine-tuner 106 enters the third state 1106 of the example with the third operating condition 1120 of the example. In the third state 1106 of the example, the single-shot fine-tuner 106 compares the duration of the adaptation_pulse signal with the duration of the reference_pulse signal. More specifically, in the third state 1106 of the example, the pulse comparator 514 compares the duration of the adaptation_pulse signal with the duration of the reference_pulse signal. The third operating condition 1120 of the example is satisfied when the single-shot fine-tuner 106 generates the ss_too_long signal.

[0173] exist Figure 11 In the illustrated example, in response to the ss_too_long signal, the single-shot tuner 106 enters the fourth state 1108, which includes the fourth operating condition 1122. In the fourth state 1108, the single-shot tuner 106 determines a new count value for the counter 526. More specifically, in the fourth state 1108, the instance pulse comparator 514 adjusts the count value of the counter 526 by incrementing or decrementing it based on the ss_too_long signal. The output of the counter 526 has been adjusted when the ref_cntr_done signal transitions from a logic low to a logic high value. The output of the counter 526 (e.g., the trim_adaptation signal) is updated with the adjusted count value at the next rising edge of the clk_sys signal. After adjusting the count value of the counter 526 (e.g., at the rising edge of the ref_cntr_done signal), the fourth operating condition 1122 is satisfied.

[0174] exist Figure 11 In the illustrated example, in response to adjusting the count value of the counter 526, the single-shot tuner 106 enters instance fifth state 1110, which has instance fifth operating condition 1124 and instance sixth operating condition 1126. In instance fifth state 1110, the single-shot tuner 106 determines whether a trigger event has been detected. More specifically, in instance fifth state 1110, the ready detector 542 determines whether a trigger event has been detected. When the single-shot tuner 106 detects a trigger event, the sixth operating condition 1126 has been satisfied. Instance fifth operating condition 1124 is satisfied when the start_adapt_cycle signal transitions from a logic low value to a logic high value. In response to a rising edge on the start_adapt_cycle signal, instance single-shot tuner 106 enters instance second state 1104.

[0175] exist Figure 11In the illustrated example, in response to the detection of a trigger event, the single-shot tuner 106 enters the sixth state 1112 with the seventh operating condition 1128. In the illustrated example, after satisfying the fifth operating condition 1124, the single-shot tuner 106 executes the second state 1104. The single-shot tuner 106 executes the sixth state 1112 after satisfying the sixth operating condition 1126. In the sixth state 1112, the single-shot tuner 106 transmits a tuning signal to one or more single-shot circuits. When the single-shot tuner 106 transmits the tuning signal to one or more single-shot circuits, the single-shot tuner 106 generates an adaptation_ready signal. When the single-shot tuner 106 generates the adaptation_ready signal, the seventh operating condition 1128 has been satisfied.

[0176] exist Figure 11 In the illustrated example, in response to the detection of the adaptation_ready signal, the instance single-shot tuner 106 enters instance seventh state 1114, which includes instance eighth operating condition 1130. In instance seventh state 1114, the single-shot tuner 106 monitors the refresh pulse. More specifically, in instance seventh state 1114, the instance activation detector 502 monitors the instance refresh pulse generated by the refresh pulse generator 500. When a refresh pulse is detected, instance eighth operating condition 1130 is satisfied, and the single-shot tuner 106 enters instance second state 1104.

[0177] exist Figure 11In the illustrated example, each of the following states—second state 1104, third state 1106, fourth state 1108, fifth state 1110, sixth state 1112, and seventh state 1114—contains the following operation conditions: ninth operation condition 1132, tenth operation condition 1134, eleventh operation condition 1136, twelfth operation condition 1138, thirteenth operation condition 1140, and fourteenth operation condition 1142, respectively. In this example, each of the following operation conditions determines whether the instance single-shot fine-tuner 106 returns to the first state 1102 from the second state 1104, third state 1106, fourth state 1108, fifth state 1110, sixth state 1112, and seventh state 1114, respectively. When the single-shot fine-tuner 106 is disconnected from the power supply, it satisfies each of the ninth operating condition 1132, the tenth operating condition 1134, the eleventh operating condition 1136, the twelfth operating condition 1138, the thirteenth operating condition 1140, and the fourteenth operating condition 1142, and the single-shot fine-tuner 106 returns to the first state 1102 from the second state 1104, the third state 1106, the fourth state 1108, the fifth state 1110, the sixth state 1112, and the seventh state 1114, respectively.

[0178] Although Figure 5A and 5B Implementation instructions Figure 1 The example of the core control circuit 106 is shown in the example mode, but Figure 5A and 5B One or more of the elements, processes, and / or devices described herein may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, one or more of the instances of refresh pulse generator 500, instance start detector 502, instance sequencer 504, instance reference pulse generator 506, instance pulse comparator 514, instance counter 526, instance fine-tuning distributor 536, instance ready detector 542, instance adapting pulse generator 544, instance single-shot counter 552, and single-shot circuits 108a, 108b, 108c, 108d, 108e, and / or more generally... Figure 5A and 5BThe instance core control circuit 102 can be implemented in hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, the instance refresh pulse generator 500, instance start detector 502, instance sequencer 504, instance reference pulse generator 506, instance pulse comparator 514, instance counter 526, instance fine-tuning distributor 536, instance ready detector 542, instance adaptation pulse generator 544, instance single-shot counter 552, and any of the instances of single-shot circuits 108a, 108b, 108c, 108d, 108e, and / or more generally, any of the instance core control circuit 102, can be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs). When reading any of the device or system claims of this patent to cover purely software and / or firmware implementations, at least one of the instances of refresh pulse generator 500, instance start detector 502, instance sequencer 504, instance reference pulse generator 506, instance pulse comparator 514, instance counter 526, instance fine-tuning distributor 536, instance ready detector 542, instance adapting pulse generator 544, instance single-shot counter 552, and single-shot circuits 108a, 108b, 108c, 108d, 108e is hereby expressly defined as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, digital versatile disk (DVD), optical disc (CD), Blu-ray disc, etc., comprising software and / or firmware. Furthermore, Figure 5A and 5B The core control circuit 102 of the example may include, in addition to or replace, Figure 5A and 5B It may include one or more elements, processes and / or devices other than those described herein, and / or may include any or more of the elements, processes and devices described herein. As used herein, the phrase “in communication” (including variations thereof) covers direct communication and / or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, scheduled intervals, irregular intervals and / or single events.

[0179] exist Figure 12A and 12B The text illustrates representative examples of hardware logic, machine-readable instructions, state machines implemented in the hardware, and / or any combination thereof used for implementation. Figure 5A and 5BA flowchart of the core control circuit 102. Machine-readable instructions may be one or more executable programs or portions of executable programs that are executed by a computer processor. The program may be embodied in software stored on a non-transitory computer-readable storage medium (e.g., CD-ROM, floppy disk, hard disk drive, DVD, Blu-ray disc, or memory associated with the processor); however, the entire program and / or portions thereof may alternatively be executed by a device other than the processor and / or embodied in firmware or dedicated hardware. Furthermore, although the example program is for reference... Figure 12A and 12B The flowcharts described herein may be used, but other methods of implementing the core control circuit 102 of the example implementation may be used instead. For example, the execution order of the blocks may be changed, and / or some blocks in the described blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks in the flowcharts may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers, logic circuits, etc.) constructed to perform the corresponding operations without the need for software or firmware execution.

[0180] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, and packetized format. The machine-readable instructions described herein can be stored as data (e.g., portions of instructions, code, representations of code, etc.) that can be used to create, manufacture, and / or generate machine-readable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). Machine-readable instructions may require one or more of the following to make them directly readable and / or executable by a computing device and / or another machine: installation, modification, adaptation, upgrade, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, and reassignment. For example, machine-readable instructions can be stored in multiple portions that are individually compressed, encrypted, and stored on separate computing devices, wherein these portions, when decrypted, decompressed, and combined, form a set of executable instructions that implement, for example, the programs described herein.

[0181] In another instance, machine-readable instructions may be stored in a state that is readable by a computer, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the instructions on a specific computing device or other device. In yet another instance, the machine-readable instructions and / or their corresponding programs may need to be configured (e.g., via storage setup, data input, recording of network addresses, etc.) before they can be executed wholly or partially. Therefore, the disclosed machine-readable instructions and / or their corresponding programs are intended to cover such machine-readable instructions and / or programs, regardless of their specific format or state when stored or otherwise rested or transferred.

[0182] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0183] As mentioned above, Figure 12A and 12B The instance process can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on a non-transitory computer and / or machine-readable medium, such as a hard disk drive, flash memory, read-only memory, optical disk, digital universal disk, cache, random access memory, and / or any other storage device or storage disk, wherein information can be stored for any duration (e.g., long time period, permanent, transient, temporary buffer, and / or information cache). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable storage device and / or storage disk and excludes propagation signals and transmission media.

[0184] As used herein, “comprise” and “including” (and all forms and tenses thereof) are open-ended terms. Therefore, whenever a claim uses any form of “comprise” or “including” (e.g., encompass / comprising, include / including, having, etc.) as a preamble or within any kind of claim statement, it should be understood that additional elements, items, etc., may be present without falling outside the scope of the corresponding claim or statement. As used herein, when the phrase “at least” is used as a transitional term, for example, in the preamble of a claim, it is open-ended in the same way as the terms “comprise” and “including” are open-ended. For example, when used in the form of, for example, A, B, and / or C, the term “and / or” refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, and (7) A, B, and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to an implementation comprising (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to an implementation comprising (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the performance / execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to refer to an implementation comprising (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance / execution of processes, instructions, actions, activities and / or steps, the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B and (3) any of at least one A and at least one B.

[0185] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude plurals. As used herein, the term "a" or "an" entity refers to one or more of the stated entities. The terms "a", "one or more", and "at least one" are used interchangeably herein. Furthermore, although individually listed, multiple components, elements, or method actions may be implemented by, for example, a single unit or processor. Additionally, although individual features may be included in different instances or claims, these may be combined, and combinations of features not implied in different instances or claims are not feasible and / or disadvantageous.

[0186] Figure 12A and 12B This is a flowchart illustrating a process executable by machine-readable instructions, which can be executed to carry out... Figure 1 And the core control circuit 102 of 5. Figure 12A and 12B Program 1200 begins at box 1202, where Figure 5A and 5B The refresh pulse generator 500 generates a refresh pulse. In block 1204, the instance start detector 502 determines whether a refresh pulse has been detected. If the start detector 502 does not detect a refresh pulse (block 1204: No), program 1200 continues to monitor the instance refresh pulse generator 500. If the start detector 502 does detect a refresh pulse (block 1204: Yes), program 1200 proceeds to block 1206. In block 1206, the reference pulse generator 506 generates a reference_pulse signal based on the start_adapt_cycle signal and the ref_pulse_done signal generated by the sequencer 504.

[0187] exist Figure 12A and 12B In the illustrated example, at block 1208, sequencer 504 starts a reference counter. For example, at block 1208, sequencer 504 counts the number of clock cycles on the CLK_SYS signal. After block 1208, program 1200 proceeds to blocks 1210 and 1214. At block 1210, sequencer 504 determines whether the number of clock cycles on the CLK_SYS signal has reached a first count value associated with the duration of the reference_pulse signal. If sequencer 504 determines that the number of clock cycles on the CLK_SYS signal has reached the first count value (block 1210: Yes), program 1200 proceeds to block 1224. If sequencer 504 determines that the number of clock cycles on the CLK_SYS signal has not reached the first count value (block 1210: No), program 1200 proceeds to block 1212, where sequencer 504 continues to count the number of clock cycles on the CLK_SYS signal. After box 1212, program 1200 proceeds to box 1210.

[0188] exist Figure 12A and 12BIn the illustrated example, in block 1214, the first single-shot circuit 108a generates a single-shot clock (e.g., the clk_single_shot signal). For example, in block 1214, the first single-shot circuit 108a generates a single-shot clock based on the adaptive delay circuit 622. In block 1216, the adaptation pulse generator 544 generates an adaptation_pulse signal based on a control signal from the single-shot counter 552. In block 1218, the adaptation counter is started. For example, in block 1218, the single-shot counter 552 counts the number of clock cycles on the clk_single_shot signal.

[0189] exist Figure 12A and 12B In the illustrated example, at block 1220, instance single-shot counter 552 determines whether the number of clock cycles on the clk_single_shot signal has reached a second count value associated with the duration of the adaptation_pulse signal. If single-shot counter 552 determines that the number of clock cycles on the clk_single_shot signal has reached the second count value (block 1220: Yes), program 1200 proceeds to block 1224. If single-shot counter 552 determines that the number of clock cycles on the clk_single_shot signal has not reached the second count value (block 1220: No), program 1200 proceeds to block 1222, where single-shot counter 552 continues to count the number of clock cycles on the clk_single_shot signal.

[0190] exist Figure 12A and 12B In the illustrated example, in block 1224, instance pulse comparator 514 compares the adaptation_pulse signal and the reference_pulse signal. In block 1226, instance pulse comparator 514 determines whether the duration of the adaptation_pulse signal exceeds the duration of the reference_pulse signal. If instance pulse comparator 514 determines that the duration of the adaptation_pulse signal exceeds the duration of the reference_pulse signal (block 1226: Yes), program 1200 proceeds to block 1228, where instance pulse comparator 514 counts by decrementing the count value of counter 526. After block 1228, program 1200 proceeds to block 1232. If instance pulse comparator 514 determines that the duration of the adaptation_pulse signal does not exceed the duration of the reference_pulse signal (block 1226: No), program 1200 proceeds to block 1230.

[0191] exist Figure 12A and12B In the illustrated example, in box 1230, the example pulse comparator 514 adjusts the count value by incrementing the count value of the counter 526.

[0192] exist Figure 12A and 12B In the illustrated example, in block 1232, instance-ready detector 542 determines whether a trigger event has been detected. For example, in block 1234, instance-ready detector 542 determines whether a logic high value has occurred after an alternating sequence of logic values ​​on the ss_too_long signal. If instance-ready detector 542 determines that a trigger event has been detected (block 1232: Yes), program 1200 proceeds to block 1234. If instance-ready detector 542 determines that no trigger event has been detected (block 1232: No), program 1200 proceeds to block 1206, where reference pulse generator 506 generates the reference_pulse signal.

[0193] exist Figure 12A and 12B In the illustrated example, at block 1234, in response to a trigger event, the readiness detector 542 sets the adaptation_ready signal to a logic high value, causing the trimmer distributor 536 to transmit trimming signals to one or more single-shot circuits operating in the first operating mode. At block 1236, the instance refresh pulse generator 500 determines whether to continue operation. For example, a condition that could cause the instance refresh pulse generator 500 to determine not to continue operation is that the power supply is disconnected from the core control circuitry 102. If the instance refresh pulse generator 500 determines to continue operation (block 1236: Yes), program 1200 proceeds to block 1202, where the instance refresh pulse generator 500 generates a refresh pulse signal. If the instance refresh pulse generator 500 determines not to continue operation (block 1236: No), program 1200 terminates.

[0194] As can be understood from the foregoing, examples of methods, apparatus, and articles of manufacture have been disclosed for adjusting the duration of a single-shot signal to blank the sensed signal in a power converter. The adjusted single-shot signal allows the single-shot circuitry to precisely bypass the sensed signal in the power converter. This adjusted single-shot signal is advantageous to the load. For example, an improperly adjusted blanking period (e.g., too short or too long) can lead to incorrect signal sensing, output voltage disturbances, limited output current capability, damage to the power converter, erroneous interruption signals disrupting power delivery to the load, duty cycle limitations, switching frequency limitations, higher ripple voltage on the output voltage, and additional noise in the control system. For example, in a RADAR subsystem in an automotive system, a very high switching frequency is used in the power converter to supply power to the RADAR subsystem to generate a RADAR signal. In this example, if the input voltage source has a low ripple voltage, the RADAR subsystem operates more advantageously for the user. Advantageously, the adjusted single-shot signal reduces the ripple voltage on the power converter output. Furthermore, if the input switching frequency is outside the normal radio bandwidth (e.g., AM frequencies, FM frequencies, etc.), the instance RADAR subsystem is more advantageous for the user to operate. In the case of an improperly tuned single-transmission signal, a sufficiently high switching frequency cannot be achieved in the RADAR subsystem; however, in the case of a tuned single-transmission signal, a high switching frequency advantageous to the RADAR subsystem user can be achieved. In addition, a higher switching frequency allows for smaller inductor values ​​(e.g., inductor values ​​<220nH), which are physically smaller than other inductors used in power converters. Smaller values ​​improve load transient performance, and smaller size reduces the inductor's footprint on the PCB or other circuitry. The disclosed methods, apparatus, and articles of manufacture improve the efficiency of using computing devices by reducing computational waste associated with erroneous signal sensing, increasing the operating range of the power converter, and improving the efficiency of the power converter. The disclosed methods, apparatus, and articles of manufacture are accordingly one or more improvements to computer operation.

[0195] Although specific examples of methods, apparatus, and articles of manufacture have been disclosed herein, the scope of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture that fairly fall within the scope of the claims of this patent.

[0196] The appended claims are hereby incorporated by reference into the specific embodiments, wherein each claim is an independent embodiment of the invention.

Claims

1. A circuit comprising: A first single-shot circuit has an input and an output, the first single-shot circuit including a first adaptive delay element capable of adjusting a first pulse at the output of the first single-shot circuit in response to a fine-tuning code at the input of the first single-shot circuit. The second single-shot circuit has an input and an output, and the second single-shot circuit includes a second adaptive delay element capable of adjusting the second pulse at the output of the second single-shot circuit in response to the fine-tuning code; A transistor gate control logic having an input coupled to the output of the second single-shot circuit, the gate control logic being able to provide a gate control signal in response to an adjusted second pulse; as well as The fine-tuning circuit includes: A first pulse generator has an output and is capable of generating a reference pulse at the output of the first pulse generator based on a fixed frequency; A second pulse generator has an input and an output, the input of which is coupled to the output of the first single-shot circuit, and the second pulse generator is capable of generating an adjustable pulse at the output of the second pulse generator in response to an adjusted first pulse from the first single-shot circuit. A pulse comparator includes a first input and a second input, and an output, wherein the first input of the pulse comparator is coupled to the output of a first pulse generator, and the second input of the pulse comparator is coupled to the output of a second pulse generator; and A counter comprising a first input and an output, the first input of the counter being coupled to the output of the pulse comparator, the output of the counter being coupled to the input of a first single-shot circuit and the input of a second single-shot circuit, the counter being capable of providing the fine-tuning code in response to a comparison of the reference pulse and the adjustable pulse.

2. The circuit according to claim 1, further comprising: The first pulse generator includes a first input and a second input; The second pulse generator includes a first and a second input and an output, wherein the first input of the second pulse generator is coupled to the output of the first pulse generator, and the second input of the second pulse generator is coupled to the output of the first single-shot circuit; A distributor comprising a first and a second input and an output, wherein the first input of the distributor is coupled to the output of the counter, and the output of the distributor is coupled to the second single-shot circuit; and A ready detector includes a first input and an output, the first input of the ready detector being coupled to the output of the pulse comparator, and the output of the ready detector being coupled to the second input of the distributor; A refresh pulse generator, which includes an output; and A sequencer comprising an input and first and second outputs, wherein the input of the sequencer is coupled to the output of the refresh pulse generator, and the first and second inputs of the first pulse generator are coupled to the first and second outputs of the sequencer.

3. The circuit of claim 2, wherein the pulse comparator further includes a third input, and the sequencer further includes a third output, the third input of the pulse comparator being coupled to the third output of the sequencer.

4. The circuit of claim 2, wherein the counter further includes a second input, and the sequencer further includes a third output, the second input of the counter being coupled to the third output of the sequencer.

5. The circuit of claim 2, wherein the ready detector further includes second and third inputs, and the sequencer includes a third output, the second input of the ready detector being coupled to the first output of the sequencer, and the third input of the ready detector being coupled to the third output of the sequencer.

6. The circuit of claim 2, wherein the counter is a first counter and the second pulse generator includes a third input, the circuit further includes a second counter, the second counter including first and second inputs and first and second outputs, the first input of the second counter being coupled to the output of the first pulse generator, the second input of the second counter being coupled to the output of the first single-shot circuit, the first output of the second counter being coupled to the first input of the second pulse generator, and the second output of the second counter being coupled to the third input of the second pulse generator.

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