Method of forming a micro-electromechanical system structure

Abstract

A pre-cleaning process can be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a microelectromechanical system (MEMS) structure, the duration of the acid-based etch process in the eutectic bonding sequence can be increased relative to the duration of the acid-based etch process when the pre-cleaning process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove oxide from one or more surfaces of the device wafer without using the aforementioned pre-cleaning process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of adhesion between suspended mechanical components of the MEMS structure, and / or reduces the likelihood that the MEMS structure may become defective or inoperable during manufacturing, thereby increasing process yield.

Description

Technical Field

[0001] The disclosed embodiments relate to a method for forming a micro-electromechanical system (MEMS) structure. Background Art

[0002] Integrated circuits can be manufactured on semiconductor wafers. Semiconductor wafers can be stacked or bonded on top of each other to form so-called three-dimensional integrated circuits. Some semiconductor wafers include micro-electromechanical-systems (MEMS), which involve processes for forming miniature structures with dimensions on the order of micrometers (millionths of a meter). Typically, MEMS devices are built on silicon wafers and implemented in thin films of material. MEMS applications include inertial sensor applications, such as motion sensors, accelerometers, and gyroscopes. Other MEMS applications include optical applications, such as movable mirrors, and RF applications, such as radio frequency (RF) switches and resonators. Summary of the Invention

[0003] According to an embodiment of the present invention, a method for forming a micro-electromechanical system structure includes at least the following steps: etching a first wafer using an acidic etchant for a duration to remove oxide from one or more portions of the first wafer, wherein etching the first wafer for the duration enables the oxide to be removed from the one or more portions of the first wafer without an intervening pre-cleaning process between removing a photoresist layer from the first wafer and etching the first wafer using the acidic etchant; and bonding the first wafer to a second wafer after etching the first wafer.

[0004] According to an embodiment of the present invention, a method for forming a MEMS structure includes at least the following steps: forming one or more actuators in a device wafer of the MEMS structure; immersing the device wafer in an acid-based etchant for a duration ranging from about 20 seconds to about 30 seconds to remove oxide from one or more portions of the device wafer after forming the one or more actuators; and bonding the device wafer to a circuitry wafer of the MEMS structure after etching the device wafer.

[0005] According to an embodiment of the present invention, a method for forming a MEMS structure includes at least the following steps: forming a MEMS actuator in a device wafer of the MEMS structure; after forming the MEMS actuator, wet etching the device wafer in an acid-based etchant for a duration to remove oxide from one or more portions of the device wafer without an intervening pre-cleaning process after forming the MEMS actuator; and bonding the device wafer to a complementary metal oxide semiconductor wafer after etching the device wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2 is a diagram of an example microelectromechanical system (MEMS) structure described herein.

[0009] Figures 3A to 3P is formed Figure 2 Figure 4 shows an example of a MEMS structure.

[0010] Figure 4 is a graph showing examples of X-ray photoelectron spectroscopy (XPS) data associated with various processes for forming MEMS structures.

[0011] Figure 5 yes Figure 1 A diagram of an example assembly of one or more devices.

[0012] Figures 6 to 8 is a flow chart of an example process associated with forming a MEMS structure.

[0013] Explanation of Figure Numbers

[0014] 100: Environment;

[0015] 102: Deposition tools / semiconductor processing tools;

[0016] 104: Exposure tools / semiconductor processing tools;

[0017] 106: Developer tools / semiconductor processing tools;

[0018] 108: Etching tools / semiconductor processing tools;

[0019] 110: Bonding tools / semiconductor processing tools;

[0020] 112: Wafer / die transport tool;

[0021] 200: Micro-electromechanical system structure;

[0022] 202: complementary metal oxide semiconductor wafer / second wafer;

[0023] 204: device wafer / first wafer;

[0024] 206: capping wafer;

[0025] 208: Metal pad;

[0026] 210: passivation layer;

[0027] 212: substrate / semiconductor substrate;

[0028] 214: actuator;

[0029] 216: Support structure;

[0030] 218: Germanium layer;

[0031] 220: substrate;

[0032] 222: cavity;

[0033] 300, 400: instances;

[0034] 302, 306, 310: photoresist layer;

[0035] 304, 308, 312: pattern;

[0036] 314: oxide layer;

[0037] 316: Chamber;

[0038] 318: acid-based etchant;

[0039] 320: bath;

[0040] 500: device;

[0041] 510: bus;

[0042] 520: processor;

[0043] 530: memory;

[0044] 540: storage component;

[0045] 550: input component;

[0046] 560: output component;

[0047] 570: Communication components;

[0048] 600, 700, 800: technology;

[0049] 610, 620, 710, 720, 730, 810, 820, 830: frame. DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature is formed on or on a second feature, which may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0051] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0052] A microelectromechanical system (MEMS) structure may include multiple devices or wafers bonded together to form a MEMS structure. For example, a MEMS structure may include a complementary metal oxide semiconductor (CMOS) wafer including circuitry for the MEMS structure; a device wafer including a suspended mechanical component that acts as an actuator for the MEMS structure; and a cavity (or cap) wafer for sealing the mechanical component in a cavity or microchamber. The CMOS wafer, device wafer, and cavity wafer may be bonded together using a eutectic bonding process. Eutectic bonding is a wafer bonding technique whereby the wafer of the MEMS structure is heated to form a eutectic system between the materials of the wafer. The eutectic system typically includes silicon or germanium and a metal such as gold or aluminum. Because the eutectic system is formed, there may be no discernible interface between the bonded materials.

[0053] The eutectic bonding sequence may include a pre-cleaning process to remove oxides (e.g., native oxides such as silicon dioxide) from the surface of the device wafer prior to eutectic bonding, and an acid-based etch process to remove the pre-cleaning layer from the portion of the device wafer that will be bonded to the CMOS wafer. The MEMS structure may be placed in a pre-cleaning chamber to sputter-remove the oxides. The pre-cleaning chamber may include an RF generator and a coiled structure that generates ions for sputtering the native oxides. Although the pre-cleaning process may improve the quality of the eutectic bond between the MEMS structure wafers, the operating frequency of the RF generator may be the same as or close to the resonant frequency of the suspended mechanical components of the device wafers. As a result, the RF generator may cause the suspended mechanical components to vibrate and adhere to the walls of the MEMS structure's cavity, resulting in defects or inoperability of the MEMS structure.

[0054] Some embodiments described herein provide techniques and apparatus for a eutectic bonding sequence having an extended acid-based etching process for removing oxide from a semiconductor device (e.g., a MEMS structure). In some embodiments, a pre-cleaning process may be omitted from the eutectic bonding sequence. In order to remove oxide from one or more surfaces of a device wafer of a MEMS structure, the duration of the acid-based etching process may be increased relative to the duration of the acid-based etching process when a pre-cleaning process is performed. As an example, the duration of the acid-based etching process may be increased from approximately 10 seconds to at least 20 seconds. The increased duration of the acid-based etching process enables the acid-based etching process to remove oxide from one or more surfaces of the device wafer without using the aforementioned pre-cleaning process. An acid-based etchant may be selected to provide a suitable etching rate to remove oxide while minimizing the amount of silicon and / or germanium material etched from the device.

[0055] In this way, the increased duration of the acid-based etch process allows the pre-clean process to be omitted from the eutectic bonding sequence. This reduces the complexity and cycle time of the eutectic bonding sequence because eliminating the pre-clean process results in fewer steps being performed in the eutectic bonding sequence. Furthermore, performing the eutectic bonding sequence without a pre-clean process reduces the risk of adhesion between suspended mechanical components of the MEMS structure. This reduces the likelihood that the MEMS structure may become defective or inoperable during fabrication, which increases process yield.

[0056] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 , environment 100 may include a plurality of semiconductor processing tools and a wafer / die transport tool 112. The plurality of semiconductor processing tools may include a deposition tool (also referred to as a semiconductor processing tool) 102, an exposure tool (also referred to as a semiconductor processing tool) 104, a developer tool (also referred to as a semiconductor processing tool) 106, an etch tool (also referred to as a semiconductor processing tool) 108, a bonding tool (also referred to as a semiconductor processing tool) 110, and / or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing and / or fabrication facility, and / or the like.

[0057] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, example environment 100 includes multiple types of deposition tools 102 .

[0058] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light source, and / or the like), an x-ray source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from the photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0059] Developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from exposure tool 104. In some embodiments, developer tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, developer tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, developer tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0060] The etch tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool 108 may include a wet etch tool, a dry etch tool, and / or the like. In some embodiments, the etch tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etch tool 108 may use plasma etching or plasma-assisted etching (which may involve using an ionized gas to etch one or more portions isotropically or directionally) to etch one or more portions of the substrate.

[0061] Bonding tool 110 is a semiconductor processing tool capable of bonding two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together. For example, bonding tool 110 may include a eutectic bonding tool capable of forming a eutectic bond between the two or more wafers. In these examples, bonding tool 110 may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers.

[0062] The wafer / die transport tool 112 comprises a mobile robot, a robotic arm, a trolley or rail car, and / or another type of device for transporting wafers and / or dies between the semiconductor processing tool 102 and the semiconductor processing tool 110, and / or transporting wafers and / or dies to and from other locations (e.g., wafer racks, storage rooms, and / or the like). In some embodiments, the wafer / die transport tool 112 can be a programmed device to travel a specific path, and / or can operate semi-autonomously or autonomously.

[0063] supply Figure 1 The number and arrangement of the devices shown are provided as one or more examples. Figure 1 There may be additional devices, fewer devices, different devices, or devices arranged differently than those shown. Figure 1 Two or more devices shown in FIG. 1 may be implemented in a single device, or Figure 1 A single device depicted in the environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, one set of devices (eg, one or more devices) of the environment 100 may perform one or more functions described as being performed by another set of devices of the environment 100.

[0064] Figure 2 is a diagram of an example MEMS structure 200 described herein. Figure 2, a MEMS structure 200 may include a CMOS wafer (also referred to as a second wafer) 202, a device wafer (also referred to as a first wafer) 204, and a capping wafer 206. The CMOS wafer 202 may be bonded to the device wafer 204 on a first side of the device wafer 204, and the capping wafer 206 may be bonded to the device wafer 204 on a second side of the device wafer 204 opposite the first side.

[0065] CMOS wafer 202 may be a circuit system wafer including semiconductor components (e.g., transistors, inductors, capacitors, and / or resistors), integrated circuits, and / or interconnect metallization layers including MEMS structure 200. CMOS wafer 202 may include a plurality of metal pads 208 formed of aluminum or another conductive material (e.g., gold). Metal pads 208 may be bonding pads for device wafer 204 and may provide electrical connections to the circuit system and interconnect metallization layers of MEMS structure 200. Passivation layer 210 may be disposed between adjacent metal pads and partially over adjacent metal pads to provide electrical isolation. Passivation layer 210 may be formed of a dielectric material, such as silicon nitride (SiN). x ), silicon carbide (SiC x ) or a mixture thereof, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), or another dielectric material. In some embodiments, the CMOS wafer 202 can include connections to the package or solder pads of the MEMS structure 200.

[0066] The device wafer 204 is formed from a semiconductor substrate (also referred to as a substrate) 212, such as a silicon substrate. One or more actuators 214 can be formed in the device wafer 204, which can function as MEMS actuators for the MEMS structure 200. The one or more actuators 214 can be formed by etching through portions of the substrate 212 to form elongated members that are suspended above the CMOS wafer 202 via lateral connections to one side of the substrate 212 of the device wafer 204. In this manner, the one or more actuators 214 are permitted to be displaced to function as a vibrating mass, elastic string, coil, or other type of actuator for performing functions in sensors, gyroscopes, accelerometers, RF devices, or optical devices.

[0067] The device wafer 204 can be supported on the CMOS wafer 202 by a plurality of support structures 216 formed on the substrate 212. The support structures 216 can serve as supports for the one or more actuators 214, thereby permitting the one or more actuators 214 to be suspended above the CMOS wafer 202. Each support structure 216 can be coated with a respective germanium layer 218, such that a plurality of germanium layers 218 are formed on the substrate 212. The germanium layers 218 can increase the quality and strength of the bond between the CMOS wafer 202 and the device wafer 204. In particular, a eutectic bond can be formed between the germanium layers 218 and the metal pads 208 (e.g., between respective sets of the germanium layers 218 and the metal pads 208).

[0068] The capping wafer 206 may include a substrate 220 formed of a silicon wafer or another type of wafer used in semiconductor processing that is capable of being etched and has the mechanical strength and material composition to form a cavity 222 within the MEMS structure 200. The cavity 222 may be a hermetically sealed micro-chamber in which a vacuum is formed to prevent outgassing and to prevent foreign matter and other contaminants from damaging the one or more actuators 214. The cavity 222 may be formed by the combination of the CMOS wafer 202, the device wafer 204, and the capping wafer 206, which may enclose the one or more actuators 214 in the cavity 222.

[0069] supply Figure 2 The number and arrangement of the structures, layers and / or the like shown in the drawings are examples. Figure 2 The MEMS structure may include additional structures and / or layers, fewer structures and / or layers, different structures and / or layers, or differently arranged structures and / or layers compared to the structures and / or layers depicted in FIG.

[0070] Figures 3A to 3P is formed Figure 2 FIG300 is a diagram of an example of a MEMS structure 200. In some embodiments, one or more semiconductor processing tools 102 to semiconductor processing tools 110 may be combined Figures 3A to 3P One or more of the described techniques and / or processes. In some embodiments, other semiconductor processing tools may be incorporated. Figures 3A to 3P One or more of the described techniques and / or technologies.

[0071] like Figure 3A As shown in FIG, forming a portion of MEMS structure 200 may include forming substrate 212 of device wafer 204. This may include forming a crystalline silicon wafer according to seed crystal or other wafer formation techniques.

[0072] like Figure 3B, a semiconductor processing tool (e.g., deposition tool 102) may form a photoresist layer 302 on a substrate 212. For example, the semiconductor processing tool may form the photoresist layer 302 on the substrate 212 using a spin coating process. In these examples, the substrate 212 may be preheated to remove moisture from the surface of the substrate 212, a primer material may be applied to the surface of the substrate 212 to promote adhesion of the spin-coated material, and the substrate 212 may be cooled to room temperature (e.g., using a cooling plate). The substrate 212 may then be placed on a chuck (e.g., a vacuum chuck) to hold and rotate the substrate 212 while the spin-coated material is deposited onto the surface of the substrate 212. The rotation (or spinning) of the substrate 212 distributes the material on the surface of the substrate 212 and forms the photoresist layer. The substrate 212 may be heated again to remove residual solvent from the photoresist layer.

[0073] like Figure 3C , pattern 304 can be formed in photoresist layer 302. In these examples, a semiconductor processing tool (e.g., exposure tool 104) can expose photoresist layer 302 to a radiation source, such as a UV source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray source, and / or the like. The semiconductor processing tool can expose photoresist layer 302 to the radiation source to transfer pattern 304 from the photomask to photoresist layer 302.

[0074] A semiconductor processing tool (e.g., developer tool 106) may perform a development process comprising one or more techniques to develop pattern 304 in photoresist layer 302. For example, the development process may include rinsing or immersing substrate 212 and photoresist layer 302 in a chemical developer that reacts with photoresist layer 302 on the wafer to form pattern 304. After pattern 304 has been developed, substrate 212 may be rinsed to remove any residual chemical developer and spin-dried.

[0075] like Figure 3D , the substrate 212 may be etched based on the pattern 304 formed in the photoresist layer 302 to form a plurality of support structures 216 for the device wafer 204. For example, a semiconductor processing tool (e.g., the etching tool 108) may perform a wet etching technique (e.g., in which the substrate 212 is exposed to or immersed in a chemical that etches or removes material from the substrate 212 at a specific etch rate), dry etching (e.g., in which material is sputtered from the substrate 212 using plasma), or another type of etching technique.

[0076] like Figure 3EAs shown in FIG, after etching the substrate 212 to form the plurality of support structures 216, the remaining portion of the photoresist layer 302 can be removed from the substrate 212. In some embodiments, a solvent or a chemical stripper is used to remove the remaining portion of the photoresist layer 302 from the substrate 212. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer 302. In these examples, a plasma source is used to form a plasma of oxygen ions or fluorine ions to react with the photoresist material. The reaction between the ions in the plasma and the photoresist material causes the photoresist material to form ash, which is removed using a vacuum pump.

[0077] like Figure 3F , a photoresist layer 306 may be formed on the substrate 212. For example, a semiconductor processing tool (eg, deposition tool 102) may form the photoresist layer 306 on the substrate 212 by performing a spin coating process as described above.

[0078] like Figure 3G , a pattern 308 can be formed in the photoresist layer 306. One or more semiconductor processing tools can form the pattern 308 in the photoresist layer 306 by performing one or more of the techniques described above. For example, the exposure tool 104 can expose portions of the photoresist layer 306 to a radiation source, and the developer tool 106 can develop the exposed or unexposed portions of the photoresist layer 306 by removing the exposed or unexposed portions of the photoresist layer 306 from the substrate 212 using a chemical developer.

[0079] like Figure 3H , a plurality of germanium layers 218 may be deposited onto the substrate 212 based on the pattern 308 formed in the photoresist layer 306. For example, a semiconductor processing tool (e.g., the deposition tool 102) may use a CVD process, a PVD process, an ALD process, or another type of deposition process to deposit the plurality of germanium layers 218 onto the substrate 212. In particular, the semiconductor processing tool may form a respective germanium layer 218 over each of the plurality of support structures 216 of the substrate 212.

[0080] like Figure 3I , the remaining portion of the photoresist layer 306 can be removed from the substrate 212 after the plurality of germanium layers 218 are formed on the plurality of support structures 216. In some implementations, a solvent or a chemical stripper is used to remove the remaining portion of the photoresist layer 306 from the substrate 212. In some implementations, a plasma ashing process is used to remove the remaining portion of the photoresist layer 306 from the substrate 212.

[0081] like Figure 3J, a photoresist layer 310 may be formed on the substrate 212 and the plurality of germanium layers 218. For example, a semiconductor processing tool (e.g., deposition tool 102) may form the photoresist layer 310 on the substrate 212 and the plurality of germanium layers 218 by performing a spin coating process as described above.

[0082] like Figure 3K , a pattern 312 can be formed in the photoresist layer 310. One or more semiconductor processing tools can form the pattern 312 in the photoresist layer 310 by performing one or more of the techniques described above. For example, the exposure tool 104 can expose portions of the photoresist layer 310 to a radiation source, and the developer tool 106 can develop the exposed or unexposed portions of the photoresist layer 310 by removing the exposed or unexposed portions of the photoresist layer 310 from the substrate 212 using a chemical developer.

[0083] like Figure 3L As shown in FIG, the substrate 212 can be etched based on a pattern 312 formed in the photoresist layer 310 to form one or more actuators 214 (e.g., one or more MEMS actuators) of the MEMS structure 200 in the substrate 212. For example, a semiconductor processing tool (e.g., the etching tool 108) can perform a wet etching technique (e.g., in which the substrate 212 is exposed to or immersed in a chemical that etches or removes material from the substrate 212 at a specific etching rate), a dry etching method (e.g., in which material is sputtered from the substrate 212 using plasma), or another type of etching technique. The semiconductor processing tool can etch through the substrate 212 based on the pattern 312 so that the one or more actuators 214 are suspended by a lateral connection to a side of the substrate 212. After etching the substrate 212 to form the one or more actuators 214, the remaining portion of the photoresist layer 310 can be removed from the substrate 212 and the plurality of germanium layers 218. In some embodiments, a solvent or chemical stripper is used to remove the remaining portion of the photoresist layer 302 from the substrate 212. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer 302 from the substrate 212.

[0084] Combine Figures 3M to 3O The process shown and described may be referred to as a eutectic bonding sequence. The eutectic bonding sequence may include various processes for preparing the device wafer 204 to be bonded to the CMOS wafer 202, as well as a eutectic bonding process for bonding the device wafer 204 and the CMOS wafer 202.

[0085] like Figure 3M, an oxide layer 314 may be formed on the device wafer 204 after one or more processes before and / or during the eutectic bonding sequence. For example, after removing the photoresist layer 310, the oxide layer 314 may be formed on the surface of the device wafer 204. The oxide layer 314 may include native oxide formed on the surface of the device wafer 204 due to natural oxidation between the silicon of the substrate 212 and oxygen in the air (e.g., atmospheric oxygen) and oxidation between the germanium of the plurality of germanium layers 218 and oxygen in the air. The oxidation results in the formation of a thin layer of native oxide on the device wafer 204 (e.g., silicon dioxide on the silicon portion of the device wafer 204 and germanium dioxide on the plurality of germanium layers 218).

[0086] like Figure 3M , to remove the oxide layer 314 from one or more portions of the device wafer 204 (e.g., from the substrate 212, from the one or more actuators 214, and / or from the plurality of germanium layers 218), a semiconductor processing tool (e.g., the etching tool 108) may wet etch the device wafer 204. The device wafer 204 may be placed in a chamber 316 of the semiconductor processing tool. The chamber 316 may be filled with an acid-based etchant 318. The device wafer 204 may be placed in a bath of the acid-based etchant 318 in the chamber 316 to remove the oxide layer 314 from one or more portions of the device wafer 204.

[0087] The acid-based etchant 318 may include an acidic chemical compound including a variety of acids, such as nitric acid, acetic acid, and / or phosphoric acid. As an example, the acidic chemical compound of the acid-based etchant 318 may include approximately 4% nitric acid, approximately 19% acetic acid, and approximately 77% phosphoric acid. In some embodiments, the acidic chemical compound of the acid-based etchant 318 may be selected to provide a suitable etch rate for the oxide layer 314 while minimizing or maintaining a suitable etch rate for the germanium layer 218 (e.g., 15 angstroms per second) and the silicon of the substrate 212.

[0088] The device wafer 204 may remain immersed in the bath of the acid-based etchant 318 for a duration to remove the oxide layer 314. The wet etching of the device wafer 204 may be performed after the removal of the photoresist layer 310 and without an intervening pre-cleaning process to remove the oxide layer 314 after the removal of the photoresist layer 310. To compensate for the lack of a pre-cleaning process, the device wafer 204 may remain immersed in the bath of the acid-based etchant 318 for an increased duration to remove the oxide layer 314. The duration may be increased relative to the duration that the device wafer 204 will remain immersed in the bath of the acid-based etchant 318 to remove the pre-cleaning treatment layer that will be formed from the device wafer 204 during the pre-cleaning process. Specifically, the duration that the device wafer 204 remains immersed in the bath of the acid-based etchant 318 may be increased from 10 seconds to at least 20 seconds. In some embodiments, the duration for which the device wafer 204 remains immersed in the bath of the acid-based etchant 318 is in a range from about 20 seconds to about 30 seconds to ensure that the oxide layer 314 can be removed by the acid-based etchant 318 without requiring an intervening pre-cleaning process while avoiding over-etching of the germanium layer 218 and the silicon of the substrate 212.

[0089] like Figure 3N , the device wafer 204 may be rinsed after etching the device wafer 204 to remove any residual acid-based etchant 318 from the device wafer 204. The device wafer 204 may be rinsed in a bath 320 of water (e.g., deionized water), alcohol (e.g., isopropyl alcohol), or a mixture of alcohol and water (alcohol / water). The device wafer 204 is immersed in the bath 320 for another duration to rinse and remove the residual acid-based etchant 318 from the device wafer 204. After rinsing, the device wafer 204 may be dried with a gas, such as nitrogen or another type of gas, to dissipate the water, alcohol, or alcohol / water mixture.

[0090] like Figure 3O, the device wafer 204 and the CMOS wafer 202 may be bonded. A semiconductor processing tool (e.g., bonding tool 110) may bond the device wafer 204 and the CMOS wafer 202 by performing a eutectic bonding process to form a eutectic bond between the plurality of germanium layers 218 of the device wafer 204 and the plurality of metal pads 208 of the CMOS wafer 202. Eutectic bonding may be referred to as low-temperature bonding because the bond between the materials of the germanium layers 218 and the metal pads 208 is formed at a temperature below the melting temperature of the materials of the germanium layers 218 and the metal pads 208. The bonding tool 110 may heat the device wafer 204 and the CMOS wafer 202 so that a eutectic bond is formed between the germanium layers 218 and the metal pads 208. For example, if the metal pads 208 are formed of aluminum material, the bonding tool 110 may heat the device wafer 204 and the CMOS wafer 202 so that the germanium layers 218 and the metal pads 208 are heated to approximately 425 degrees Celsius to form the eutectic bond. In some embodiments, the eutectic bonding process may be combined with an annealing process (eg, where the CMOS wafer 202 and the device wafer 204 are heated to a high temperature of 1100 degrees Celsius or greater) to reduce stress induced by the eutectic bonding process at the bonding interface.

[0091] like Figure 3P , the device wafer 204 and the capping wafer 206 can be bonded (e.g., at a side of the device wafer 204 opposite the bond between the device wafer 204 and the CMOS wafer 202). In some embodiments, a semiconductor processing tool (e.g., bonding tool 110) can form a bond between the device wafer 204 and the capping wafer 206. In some embodiments, the bond between the device wafer 204 and the capping wafer 206 is a silicon-silicon bond. In these examples, the bonding tool 110 can form a silicon-silicon bond using one or more glue layers or bonding layers between the device wafer 204 and the capping wafer 206. In some embodiments, the one or more glue layers include hydrogen-based and / or oxygen-based materials such that a silicon hydroxide bond is formed between the device wafer 204 and the capping wafer 206.

[0092] The eutectic bond between the device wafer 204 and the CMOS wafer 202, and the bond between the device wafer 204 and the capping wafer 206, forms a cavity 222 in which the one or more actuators 214 are hermetically sealed. The cavity 222 permits the one or more actuators 214 to move or actuate freely and prevents foreign matter and other contaminants from damaging the one or more actuators 214.

[0093] As indicated above, provide Figures 3A to 3P As an example. Other examples can be found in relation to Figures 3A to 3P The instances described are different.

[0094] Figure 4 is a graph of an example 400 of X-ray photoelectron spectroscopy (XPS) data associated with multiple processes for forming a MEMS structure. The XPS data shows the atomic percentage of oxide material as a function of depth (in nanometers) in the MEMS structure for a eutectic bonding sequence including a pre-clean process and a baseline acid-based etch duration, a eutectic bonding sequence without a pre-clean process and with a baseline acid-based etch duration, and a eutectic bonding sequence without a pre-clean process and with an extended acid-based etch duration as described herein.

[0095] like Figure 4 As shown in FIG, the depth of oxide on the MEMS structure for a eutectic bonding sequence including a pre-clean process and a baseline acid-based etch duration is approximately 1 nanometer. Removing the pre-clean process while maintaining the baseline acid-based etch duration exhibits an increase in oxide depth up to 3 nanometers or greater. However, increasing the acid-based etch duration to an extended acid-based etch duration while removing the pre-clean process (as described herein) produces an oxide depth similar to the pre-clean process and the baseline acid-based etch duration while providing a less complex eutectic bonding sequence.

[0096] As indicated above, provide Figure 4 As an example. Other examples can be found in relation to Figure 4 The instances described are different.

[0097] Figure 5 is a diagram of example components of device 500. In some embodiments, one or more of semiconductor processing tool 102 to semiconductor processing tool 110 and wafer / die transport tool 112 may include one or more devices 500 and / or one or more components of device 500. Figure 5 As shown in FIG. 5 , the device 500 may include a bus 510 , a processor 520 , a memory 530 , a storage component 540 , an input component 550 , an output component 560 , and a communication component 570 .

[0098] Bus 510 includes components that implement wired and / or wireless communications among the multiple components of device 500. Processor 520 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 520 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 520 includes one or more processors that can be programmed to perform functions. Memory 530 includes random access memory, read-only memory, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory).

[0099] Storage component 540 stores information and / or software related to the operation of device 500. For example, storage component 540 may include a hard drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and / or another type of non-transitory computer-readable medium. Input component 550 enables device 500 to receive input, such as user input and / or sensory input. For example, input component 550 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, an actuator, and / or the like. Output component 560 enables device 500 to provide output, such as via a display, a speaker, and / or one or more light-emitting diodes. Communication component 570 enables device 500 to communicate with other devices, such as via a wired connection and / or a wireless connection. For example, the communication component 570 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, an antenna, and / or the like.

[0100] The device 500 may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 530 and / or storage component 540) may store an instruction set (e.g., one or more instructions, codes, software codes, program codes, and / or the like) for execution by the processor 520. The processor 520 may execute the instruction set to perform one or more processes described herein. In some embodiments, execution of the instruction set by one or more processors 520 causes the one or more processors 520 and / or device 500 to perform one or more processes described herein. In some embodiments, hard-wired circuitry may be used in place of or in combination with instructions to perform one or more processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuitry and software.

[0101] supply Figure 5 The number and arrangement of components shown in FIG are examples. Figure 5 5. Device 500 may include additional components, fewer components, different components, or components arranged differently than those depicted in FIG. Additionally or alternatively, one set of components (e.g., one or more components) of device 500 may perform one or more functions described as being performed by another set of components of device 500.

[0102] Figure 6 is a flow chart of an example process 600 associated with forming a MEMS structure. In some embodiments, Figure 6 One or more process blocks of may be performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tool 102 to the semiconductor processing tool 110 and the wafer / die transport tool 112). Additionally or alternatively, Figure 6 One or more process blocks of may be performed by one or more components of device 500 , such as processor 520 , memory 530 , storage component 540 , input component 550 , output component 560 , and / or communication component 570 .

[0103] like Figure 6, process 600 may include etching the first wafer 204 using an acidic etchant for a duration ranging from about 100 nm to about 100 nm to remove oxide from one or more portions of the first wafer, wherein etching the first wafer for the duration enables the oxide to be removed from the one or more portions of the first wafer without an intervening pre-cleaning process between removing the photoresist layer from the first wafer and etching the first wafer using the acidic etchant (block 610). For example, a semiconductor processing tool (e.g., etching tool 108) may etch the first wafer 204 using an acid-based etchant 318 for a duration to remove the oxide layer 314 from one or more portions of the first wafer 204, as described above. In some embodiments, etching the first wafer 204 for the duration enables the oxide layer 314 to be removed from the one or more portions of the first wafer 204 without an intervening pre-cleaning process between removing the photoresist layer 310 from the first wafer 204 and etching the first wafer 204 using the acid-based etchant 318.

[0104] like Figure 6 , process 600 may include bonding the first wafer to the second wafer after etching the first wafer (block 620). For example, a semiconductor processing tool (e.g., bonding tool 110) may bond the first wafer 204 to the second wafer 202 after etching the first wafer 204, as described above.

[0105] Process 600 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0106] In a first embodiment, the duration is in a range of about 20 seconds to about 30 seconds. In a second embodiment, either alone or in combination with the first embodiment, the first wafer 204 comprises a MEMS device wafer, and the second wafer 202 comprises a MEMS circuit system wafer. In a third embodiment, either alone or in combination with one or more of the first and second embodiments, bonding the first wafer 204 to the second wafer 202 comprises performing eutectic bonding of the first wafer 204 and the second wafer 204.

[0107] In a fourth embodiment, alone or in combination with one or more of the first through third embodiments, the one or more portions of the first wafer 204 include at least one of one or more silicon portions of the first wafer 204 (e.g., substrate 212, one or more actuators 214) or one or more germanium portions of the first wafer 204 (e.g., multiple germanium layers 218). In a fifth embodiment, alone or in combination with one or more of the first through fourth embodiments, the acid-based etchant 318 includes at least one of nitric acid, acetic acid, or phosphoric acid. In a sixth embodiment, alone or in combination with one or more of the first through fifth embodiments, the process 600 includes rinsing the first wafer 204 in an alcohol / water bath 320 for a duration after etching the first wafer 204, and drying the first wafer 204 after rinsing the first wafer 204, wherein bonding the first wafer 204 to the second wafer 202 includes bonding the first wafer 204 to the second wafer 202 after drying the first wafer 204.

[0108] although Figure 6 Multiple example blocks of process 600 are shown, but in some embodiments, Figure 6 The process 600 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner than those depicted in FIG. Additionally or alternatively, two or more of the multiple blocks of the process 600 may be performed in parallel.

[0109] Figure 7 is a flow chart of an example process 700 associated with forming a MEMS structure. In some embodiments, Figure 7 One or more process blocks of may be performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tool 102 to the semiconductor processing tool 110 and the wafer / die transport tool 112). Additionally or alternatively, Figure 7 One or more process blocks of may be performed by one or more components of device 500 , such as processor 520 , memory 530 , storage component 540 , input component 550 , output component 560 , and / or communication component 570 .

[0110] like Figure 7 , process 700 may include forming one or more actuators 214 in a device wafer of the MEMS structure 200 (block 710). For example, a semiconductor processing tool (e.g., deposition tool 102, exposure tool 104, developer tool 106, etch tool 108, and / or another semiconductor processing tool) may form one or more actuators 214 in the device wafer 204 of the MEMS structure 200, as described above.

[0111] like Figure 7As further shown in FIG, process 700 may include immersing the device wafer in an acid-based etchant for a duration in a range of about 20 seconds to about 30 seconds after forming the one or more actuators to remove oxide from one or more portions of the device wafer (block 720). For example, a semiconductor processing tool (e.g., etching tool 108) may immerse the device wafer 204 in an acid-based etchant 318 for a duration in a range of about 20 seconds to about 30 seconds after forming the one or more actuators 214 to remove oxide layer 314 from one or more portions of the device wafer 204 (e.g., substrate 212, one or more actuators 214, and / or plurality of germanium layers 218), as described above.

[0112] like Figure 7 , process 700 may include bonding the device wafer to the circuitry wafer of the MEMS structure after etching the device wafer (block 730). For example, a semiconductor processing tool (e.g., bonding tool 110) may bond the device wafer 204 to the CMOS wafer 202 of the MEMS structure 200 after etching the device wafer 204, as described above.

[0113] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0114] In a first embodiment, forming the one or more actuators 214 includes forming a photoresist layer 310 on a surface of the device wafer 204, etching (e.g., using an etching tool 108) the device wafer 204 based on the photoresist layer 310 (e.g., based at least in part on a pattern 312 formed in the photoresist layer 310) to form the one or more actuators 214, and performing a plasma ashing process to remove the photoresist layer 310. In a second embodiment, either alone or in combination with the first embodiment, immersing the device wafer 204 in the acid-based etchant 318 for the duration includes immersing the device wafer 204 in the acid-based etchant 318 for the duration after performing the plasma ashing process without an intervening process to form a pre-cleaning treatment layer on the device wafer 204. In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 700 includes rinsing the device wafer 204 with deionized water 320 for another duration after etching the device wafer 204, and drying the device wafer after rinsing the device wafer (e.g., with a deionized water bath), wherein bonding the device wafer 204 to the CMOS wafer 202 includes bonding the device wafer 204 to the CMOS wafer 202 after drying the device wafer 204.

[0115] In a fourth embodiment, alone or in combination with one or more of the first through third embodiments, process 700 includes bonding the device wafer 204 to the capping wafer 206 on an opposite side of the device wafer 204 from the bonded CMOS wafer 202 (e.g., the bonding tool 110), wherein the device wafer 204, the CMOS wafer 202, and the capping wafer 206 form a cavity 222 for the one or more actuators 214. In a fifth embodiment, alone or in combination with one or more of the first through fourth embodiments, one or more portions of the device wafer 204 include one or more silicon portions of the device wafer 204 (e.g., the substrate 212 and / or the one or more actuators 214) and one or more germanium portions of the device wafer 204 (e.g., the plurality of germanium layers 218). In a sixth embodiment, alone or in combination with one or more of the first through fifth embodiments, the acid-based etchant 318 includes approximately 4% nitric acid, approximately 19% acetic acid, and approximately 77% phosphoric acid.

[0116] although Figure 7 Multiple example blocks of process 700 are shown, but in some embodiments, Figure 7 The process 700 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner than those depicted in FIG. Additionally or alternatively, two or more of the multiple blocks of the process 700 may be performed in parallel.

[0117] Figure 8 is a flow chart of an example process 800 associated with forming a MEMS structure. In some embodiments, Figure 8 One or more process blocks of may be performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tool 102 to the semiconductor processing tool 110 and the wafer / die transport tool 112). Additionally or alternatively, Figure 8 One or more process blocks of may be performed by one or more components of device 500 , such as processor 520 , memory 530 , storage component 540 , input component 550 , output component 560 , and / or communication component 570 .

[0118] like Figure 8 , process 800 may include forming a MEMS actuator in a device wafer of a MEMS structure (block 810). For example, a semiconductor processing tool (e.g., deposition tool 102, exposure tool 104, developer tool 106, etch tool 108, and / or another semiconductor processing tool) may form MEMS actuator 214 in device wafer 204 of MEMS structure 200, as described above.

[0119] like Figure 8As further illustrated in FIG, process 800 may include, after forming the MEMS actuators, wet etching the device wafer in an acid-based etchant for a duration to remove oxide from one or more portions of the device wafer without an intervening pre-cleaning process after forming the MEMS actuators (block 820). For example, a semiconductor processing tool (e.g., etching tool 108) may wet etch the device wafer 204 in an acid-based etchant 318 for a duration to remove oxide from one or more portions of the device wafer 204 after forming the MEMS actuators 214, without an intervening pre-cleaning process after forming the MEMS actuators 214, as described above.

[0120] like Figure 8 , process 800 may include bonding the device wafer to the CMOS wafer after etching the device wafer (block 830). For example, a semiconductor processing tool (e.g., bonding tool 110) may bond the device wafer 204 to the CMOS wafer 202 after etching the device wafer 204, as described above.

[0121] Process 800 can include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0122] In a first embodiment, the acid-based etchant 318 comprises a combination of nitric acid, acetic acid, and phosphoric acid. In a second embodiment, alone or in combination with the first embodiment, one or more portions of the device wafer 204 comprise one or more germanium portions of the device wafer 204 (e.g., the plurality of germanium layers 218). In a third embodiment, alone or in combination with one or more of the first and second embodiments, wet etching the device wafer 204 without an intervening pre-cleaning process reduces the likelihood of the MEMS actuator 214 adhering to the walls of the cavity 222 within the MEMS structure 200 relative to performing an intervening pre-cleaning process.

[0123] In a fourth embodiment, bonding the device wafer 204 to the CMOS wafer 202 includes forming a eutectic bond between the germanium layer 218 of the device wafer 204 and the metal pad 208 of the CMOS wafer 202, either alone or in combination with one or more of the first through third embodiments. In a fifth embodiment, wet etching the device wafer 204 without an intervening pre-cleaning process reduces the likelihood of plasma damage to the device wafer 204 relative to performing an intervening pre-cleaning process. In a sixth embodiment, wet etching the device wafer 204 without an intervening pre-cleaning process, either alone or in combination with one or more of the first through fifth embodiments, the duration is in a range from about 20 seconds to about 30 seconds.

[0124] although Figure 8 Multiple example blocks of process 800 are shown, but in some embodiments, Figure 8 The process 800 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner than those depicted in FIG. Additionally or alternatively, two or more of the multiple blocks of the process 800 may be performed in parallel.

[0125] In this manner, a pre-cleaning process can be omitted from the eutectic bonding sequence. To remove oxide from one or more surfaces of the device wafer of the MEMS structure, the duration of the acid-based etch process in the eutectic bonding sequence can be increased relative to the duration of the acid-based etch process when the pre-cleaning process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove oxide from one or more surfaces of the device wafer without the use of the aforementioned pre-cleaning process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of adhesion between suspended mechanical components of the MEMS structure, and / or reduces the likelihood that the MEMS structure may become defective or inoperable during fabrication, thereby increasing process yield.

[0126] As described in more detail above, some embodiments described herein provide a method. The method includes etching a first wafer using an acidic etchant for a duration to remove oxide from one or more portions of the first wafer. Etching the first wafer for the duration enables removal of oxide from the one or more portions of the first wafer, without an intervening pre-cleaning process between removing a photoresist layer from the first wafer and etching the first wafer using the acidic etchant. The method includes bonding the first wafer to a second wafer after etching the first wafer. In some embodiments, the duration is in a range from approximately 20 seconds to approximately 30 seconds. In some embodiments, the first wafer comprises a microelectromechanical system (MEMS) device wafer; and wherein the second wafer comprises a microelectromechanical system (MEMS) circuit system wafer. In some embodiments, bonding the first wafer to the second wafer comprises performing eutectic bonding of the first wafer and the second wafer. In some embodiments, the one or more portions of the first wafer comprise at least one of: one or more silicon portions of the first wafer, or one or more germanium portions of the first wafer. In some embodiments, the acidic etchant comprises at least one of: nitric acid, acetic acid, or phosphoric acid. In some embodiments, the method further includes rinsing the first wafer in an alcohol / water bath for a duration after etching the first wafer; and drying the first wafer after rinsing the first wafer, wherein bonding the first wafer to the second wafer includes bonding the first wafer to the second wafer after drying the first wafer.

[0127] As described in more detail above, some embodiments described herein provide a method. The method includes forming one or more actuators in a device wafer of a MEMS structure. The method includes, after forming the one or more actuators, immersing the device wafer in an acid-based etchant for a duration to remove oxide from one or more portions of the device wafer, the duration being in the range of about 20 seconds to about 30 seconds. The method includes, after etching the device wafer, bonding the device wafer to a circuit system wafer of a MEMS structure. In some embodiments, forming the one or more actuators includes: forming a photoresist layer on a surface of the device wafer; etching the device wafer based on the photoresist layer to form the one or more actuators; and performing a plasma ashing process to remove the photoresist layer. In some embodiments, immersing the device wafer in the acid-based etchant for the duration includes: after performing the plasma ashing process, immersing the device wafer in the acid-based etchant for the duration without an intervening process for forming a pre-cleaning treatment layer on the device wafer. In some embodiments, the method further includes: rinsing the device wafer with deionized water for another duration after etching the device wafer; and drying the device wafer after rinsing the device wafer, wherein bonding the device wafer to the circuit system wafer includes: bonding the device wafer to the circuit system wafer after drying the device wafer. In some embodiments, the method further includes: bonding the device wafer to a capping wafer on an opposite side of the device wafer from that bonded to the circuit system wafer, wherein the device wafer, the circuit system wafer, and the capping wafer form a cavity for the one or more actuators. In some embodiments, the one or more portions of the device wafer include: one or more silicon portions of the device wafer, and one or more germanium portions of the device wafer. In some embodiments, the acid-based etchant includes: approximately 4% nitric acid, approximately 19% acetic acid, and approximately 77% phosphoric acid.

[0128] As described in greater detail above, some embodiments described herein provide a method. The method includes forming a MEMS actuator in a device wafer of a MEMS structure. The method includes, after forming the MEMS actuator and without intervening pre-cleaning, wet etching the device wafer in an acid-based etchant for at least 20 seconds to remove oxide from one or more portions of the device wafer. The method includes, after etching the device wafer, bonding the device wafer to a CMOS wafer.

[0129] As described in more detail above, some embodiments described herein provide a method. The method includes forming a MEMS actuator in a device wafer of a MEMS structure. After forming the MEMS actuator, wet etching the device wafer in an acid-based etchant for a duration to remove oxide from one or more portions of the device wafer, without an intervening pre-cleaning process after forming the MEMS actuator. The method includes bonding the device wafer to a CMOS wafer after etching the device wafer. In some embodiments, the acid-based etchant comprises a combination of nitric acid, acetic acid, and phosphoric acid. In some embodiments, the one or more portions of the device wafer include one or more germanium portions of the device wafer. In some embodiments, wet etching the device wafer without an intervening pre-cleaning process reduces the likelihood of the MEMS actuator adhering to a wall of a cavity within the MEMS structure, relative to performing an intervening pre-cleaning process. In some embodiments, bonding the device wafer to the complementary metal oxide semiconductor wafer includes forming a eutectic bond between a germanium layer of the device wafer and a metal pad of the complementary metal oxide semiconductor wafer. In some embodiments, the duration is in the range of approximately 20 seconds to approximately 30 seconds.

[0130] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a micro-electromechanical system structure, comprising: After removing the photoresist layer from the first wafer, etching the first wafer using an acidic etchant for a duration to remove native oxide from a surface of one or more portions of the first wafer, wherein the duration is in the range of about 20 seconds to about 30 seconds, The acidic etchant comprises at least one of nitric acid, acetic acid, or phosphoric acid. wherein etching the first wafer for the duration enables removal of the native oxide from the surface of the one or more portions of the first wafer without an intervening pre-cleaning process between removing the photoresist layer from the first wafer and etching the first wafer using the acidic etchant; as well as Eutectic bonding of the first wafer and the second wafer is performed after etching the first wafer.

2. The method of forming a MEMS structure according to claim 1, wherein the first wafer comprises a MEMS device wafer; and The second chip includes a micro-electromechanical system circuit system chip.

3. The method of forming a MEMS structure according to claim 1 , wherein the one or more portions of the first wafer include at least one of: one or more silicon portions of the first wafer, or One or more germanium portions of the first wafer.

4. The method of forming a MEMS structure according to claim 1 , wherein the method further comprises: rinsing the first wafer in an alcohol / water bath for a duration after etching the first wafer; as well as drying the first wafer after rinsing the first wafer, The step of bonding the first wafer to the second wafer comprises: The first wafer is bonded to the second wafer after drying the first wafer.

5. A method of forming a micro-electromechanical system structure, comprising: forming a photoresist layer on a surface of a device wafer of a MEMS structure; etching the device wafer based on the photoresist layer to form one or more actuators in the device wafer of the MEMS structure; After forming the one or more actuators, removing the photoresist layer; immersing the device wafer in an acid-based etchant for a duration in a range of about 20 seconds to about 30 seconds to remove native oxide from a surface of one or more portions of the device wafer after removing the photoresist layer and without an intervening pre-cleaning process after forming the one or more actuators; After etching the device wafer, the device wafer is eutectically bonded to a circuit system wafer of the micro-electromechanical system structure.

6. The method of forming a MEMS structure according to claim 5, wherein A plasma ashing process is performed to remove the photoresist layer.

7. The method of forming a MEMS structure according to claim 6, wherein immersing the device wafer in the acid-based etchant for the duration comprises: After performing the plasma ashing process, the device wafer is immersed in the acid-based etchant for the duration without an intervening process for forming a pre-cleaning treatment layer on the device wafer.

8. The method of forming a MEMS structure according to claim 5, further comprising: rinsing the device wafer with deionized water for another duration after etching the device wafer; as well as drying the device wafer after rinsing the device wafer, Wherein bonding the device wafer to the circuit system wafer comprises: After drying the device wafer, the device wafer is bonded to the circuitry wafer.

9. The method of forming a MEMS structure according to claim 5, further comprising: bonding the device wafer to a capping wafer on an opposite side of the device wafer to which the circuitry wafer is bonded, The device wafer, the circuit system wafer, and the capping wafer form a cavity for the one or more actuators.

10. The method of forming a MEMS structure according to claim 5, wherein the one or more portions of the device wafer comprise: one or more silicon portions of the device wafer, and one or more germanium portions of the device wafer.

11. The method for forming a MEMS structure according to claim 5, wherein the acid-based etchant comprises: About 4% nitric acid, approximately 19% acetic acid, and Approximately 77% phosphoric acid.

12. A method of forming a micro-electromechanical system structure, comprising: forming a MEMS actuator in a device wafer of a MEMS structure; wet etching the device wafer in an acid-based etchant for a duration to remove native oxide from a surface of one or more portions of the device wafer after forming the MEMS actuator without an intervening pre-cleaning process after forming the MEMS actuator, wherein the acid-based etchant comprises a combination of: nitric acid, acetic acid, and phosphoric acid, wherein the duration is in a range of about 20 seconds to about 30 seconds; and bonding the device wafer to a complementary metal oxide semiconductor wafer after etching the device wafer, wherein bonding the device wafer to the complementary metal oxide semiconductor wafer comprises: A eutectic bond is formed between the germanium layer of the device wafer and the metal pad of the complementary metal oxide semiconductor wafer.

13. The method of forming a MEMS structure of claim 12, wherein the one or more portions of the device wafer comprise one or more germanium portions of the device wafer.

14. The method of forming a MEMS structure of claim 12, wherein wet etching the device wafer without an intervening pre-cleaning process reduces the likelihood of the MEMS actuator adhering to the walls of the cavity within the MEMS structure relative to performing an intervening pre-cleaning process.

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